WV3HG2128M64EEU665D4SG [WEDC]
2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED; 2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED
| 型号： | WV3HG2128M64EEU665D4SG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 2GB - 2x128Mx64 DDR2 SDRAM UNBUFFERED |
| 文件： | 总11页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED*
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
ꢀ
200-pin, dual in-line memory module (SO-DIMM)
The WV3HG2128M64EEU is a 2x128Mx64 Double Data
Rate DDR2 SDRAM high density SO-DIMM. This memory
module consists of sixteen 128Mx8 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
200-pin SO-DIMM FR4 substrate.
ꢀ
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
ꢀ
Utilizes 800*, 667*, 533 and 400 Mb/s DDR2
SDRAM components
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
CC = 1.8V 0.1V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
CCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
Dual Rank
RoHS compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
February 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
Pin Name
Function
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQS2
DM2
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A1
A0
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
VSS
CK0,CK1
CK0#, CK1#
CKE0, CKE1
RAS#
CAS#
WE#
CS0#, CS1#
A0-A13
A10/AP
BA0 - BA2
ODT0,ODT1
SCL
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
2
3
VSS
VCC
4
DQ4
DQ0
DQ5
DQ1
VSS
VSS
VCC
5
DQ18
DQ22
DQ19
DQ23
VSS
A10/AP
BA1
BA0
6
VSS
7
DQ48
DQ52
DQ49
DQ53
VSS
8
RAS#
WE#
CS0#
VCC
Chip Selects
Address Inputs
9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DM0
DQS0#
VSS
VSS
Address Input/Auto precharge
SDRAM Bank Address
On-die termination control
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD address
Data Input/Output
Data Masks
Data strobes
Data strobes complement
Core and I/O Power
Ground
Input/Output Reference
SPD Power
DQ24
DQ28
DQ25
DQ29
VSS
VCC
VSS
DQS0
DQ6
VSS
DQ7
DQ2
VSS
DQ3
DQ12
VSS
DQ13
DQ8
VSS
CAS#
ODT0
CS1#
A13
NC
CK1
SDA
VSS
VSS
CK1#
DQS6#
VSS
SA0, SA1
DQ0-DQ63
DM0-DM7
DQS0-DQS7
DQS0#-DQS7#
VCC
DM3
DQS3#
NC
VCC
VCC
ODT1
NC
VSS
VSS
DQS6
DM6
VSS
DQS3
VSS
VSS
VSS
VSS
VREF
DQ26
DQ30
DQ27
DQ31
VSS
DQ32
DQ36
DQ33
DQ37
VSS
DQ50
DQ54
DQ51
DQ55
VSS
DQ9
DM1
VSS
VCCSPD
NC
Spare pins, No connect
VSS
VSS
VSS
VSS
DQS1#
CK0
DQS1
CK0#
VSS
CKE0
CKE1
VCC
DQS4#
DM4
DQS4
VSS
DQ56
DQ60
DQ57
DQ61
VSS
VCC
NC
VSS
VSS
NC
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
BA2
NC
DM7
DQS7#
VSS
VCC
VCC
DQS7
DQ58
VSS
DQ59
DQ62
VSS
DQ63
SDA
VSS
SCL
SA0
VCCSPD
SA1
A12
A11
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
A9
VSS
A7
DQ16
DQ20
DQ17
DQ21
VSS
A8
A6
VCC
VSS
VCC
DQS5#
DM5
DQS5
VSS
A5
VSS
DQS2#
NC
A4
A3
A2
VSS
February 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
+
10 ohm 5ꢀ
CKE1
ODT1
CS1#
CKE0
ODT0
CS0#
CS0#
CS1#
CS0#
CS1#
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DQS
DQS#
DM
DQS
DQS#
DM
DQS
DQS#
DM
DQS
DQS#
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0#
CS1#
CS0#
CS1#
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DQS
DQS#
DM
O
D
T
0
C
K
E
0
DQS
DQS#
DM
O
D
T
1
C
K
E
1
DQS
DQS#
DM
O
D
T
0
C
K
E
0
DQS
DQS#
DM
O
D
T
1
C
K
E
1
DQ8
I/O 8
I/O 8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS0#
CS1#
CS0#
CS1#
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
O
D
T
0
C
K
E
0
O
D
T
1
C
K
E
1
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DQS
DQS#
DM
DQS
DQS#
DM
DQS
DQS#
DM
DQS
DQS#
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0#
CS1#
CS0#
CS1#
DQS3
DQS3#
DM3
DQS
DQS#
DM
O
D
T
0
C
K
E
0
DQS
DQS#
DM
O
D
T
1
C
K
E
1
DQS7
DQS7#
DM7
DQS
DQS#
DM
O
D
T
0
C
K
E
0
DQS
DQS#
DM
O
D
T
1
C
K
E
1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
* Clock Wiring
DDR2 SDRAMs
10 ohm 5ꢀ
BA0 - BA2
A0 - A13
RAS#
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
SCL
SA0
SA1
SCL
A0
Clock Input
SPD
*CK0/CK0#
*CK1/CK1#
8 DDR2 SDRAMs
8 DDR2 SDRAMs
A1
SDA
A2
WP
* Wire per Clock Loading
Table/Wiring Diagrams
CAS#
WE#
V
V
V
V
SPD
Serial PD
DDR2 SDRAMs
CC
Notes :
1. All resistor values are 22 ohms 5ꢀ unless otherwise specified
2. BAx, Ax, RAS#, CAS#, WE# resistors : 3.0 Ohms 5ꢀ.
REF
CC
DDR2 SDRAMs, VCC,
DDR2 SDRAMs, SPD
VCCQ and VCCL
SS
February 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
1.8
Max.
1.9
Units
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
Notes:
V
V
V
VREF
VTT
0.49 x VCC
VREF-0.04
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
1
2
1.
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurment is to be taken at the nearest VREF bypass capacitor.
TT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
2.
V
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-1.0
-0.5
-55
Max
2.3
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
2.3
V
100
˚C
Command/Address,
RAS#, CAS#, WE#
-80
80
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
DM
-40
-40
-10
40
40
10
µA
µA
µA
IL
Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable
IOZ
DQ, DQS, DQS#
-10
-32
10
32
µA
µA
IVREF
VREF leakage current; VREF = Valid VREF level
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Symbol
Parameter
Min
20
12
12
12
9
Max
36
20
20
20
11
Units
Input Capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance (CS0#, CS1#)
CIN1
CIN2
pF
pF
pF
pF
pF
pF
pF
CIN3
Input Capacitance (CK0, CK0#, CK1, CK1#)
CIN4
CIN5 (667)*
IN5 (533 & 400)
COUT1 (667)*
Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7)
C
9
12
11
9
Input Capacitance (DQ0 ~ DQ63)
* 800Mb/s = TBD
COUT1
(533 & 400)
9
12
pF
February 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Operating temperature
Notes:
Symbol
Rating
Units
Notes
TOPER
0° to 85°
°C
1, 2
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.300
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIH(DC)
VIL(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
Input Low (Logic 1) Voltage DDR2-667
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
Input Low (Logic 0) Voltage DDR2-667, DDR2-800 TBD
VREF + 0.250
-
V
V
V
V
VREF + 0.200
-
-
-
VREF - 0.250
VREF - 0.200
February 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge;
806
665
534
403
Units
t
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid
816
776
736
mA
TBD
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
896
856
816
mA
TBD
ICC2P** Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
192
140
720
192
560
640
192
560
640
mA
mA
mA
TBD
TBD
TBD
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
480
192
400
192
400
192
mA
mA
TBD
TBD
Slow PDN Exit MRS(12) = 1
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
800
720
720
mA
mA
mA
TBD
TBD
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1,336 1,136 1,016
1,336 1,136 1,016
3,520 3,440 3,360
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
mA
mA
TBD
TBD
TBD
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
ICC6**
ICC7*
Normal
160
160
160
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
2,496 2,336 2,176
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
February 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
ps
ps
ps
tCK
tCK
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
TBD
TBD
CK high-level width
CK low-level width
tCL
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
MIN (tCH
,
MIN (tCH
,
MIN (tCH
,
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
DQ and DM input setup time relative to
tHP
ps
tCL
)
tCL
)
tCL
)
tJIT
tAC
TBD
TBD
TBD
TBD
TBD
TBD
-125
-450
125
+450
-125
-500
125
+500
-125
-600
125
+600
ps
ps
tHZ
tLZ
tAC MAX
tAC MAX
tAC MAX
ps
ps
TBD
TBD
TBD
TBD
tAC MIN tAC MAX tAC MIN tAC MAX tAC MIN tAC MAX
tDS
tDH
100
225
0.35
100
225
0.35
150
275
0.35
ps
ps
tCK
ps
ps
DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
TBD
TBD
TBD
TBD
tDIPW
tQHS
tQH
input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
TBD
TBD
TBD
TBD
340
400
450
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
0.35
-400
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
ns
tCK
tCK
ps
+400
240
+450
300
+500
350
tCK
DQS falling edge from CK rising … hold
time
tDSH
0.2
0.2
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per
TBD
TBD
group,
tDQSQ
ps
per access
DQS read preamble
tRPRE
tRPST
tWPRES
tWPRE
tWPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
1.1
0.6
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
1.1
0.6
0.9
0.4
0
0.35
0.4
WL
- 0.25
0.6
1.1
0.6
tCK
tCK
p s
tCK
tCK
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching
transition
0.6
WL +
0.25
0.6
WL +
0.25
0.6
WL +
0.25
tDQSS
tIPW
tCK
tCK
Address and control input pulse width for
each input
TBD
TBD
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIS
tIH
tCCD
200
275
2
250
375
2
350
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
February 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
800
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
55
7.5
15
37.5
45
7.5
15
MAX
MIN
60
7.5
15
37.5
45
7.5
15
MAX
MIN
65
7.5
15
37.5
45
7.5
15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRC
TBD
tRRD
TBD
tRCD
TBD
tFAW
37.5
70,000
37.5
70,000
37.5
70,000
TBD
tRAS
TBD
tRTP
TBD
tWR
TBD
Auto precharge write recovery + precharge
tDAL
tWR
+
tWR
+
tWR
+
TBD
time
tRP
tRP
tRP
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tWTR
tRP
tRPA
tMRD
7.5
15
7.5
15
10
15
tRP+tCK
ns
ns
ns
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tRP+ CK
t
tRP+ CK
t
TBD
2
2
2
TBD
tDELAY
tIS + tCK
tIS + tCK
tIS + tCK
TBD
+ tIH
+ tIH
+ tIH
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interval
tRFC
127.5
70,000
7.8
127.5
70,000
7.8
127.5
70,000
7.8
ns
TBD
TBD
TBD
Average periodic refresh interval
tREFI
µs
ns
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
TBD
Exit self refresh to non-READ command
tXSNR
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
200
tIS
2
200
tIS
2
200
tIS
2
tCK
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
2
2
tAC
tAC
tAC
tAC
tAC
tAC
ODT turn-on
tAON
tAOFD
tAOF
(MAX) +
(MAX) +
(MAX) +
ps
tCK
ps
(MIN)
(MIN)
(MIN)
1000
1000
1000
ODT turn-off delay
ODT turn-off
TBD
TBD
TBD
TBD
2.5
2.5
tAC
(MAX) +
600
2.5
2.5
tAC
(MAX) +
600
2.5
2.5
tAC
(MAX) +
600
tAC
tAC
tAC
(MIN)
(MIN)
(MIN)
2 x tCK
2 x tCK
2 x tCK
TBD
TBD
TBD
TBD
tAC
tAC
tAC
+ tAC
+ tAC
+ tAC
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
(MIN) +
2000
(MIN) +
2000
(MIN) +
2000
ps
ps
(MAX) +
1000
(MAX) +
1000
(MAX) +
1000
2.5 x
2.5 x
2.5 x
tAC
tAC
tAC
t
CK + tAC
t
CK + tAC
tCK + tAC
tAOFPD
(MIN) +
2000
(MIN) +
2000
(MIN) +
2000
(MAX) +
1000
(MAX) +
1000
(MAX) +
1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
TBD
TBD
TBD
TBD
TBD
TBD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tXP
7 - AL
6 - AL
6 - AL
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
A Exit precharge power-down to any non-
2
2
3
2
3
READ command.
CKE minimum high/low time
tCKE
3
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
February 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D4
Part Number
Clock Speed
CAS Latency tRCD tRP
Height**
WV3HG2128M64EEU806D4xG*
WV3HG2128M64EEU665D4xG*
WV3HG2128M64EEU534D4xG
WV3HG2128M64EEU403D4xG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
6
5
4
3
6
5
4
3
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
* Consult factory for availability
NOTES:
• RoHS product. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
6.35 (0.250)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161)
3.90(0.154)
(2X)
30.15 (1.187)
29.85 (1.175)
20.00 (0.787)
TYP
1.80 (0.071)
(2X)
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
February 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 128M 64 E E U xxx D4 x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
February 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2128M64EEU-D4
White Electronic Designs
ADVANCED
Document Title
2GB – 2x128Mx64 DDR2 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev 0
Created
February 2006
Advanced
February 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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