WV3HG264M72EEU806D4MG [WEDC]
DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, SODIMM-200;
| 型号： | WV3HG264M72EEU806D4MG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 128MX72, CMOS, ROHS COMPLIANT, SODIMM-200 动态存储器 双倍数据速率 |
| 文件： | 总11页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED*
1GB – 2x64Mx72 DDR2 SDRAM UDIMM, SO-DIMM w/PLL
FEATURES
DESCRIPTION
ꢀ
Unbuffered 200-pin (SO-DIMM) small-outline dual
The WV3HG264M72EEU is a 2x64Mx72 Double Data
Rate DDR2 SDRAM high density module. This memory
module consists of eighteen 64Mx8 bit DDR2 Synchronous
DRAMs in FBGA packages, mounted on a 200-pin SO-
DIMM FR4 substrate.
in-line memory module
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ꢀ
Support ECC detection and correction
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4200 and PC2-3200
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ꢀ
V
CC = VCCQ = 1.8V 0.1V
CCSPD = 1.7V to 3.6V
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock input (CK,CK#)
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
ꢀ
ꢀ
ꢀ
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ꢀ
ꢀ
ꢀ
ꢀ
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Programmable CAS# latency (CL): 3 4, 5*, and 6*
Adjustable data-output drive strength
7.8µs average periodic refresh interval
On-die termination (ODT)
Posted CAS# latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
Dual Rank
RoHS compliant
JEDEC proposed pin-out
Package option
• 200 Pin SO-DIMM: 30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4200
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
April 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
Pin Name
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VCC
A6
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VSS
VSS
A0-A13
BA0, BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
ODT0, ODT1
CK,CK#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
RESET#
VCC
VSS
2
3
4
5
6
7
8
9
DQ0
DQ4
VSS
DQ5
DQ1
VSS
DQS0#
DM0
DQS0
VSS
DQ19
DQ28
VSS
DQ29
DQ24
VSS
DQ25
DM3
VSS
A5
A4
A3
VCC
A2
A1
VCC
A0
A10/AP
BA1
BA0
VCC
RAS#
WE#
VCC
CS0#
CAS#
ODT0
CS1#
A13
VCC
VCC
ODT1
CK
NC
DQS5#
DM5
DQS5
VSS
Data strobes
VSS
Data strobes complement
On-die termination controls
Clock inputs
Clock enable inputs
Chip select inputs
Row Address Strobe
Column Address Strobe
Write Enable
DQ46
DQ42
DQ47
DQ43
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
VSS
DQ6
DQ2
DQ7
DQ3
VSS
DQ52
DQ48
DQ53
DQ49
VSS
Register reset input
Core Power
Ground
VSS
VSS
DQ26
CB4
DQ27
CB5
VSS
VSS
SA0-SA1
SDA
VREF
DM0-DM8
VCCSPD
SCL
SPD address
DQ12
DQ8
DQ13
DQ9
VSS
DM6
DQS6#
VSS
DQS6
DQ54
VSS
DQ55
DQ50
VSS
DQ51
DQ60
VSS
DQ61
DQ56
VSS
DQ57
DM7
VSS
DQ62
DQS7#
VSS
DQS7
DQ63
DQ58
SDA
Serial Data Input/Output
Input/Output Reference Voltage
Data-in mask
Serial EEPROM power supply
SPD Clock Input
No connect
VSS
VSS
CB0
DM8
CB1
VSS
DM1
DQS1#
VSS
DQS1
DQ14
VSS
DQ15
DQ10
VSS
DQ11
DQ20
VSS
DQ21
DQ16
VSS
DQ17
RESET#
VSS
DM2
DQS2#
VSS
DQS2
DQ22
VSS
NC
CK#
DQ32
VSS
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
DQ36
DQ33
DQ37
DQS4#
VSS
DQS4
DM4
VSS
VSS
CB2
CKE0
CB3
NC
VSS
NC
NC
VCC
NC
A12
VSS
DQ34
DQ38
DQ35
DQ39
VSS
VSS
SCL
DQ59
SA1
VCCSPD
SA0
A11
A9
VCC
A7
VSS
DQ40
DQ44
DQ41
DQ45
DQ23
A8
April 2006
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS5
DQS5#
DM5
DM
DM
DM
DM
DQ8
DQ9
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2#
DM2
DQS6
DQS6#
DM6
DM
DM
DM
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS7
DQS7#
DM7
DM
DM
DM
DM
CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS8
DQS8#
DM8
Serial PD
SCL
SDA
DM#
DM
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
WP A0 A1 A2
SA0 SA1
SA2
VCCSPD
VCC/VCCQ
VREF
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
CS# : DDR2 SDRAMs
CS# : DDR2 SDRAMs
CS0#
CS1#
VSS
BA0 - BA1 : DDR2 SDRAMs
A0 - A13 : DDR2 SDRAMs
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
BA0 - BA1
A0 - A13
RAS#
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
120Ω
CK
CK#
CK0
CK0#
PLL
RESET#
NOTE: All resistor values are 22 ohms unless otherwise specified.
April 2006
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
Max
1.9
Unit
V
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
1.8
0.50 x VCC
VREF
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.51 x VCC
VREF+0.04
3.6
V
VTT
V
VCCSPD
-
V
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
3. CCQ of all IC's are tied to VCC
.
V
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-90
Max
2.3
2.3
90
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
VIN, VOUT
V
Command/Address,
RAS#, CAS#, WE#,
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
CS#, CKE
CK, CK#
-45
-10
-10
-10
-36
45
10
10
10
36
µA
µA
µA
µA
µA
IL
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
IVREF
INPUT/OUTPUT CAPACITANCE
TA=25°C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (0A~A13, BA0~BA1,
CIN1
22
13
40
pF
RAS#, CAS#, WE#)
Input capacitance (CKE0, CKE1),
(ODT0, ODT1)
CIN2
22
pF
Input capacitance (CS0# - CS1#)
Input capacitance (CK, CK#)
Input capacitance (DM0~DM8),
(DQS0~DQS8)
CIN3
CIN4
CIN5 (665)
CIN5 (534, 403)
OUT1 (665)
COUT1 (534, 403)
13
6
9
9
9
22
7
11
12
11
12
pF
pF
pF
pF
pF
pF
C
Input capacitance (DQ0~DQ63),
(CB0~CB7)
9
April 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (Commercial)
Notes:
TOPER
0° to 85°
°C
1, 2
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF + 0.250
-
V
DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage
DDR2-667
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 0) Voltage
DDR2-667
VREF + 0.200
-
V
V
V
-
-
VREF - 0.250
VREF - 0.200
April 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
VCC = +1.8V 0.1V
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge current;
806
665
534
403
Units
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,137 1,092 1,092
mA
TBD
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as ICC4W
1,272 1,227 1,227
mA
TBD
ICC2P* Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
444
930
444
840
930
444
840
930
mA
mA
mA
TBD
TBD
TBD
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
1,020
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
840
516
840
516
840
516
mA
mA
TBD
TBD
Slow PDN Exit MRS(12) = 1
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
1,290 1,200 1,200
1,632 1,452 1,362
1,677 1,497 1,362
3,000 2,820 2,820
mA
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
TBD
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as ICC4W
ICC5B** Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC6**
Self refresh current;
CK and CK\ at 0V; CKE 0.2V; Other control and address bus
inputs
are FLOATING; Data bus inputs are FLOATING
Normal
144
144
144
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
2,352 2,352 2,352
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reflects all module ranks in this operating condition.
April 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
VCC = +1.8V 0.1V
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL MIN
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
ps
ps
ps
tCK
tCK
ps
ps
ps
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
TBD
TBD
TBD
TBD
TBD
TBD
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
Clock cycle time
TBD
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
TBD
TBD
CK high-level width
CK low-level width
Half clock period
Clock jitter
DQ output access time from CK/CK#
Data-out high-impedance window from
CK/CK#
Data-out low-impedance window from
CK/CK#
DQ and DM input setup time relative to
tCL
tHP
tJIT
tAC
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.45
0.55
0.45
0.55
0.45
0.55
MIN(tCH, CL
-125
-450
t
)
MIN(tCH, CL
-125
-500
t
)
MIN(tCH, CL
-125
-600
t
)
125
+450
125
+500
125
+600
tHZ
tLZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
ps
ps
TBD
TBD
TBD
TBD
tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX) tAC(MIN) tAC(MAX)
tDS
tDH
100
225
0.35
100
225
0.35
150
275
0.35
DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each
TBD
TBD
TBD
TBD
tDIPW
tQHS
tQH
tCK
ps
ps
input)
Data hold skew factor
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access
TBD
TBD
TBD
TBD
340
400
450
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tQH - tDQSQ
0.35
0.35
-400
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
ns
tCK
tCK
ps
+400
240
+450
300
+500
350
tCK
DQS falling edge from CK rising … hold
time
tDSH
0.2
0.2
0.2
tCK
DQS…DQ skew, DQS to last DQ valid, per
TBD
TBD
group,
tDQSQ
ps
per access
DQS read preamble
tRPRE
tRPST
tWPRES
tWPRE
tWPST
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9
0.4
0
0.35
0.4
WL-
0.25
0.6
1.1
0.6
0.9
0.4
0
0.35
0.4
WL-
0.25
0.6
1.1
0.6
0.9
0.4
0
0.35
0.4
WL-
0.25
0.6
1.1
0.6
tCK
tCK
p s
tCK
tCK
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
Write command to first DQS latching
transition
0.6
WL+
0.25
0.6
WL+
0.25
0.6
WL+
0.25
tDQSS
tIPW
tCK
tCK
Address and control input pulse width for
each input
TBD
TBD
Address and control input setup time
Address and control input hold time
Address and control input hold time
tIS
tIH
tCCD
200
275
2
250
375
2
250
475
2
ps
ps
tCK
TBD
TBD
TBD
TBD
TBD
TBD
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
April 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
VCC = +1.8V 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL MIN
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
MIN
55
7.5
15
37.5
45
7.5
15
MAX
MIN
55
7.5
15
37.5
45
7.5
15
MAX
MIN
55
7.5
15
37.5
45
7.5
15
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
tRC
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
37.5
70,000
37.5
70,000
37.5
70,000
Auto precharge write recovery + precharge
tDAL
tWR
+
tWR
+
tWR
+
time
tRP
tRP
tRP
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tWTR
tRP
tRPA
tMRD
tDELAY
ns
ns
ns
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
7.5
15
7.5
15
10
15
tRP+tCK
tRP+ CK
t
tRP+ CK
t
2
2
2
tIS + tCK
tIS + tCK
tIS + tCK
+ tIH
+ tIH
+ tIH
TBD
TBD
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
105
70,000
7.8
105
70,000
7.8
105
70,000
7.8
ns
TBD
TBD
TBD
TBD
Average periodic refresh interval
tREFI
µs
ns
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
Exit self refresh to non-READ command
tXSNR
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
200
tIS
2
200
tIS
2
200
tIS
2
tCK
ps
tCK
2
2
2
tAC
tAC
tAC
tAC
tAC
tAC
ODT turn-on
tAON
tAOFD
tAOF
(MAX)
(MAX)
(MAX)
ps
tCK
ps
(MIN)
(MIN)
(MIN)
+ 1000
+ 1000
+ 1000
ODT turn-off delay
ODT turn-off
TBD
TBD
TBD
TBD
2.5
2.5
2.5
2.5
2.5
2.5
tAC
tAC
tAC
tAC
tAC
tAC
(MAX)
(MAX)
(MAX)
(MIN)
(MIN)
(MIN)
+ 600
+ 600
+ 600
TBD
TBD
TBD
TBD
2 x tCK
+ tAC
2 x tCK
+ tAC
2 x tCK
+ tAC
tAC
tAC
tAC
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
(MIN) +
2000
(MIN) +
2000
(MIN) +
2000
ps
ps
(MAX)
+ 1000
(MAX)
+ 1000
(MAX)
+ 1000
2.5
2.5
2.5
tAC
x tCK
tAC
x tCK
tAC
x tCK
tAOFPD
(MIN) +
2000
+ tAC
(MIN) +
2000
+ tAC
(MIN) +
2000
+ tAC
(MAX)
+ 1000
(MAX)
+ 1000
(MAX)
+ 1000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
TBD
TBD
TBD
TBD
TBD
TBD
3
8
3
8
3
8
tCK
tCK
tCK
Exit active power-down to READ command,
2
2
2
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tXP
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
7 - AL
6 - AL
6 - AL
A Exit precharge power-down to any non-
2
3
2
3
2
3
READ command.
CKE minimum high/low time
tCKE
* AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
April 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR PD4
Part Number
Speed/Data Rate CAS Latency tRCD
tRP
6
Height*
WV3HG264M72EEU806PD4xxG** 400MHz/800Mb/s
WV3HG264M72EEU665PD4xxG** 333MHz/667Mb/s
6
5
4
3
6
5
4
3
30.00mm (1.81")TYP
30.00mm (1.81")TYP
30.00mm (1.81")TYP
30.00mm (1.81")TYP
5
WV3HG264M72EEU534PD4xxG
WV3HG264M72EEU403PD4xxG
266MHz/533Mb/s
200MHz/400Mb/s
4
3
** Consult factory for availability
NOTES:
• RoHS product. (“G” = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
PACKAGE DIMENSIONS FOR PD4
FRONT VIEW
67.75 (2.667)
67.45 (2.656)
3.80 (0.150)
MAX
4.10(0.161)
3.90(0.154)
(2X)
30.15 (1.187)
29.85 (1.175)
1.800 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
2.504 (63.60)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
Tolerances: 0.13 (0.005) unless otherwise specified
April 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 64M 72 E E U xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED (UDIMM)
SPEED (Mb/s)
PACKAGE 200 PIN SO-DIMM
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
April 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG264M72EEU-PD4
White Electronic Designs
ADVANCED
Document Title
1GB – 2x64Mx72 DDR2 SDRAM UNBUFFERED, SO-DIMM w/PLL
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• MICRON: U37Y: B-Die
Revision History
Rev #
History
Release Date Status
Rev 0
Created
August 2005
Concept
Rev 1
1.0 Updated ICC, CAP & AC specs
March 2006
Advanced
1.1 Added industrial temp option to part numbering guide
1.2 Changed from concept to advanced
Rev 2
2.0 Update ICC, CAP & AC specs
2.1 Added "P" for JEDEC proposed pin-out
2.2 Added die Rev info
April 2006
Advanced
April 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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