WV3HG32M40SEU534PD4IEG [WEDC]
128MB - 32Mx40 DDR2 SDRAM UNBUFFERED, ECC, w/PLL; 128MB - 32Mx40 DDR2 SDRAM缓冲， ECC ，W / PLL
| 型号： | WV3HG32M40SEU534PD4IEG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128MB - 32Mx40 DDR2 SDRAM UNBUFFERED, ECC, w/PLL |
| 文件： | 总11页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED*
128MB – 32Mx40 DDR2 SDRAM UNBUFFERED, ECC, w/PLL
FEATURES
DESCRIPTION
ꢀ
Unbuffered 200-pin, Small-Outline DIMM (SO-
DIMM)
The WV3HG32M40SEU is a 32Mx40 Double Data Rate 2
SDRAM memory module based on 512Mb DDR2 SDRAM
components. The module consists of three 32Mx16, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
ꢀ
ꢀ
Suppot ECC error detection and correction
Fast data transfer rates: PC2-5300*, PC2-4200 and
PC2-3200
ꢀ
Utilizes 667*, 533 and 400 Mb/s DDR2 SDRAM
components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
ꢀ
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ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
CC = 1.8V ±0.1V
VCCSPD = 1.7V to 3.6V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Differential clock inputs (CK, CK#)
Four-bit prefetch architecture
Programmable CAS# latency (CL): 3, 4, and 5
Posted CAS# additive latency; 0, 1, 2, 3 and 4
Programmable burst: length (4, 8)
On-die termination (ODT)
On memory PLL clock
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
RoHS Compliant
JEDEC proposed Pin-out
Package option:
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
Clock Speed
CL-tRCD-tRP
Note:
•
Consult factory for availability
June 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol
SYMBOL
A0-A12
ODT0
DESCRIPTION
Address input
On-Die Termination
Clock Input
1
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ18
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
VCC
A6
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
VSS
VSS
NC
2
3
DQ0
DQ4
VSS
DQ19
DQ28
VSS
A5
CK, CK#
CB0 - CB7
CKE0
4
A4
NC
Check Bits
5
A3
NC
Clock Enable input
Chip select
6
DQ5
DQ1
VSS
DQ29
DQ24
VSS
VCC
A2
VSS
VSS
NC
CS0#
7
8
A1
RAS#, CAS#, WE# Command Inputs
9
DQS0#
DM0
DQS0
VSS
DQ25
DM3
VSS
VCC
A0
NC
BA0, BA1
Bank Address Inputs
Input Data Mask
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DM0-DM3, DM8
DQ0-DQ31
A10/AP
BA1
BA0
VCC
RAS#
WE#
VCC
CS0#
CAS#
ODT0
NC
NC
Data Input/Output
VSS
VSS
VSS
NC
DQS0-DQS3,
DQS8
VSS
DQS3#
DQ30
DQS3
DQ31
VSS
Data Strobe
DQ6
DQ2
DQ7
DQ3
VSS
DQS03-DQS3#,
DQS8#
NC
Data Strobe Complement
NC
SCL
SPD Clock Input
NC
VSS
VSS
VSS
NC
SA0-SA1
SDA
VCC
SPD Address Inputs
Serial Data Input/Output
Power Supply
VSS
DQ26
CB4
DQ27
CB5
VSS
DQ12
DQ8
DQ13
DQ9
VSS
NC
VREF
VSS
Input/Output reference voltage
Ground
NC
VSS
NC
VCC
VCC
NC
VCCSPD
NC
Serial EEPROM Power Supply
No Connect
VSS
NC
VSS
CB0
DM8
CB1
VSS
VSS
NC
DM1
DQS1#
VSS
CK
NC
NC
CK#
NC
VSS
NC
DQS1
DQ14
VSS
VSS
CB6
DQS8#
CB7
DQS8
VSS
VSS
VSS
NC
NC
VSS
NC
DQ15
DQ10
VSS
NC
NC
NC
VSS
NC
DQ11
DQ20
VSS
VSS
NC
CB2
CKE0
CB3
NC
VSS
NC
NC
VSS
NC
DQ21
DQ16
VSS
NC
VSS
VSS
NC
NC
VSS
VSS
NC
DQ17
NC
NC
NC
NC
NC
VSS
VCC
NC
NC
DM2
DQS2#
VSS
NC
NC
SDA
VSS
SCL
NC
A12
VSS
VSS
NC
A11
DQS2
DQ22
VSS
A9
VCC
NC
SA1
VCCSPD
SA0
A7
NC
DQ23
A8
NC
June 2006
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS0#
CS
DQS0
DQS0#
DM0
DQS
DQS#
DM/RDQS
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS1#
DM1
DQS
DQS#
DM/RDQS
DQ8
DQ9
I/O 8
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
DQS2
DQS2#
DM2
DQS
DQS#
DM/RDQS
I/O 0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DQS3#
DM3
DQS
DQS#
DM/RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CS
DQS
DQS8
DQS8#
DM8
DQS#
DM/RDQS
I/O 0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS#
DM/RDQS
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
CK
PCK0-PCK2 → CK: DDR2 SDRAMs
P
L
L
CK#
PCK0# → PCK2# → CK#: DDR2 SDRAMs
CS0#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CS0# → CS#: DDR2 SDRAMs
SCL
Serial PD
WP A0 A1 A2
SDA
BA0-BA1 → BA0-BA1: DDR2 SDRAMs
A0-A12 → A0-A12: DDR2 SDRAMs
RAS# → RAS#: DDR2 SDRAMs
CAS# → CAS#: DDR2 SDRAMs
WE# → WE#: DDR2 SDRAMs
CKE0 → CKE: DDR2 SDRAMs
ODT0 → ODT: DDR2 SDRAMs
SA0 SA1
CKE0
ODT0
V
CCSPD
Serial PD
VCC
DDR2 SDRAMs
V
REF
DDR2 SDRAMs
DDR2 SDRAMs
V
SS
NOTE: All resistor value, are 22 ohms ± 5% unless otherwise specified.
June 2006
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
2.3
V
100
˚C
Command/Address,
RAS#, CAS#, WE#
-15
15
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
CS#, CKE
CK, CK#
DM
-15
-10
-5
15
10
5
µA
µA
µA
IL
0V<VIN<0.95V; Other pins not under test = 0V
Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable
IOZ
DQ, DQS, DQS#
-5
-6
5
6
µA
µA
IVREF
VREF leakage current; VREF = Valid VREF level
DC OPERATING CONDITIONS
All voltages referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
Max.
1.9
Units
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
1.8
0.50 x VCC
VREF
V
V
V
V
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.51 x VCC
VREF+0.04
3.6
VTT
VCCSPD
-
1.
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2.
3.
V
V
TT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
CCQ of all IC's are tied to VCC
.
June 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
Min
7
Max
10
10
10
7
Units
pF
Input Capacitance (A0~A12, BA0~BA1, RAS#, CAS#, WE#)
Input Capacitance CKE0, ODT0
CIN1
CIN2
7
pF
Input Capacitance CS0#
CIN3
7
pF
Input Capacitance (CK, CK#)
CIN4
6
pF
CIN5 (665)
CIN5 (534)
6.5
6.5
6.5
6.5
7.5
8
pF
Input Capacitance (DM0 ~ DM3, DM8), (DQS0 ~ DQS3, DQS8)
Input Capacitance (DQ0 ~ DQ31) (CB0 ~ CB7)
pF
COUT1 (665)
7.5
8
pF
C
OUT1 (534)
pF
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
0° to 85°
Units
°C
Notes
Operating temperature (Commercial)
TOPER
1, 2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.300
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
Input Low (Logic 1) Voltage DDR2-667
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
Input Low (Logic 0) Voltage DDR2-667
VREF + 0.250
-
V
V
V
V
VREF + 0.200
-
-
-
VREF - 0.250
VREF - 0.200
June 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATION AND CONDITIONS
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge;
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
665
534
403
Units
t
660
630
615
mA
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as ICC4W
720
690
675
mA
ICC2P** Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
330
390
405
330
375
390
324
360
375
mA
mA
mA
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
405
360
390
360
330
360
mA
mA
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
480
990
990
450
885
885
450
780
780
mA
mA
mA
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
=
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,110
18
1,050
18
990
18
mA
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs Normal
are FLOATING; Data bus inputs are FLOATING
ICC6**
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
1,725
1,470
1,245
mA
ICC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
June 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
PARAMETER
665
534
403
SYMBOL
tCK (5)
tCK (4)
tCK (3)
tCH
MIN
3,000
3,750
5,000
0.45
MAX
8,000
8,000
8,000
0.55
MIN
MAX
MIN
MAX
UNIT
ps
CL = 5
CL = 4
CL = 3
Clock Cycle Time
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
ps
CK high-level width
CK low-level width
tCK
tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
MIN (tCH
,
MIN (tCH
,
MIN (tCH,
tCL)
Half clock period
tHP
ps
tCL)
tCL)
Clock jitter
tJIT
tAC
-125
-450
125
-125
-500
125
-125
-600
125
ps
ps
ps
ps
ps
ps
tCK
ps
DQ output access time from CK/CK#
+450
+500
+600
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
tHZ
tAC MAX
tAC MAX
tAC MAX
tAC MAX
tAC MAX
tAC MAX
tLZ
tAC MIN
100
tAC MIN
100
tAC MIN
150
tDS
tDH
175
225
275
tDIPW
tQHS
0.35
0.35
0.35
340
400
450
DQ…DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
-400
+400
240
-450
+450
300
-500
+500
350
0.2
0.2
0.2
tCK
tCK
tDSH
0.2
0.2
0.2
DQS…DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
ps
DQS read preamble
tRPRE
tRPST
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
0.9
0.4
0
1.1
0.6
tCK
tCK
ps
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
DQS write postamble
0.6
0.6
0.6
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
Write command to first DQS latching transition
tDQSS
tCK
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
tIPW
tIS
0.6
200
275
2
0.6
250
375
2
0.6
350
475
2
tCK
ps
ps
tCK
tIH
Address and control input hold time
tCCD
Note:
AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
Continued on next page
June 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
665
534
403
PARAMETER
SYMBOL
tRC
MIN
55
MAX
MIN
55
MAX
MIN
55
MAX
UNIT
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
tRRD
tRCD
tFAW
tRAS
10
10
10
ns
15
15
15
ns
50
50
50
ns
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
45
70,000
45
70,000
40
70,000
ns
tRTP
7.5
7.5
7.5
ns
tWR
15
15
15
ns
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWR + tRP
7.5
tWR + tRP
7.5
tWR + tRP
10
ns
tWTR
tRP
ns
15
15
15
ns
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRPA
tRP+ CK
t
tRP+ CK
t
tRP+ CK
t
ns
tMRD
tDELAY
2
2
2
tCK
ns
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
REFRESH to Active of Refresh to Refresh command
interfal
tRFC
105
70,000
7.8
105
70,000
7.8
105
70,000
7.8
ns
Average periodic refresh interval
t
REFI
µs
ns
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
Exit self refresh to non-READ command
tXSNR
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
200
tIS
200
tIS
200
tIS
tCK
ps
2
2
2
2
2
2
tCK
tAC (MAX)
+ 700
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
ODT turn-on
tAON
tAC (MIN)
tAC (MIN)
tAC (MIN)
ps
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
tAC (MAX)
+ 600
tAC (MAX)
+ 600
tAC (MAX)
+ 600
tAC (MIN)
tAC (MIN)
tAC (MIN)
2 x tCK
+
2 x tCK
+
2 x tCK +
tAC (MIN)
+ 2000
t
AC (MIN)
+ 2000
t
AC (MIN)
+ 2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
ps
ps
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tXP
7 - AL
6 - AL
6 - AL
tCK
tCK
tCK
A Exit precharge power-down to any non-READ
command.
2
3
2
3
2
3
CKE minimum high/low time
tCKE
Note:
AC specification is based on ELPIDA components. Other DRAM manufactures specification may be different.
June 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR PD4
Clock/Data Rate
Frequency
Part Number
CAS Latency tRCD tRP
Height**
WV3HG32M40SEU665PD4xxG*
WV3HG32M40SEU534PD4xxG
WV3HG32M40SEU403PD4xxG
* Consult Factory for availability
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
5
4
3
5
4
3
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung, Elpida & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR PD4
FRONT VIEW
3.302 (0.130)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161)
3.90(0.154)
(2X)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
June 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 32M 40 S E U xxx PD4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x16
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
(P = JEDEC proposed pin-out)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(E = Elpida)
G = RoHS COMPLIANT
June 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG32M40SEU-PD4
White Electronic Designs
ADVANCED
Document Title
128MB – 32Mx40 DDR2 SDRAM UNBUFFERED
DRAM DIE OPTIONS:
• ELPIDA: F-Die
Rev #
Rev 0
History
Release Date Status
Created
6-06
Concept
Concept
Rev 1
1.0 Update to x40 depth
6-8-06
1.1 Added CB4, CB5, CB6, and CB7
1.2 Indicated SPD supply voltage
1.3 Change part number to indicated x40 (8 ECC bits)
Rev 2
2.0 Moved from concept to advanced
6-9-06
Advanced
June 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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