WV3HG64M64EEU403D4ISG [WEDC]
512MB - 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM; 512MB - 64Mx64 DDR2 SDRAM缓冲， SO -DIMM
| 型号： | WV3HG64M64EEU403D4ISG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 512MB - 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| 文件： | 总11页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED*
512MB – 64Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
Unbuffered 200-pin, Small-Outline DIMM (SO-
The WV3HG64M64EEU is a 64Mx64 Double Data Rate 2
SDRAM memory module based on 512Mb DDR2 SDRAM
components. The module consists of eight 64Mx8, in
FBGA package mounted on a 200 pin SO-DIMM FR4
substrate.
DIMM)
Fast data transfer rates: PC2-5300*, PC2-4200 and
PC2-3200
Utilizes 667*, 533 and 400 MT/s DDR2 SDRAM
components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
V
V
CC = 1.8V 0.1V
CCSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, and 5*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
RoHS Compliant
JEDEC Package option
• 200 Pin (SO-DIMM)
• PCB – 30.00mm (1.181") TYP.
OPERATING FREQUENCIES
PC2-5300*
333MHz
5-5-5
PC2-4200
266MHz
4-4-4
PC2-3200
200MHz
3-3-3
Clock Speed
CL-tRCD-tRP
Note:
•
Consult factory for availability
May 2006
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
SYMBOL
A0-A13
ODT0
CK0, CK0#
CK1, CK1#
CKE0
DESCRIPTION
Address input
1
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQS2
DM2
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A1
A0
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
VSS
VREF
2
VSS
On-Die Termination
Differential Clock Inputs
Differential Clock inputs
Clock Enable input
Chip select
3
VSS
VCC
4
DQ4
DQ0
DQ5
DQ1
VSS
VSS
VCC
5
DQ18
DQ22
DQ19
DQ23
VSS
A10/AP
BA1
BA0
RAS#
WE#
CS0#
VCC
6
VSS
CS0#
7
DQ48
DQ52
DQ49
DQ53
VSS
8
RAS#, CAS#, WE# Command Inputs
9
VSS
BA0, BA1
DM0-DM7
DQ0-DQ63
DQS0-DQS7
DQS0#-DQS7#
Bank Address Inputs
Input Data Mask
Data Input/Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DM0
DQS0#
VSS
VSS
DQ24
DQ28
DQ25
DQ29
VSS
VSS
VCC
DQS0
DQ6
VSS
DQ7
DQ2
VSS
DQ3
DQ12
VSS
DQ13
DQ8
VSS
CAS#
ODT0
NC
A13
VCC
NC
Data Strobe
CK1
SCL
Serial Clock for Presence Detect
Presence Detect Address Inputs
Serial Presence Detect Data
Power Supply
Reference voltage
Ground
VSS
SA0-SA1
SDA
VCC
VREF
VSS
VSS
CK1#
DQS6#
VSS
DM3
DQS3#
NC
VCC
NC
DQS6
DM6
VSS
DQS3
VSS
VSS
NC
VSS
VCCSPD
NC
Serial EEPROM Power Supply
No Connect
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
DQ32
DQ36
DQ33
DQ37
VSS
DQ50
DQ54
DQ51
DQ55
VSS
DQ9
DM1
VSS
VSS
VSS
VSS
VSS
DQS1#
CK0
DQS1
CK0#
VSS
CKE0
NC
DQS4#
DM4
DQS4
VSS
DQ56
DQ60
DQ57
DQ61
VSS
VCC
VCC
NC
VSS
VSS
NC
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
NC
DM7
DQS7#
VSS
NC
VCC
DQS7
DQ58
VSS
DQ59
DQ62
VSS
VCC
A12
A11
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
A9
VSS
A7
DQ16
DQ20
DQ17
DQ21
VSS
A8
A6
DQ63
SDA
VSS
VSS
VCC
DQS5#
DM5
DQS5
VSS
VCC
A5
SCL
VSS
DQS2#
NC
A4
SA0
A3
VCCSPD
A2
VSS
SA1
May 2006
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
3
CS0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DM CS#DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1#
DQS1
DM1
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2#
DQS2
DM2
DQS6#
DQS6
DM6
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7#
DQS7
DM7
DQS3#
DQS3
DM3
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
100
100
3
SCL
Serial PD
WP A0 A1 A2
SDA
BA0-BA1
A0-A13
RAS#
CAS#
WE#
BA0-BA1: DDR2 SDRAMs
A0-A13: DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
CK0
CK0#
SA0 SA1
RAS#:
CAS#:
WE#:
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
V
CCSPD
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
CKE0
ODT0
CKE0:
CK1
CK1#
VCC
DDR2 SDRAMs
ODT0:
V
REF
DDR2 SDRAMs
DDR2 SDRAMs
NOTE: All resistor value, are 22 ohms 5ꢀ unless otherwise specified.
V
SS
May 2006
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
2.3
100
80
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
˚C
IL
Input leakage current; Any input 0V<VIN<VCC
0V<VIN<0.95V; Other pins not under test = 0V
;
VREF iput
Command/Address,
RAS#, CAS#, WE#
-80
uA
CS#, CKE
CK, CK#
-40
-20
-5
40
20
5
uA
uA
uA
uA
DM
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are
disable
DQ, DQS, DQS#
-5
5
IVREF
VREF leakage current; VREF = Valid VREF level
-16
16
uA
DC OPERATING CONDITIONS
All voltages referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
1.8
Max.
1.9
Units
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
Notes:
V
V
V
VREF
VTT
0.49 x VCC
VREF-0.04
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
1
2
1.
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1percent of the DC
value. Peak-to-peak AC noise on VREF may not excedd +/-2 persent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2.
VTT in sot applied directly to the device. VTT is a system supply for signal terminaion resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
May 2006
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
Min
12
Max
20
20
20
12
7.5
8
Units
pF
Input Capacitance (A0~A13, BA0~BA1, RAS#, CAS#, WE#)
Input Capacitance CKE0, ODT
CIN1
CIN2
12
pF
Input Capacitance CS0#
CIN3
12
pF
Input Capacitance (CK0, CK0#, CK1, CK1#)
Input Capacitance (DM0 ~ DM7), (DQS0 ~ DQS7)
CIN4
8
pF
CIN5 (667)
CIN5 (533)
COUT1 (667)
6.5
6.5
6.5
6.5
pF
pF
Input Capacitance (DQ0 ~ DQ63)
7.5
8
pF
C
OUT1 (533)
pF
Notes:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
OPERATING TEMPERATURE CONDITION
Parameter
Operating temperature
Notes:
Symbol
Rating
0° to 85°
Units
°C
Notes
TOPER
1, 2
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measuremnet conditions, please refer to JEDED JESD51.2
2. At 0°C - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.125
-0.300
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIH(DC)
VIL(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage DDR2-400 & DDR2-533
Input Low (Logic 1) Voltage DDR2-667
Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
Input Low (Logic 0) Voltage DDR2-667
VREF + 0.250
-
V
V
V
V
VREF + 0.200
-
-
-
VREF - 0.250
VREF - 0.200
May 2006
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
ICC SPECIFICATION
Symbol Proposed Conditions
ICC0* Operating one bank active-precharge;
665
534
403
Units
t
CK = tCK(ICC), tRC = tRC(ICC), tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between valid commands;
680
640
640
mA
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
ICC1*
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRAS min(ICC); CKE is
HIGH, CS# is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is
same as ICC4W
800
760
720
mA
ICC2P** Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
64
64
64
mA
mA
mA
ICC2Q** Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputsare
STABLE; Data bus inputs are FLOATING
280
320
240
280
240
280
ICC2N** Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING
ICC3P** Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
240
96
280
96
240
96
mA
mA
Slow PDN Exit MRS(12) = 1
ICC3N** Active standby current;
All banks open; tCK = tCK(ICC), tRC = tRC(ICC, tRAS = tRAS min(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
440
1120
1160
400
960
400
880
880
mA
mA
mA
ICC4W* Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC),
tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
ICC4R* Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
1000
tRASmax(ICC), tRP = tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
ICC5**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1200
64
1120
64
1120
64
mA
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs Normal
vre FLOATING; Data bus inputs are FLOATING
ICC6**
ICC7*
Operating bank interleave read current;
All bank interleaVINg reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data bus inputs are SWITCHING.
1760
1760
1760
mA
ICC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Note:
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
May 2006
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
665
534
403
PARAMETER
SYMBOL
tCK (5)
tCK (4)
tCK (3)
tCH
MIN
3,000
3,750
5,000
0.45
MAX
8,000
8,000
8,000
0.55
MIN
MAX
MIN
MAX
UNIT
ps
ps
ps
tCK
tCK
CL = 5
CL = 4
CL = 3
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
CK high-level width
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
MIN (tCH
,
MIN (tCH
,
MIN (tCH,
tCL)
Half clock period
tHP
ps
tCL
)
tCL
)
Clock jitter
DQ output access time from CK/CK#
tJIT
tAC
tHZ
tLZ
tDS
tDH
tDIPW
tQHS
250
250
250
ps
ps
ps
ps
ps
ps
tCK
ps
-450
+450
tAC MAX
tAC MAX
-500
+500
tAC MAX
tAC MAX
-600
+600
tAC MAX
tAC MAX
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input pulse width (for each input)
Data hold skew factor
tAC MIN
100
225
tAC MIN
100
225
tAC MIN
150
275
0.35
0.35
0.35
340
400
450
DQ…DQS hold, DQS to first DQ to go nonvalid, per
access
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
DQS input high pulse width
DQS input low pulse width
DQS output access time from CK/CK#
DQS falling edge to CK rising … setup time
DQS falling edge from CK rising … hold time
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35
0.35
-400
0.2
tQH - tDQSQ
0.35
0.35
-450
0.2
tQH - tDQSQ
0.35
0.35
-500
0.2
ns
tCK
tCK
ps
tCK
tCK
+400
240
+450
300
+500
350
tDSH
0.2
0.2
0.2
DQS…DQ skew, DQS to last DQ valid, per group,
tDQSQ
ps
per access
DQS read preamble
tRPRE
tRPST
tWPRES
tWPRE
tWPST
0.9
0.4
0
0.35
0.4
1.1
0.6
0.9
0.4
0
0.35
0.4
1.1
0.6
0.9
0.4
0
0.35
0.4
1.1
0.6
tCK
tCK
p s
tCK
tCK
DQS read postamble
DQS write preamble setup time
DQS write preamble
DQS write postamble
0.6
0.6
0.6
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
Write command to first DQS latching transition
tDQSS
tCK
Address and control input pulse width for each input
Address and control input setup time
Address and control input hold time
tIPW
tIS
tIH
0.6
200
275
2
0.6
250
375
2
0.6
350
475
2
tCK
ps
ps
tCK
Address and control input hold time
tCCD
Note:
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
May 2006
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (cont'd)
AC CHARACTERISTICS
665
534
403
PARAMETER
SYMBOL
tRC
tRRD
tRCD
tFAW
tRAS
MIN
55
7.5
15
37.5
45
MAX
MIN
60
7.5
15
37.5
45
MAX
MIN
65
7.5
15
37.5
45
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
37.5
70,000
37.5
70,000
37.5
70,000
tRTP
tWR
7.5
15
7.5
15
7.5
15
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
tDAL
tWTR
tRP
tWR + tRP
7.5
15
tWR + tRP
7.5
15
tWR + tRP
10
15
ns
ns
ns
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK,CK# uncertainty
tRPA
tMRD
tDELAY
tRP+ CK
2
t
tRP+ CK
2
t
tRP+ CK
2
t
ns
tCK
ns
tIS + tCK
tIS + tCK
tIS + tCK
+ tIH
+ tIH
+ tIH
REFRESH to Active of Refresh to Refresh command
interfal
tRFC
105
70,000
7.8
105
70,000
7.8
105
70,000
7.8
ns
Average periodic refresh interval
t
REFI
µs
ns
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
Exit self refresh to non-READ command
tXSNR
Exit self refresh to READ command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
tAOND
200
tIS
2
200
tIS
2
200
tIS
2
tCK
ps
tCK
2
2
2
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
tAC (MAX)
+ 1000
ODT turn-on
tAON
tAC (MIN)
tAC (MIN)
tAC (MIN)
ps
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ps
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
tAC (MIN)
tAC (MIN)
+ 600
+ 600
+ 600
2 x tCK
+
2 x tCK
+
2 x tCK +
tAC (MIN)
+ 2000
t
AC (MIN)
+ 2000
t
AC (MIN)
+ 2000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
tAC (MAX)
tAC (MAX)
tAC (MAX)
ps
ps
+ 1000
+ 1000
+ 1000
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
2.5 x
tCK + tAC
(MAX) +
1000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAC (MIN)
+ 2000
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
tXARD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
Exit active power-down to READ command,
MR[bit12=0]
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
tXP
7 - AL
6 - AL
6 - AL
tCK
tCK
tCK
A Exit precharge power-down to any non-READ
2
3
2
3
2
3
command.
CKE minimum high/low time
tCKE
Note:
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
May 2006
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D4
Clock/Data Rate
Frequency
Part Number
CAS Latency tRCD tRP
Height**
WV3HG64M64EEU665D4xxG*
WV3HG64M64EEU534D4xxG
WV3HG64M64EEU403D4xxG
* Consult Factory for availability
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
5
4
3
5
4
3
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
NOTES:
• RoHS product. ("G" = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
FRONT VIEW
3.80 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
4.10(0.161)
3.90(0.154)
(2X)
30.15 (1.187)
29.85 (1.175)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.00 (0.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
PIN 1
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
63.60 (2.504)
TYP
BACK VIEW
4.2 (0.165)
TYP
PIN 200
PIN 2
47.40 (1.866)
TYP
11.40 (0.449)
TYP
** ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2006
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 64M 64 E E U xxx D4 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x8
1.8V
UNBUFFERED
SPEED (Mb/s)
PACKAGE 200 PIN
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
May 2006
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG64M64EEU-D4
White Electronic Designs
ADVANCED
Document Title
512MB – 64Mx64 DDR2 SDRAM UNBUFFERED
DRAM DIE OPTIONS:
• SAMSUNG: C-Die, will move to E-Die Q2'06
• MICRON: U37Y: B-Die
Revision History
Rev #
Rev 0
History
Created
Release Date Status
January 2006
Advanced
Rev 1
1.0 Updated VCC spec
Feburary 2006
Advanced
Rev 2
2.1 Updated AC specs
May 2006
Advanced
2.2 Updated ordering information
2.3 Added industrial temp option on part numbering guide
2.4 Added die rev info
May 2006
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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