WCSN0436V1P [WEIDA]
128Kx36 Pipelined SRAM with NoBL TM Architecture; 128Kx36流水线SRAM与NOBL TM架构
| 型号： | WCSN0436V1P |
| 厂家： | 
WEIDA SEMICONDUCTOR, INC. |
| 描述： | 128Kx36 Pipelined SRAM with NoBL TM Architecture |
| 文件： | 总14页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Y7C1350B
WCSN0436V1P
128Kx36 Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
• Pin compatible and functionally equivalent to ZBT™
devices IDT71V546, MT55L128L36P, and MCM63Z736
• Supports 166-MHz bus operations with zero wait states
— Data is transferred on every clock
The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipe-
lined Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The WCSN0436V1P is equipped with the ad-
vanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.The WCSN0436V1P is
pin/functionally compatible to ZBT SRAMsIDT71V546,
MT55L128L36P, and MCM63Z736.
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
Write operations are controlled by the four Byte Write Select
(BWS[3:0]) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
— 7.0 ns (for 80-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable
• JEDEC-standard 100 TQFP package
• Burst Capability—linear or interleaved burst order
• Low standby power (17.325 mW max.)
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
36
D
CLK
Data-In REG.
CE
Q
36
ADV/LD
17
A
[16:0]
CEN
CE
CONTROL
and WRITE
LOGIC
36
128Kx36
1
CE
MEMORY
2
DQ
[31:0]
[3:0]
CE
ARRAY
17
3
36
DP
WE
BWS
[3:0]
MODE
OE
.
Selection Guide
-166
3.5
400
5
-150
-143
4.0
350
5
-133
4.2
300
5
-100
-80
7.0
200
5
Maximum Access Time (ns)
3.8
375
5
5.0
250
5
Maximum Operating Current (mA)
Commercial
Commercial
Maximum CMOS Standby Current (mA)
.
.
Document#: 38-05246
Revised Jan 06,2002
WCSN0436V1P
Pin Configuration
100-Pin TQFP
1
DP
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DP
1
2
2
DQ
DQ
DQ
V
16
15
14
3
DQ
17
4
V
DDQ
DDQ
SS
5
V
SS
V
6
DQ
DQ
DQ
DQ
DQ
V
18
13
12
11
10
7
DQ
19
8
DQ
20
9
DQ
21
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
DQ
DQ
DQ
22
9
WCSN0436V1P
DQ
23
8
V
DDQ
V
V
V
SS
V
DD
DD
V
DD
DD
V
V
SS
SS
DQ
DQ
DQ
V
24
7
DQ
25
6
V
DDQ
DDQ
SS
V
V
SS
DQ
DQ
DQ
DQ
DQ
V
26
5
4
3
2
DQ
27
DQ
28
DQ
29
V
SS
SS
V
V
DDQ
DDQ
DQ
DQ
DQ
DP
30
1
0
DQ
31
DP
3
0
Document #: 38-05246 Rev. **
Page 2 of 14
WCSN0436V1P
Pin Definitions
Pin Number
Name
A[16:0]
I/O
Description
50–44,
81–82, 99,
100, 32–37
Input-
Synchronous
Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.
96–93
BWS[3:0] Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1
controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls
DQ[31:24] and DP3. See Write Cycle Description table for details.
88
85
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.
89
98
97
92
86
CLK
CE1
CE2
CE3
OE
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2, and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the
Asynchronous device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as inputdatapins. OEis masked duringthedataportion of awrite sequence, during
the first clock when emerging from a deselected state, when the device has been
deselected.
87
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
29–28,
25–22,
19–18,
13–12, 9–6,
3–2, 79–78,
75–72,
69–68, 63–62
59–56, 53–52
DQ[31:0] I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A[16:0] during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ[31:0] are placed in a three-state condition. The outputs are automatically
three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.
30, 1, 80 51
31
DP[3:0]
MODE
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by
BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3.
Input Strap pin Mode Input. Selects the burst order of the device. Tied HIGH selects the inter-
leaved burst order. Pulled LOW selects the linear burst order. MODE should not
change states during operation. When left floating MODE will default HIGH, to an
interleaved burst order.
15, 16, 41, 65, VDD
66, 91
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
4, 11, 14, 20, VDDQ
27, 54, 61, 70,
77
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Document #: 38-05246 Rev. **
Page 3 of 14
WCSN0436V1P
Pin Definitions (continued)
Pin Number
Name
I/O
Ground
Description
5, 10, 17, 21, VSS
26, 40, 55, 60,
64, 67, 71, 76,
90
Ground for the device. Should be connected to ground of the system.
83, 84
NC
-
-
No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will
be used for 256K and 512K depths respectively.
38, 39, 42, 43 DNU
Do Not Use pins. These pins should be left floating or tied to VSS.
Burst Read Accesses
Introduction
The WCSN036V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Functional Overview
The WCSN0436V1P is a synchronous-pipelined Burst SRAM
designed specifically to eliminate wait states during
Write/Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.5 ns (166-MHz de-
vice).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS[3:0] can be used to con-
duct byte write operations.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to A0−A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ[31:0] and
DP[3:0]. In addition, the address for the subsequent access
(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.
On the next clock rise the data presented to DQ[31:0] and
DP[3:0] (or a subset for byte write operations, see Write Cycle
Description table for details) inputs is latched into the device
and the write is complete.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
The data written during the Write operation is controlled by
BWS[3:0] signals. The WCSN0436V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS[3:0]) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.
LOW. The address presented to the address inputs (A0−A16
)
is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.
Because the WCSN0436V1P is a common I/O device, data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[31:0]
Document #: 38-05246 Rev. **
Page 4 of 14
WCSN0436V1P
and DP[3:0] are automatically three-stated during the data por-
tion of a write cycle, regardless of the state of OE.
Linear Burst Sequence
Burst Write Accesses
First
Address
Second
Address
Third
Address
Fourth
Address
The WCSN0436V1p has an on-chip burst counter that allows
the user the ability to supply a single address and conduct up
to four WRITE operations without reasserting the address in-
puts. ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the chip enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BWS[3:0] inputs must be driven in each cycle of the burst write
in order to write the correct bytes of data.
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
Ax+1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
[
]
Cycle Description Truth Table 1, 2, 3, 4, 5, 6
Address
Used
ADV/
LD/
Operation
CE
CEN
WE
BWSx
CLK
Comments
Deselected
External
1
0
L
X
X
L-H
I/Os three-state following next rec-
ognized clock.
Suspend
-
X
1
X
X
X
L-H
Clock ignored, all operations sus-
pended.
Begin Read
Begin Write
External
External
0
0
0
0
0
0
1
0
X
L-H
L-H
Address latched.
Valid
Address latched, data presented
two valid clocks later.
Burst Read
Operation
Internal
X
0
1
X
X
L-H
Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.
Burst Write
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS[3:0]
.
Notes:
1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWS = 0 signifies at least one Byte Write Select is active, BWS
=
x
x
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWS
3. The DQ and DP pins are controlled by the current cycle and the OE signal.
4. CEN=1 inserts wait states.
5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
6. OE assumed LOW.
. See Write Cycle Description table for details.
[3:0]
Document #: 38-05246 Rev. **
Page 5 of 14
WCSN0436V1P
Write Cycle Description[7, 8]
Function
WE
1
BWS3
BWS2
BWS1
BWS0
Read
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Write − No bytes written
Write Byte 0 − (DQ[7:0] and DP0)
Write Byte 1 − (DQ[15:8] and DP1)
Write Bytes 1, 0
0
0
0
0
Write Byte 2 − (DQ[23:16] and DP2)
Write Bytes 2, 0
0
0
Write Bytes 2, 1
0
Write Bytes 2, 1, 0
0
Write Byte 3 − (DQ[31:24] and DP3)
Write Bytes 3, 0
0
0
Write Bytes 3, 1
0
Write Bytes 3, 1, 0
0
Write Bytes 3, 2
0
Write Bytes 3, 2, 0
0
Write Bytes 3, 2, 1
0
Write All Bytes
0
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current.................................................... >200 mA
Storage Temperature..................................−65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Ambient
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
Com’l
Ind’l
Temperature[10]
0°C to +70°C
VDD/VDDQ
DC Voltage Applied to Outputs
in High Z State[9] .....................................−0.5V to VDDQ + 0.5V
3.3V ± 5%
DC Input Voltage[9]..................................−0.5V to VDDQ + 0.5V
–40°C to +85°C
Notes:
7. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW.
8. Write is initiated by the combination of WE and BWSx. Bytes written are determined by BWS[3:0]. Bytes not selected during byte writes remain unaltered. All
I/Os are three-stated during byte writes.
9. Minimum voltage equals –2.0V for pulse duration less than 20 ns.
10. TA is the case temperature.
Document #: 38-05246 Rev. **
Page 6 of 14
WCSN0436V1P
Electrical Characteristics Over the Operating Range
Parame-
ter
Description
Test Conditions
Min.
3.135
3.135
2.4
Max.
3.465
3.465
Unit
V
VDD
Power Supply Voltage
VDDQ
VOH
VOL
VIH
VIL
I/O Supply Voltage
V
Output HIGH Voltage VDD = Min., IOH = –4.0 mA[11]
Output LOW Voltage VDD = Min., IOL = 8.0 mA[11]
Input HIGH Voltage
V
0.4
V
2.0
−0.3
−5
V
DD + 0.3V
V
Input LOW Voltage[9]
0.8
5
V
IX
Input Load Current
GND ≤ VI ≤ VDDQ
µA
µA
Input Current of
MODE
−30
30
IOZ
ICC
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
µA
VDD Operating
Supply
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
5.0-ns cycle, 166 MHz
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
All speed grades
400
375
350
300
250
200
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Automatic CE
Power-Down
Current—TTL Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
70
60
50
40
35
ISB2
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected,
IN ≤ 0.3V or VIN
VDDQ – 0.3V, f = 0
5
V
>
ISB3
Automatic CE
Power-Down
Current—CMOS
Inputs
Max. VDD, Device Deselected, or 5.0-ns cycle, 166 MHz
70
60
50
40
30
25
mA
mA
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
6.6-ns cycle, 150 MHz
7.0-ns cycle, 143 MHz
7.5-ns cycle, 133 MHz
10.0-ns cycle, 100 MHz
12.5-ns cycle, 80 MHz
f = fMAX = 1/tCYC
Note:
11. The load used for VOH and VOL testing is shown in Figure (b) of the AC Test Loads.
Document #: 38-05246 Rev. **
Page 7 of 14
WCSN0436V1P
Capacitance[12]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
4
4
4
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
R=317Ω
3.3V
OUTPUT
[13]
OUTPUT
ALL INPUT PULSES
Z =50Ω
0
3.0V
R =50Ω
L
5 pF
R=351Ω
GND
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
1350B-2
(a)
(b)
Thermal Resistance
Description
Test Conditions
Symbol
TQFP Typ.
Units
Notes
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
ΘJA
28
°C/W
12
Thermal Resistance
(Junction to Case)
ΘJC
4
°C/W
12
Notes:
12. Tested initially and after any design or process change that may affect these parameters.
13. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in
part (a) of AC Test Loads.
Document #: 38-05246 Rev. **
Page 8 of 14
WCSN0436V1P
Switching Characteristics Over the Operating Range[13, 14, 15]
-166
-150
-143
-133
-100
-80
Parameter
tCYC
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.4
1.4
1.5
6.6
2.5
2.5
1.5
7.0
2.8
2.8
2.0
7.5
3.0
3.0
2.0
10
4.0
4.0
2.2
12.5
4.0
4.0
2.5
ns
ns
ns
ns
tCH
Clock HIGH
Clock LOW
tCL
tAS
Address Set-Up Before CLK
Rise
tAH
tCO
Address Hold After CLK Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
ns
Data Output Valid After CLK
Rise
3.5
3.8
4.0
4.2
5.0
7.0
tDOH
Data Output Hold After CLK
Rise
1.5
1.5
1.5
1.5
1.5
ns
tCENS
tCENH
tWES
CEN Set-Up Before CLK Rise 1.5
1.5
0.5
1.5
2.0
0.5
2.0
2.0
0.5
2.0
2.2
0.5
2.2
2.5
1.0
2.5
ns
ns
ns
CEN Hold After CLK Rise
0.5
1.5
GW, BWS[3:0] Set-Up Before
CLK Rise
tWEH
tALS
GW, BWS[3:0] Hold After CLK 0.5
Rise
0.5
1.5
0.5
2.0
0.5
2.0
0.5
2.2
1.0
2.5
ns
ns
ADV/LD Set-Up Before CLK
Rise
1.5
tALH
tDS
ADV/LD Hold after CLK Rise
0.5
0.5
1.5
0.5
1.7
0.5
1.7
0.5
2.0
1.0
2.5
ns
ns
Data Input Set-Up Before CLK 1.5
Rise
tDH
Data Input Hold After CLK Rise 0.5
0.5
1.5
0.5
2.0
0.5
2.0
0.5
2.2
1.0
2.5
ns
ns
tCES
Chip Enable Set-Up Before
CLK Rise
1.5
tCEH
Chip Enable Hold After CLK
Rise
0.5
0.5
0.5
0.5
0.5
1.0
ns
tCHZ
tCLZ
Clock to High-Z[12, 14, 15, 16]
Clock to Low-Z[12, 14, 15, 16]
1.5 3.2 1.5 3.2 1.5 3.5 1.5 3.5 1.5 3.5 1.5 5.0
ns
ns
ns
1.5
1.5
0
1.5
0
1.5
0
1.5
0
1.5
0
tEOHZ
OE HIGH to Output High-Z[12,
3.0
3.0
4.0
4.2
5.0
7.0
14, 15, 16]
tEOLZ
OE LOW to Output Low-Z[12,
0.0
ns
ns
14, 15, 16]
tEOV
OE LOW to Output Valid[14]
3.2
3.5
4.0
4.2
5.0
7.0
Notes:
14.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
Document #: 38-05246 Rev. **
Page 9 of 14
WCSN0436V1P
Switching Waveforms
READ/WRITE/DESELECT Sequence
CLK
CEN
tCENH
tCENS
tCL
tCH
tCYC
tAH
tAS
CEN HIGH blocks
all synchronous inputs
WA2
WA5
RA1
RA3
RA4
RA6
ADDRESS
RA7
WE &
BWS[3:0]
tWS
tWH
tCEH
tCES
CE
tDH
tDS
tCHZ
tCHZ
tDOH
tCLZ
tDOH
Q1
Out
D2
In
Data-
In/Out
Q4
Out
D5
In
Q3
Out
Q6
Out
Q7
Out
Device
originally
tCO
deselected
The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.
OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05246 Rev. **
Page 10 of 14
WCSN0436V1P
Switching Waveforms (continued)
Burst Sequences
CLK
tCYC
tALH
tALS
ADV/LD
tCL
tCH
tAH
tAS
RA1
WA2
ADDRESS
WE
RA3
tWS
tWH
tWS
tWH
BWS[3:0]
tCES
tCEH
CE
tCLZ
tCHZ
tDH
tDOH
tCLZ
Q3
Out
Data-
In/Out
Q1
Q1+2
Out
Q1+3
Out
D2
In
D2+2
In
D2+3
In
Q1+1
Out
D2+1
In
Out
Device
originally
deselected
tCO
tCO
tDS
The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).
CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select
the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for
Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held
LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals.
Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW.
= UNDEFINED
= DON’T CARE
Document #: 38-05246 Rev. **
Page 11 of 14
WCSN0436V1P
Switching Waveforms (continued)
OE Timing
OE
tEOV
tEOHZ
Three-state
I/O’s
tEOLZ
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
166
WCSN0436V1P-166AC
WCSN0436V1P-150AC
WCSN0436V1P-143AC
WCSN0436V1P-133AC
WCSN0436V1P-133AI
WCSN0436V1P-100AC
WCSN0436V1P-100AI
A101
A101
A101
A101
A101
A101
A101
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
Industrial
150
143
133
100
Commercial
Industrial
Document #: 38-05246 Rev. **
Page 12 of 14
WCSN0436V1P
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05246 Rev. **
Page 13 of 14
WCSN0436V1P
Document Title: WCSN0436V1P 128K x 36 Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05246
Issue
Date
Orig. of
Change
REV.
**
ECN NO.
109953
113259
Description of Change
01/07/02
02/03/02
SZV
GLC
Change from Spec number: 38-00910 to 38-05045
Change from Spec number: 38-05045 to 38-05246
New
Document #: 38-05246 Rev. **
Page 14 of 14
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