WL2863D33-4/TR [WILLSEMI]
Ultra-Low Noise, High PSRR LDO, 250mA Linear Regulator for RF and Analog Circuits;
| 型号： | WL2863D33-4/TR |
| 厂家： | 
WILLSEMI |
| 描述： | Ultra-Low Noise, High PSRR LDO, 250mA Linear Regulator for RF and Analog Circuits 输出元件 调节器 |
| 文件： | 总10页 (文件大小：823K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WL2863D
WL2863D
Ultra-Low Noise, High PSRR LDO, 250mA Linear
Http://www.sh-willsemi.com
Regulator for RF and Analog Circuits
Descriptions
The WL2863D is a linear regulator capable of supplying
250-mA output current. Designed to meet the requirements
of RF and analog circuits, the WL2863D device provides low
noise, high PSRR, low quiescent current and very good
load /line transients.
The device is designed to work with a 1μF input and 1μF
output ceramic capacitor (no separate noise Operation
bypass capacitor is required).
DFN1X1-4L
VIN
EN
The WL2863D regulators are available in standard
DFN1x1-4L Package. Standard products are Pb-free and
Halogen-free.
3
4
1
EP
Features
2
Input Voltage Range
Output Voltage Range
Output current
PSRR
:2.2V~5.5V
:1.2V~4.3V
:250mA
VOUT GND
:
Typ.100dB at 10mA，f =1KHz
:Typ. 45dB at 10mA , f =1MHz
:Typ. 100mV at 250mA
:Typ. 21μA
Pin Configuration (Top View)
Low Dropout
Quiescent current
Low Output Voltage Noise:Typ. 4.8μVRMS
Output Voltage Tolerance :±2%
G *
Y W
Shutdown Current
:Typ. 0.01μA
:Typ. 1.90V
:1uF
UVLO Threshold(V)
Recommend capacitor
Stable with 1μF Ceramic Input and Output capacitor
No Noise Bypass Capacitor Required
Thermal-Overload Protection
Marking
G : Device Code
* : Voltage Code
Y : Year Code
W: Week Codes
Applications
Cell phones , radiophone, digital cameras
Bluetooth, wireless handsets
Hifi products
Order Information
For detail order information, please see page 8
Others portable electronics device
Will Semiconductor Ltd.
1
Dec, 2018 – Rev 1.2
WL2863D
Typical Application
VIN
1uF
VOUT
VIN
EN
VOUT
1uF
WL2863
ON
OFF
GND
Note : The input and output capacitor must be located a distance of not more than 1 cm
PIN Functions
PIN
1
Symbol
VOUT
GND
Description
Regulated output voltage. 1μF capacitor should be
connected at this input
2
Common ground connection
Chip enable: Applying VEN < 0.4 V disables the regulator,
Pulling VEN > 1.2 V enables the LDO.
Input voltage supply pin , 1μF capacitor should be
connected at this input
3
EN
4
VIN
Expose pad can be tied to ground plane for better power
dissipation
EP
Block Diagram
VOUT
VIN
Current
Limit
VREF
Enable
Control
EN
OTP
GND
Will Semiconductor Ltd.
2
Dec, 2018 – Rev 1.2
WL2863D
Absolute Maximum Ratings
Parameter
Value
Unit
Power Dissipation, PD@TA=25℃
VIN Range
Internally Limited
-0.3～6.0
−0.3 to VIN + 0.3
−0.3 to VIN + 0.3
250
mW
V
VEN Range
V
VOUT Range
V
IOUT
mA
oC
oC
oC
V
Lead Temperature Range
Storage Temperature Range
Operating Junction Temperature Range
260
-55 ~ 150
150
HBM
MM
2000
ESD Ratings
200
V
Recommend Operating Ratings
Parameter
Value
Unit
V
oC
Operating Supply voltage
Operating Temperature Range
Thermal Resistance, RθJA
2.2～5.5
-40～85
250
oC/W
Will Semiconductor Ltd.
3
Dec, 2018 – Rev 1.2
WL2863D
Electronics Characteristics (VIN=VOUT(NOM)+1V, CIN=COUT=1uF, VEN = 1.2 V. Typical values are at Ta =
+25°C ,unless otherwise noted)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Operating Input Voltage
VIN
2.2
5.5
V
VIN = VOUT(NOM) + 1 V
Output Voltage Accuracy
Output Current Limit
VOUT
ILIM
-2
+2
%
IOUT=1mA
VOUT = 90% VOUT(NOM)
VOUT=2.8V(NOM), IOUT=250mA
250
mA
100
98
170
162
150
VOUT=3.0V(NOM), IOUT=250mA
VOUT=3.3V(NOM), IOUT=250mA
Dropout Voltage
mV
92
Line Regulation
Load Regulation
Quiescent Current
Short Current
△VLINE
△VLoad
IQ
VIN=2.2V~5V ,IOUT=1mA
IOUT=1~200mA
IOUT=0mA
0.1
15
mV
mV
μA
21
350
0.01
90
25
ISHORT
ISHDN
VOUT=0V
mA
μA
Shut-down Current
VEN 0.4 V, VIN = 4.8 V
f=100Hz
1.0
f=1KHz
IOUT =10mA
100
60
Power Supply Rejection Rate
PSRR
dB
f=100KHz
f=1MHz
VIN=5.5V, IOUT=1mA
VIN=5.5V, VOUT=0V
VEN = 0 to 5.5V
45
EN logic high voltage
EN logic low voltage
EN Input Current
VENH
VENL
IEN
1.2
V
V
0.4
1
μA
C
OUT = 1μF, From assertion of VEN to
Turn−On Time
1.5
mS
VOUT = 95% VOUT (NOM)
IOUT =1mA
7
Output Voltage Noise
Thermal shutdown threshold
eNO
10Hz to 100KHz,
μVRMS
IOUT =200mA
4.8
150
120
oC
oC
TSDH
TSDL
Temperature rising
Temperature falling
Under voltage lock out
threshold
VUVLO
1.9
V
Active Output Discharge
Resistance
Ω
RLOW
VEN<0.4V
300
VIN = ( VOUT(NOM) + 2 V ) to ( VOUT(NOM)
+ 1 V ) in 30 us, IOUT = 1 mA
−1
mV
mV
Line Transient
Load Transient
TranLINE
VIN = ( VOUT(NOM) + 1 V ) to ( VOUT(NOM)
+ 2 V ) in 30 us, IOUT = 1 mA
+1
IOUT = 1 mA to 200 mA in 10 us
IOUT = 200 mA to 1 mA in 10 us
−10
TranLOAD
+10
Will Semiconductor Ltd.
4
Dec, 2018 – Rev 1.2
WL2863D
Typical characteristics (Ta=25 oC, VIN=3.8V, VOUT = 2.8V CIN=COUT=1uF, unless otherwise noted)
20
18
16
14
12
10
8
800
700
600
500
400
300
200
100
0
T=25OC
6
VIN=3.8V
VOUT=2.8V
CIN=1uF
VOUT=2.8V
IO=0mA
4
COUT=1uF
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
50
100
150
200
250
300
Input Voltage (V)
Output Current (mA)
Quiescent current vs. Supply voltage
Ground Current vs. Load Current
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
WL2863D28
T=25OC
0.8
0.6
0.4
0.2
0.0
VOUT=2.8V
IO=1mA
VIN=3.8V
VIN=4.2V
VIN=5V
IO=100mA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
50
100
150
200
250
300
350
400
Output Current(mA)
Input Voltage (V)
Output voltage vs. Supply voltage
Output voltage vs. Output current
3.0
2.5
2.0
1.5
Short Circuit Event
Overheating
IOUT
WL2863D28
1.0
Thermal
Shutdown
T=85OC
VOUT
VIN=3.8V
VIN=4.2V
VIN=5V
0.5
0.0
VIN=3.8V,
VOUT =2.8V
CIN=COUT=1uF
0
50
100
150
200
250
300
350
400
Output Current (mA)
Output voltage vs. Output current
Short Circuit and Thermal Shutdown
Will Semiconductor Ltd.
5
Dec, 2018 – Rev 1.2
WL2863D
120
100
80
60
40
20
0
140
120
100
80
60
40
WL2863D30
0.98*VOUT
WL2863D28
0.98*VOUT
20
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Current(mA)
Output Current(mA)
Dropout Voltage vs. Output Current
Dropout Voltage vs. Output Current
120
110
100
90
110
100
90
80
80
70
70
60
60
50
WL2863D28 COUT=1uF
VIN=3.8VDC+0.5VPP
WL2863D30 COUT=1uF
VIN=4VDC+0.5VPP
50
40
IO=10mA
IO=20mA
IO=50mA
IO=100mA
IO=150mA
IO=250mA
40
30
20
10
0
IO=10mA
30
20
10
0
IO=20mA
IO=50mA
IO=100mA
IO=150mA
IO=250mA
1
10
100
1000
10000
100000
1000000
1
10
100
1000
10000
100000
1000000
Frequency(Hz)
Frequency(Hz)
PSRR
PSRR
VIN=3.8V,
VOUT =2.8V
IOUT=10mA
VIN=3.8V,
VOUT =2.8V
IOUT=300mA
Soft-Start From EN
Soft-Start From EN
Will Semiconductor Ltd.
6
Dec, 2018 – Rev 1.2
WL2863D
VIN=3.8V,
VOUT =2.8V
IOUT=300mA
VIN=3.8V,
VOUT =2.8V
IOUT=10mA
EN Shutdown
EN Shutdown
tFALL=1 u s
VIN=3.8V,
VOUT =2.8V
IOUT=200~1mA
VIN=3.8V,
VOUT =2.8V
IOUT=1~200mA
tRISE=1 u s
Load Transient Response
Load Transient Response
VIN=3.8~4.8V
VOUT =2.8V
IOUT=1mA
Line Transient Response
Will Semiconductor Ltd.
7
Dec, 2018 – Rev 1.2
WL2863D
ORDER INFORMATION
Vout
(V)
Operating
Ordering No.
WL2863D18-4/TR
WL2863D25-4/TR
WL2863D28-4/TR
WL2863D285-4/TR
WL2863D30-4/TR
WL2863D33-4/TR
Package
Marking
Shipping
Temperature
GH
YW
GK
YW
GL
Tape and Reel,
10000
1.8
2.5
2.8
2.85
3.0
3.3
DFN1x1-4L
DFN1x1-4L
DFN1x1-4L
DFN1x1-4L
DFN1x1-4L
DFN1x1-4L
-40~+85°C
Tape and Reel,
10000
-40~+85°C
-40~+85°C
-40~+85°C
-40~+85°C
-40~+85°C
Tape and Reel,
10000
YW
GV
YW
GM
YW
GN
YW
Tape and Reel,
10000
Tape and Reel,
10000
Tape and Reel,
10000
Marking:
G* = Device Code
Y
= Year
W
= Week
Will Semiconductor Ltd.
8
Dec, 2018 – Rev 1.2
WL2863D
PACKAGE OUTLINE DIMENSIONS
DFN1x1-4L
D
E1
D1
L
TOP VIEW
BOTTOM VIEW
SIDE VIEW
Dimensions in Millimeters
Symbol
Min.
0.34
0.00
Typ.
0.37
Max.
0.40
0.05
A
A1
0.02
A3
0.10 Ref.
0.22
b
0.17
0.17
0.95
0.95
0.43
0.43
0.28
0.33
1.05
1.05
0.53
0.53
L
-
D
1.00
E
1.00
D1
0.48
E1
0.48
e
0.65BSC
0.22Ref.
K
Recommend PCB Layout (Unit: mm)
0 . 5 0
0 . 5 0
0
.
5 0
Notes:
This recommended land pattern is for reference
purposes only. Please consult your manufacturing
group to ensure your PCB design guidelines are met.
0 . 3 1 5
.
2 0
0
.
5 0
0
Will Semiconductor Ltd.
9
Dec, 2018 – Rev 1.2
WL2863D
TAPE AND REEL INFORMATION
Reel Dimensions
Tape Dimensions
P1
Quadrant Assignments For PIN1 Orientation In Tape
Q1 Q2
Q3
Q1 Q2
Q3
Q4
Q4
User Direction of Feed
RD
W
Reel Dimension
7inch
8mm
2mm
Q1
13inch
12mm
16mm
Overall width of the carrier tape
Pitch between successive cavity centers
4mm
Q2
8mm
Q3
P1
Q4
Pin1 Pin1 Quadrant
Will Semiconductor Ltd.
10
Dec, 2018 – Rev 1.2
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