ISD2564 [WINBOND]
SINGLE-CHIP, MULTIPLE-MESSAGES, VOICE RECORD/PLAYBACK DEVICE 32-, 40-, 48-, AND 64-SECOND DURATION; 单芯片，多留言，语音记录/播放设备， 32-， 40- ， 48- ，和64秒的持续时间
| 型号： | ISD2564 |
| 厂家： | 
WINBOND |
| 描述： | SINGLE-CHIP, MULTIPLE-MESSAGES, VOICE RECORD/PLAYBACK DEVICE 32-, 40-, 48-, AND 64-SECOND DURATION |
| 文件： | 总42页 (文件大小：1242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISD2532/40/48/64
SINGLE-CHIP, MULTIPLE-MESSAGES,
VOICE RECORD/PLAYBACK DEVICE
32-, 40-, 48-, AND 64-SECOND DURATION
Publication Release Date: June 2003
Revision 1.0
- 1 -
ISD2532/40/48/64
1. GENERAL DESCRIPTION
Winbond’s ISD2500 ChipCorder® Series provide high-quality, single-chip, Record/Playback solutions
for 32- to 64-second messaging applications. The CMOS devices include an on-chip oscillator,
microphone preamplifier, automatic gain control, antialiasing filter, smoothing filter, speaker amplifier,
and high density multi-level storage array. In addition, the ISD2500 is microcontroller compatible,
allowing complex messaging and addressing to be achieved. Recordings are stored into on-chip
nonvolatile memory cells, providing zero-power message storage. This unique, single-chip solution is
made possible through Winbond’s patented multilevel storage technology. Voice and audio signals
are stored directly into memory in their natural form, providing high-quality, solid-state voice
reproduction.
2. FEATURES
• Single 5 volt power supply
• Single-chip with duration of 32, 40, 48, or 64 seconds.
• Easy-to-use single-chip, voice record/playback solution
• High-quality, natural voice/audio reproduction
• Manual switch or microcontroller compatible
• Playback can be edge- or level-activated
• Directly cascadable for longer durations
• Automatic power-down (push-button mode)
- Standby current 1 µA (typical)
• Zero-power message storage
- Eliminates battery backup circuits
• Fully addressable to handle multiple messages
• 100-year message retention (typical)
• 100,000 record cycles (typical)
• On-chip clock source
• Programmer support for play-only applications
• Available in die form, PDIP, SOIC and TSOP packaging
• Temperature options: die (0°C to +50°C) and package (0°C to +70°C)
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ISD2532/40/48/64
3. BLOCK DIAGRAM
Internal Clock
Timing
XCLK
Sampling Clock
5-Pole Active
Antialiasing Filter
Analog Transceivers
ANA IN
Amp
256K Cell
Nonvolatile
Multilevel Storage
Array
ANA OUT
5-Pole Active
Smoothing Filter
MIC
Pre-
Amp
SP +
MIC REF
Amp
Mux
Automatic
AGC
SP -
Gain Control
(AGC)
Power Conditioning
Device Control
Address Buffers
VCCA VSSA VSSD VCCD
A0 A1 A2 A3 A4 A5 A6 A7 A8
PD OVF
P/R CE EOM
AUX IN
Publication Release Date: June 2003
Revision 1.0
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ISD2532/40/48/64
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 5
6. PIN DESCRIPTION............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION.......................................................................................................... 10
7.1. Detailed Description.................................................................................................................... 10
7.2. Operational Modes ..................................................................................................................... 11
7.2.1. Operational Modes Description............................................................................................ 12
8. TIMING DIAGRAMS.......................................................................................................................... 16
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 19
9.1 Operating Conditions................................................................................................................... 20
10. ELECTRICAL CHARACTERISTICS............................................................................................... 21
10.1. Parameters For Packaged Parts .............................................................................................. 21
10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts ................ 24
10.2. Parameters For Die .................................................................................................................. 25
10.2.1. Typical Parameter Variation with Voltage and Temperature - Die .................................... 28
10.3. Parameters For Push-Button Mode.......................................................................................... 29
11. TYPICAL APPLICATION CIRCUIT................................................................................................. 30
12. PACKAGE DRAWING AND DIMENSIONS.................................................................................... 35
12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 35
12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP)............................................................... 36
12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1................................ 37
12.4. Die Bonding Physical Layout [1] ................................................................................................ 38
14. VERSION HISTORY ....................................................................................................................... 41
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ISD2532/40/48/64
5. PIN CONFIGURATION
A0/M0
A1/M1
A2/M2
A3/M3
1
2
3
4
28
27
26
25
VCCD
P/R
XCLK
EOM
A4/M4
A5/M5
A6/M6
5
6
7
24
23
22
PD
CE
ISD2532
ISD2540
ISD2548
ISD2564
OVF
NC
A7
A8
8
9
21
20
19
ANA OUT
ANA IN
AGC
10
AUX IN
VSSD
11
12
18
17
MIC REF
MIC
VSSA
SP +
13
14
16
15
VCCA
SP-
SOIC/PDIP
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OVF
CE
ANA OUT
ANA IN
AGC
MIC REF
MIC
PD
EOM
5
6
7
XCLK
P/R
ISD2532
ISD2340
ISD2548
ISD2564
VCCA
VCCD
SP-
8
A0/M0
A1/M1
A2/M2
A3/M3
A4M4
A5/M5
A6/M6
SP+
9
VSSA
10
11
12
13
14
VSSD
AUX IN
A8
A7
NC
TSOP
Publication Release Date: June 2003
Revision 1.0
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ISD2532/40/48/64
6. PIN DESCRIPTION
PIN NO.
FUNCTION
PIN NAME
SOIC /
TSOP
PDIP
A0, A1, A2,
A3, A4, A5,
A6, A7, A8
1, 2, 3, 8, 9, 10,
4, 5, 6, 11, 12, 13,
7, 9, 10 14, 16, 17
Address/Mode Inputs: The Address/Mode Inputs have two functions
depending on the level of the two Most Significant Bits (MSB) of the
address pins A7 and A8.
/ M0, M1,
/ 1, 2,
/ 8, 9,
If either or both of the two MSBs are LOW, the inputs are all interpreted
as address bits and are used as the start address for the current record
or playback cycle. The address pins are inputs only and do not output
any internal address information during the operation. Address inputs
M2, M3,
3, 4,
10, 11,
M4, M5, M6
5, 6, 7 12, 13, 14
are latched by the falling edge of CE.
If both MSBs are HIGH, the Address/Mode inputs are interpreted as
Mode bits according to the Operational Mode table on page 12. There
are six operational modes (M0…M6) available as indicated in the table.
It is possible to use multiple operational modes simultaneously.
Operational Modes are sampled on each falling edge of CE, and thus
Operational Modes and direct addressing are mutually exclusive.
NC
AUX IN
8
11
15
18
No Connect.
Auxiliary Input: The Auxiliary Input is multiplexed through to the output
amplifier and speaker output pins when CE is HIGH, P/R is HIGH,
and playback is currently not active or if the device is in playback
overflow. When cascading multiple ISD2500 devices, the AUX IN pin is
used to connect a playback signal from a following device to the
previous output speaker drivers. For noise considerations, it is
suggested that the auxiliary input not be driven when the storage array
is active.
VSSA, VSSD
SP+, SP-
13, 12
14, 15
20, 19
21, 22
Ground: The ISD2500 series of devices utilizes separate analog and
digital ground busses. These pins should be connected separately
through a low-impedance path to power supply ground.
Speaker Outputs: All devices in the ISD2500 series include an on-chip
differential speaker driver, capable of driving 50 mW into 16 Ω from
AUX IN (12.2mW from memory).
[1] The speaker outputs are held at VSSA levels during record and power
down. It is therefore not possible to parallel speaker outputs of multiple
ISD2500 devices or the outputs of other speaker drivers.
[2]
A single-end output may be used (including a coupling capacitor
between the SP pin and the speaker). These outputs may be used
individually with the output signal taken from either pin. However, the
use of single-end output results in a 1 to 4 reduction in its output power.
[1]
[2]
Connection of speaker outputs in parallel may cause damage to the device.
Never ground or drive an unused speaker output.
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ISD2532/40/48/64
PIN NO.
PIN NAME
FUNCTION
SOIC/ TSOP
PDIP
VCCA, VCCD
16, 28
17
23, 7
24
Supply Voltage: To minimize noise, the analog and digital circuits
in the ISD2500 series devices use separate power busses. These
voltage busses are brought out to separate pins and should be tied
together as close to the supply as possible. In addition, these
supplies should be decoupled as close to the package as possible.
MIC
Microphone: The microphone pin transfers input signal to the on-
chip preamplifier. A built-in Automatic Gain Control (AGC) circuit
controls the gain of this preamplifier from –15 to 24dB. An external
microphone should be AC coupled to this pin via a series capacitor.
The capacitor value, together with the internal 10 KΩ resistance on
this pin, determines the low-frequency cutoff for the ISD2500 series
passband. See Winbond’s Application Information for additional
information on low-frequency cutoff calculation.
MIC REF
AGC
18
19
25
26
Microphone Reference: The MIC REF input is the inverting input
to the microphone preamplifier. This provides a noise-canceling or
common-mode rejection input to the device when connected to a
differential microphone.
Automatic Gain Control: The AGC dynamically adjusts the gain of
the preamplifier to compensate for the wide range of microphone
input levels. The AGC allows the full range of whispers to loud
sounds to be recorded with minimal distortion. The “attack” time is
determined by the time constant of a 5 KΩ internal resistance and
an external capacitor (C2 on the schematic of Figure 5 in section
11) connected from the AGC pin to VSSA analog ground. The
“release” time is determined by the time constant of an external
resistor (R2) and an external capacitor (C2) connected in parallel
between the AGC pin and VSSA analog ground. Nominal values of
470 KΩ and 4.7 µF give satisfactory results in most cases.
ANA IN
20
27
Analog Input: The analog input transfers analog signal to the chip
for recording. For microphone inputs, the ANA OUT pin should be
connected via an external capacitor to the ANA IN pin. This
capacitor value, together with the 3.0 KΩ input impedance of ANA
IN, is selected to give additional cutoff at the low-frequency end of
the voice passband. If the desired input is derived from a source
other than a microphone, the signal can be fed, capacitively
coupled, into the ANA IN pin directly.
Publication Release Date: June 2003
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Revision 1.0
ISD2532/40/48/64
PIN NO.
PIN NAME
FUNCTION
SOIC/ TSOP
PDIP
ANA OUT
21
22
28
1
Analog Output: This pin provides the preamplifier output to the
user. The voltage gain of the preamplifier is determined by the
voltage level at the AGC pin.
Overflow: This signal pulses LOW at the end of memory array,
OVF
indicating the device has been filled and the message has
overflowed. The OVF output then follows the CE input until a
PD pulse has reset the device. This pin can be used to cascade
several ISD2500 devices together to increase record/playback
durations.
23
24
2
3
CE
PD
Chip Enable: The CE input pin is taken LOW to enable all
playback and record operations. The address pins and
playback/record pin (P/R ) are latched by the falling edge of CE.
CE has additional functionality in the M6 (Push-Button)
Operational Mode as described in the Operational Mode section.
Power Down: When neither record nor playback operation, the PD
pin should be pulled HIGH to place the part in standby mode (see
ISB specification). When overflow ( OVF ) pulses LOW for an
overflow condition, PD should be brought HIGH to reset the
address pointer back to the beginning of the memory array. The PD
pin has additional functionality in the M6 (Push-Button) Operation
Mode as described in the Operational Mode section.
25
4
End-Of-Message: A nonvolatile marker is automatically inserted at
EOM
the end of each recorded message. It remains there until the
message is recorded over. The EOM output pulses LOW for a
period of TEOM at the end of each message.
In addition, the ISD2500 series has an internal VCC detect circuit to
maintain message integrity should VCC fall below 3.5V. In this case,
EOM goes LOW and the device is fixed in Playback-only mode.
When the device is configured in Operational Mode M6 (Push-
Button Mode), this pin provides an active-HIGH signal, indicating
the device is currently recording or playing. This signal can
conveniently drive an LED for visual indicator of a record or
playback operation in process.
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ISD2532/40/48/64
PIN NO.
PIN NAME
FUNCTION
SOIC/ TSOP
PDIP
XCLK
26
5
External Clock: The external clock input has an internal pull-down
device. The device is configured at the factory with an internal
sampling clock frequency centered to ±1 percent of specification.
The frequency is then maintained to a variation of ±2.25 percent
over the entire commercial temperature and operating voltage
ranges. If greater precision is required, the device can be clocked
through the XCLK pin as follows:
Part Number
Sample Rate
Required Clock
ISD2532
8.0 kHz
1024 kHz
ISD2540
6.4 kHz
819.2 kHz
682.7 kHz
512 kHz
ISD2548
5.3 kHz
ISD2564
4.0 kHz
These recommended clock rates should not be varied because the
antialiasing and smoothing filters are fixed, and aliasing problems
can occur if the sample rate differs from the one recommended.
The duty cycle on the input clock is not critical, as the clock is
immediately divided by two. If the XCLK is not used, this input
must be connected to ground.
27
6
P/R
Playback/Record: The P/R input pin is latched by the falling edge
of the CE pin. A HIGH level selects a playback cycle while a LOW
level selects a record cycle. For a record cycle, the address pins
provide the starting address and recording continues until PD or
CE is pulled HIGH or an overflow is detected (i.e. the chip is full).
When a record cycle is terminated by pulling PD or CE HIGH,
then End-Of-Message ( EOM ) marker is stored at the current
address in memory. For a playback cycle, the address inputs
provide the starting address and the device will play until an EOM
marker is encountered. The device can continue to pass an EOM
marker if CE is held LOW in address mode, or in an Operational
Mode. (See Operational Modes section)
Publication Release Date: June 2003
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Revision 1.0
ISD2532/40/48/64
7. FUNCTIONAL DESCRIPTION
7.1. DETAILED DESCRIPTION
Speech/Sound Quality
The Winbond’s ISD2500 series includes devices offered at 4.0, 5.3, 6.4, and 8.0 kHz sampling
frequencies, allowing the user a choice of speech quality options. Increasing the duration within a
product series decreases the sampling frequency and bandwidth, which affects the sound quality.
Please refer to the ISD2532/40/48/64 Product Summary table below to compare the duration,
sampling frequency and filter pass band.
The speech samples are stored directly into the on-chip nonvolatile memory without any digitization
and compression associated like other solutions. Direct analog storage provides a very true, natural
sounding reproduction of voice, music, tones, and sound effects not available with most solid state
digital solutions.
Duration
To meet various system requirements, the ISD2532/40/48/64 products offer single-chip solutions at
32, 40, 48, and 64 seconds. Parts may also be cascaded together for longer durations.
TABLE 1: ISD2532/40/48/64 PRODUCT SUMMARY
Part Number
Duration
Input Sample
Typical Filter Pass
(Seconds)
Rate (kHz)
Band * (kHz)
ISD2532
ISD2540
ISD2548
ISD2564
32
40
48
64
8.0
6.4
5.3
4.0
3.4
2.7
2.3
1.7
*
3dB roll off point. This parameter is not checked during production testing and may vary due
to process variations and other factors. Therefore, customer should not rely on this value for
testing purposes.
EEPROM Storage
One of the benefits of Winbond’s ChipCorder® technology is the use of on-chip nonvolatile memory,
providing zero-power message storage. The message is retained for up to 100 years typically without
power. In addition, the device can be re-recorded typically over 100,000 times.
Microcontroller Interface
In addition to its simplicity and ease of use, the ISD2500 series includes all the interfaces necessary
for microcontroller-driven applications. The address and control lines can be interfaced to a
microcontroller and manipulated to perform a variety of tasks, including message assembly, message
concatenation, predefined fixed message segmentation, and message management.
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ISD2532/40/48/64
Programming
The ISD2500 series is also ideal for playback-only applications, where single or multiple messages
are referenced through buttons, switches, or a microcontroller. Once the desired message
configuration is created, duplicates can easily be generated via a gang programmer.
7.2. OPERATIONAL MODES
The ISD2500 series is designed with several built-in Operational Modes that provide maximum
functionality with minimum external components. These modes are described in details as below. The
Operational Modes are accessed via the address pins and mapped beyond the normal message
address range. When the two Most Significant Bits (MSB), A7 and A8, are HIGH, the remaining
address signals are interpreted as mode bits and not as address bits. Therefore, Operational Modes
and direct addressing are not compatible and cannot be used simultaneously.
There are two important considerations for using Operational Modes. First, all operations begin initially
at address 0 of its memory. Later operations can begin at other address locations, depending on the
Operational Mode(s) chosen. In addition, the address pointer is reset to 0 when the device is changed
from record to playback, playback to record (except M6 mode), or when a Power-Down cycle is
executed.
Second, Operational Modes are executed when CE goes LOW. This Operational Mode remains in
effect until the next LOW-going CE signal, at which point the current mode(s) are sampled and
executed.
TABLE 2: OPERATIONAL MODES
Mode [1]
M0
Function
Message cueing
Typical Use
Fast-forward through messages
Jointly Compatible [2]
M4, M5, M6
M1
M3, M4, M5, M6
Delete EOM markers
Position EOM marker at the end of
the last message
M2
M3
M4
Not applicable
Looping
Consecutive
addressing
Reserved
N/A
Continuous playback from Address 0 M1, M5, M6
Record/playback multiple
consecutive messages
M0, M1, M5
M5
M6
Allows message pausing
M0, M1, M3, M4
M0, M1, M3
CE level-activated
Push-button control
Simplified device interface
[1]
Besides mode pin needed to be “1”, A7 and A8 pin are also required to be “1” in order to enter into the related operational
mode.
[2]
Indicates additional Operational Modes which can be used simultaneously with the given mode.
Publication Release Date: June 2003
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Revision 1.0
ISD2532/40/48/64
7.2.1. Operational Modes Description
The Operational Modes can be used in conjunction with a microcontroller, or they can be hardwired to
provide the desired system operation.
M0 – Message Cueing
Message Cueing allows the user to skip through messages, without knowing the actual physical
addresses of each message. Each CE LOW pulse causes the internal address pointer to skip to the
next message. This mode is used for playback only, and is typically used with the M4 Operational
Mode.
M1 – Delete EOM Markers
The M1 Operational Mode allows sequentially recorded messages to be combined into a single
message with only one EOM marker set at the end of the final message. When this Operational
Mode is configured, messages recorded sequentially are played back as one continuous message.
M2 – Unused
When Operational Modes are selected, the M2 pin should be LOW.
M3 – Message Looping
The M3 Operational Mode allows for the automatic, continuously repeated playback of the message
located at the beginning of the address space. A message can completely fill the ISD2500 device and
will loop from beginning to end without OVF going LOW.
M4 – Consecutive Addressing
During normal operation, the address pointer will reset when a message is played through an EOM
marker. The M4 Operational Mode inhibits the address pointer reset on EOM , allowing messages to
be played back consecutively.
M5 - CE-Level Activated
The default mode for ISD2500 devices is for CE to be edge-activated on playback and level-
activated on record. The M5 Operational Mode causes the CE pin to be interpreted as level-
activated as opposed to edge-activated during playback. This is especially useful for terminating
playback operations using the CE signal. In this mode, CE LOW begins a playback cycle, at the
beginning of the device memory. The playback cycle continues as long as CE is held LOW. When
CE goes HIGH, playback will immediately end. A new CE LOW will restart the message from the
beginning unless M4 is also HIGH.
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ISD2532/40/48/64
M6 – Push-Button Mode
The ISD2500 series contain a Push-Button Operational Mode. The Push-Button Mode is used
primarily in very low-cost applications and is designed to minimize external circuitry and components,
thereby reducing system cost. In order to configure the device in Push-Button Operational Mode, the
two most significant address bits must be HIGH, and the M6 mode pin must also be HIGH. A device in
this mode always powers down at the end of each playback or record cycle after CE goes HIGH.
When this operational mode is implemented, three of the pins on the device have alternate
functionality as described in the table below.
TABLE 3: ALTERNATE FUNCTIONALITY IN PINS
Pin Name
Alternate Functionality in Push-Button Mode
Start/Pause Push-Button (LOW pulse-activated)
CE
PD
Stop/Reset Push-Button (HIGH pulse-activated)
Active-HIGH Run Indicator
EOM
CE (START/PAUSE)
In Push-Button Operational Mode, CE acts as a LOW-going pulse-activated START/PAUSE signal.
If no operation is currently in progress, a LOW-going pulse on this signal will initiate a playback or
record cycle according to the level on the P/R pin. A subsequent pulse on the CE pin, before an
EOM is reached in playback or an overflow condition occurs, will pause the current operation, and
the address counter is not reset. Another CE pulse will cause the device to continue the operation
from the place where it is paused.
PD (STOP/RESET)
In Push-Button Operational Mode, PD acts as a HIGH-going pulse-activated STOP/RESET signal.
When a playback or record cycle is in progress and a HIGH-going pulse is observed on PD, the
current cycle is terminated and the address pointer is reset to address 0, the beginning of the
message space.
EOM (RUN)
In Push-Button Operational Mode, EOM becomes an active-HIGH RUN signal which can be used to
drive an LED or other external device. It is HIGH whenever a record or playback operation is in
progress.
Recording in Push-Button Mode
1. The PD pin should be LOW, usually using a pull-down resistor.
Publication Release Date: June 2003
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ISD2532/40/48/64
2. The P/R pin is taken LOW.
3. The CE pin is pulsed LOW. Recording starts, EOM goes HIGH to indicate an
operation in progress.
4. When the CE pin is pulsed LOW. Recording pauses, EOM goes back LOW. The
internal address pointers are not cleared, but the EOM marker is stored in memory to
indicate as the message end. The P/ R pin may be taken HIGH at this time. Any
subsequent CE would start a playback at address 0.
5. The CE pin is pulsed LOW. Recording starts at the next address after the previous set
EOM marker. EOM goes back HIGH.[3]
6. When the recording sequences are finished, the final CE pulse LOW will end the last
record cycle, leaving a set EOM marker at the message end. Recording may also be
terminated by a HIGH level on PD, which will leave a set EOM marker.
Playback in Push-Button Mode
1. The PD pin should be LOW.
2. The P/R pin is taken HIGH.
3. The CE pin is pulsed LOW. Playback starts, EOM goes HIGH to indicate an operation
in progress.
4. If the CE pin is pulsed LOW or an EOM marker is encountered during an operation,
the part will pause. The internal address pointers are not cleared, and EOM goes back
LOW. The P/R pin may be changed at this time. A subsequent record operation would
not reset the address pointers and the recording would begin where playback ended.
5. CE is again pulsed LOW. Playback starts where it left off, with EOM going HIGH to
indicate an operation in progress.
6. Playback continues as in steps 4 and 5 until PD is pulsed HIGH or overflow occurs.
7. If in overflow, pulling CE LOW will reset the address pointer and start playback from the
beginning. After a PD pulse, the part is reset to address 0.
Note: Push-Button Mode can be used in conjunction with modes M0, M1, and M3.
[3]
If the M1 Operational Mode pin is also HIGH, the just previously written EOM bit is erased, and recording starts at that
address.
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ISD2532/40/48/64
Good Audio Design Practices
Winbond ChipCorder products are very high-quality single-chip voice recording and playback
devices. To ensure the highest quality voice reproduction, it is important that good audio design
practices on layout and power supply decoupling are followed. Please refer to Application Information
Section of ChipCorder products in Winbond website (www.winbond-usa.com) for details.
Good Audio Design Practices (apin11.pdf)
Single-Chip Board Layout Diagrams (apin12.pdf)
Publication Release Date: June 2003
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Revision 1.0
ISD2532/40/48/64
8. TIMING DIAGRAMS
TCE
CE
TSET
Don't Care
TPDH
P/R
THOLD
TPDS
TPDR
Don't Care
Don't Care
PD
A0-A8
Don't Care
TSET
TPUD
MIC
ANA IN
TOVF
OVF
FIGURE 1: RECORD
TCE
CE
TSET
Don't Care
TPDH
P/R
THOLD
TPDS
TPDP
Don't Care
Don't Care
PD
Don't Care
A0-A8
TSET
SP+/-
TOVF
OVF
EOM
TPUD
TEOM
FIGURE 2: PLAYBACK
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ISD2532/40/48/64
Start
TCE
Pause
TCE
Start
TCE
Stop
CE
(Start/Pause)
TSET
TSET
TSET
P/R
TPD
TSET
TSET
TSET
PD
(Stop/Reset)
A0-A8
MIC ANA IN
OVF
TPAUSE
TRUN
EOM
TDB
TDB
(Run)
TPUD
TDB
TPUD
Notes
(1)
(2)
(3)
(4, 5)
(6, 7)
(8)
FIGURE 3: PUSH-BUTTON MODE RECORD
Start
TCE
Pause
TCE
Start
Stop
CE
(Start/Pause)
TSET
TSET
TSET
P/R
TPD
TSET
TSET
TSET
PD
(Stop/Reset)
A0-A8
SP+/-
OVF
TPAUSE
TRUN
EOM
TDB
TDB
(Run)
TPUD
TDB
TPUD
Notes
(1)
(2)
(3)
(4, 5)
(6, 7)
(8)
FIGURE 4: PUSH-BUTTON MODE PLAYBACK
Publication Release Date: June 2003
Revision 1.0
- 17 -
ISD2532/40/48/64
Notes for Push-Button modes:
1. A8, A7, and A6 = 1 for push-button operation.
2. The first CE LOW pulse performs a start function.
3. The part will begin to play or record after a power-up delay TPUD
.
4. The part must have CE HIGH for a debounce period TDB before it will recognize another falling edge of
CE and pause.
5. The second CE LOW pulse, and every even pulse thereafter, performs a Pause function.
6. Again, the part must have CE HIGH for a debounce period TDB before it will recognize another falling
edge of CE , which would restart an operation. In addition, the part will not do an internal power down
until CE is HIGH for the TDB time.
7. The third CE LOW pulse, and every odd pulse thereafter, performs a Resume function.
8. At any time, a HIGH level on PD will stop the current function, reset the address counter, and power
down the device.
- 18 -
ISD2532/40/48/64
9. ABSOLUTE MAXIMUM RATINGS
TABLE 4: ABSOLUTE MAXIMUM RATINGS (DIE)
CONDITIONS
Junction temperature
VALUES
150°C
Storage temperature range
Voltage applied to any pad
-65°C to +150°C
(VSS –0.3V) to
(VCC +0.3V)
(VSS –1.0V) to
(VCC +1.0V)
Voltage applied to any pad (Input current limited to ±20mA)
VCC – VSS
-0.3V to +7.0V
TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
CONDITIONS
VALUES
150°C
Junction temperature
Storage temperature range
Voltage applied to any pin
-65°C to +150°C
(VSS –0.3V) to
(VCC +0.3V)
(VSS –1.0V) to
(VCC +1.0V)
Voltage applied to any pin (Input current limited to ±20 mA)
Lead temperature (Soldering – 10sec)
VCC – VSS
300°C
-0.3V to +7.0V
Note: Stresses above those listed may cause permanent damage to the device. Exposure to the
absolute maximum ratings may affect device reliability and performance. Functional
operation is not implied at these conditions.
Publication Release Date: June 2003
- 19 -
Revision 1.0
ISD2532/40/48/64
9.1 OPERATING CONDITIONS
TABLE 6: OPERATING CONDITIONS (DIE)
CONDITIONS
Commercial operating temperature range
Supply voltage (VCC) [1]
Ground voltage (VSS) [2]
VALUES
0°C to +50°C
+4.5V to +6.5V
0V
TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)
CONDITIONS
Commercial operating temperature range [3]
Supply voltage (VCC) [1]
VALUES
0°C to +70°C
+4.5V to +5.5V
0V
Ground voltage (VSS) [2]
Notes:
[1]
V
V
= VCCA = VCCD
= VSSA = VSSD
CC
[2]
SS
[3] Case Temperature
- 20 -
ISD2532/40/48/64
10. ELECTRICAL CHARACTERISTICS
10.1. PARAMETERS FOR PACKAGED PARTS
TABLE 8: DC PARAMETERS – Packaged Parts
MIN [2]
TYP [1]
MAX [2] UNITS
CONDITIONS
SYMBOL
VIL
VIH
VOL
VOH
PARAMETERS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
V
V
V
V
V
2.0
0.4
IOL = 4.0 mA
IOH = -10 µA
IOH = -1.6 mA
VCC - 0.4
2.4
VOH1
OVF Output High Voltage
VOH2
VCC – 1.0 VCC - 0.8
V
IOH = -3.2 mA
EOM Output High Voltage
VCC Current (Operating)
VCC Current (Standby)
Input Leakage Current
REXT = ∞ [3]
ICC
ISB
IIL
25
1
30
10
mA
µA
µA
µA
[3]
±1
130
[4]
Input Current HIGH w/Pull
Down
IILPD
Force VCC
Output Load Impedance
Preamp Input Resistance
REXT
RMIC
16
4
Ω
Speaker Load
MIC and MIC
REF Pins
9
15
KΩ
AUX IN Input Resistance
ANA IN Input Resistance
Preamp Gain 1
Preamp Gain 2
AUX IN/SP+ Gain
RAUX
RANA IN
APRE1
APRE2
AAUX
5
2.3
21
11
3
20
5
26
5
1.0
26
9.5
KΩ
KΩ
dB
dB
V/V
dB
24
-15
0.98
23
5
AGC = 0.0V
AGC = 2.5V
ANA IN to SP+/- Gain
AGC Output Resistance
AARP
RAGC
21
2.5
KΩ
Notes:
[1]
Typical values @ TA = 25º and VCC = 5.0V.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
[3]
[4]
V
CCA and VCCD connected together.
XCLK pin only.
Publication Release Date: June 2003
Revision 1.0
- 21 -
ISD2532/40/48/64
TABLE 9: AC PARAMETERS – Packaged Parts
CHARACTERISTIC
Sampling Frequency
ISD2532
SYMBOL
FS
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
[7]
[7]
[7]
[7]
8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
ISD2540
ISD2548
ISD2564
Filter Pass Band
ISD2532
FCF
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
ISD2540
ISD2548
ISD2564
Record Duration
ISD2532
TREC
TPLAY
TCE
[7]
[7]
[7]
[7]
32
40
48
64
sec
sec
sec
sec
ISD2540
ISD2548
ISD2564
Playback Duration
ISD2532
[7]
[7]
[7]
[7]
32
40
48
64
sec
sec
sec
sec
ISD2540
ISD2548
ISD2564
100
nsec
CE Pulse Width
Control/Address Setup Time
Control/Address Hold Time
Power-Up Delay
ISD2532
TSET
THOLD
TPUD
300
0
nsec
nsec
25.0
31.0
37.0
50.0
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
- 22 -
ISD2532/40/48/64
TABLE 9: AC PARAMETERS – Packaged Parts (Cont’d)
CHARACTERISTIC
PD Pulse Width (record)
ISD2532
SYMBOL
TPDR
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
25.0
31.25
37.5
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
50.0
PD Pulse Width (Play)
ISD2532
TPDP
12.5
15.625
18.75
25.0
100
msec
msec
msec
msec
nsec
nsec
ISD2540
ISD2548
ISD2564
[6]
PD Pulse Width (Static)
Power Down Hold
TPDS
TPDH
TEOM
0
EOM Pulse Width
ISD2532
12.5
15.625
18.75
25.0
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
Overflow Pulse Width
Total Harmonic Distortion
Speaker Output Power
Voltage Across Speaker Pins
MIC Input Voltage
ANA IN Input Voltage
AUX Input Voltage
TOVF
THD
POUT
VOUT
VIN1
6.5
1
µsec
%
2
50
@ 1 kHz
REXT = 16 Ω [4]
12.2
mW
V p-p
mV
mV
V
REXT = 600 Ω, Aux In=1.25Vp-p
Peak-to-Peak [5]
2.5
20
VIN2
50
Peak-to-Peak
VIN3
1.25
Peak-to-Peak; REXT = 16 Ω
Notes:
[1]
Typical values @ TA = 25ºC, VCC = 5.0V and timing measured at 50% levels.
[2]
[3]
[4]
[5]
[6]
[7]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical.
With 5.1 K Ω series resistor at ANA IN.
TPDS is required during a static condition, typically overflow.
Sampling Frequency and Duration can vary as much as ±2.25 percent over the commercial temperature range. For greater stability, an
external clock can be utilized (see Pin Descriptions)
[8]
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of
passing through both filters.
Publication Release Date: June 2003
- 23 -
Revision 1.0
ISD2532/40/48/64
10.1.1. Typical Parameter Variation with Voltage and Temperature - Packaged Parts
Chart 1: Record Mode Operating
Current (ICC)
Chart 3: Standby Current (ISB)
25
1.2
1.0
20
15
0.8
0.6
10
5
0.4
0.2
0
0
-40
25
70
85
-40
25
70
85
Temperature (C)
Temperature (C)
5.5 Volts 4.5 Volts
5.5 Volts 4.5 Volts
Chart 2: Total Harmonic Distortion
Chart 4: Oscillator Stability
0.4
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
25
70
85
-40
25
70
85
Temperature (C)
Temperature (C)
5.5 Volts 4.5 Volts
5.5 Volts 4.5 Volts
- 24 -
ISD2532/40/48/64
10.2. PARAMETERS FOR DIE
TABLE 10: DC PARAMETERS – Die
SYMBOL
VIL
VIH
VOL
VOH
PARAMETERS
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
MIN[2]
TYP[1]
MAX[2] UNITS
CONDITIONS
0.8
V
V
V
V
V
2.0
0.4
IOL = 4.0 mA
IOH = -10 µA
IOH = -1.6 mA
VCC - 0.4
2.4
VOH1
OVF Output High Voltage
EOM Output High Voltage
VOH2
VCC – 1.0
VCC
0.8
-
V
IOH = -3.2 mA
R
EXT = ∞ [3]
VCC Current (Operating)
VCC Current (Standby)
Input Leakage Current
ICC
ISB
IIL
25
1
30
10
mA
µA
µA
µA
[2]
±1
130
[4]
Input Current HIGH w/Pull
Down
IILPD
Force VCC
Output Load Impedance
Preamp IN Input
Resistance
REXT
RMIC
16
4
Ω
Speaker Load
MIC and MIC
REF Pads
9
15
KΩ
AUX IN Input Resistance
ANA IN Input Resistance
Preamp Gain 1
Preamp Gain 2
AUX IN/SP+ Gain
RAUX
RANA IN
APRE1
APRE2
AAUX
5
2.3
21
11
3
24
-15
0.98
23
5
20
5
26
5
1.0
26
9.5
KΩ
KΩ
dB
dB
V/V
dB
AGC = 0.0V
AGC = 2.5V
ANA IN to SP+/- Gain
AGC Output Resistance
AARP
RAGC
21
2.5
KΩ
Notes:
[1]
Typical values @ TA = 25°C and VCC = 5.0V.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
[3]
[4]
V
CCA and VCCD connected together.
XCLK pad only.
Publication Release Date: June 2003
Revision 1.0
- 25 -
ISD2532/40/48/64
TABLE 11: AC PARAMETERS – Die
CHARACTERISTIC
Sampling Frequency
ISD2532
SYMBOL
FS
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
[7]
[7]
[7]
[7]
8.0
6.4
5.3
4.0
kHz
kHz
kHz
kHz
ISD2540
ISD2548
ISD2564
Filter Pass Band
ISD2532
FCF
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3 dB Roll-Off Point [3][8]
3.4
2.7
2.3
1.7
kHz
kHz
kHz
kHz
ISD2540
ISD2548
ISD2564
Record Duration
ISD2532
TREC
TPLAY
TCE
[7]
[7]
[7]
[7]
32
40
48
64
sec
sec
sec
sec
ISD2540
ISD2548
ISD2564
Playback Duration
ISD2532
[7]
[7]
[7]
[7]
32
40
48
64
sec
sec
sec
sec
ISD2540
ISD2548
ISD2564
100
nsec
CE Pulse Width
Control/Address Setup Time
Control/Address Hold Time
Power-Up Delay
ISD2532
TSET
THOLD
TPUD
300
0
nsec
nsec
25.0
31.3
37.5
50.0
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
- 26 -
ISD2532/40/48/64
TABLE 11: AC PARAMETERS – Die (Cont’d)
CHARACTERISTIC
PD Pulse Width (Record)
ISD2532
SYMBOL
TPDR
MIN[2]
TYP[1]
MAX[2]
UNITS
CONDITIONS
25.0
31.25
37.5
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
50.0
PD Pulse Width (Play)
ISD2532
TPDP
12.5
15.625
18.75
25.0
100
msec
msec
msec
msec
nsec
nsec
ISD2540
ISD2548
ISD2564
[6]
PD Pulse Width (Static)
Power Down Hold
TPDS
TPDH
TEOM
0
EOM Pulse Width
ISD2532
12.5
15.625
18.75
25.0
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
Overflow Pulse Width
Total Harmonic Distortion
Speaker Output Power
Voltage Across Speaker Pins
MIC Input Voltage
ANA IN Input Voltage
AUX Input Voltage
TOVF
THD
POUT
VOUT
VIN1
6.5
1
µsec
%
2
50
@ 1 kHz
REXT = 16 Ω [4]
12.2
mW
V p-p
mV
mV
V
REXT=600 Ω, Aux In=1.25Vp-p
Peak-to-Peak [5]
2.5
20
VIN2
50
Peak-to-Peak
VIN3
1.25
Peak-to-Peak; REXT = 16 Ω
Notes:
[1]
Typical values @ TA = 25°C, VCC = 5.0V and timing measured at 50% levels.
[2]
[3]
[4]
[5]
[6]
[7]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested.
Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)
From AUX IN; if ANA IN is driven at 50 mV p-p, the POUT = 12.2 mW, typical.
With 5.1 K Ω series resistor at ANA IN.
TPDS is required during a static condition, typically overflow.
Sampling Frequency and playback Duration can vary as much as ±2.25 percent over the commercial temperature range. For greater stability,
an external clock can be utilized (see Pin Descriptions)
[8]
Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to output, expect a 6 dB drop by nature of
passing through both filters.
Publication Release Date: June 2003
- 27 -
Revision 1.0
ISD2532/40/48/64
10.2.1. Typical Parameter Variation with Voltage and Temperature - Die
Chart 5: Record Mode Operating
Current (ICC)
Chart 7: Standby Current (ISB)
30
25
1.0
0.8
0.6
20
15
0.4
0.2
0
10
5
0
-40
25
50
-40
25
50
Temperature (C)
Temperature (C)
6.5 Volts
5.5 Volts
4.5 Volts
6.5 Volts
5.5 Volts
4.5 Volts
Chart 6: Total Harmonic Distortion
Chart 8: Oscillator Stability
0.2
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
25
50
-40
25
50
Temperature (C)
Temperature (C)
6.5 Volts
5.5 Volts
4.5 Volts
6.5 Volts
5.5 Volts
4.5 Volts
- 28 -
ISD2532/40/48/64
10.3. PARAMETERS FOR PUSH-BUTTON MODE
TABLE 12: PARAMETERS FOR PUSH-BUTTON MODE
PARAMETERS
SYMBOL
TCE
MIN[2]
TYP[1]
300
MAX[2] UNITS CONDITIONS
nsec
CE Pulse Width
(Start/Pause)
Control/Address Setup Time
Power-Up Delay
ISD2532
TSET
TPUD
300
nsec
25.0
31.25
37.25
50.0
msec
msec
msec
msec
nsec
ISD2540
ISD2548
ISD2564
PD Pulse Width (Stop/Restart) TPD
300
TRUN
25
50
400
400
nsec
CE to EOM HIGH
TPAUSE
TDB
nsec
CE to EOM LOW
CE HIGH Debounce
ISD2532
70
85
105
135
105
135
160
215
msec
msec
msec
msec
ISD2540
ISD2548
ISD2564
Notes:
[1]
Typical values @ TA = 25°C, VCC = 5.0V and timing measured at 50% levels.
[2]
All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100
percent tested.
Publication Release Date: June 2003
- 29 -
Revision 1.0
ISD2532/40/48/64
11. TYPICAL APPLICATION CIRCUIT
VCC
ISD2532/40/48/64
1
2
3
4
5
6
7
28
16
VCCD
VCCA
A0
A1
A2
A3
A4
A5
A6
VCC
VSS
C6
F
C7
0.1
C8
22
0.1
F
µ
µ
12
13
F
µ
VSSD
VSSA
R4
CHIP ENABLE
POWER DOWN
100 K
Ω
14
15
11
20
SP+
SP-
AUX IN
9
10
16 Ω
A7
A8
SPEAKER
ANA IN
R6
5.1 K
C3
0.1
Ω
F
µ
23
24
27
25
22
26
21
CE
PD
P/R
OEM
OVF
XCLK
ANA OUT
PLAYBACK/RECORD
18
17
(Note)
MIC REF
MIC
C1
VCC
0.1
F
µ
C5
0.1
19
AGC
F
µ
R1
1 K
R3
10 K
Ω
Ω
C2
4.7
R2
470 K
C4
220
F
µ
Ω
ELECTRET
MICROPHONE
F
µ
R5
10 K
Ω
FIGURE 5: DESIGN SCHEMATIC
Note: If desired, pin 18 (PDIP package) may be left unconnected (microphone preamplifier noise will be higher). In
this case, pin 18 must not be tied to any other signal or voltage. Additional design example schematics are
provided below.
- 30 -
ISD2532/40/48/64
TABLE 13: APPLICATION EXAMPLE – BASIC DEVICE CONTROL
Control Step
Function
Action
1
Power up chip and select Record/Playback Mode
1. PD = LOW, 2. P/R = As desired
Set addresses A0-A8
2
3A
Set message address for record/playback
Begin playback
P/R = HIGH, CE = Pulse LOW
3B
Begin record
P/R = LOW, CE = LOW
Automatic
4A
4B
End playback
End record
PD or CE = HIGH
TABLE 14: APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Parts
Function
Microphone power supply decoupling
Release time constant
Comments
Reduces power supply noise
Sets release time for AGC
R1
R2
R3, R5
R4
Microphone biasing resistors
Series limiting resistor
Provides biasing for microphone operation
Reduces level to prevent distortion at
higher supply voltages
R6
Series limiting resistor
Reduces level to high supply voltages
C1, C5
Microphone DC-blocking capacitor Low- Decouples microphone bias from chip.
frequency cutoff
Provides single-pole low-frequency cutoff
and command mode noise rejection.
C2
C3
Attack/Release time constant
Low-frequency cutoff capacitor
Sets attack/release time for AGC
Provides additional pole for low-frequency
cutoff
C4
C6, C7, C8
Microphone power supply decoupling
Power supply capacitors
Reduces power supply noise
Filter and bypass of power supply
Publication Release Date: June 2003
Revision 1.0
- 31 -
ISD2532/40/48/64
VCC
D1
RUN
S1
S2
S3
RECORD
PLAY
MSG#
MC68HC705K1A
OSC1
OSC2
ISD2532/40/48/64
PB0
PB1
1
2
3
4
5
6
7
28
16
VCCD
VCCA
A0
A1
A2
A3
A4
A5
A6
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
R1
TBD
RESET
IRQ
12
13
VSSD
VSSA
U1
14
15
11
20
VDD
VSS
SP+
SP-
AUX IN
ANA IN
9
10
U2
A7
A8
23
24
27
25
22
26
21
CE
PD
P/R
OEM
OVF
XCLK
ANA OUT
18
17
MIC REF
MIC
19
AGC
FIGURE 6: ISD2532/40/48/64 APPLICATION EXAMPLE – MICROCONTROLLER/ISD2500
INTERFACE
In this simplified block diagram of a microcontroller application, the Push-Button Mode and message
cueing are used. The microcontroller is a 16-pin version with enough port pins for buttons, an LED,
and the ISD2500 series device. The software can be written to use three buttons: one each for play
and record, and one for message selection. Because the microcontroller is interpreting the buttons
and commanding the ISD2500 device, software can be written for any function desired in a particular
application.
Note: Winbond does not recommend connecting address lines directly to a microprocessor bus.
Address lines should be externally latched.
- 32 -
ISD2532/40/48/64
VCC
ISD2532/40/48/64
VCCD
1
2
3
4
5
6
7
28
16
A0
A1
A2
A3
A4
A5
A6
VCC
VCCA
VSS
VCC
C4
F
C1
C5
22
0.1
0.1
F
µ
µ
12
13
F
µ
VSSD
VSSA
R7
100 K
R6
100 K
Ω
VCC
14
15
11
20
SP+
START/PAUSE
SP-
AUX IN
ANA IN
9
10
16 Ω
A7
A8
SPEAKER
STOP/RESET
R4
5.1 K
C3
0.1
Ω
F
µ
23
24
27
25
22
26
21
CE
PD
P/R
OEM
OVF
XCLK
ANA OUT
(Note)
18
17
MIC REF
MIC
C1
VCC
PLAYBACK/RECORD
0.1
F
µ
C5
0.1
19
AGC
F
µ
R1
1 K
R3
10 K
Ω
Ω
C2
4.7
R2
470 K
C4
220
F
µ
Ω
ELECTRET
MICROPHONE
F
µ
R5
10 K
Ω
FIGURE 7: ISD2532/40/48/64 APPLICATION EXAMPLE – PUSH-BUTTON
Note: Please refer to page 13 for more details.
Publication Release Date: June 2003
Revision 1.0
- 33 -
ISD2532/40/48/64
TABLE 15: APPLICATION EXAMPLE – PUSH-BUTTON CONTROL
Control Step
Function
Action
1
Select Record/Playback Mode
P/R = As desired
2A
2B
3
Begin playback
Begin record
P/R = HIGH, CE = Pulse LOW
P/R = LOW, CE = Pulse LOW
CE = Pulsed LOW
Pause record or playback
End playback
4A
4B
Automatic at EOM marker or PD = Pulsed HIGH
PD = Pulsed HIGH
End record
TABLE 16: APPLICATION EXAMPLE – PASSIVE COMPONENT FUNCTIONS
Parts
Function
Release time constant
Comments
Sets release time for AGC
R2
R4
Series limiting resistor
Reduces level to prevent distortion at
higher supply voltages
R6, R7
C1, C4, C5
C2
Pull-up and pull-down resistors
Power supply capacitors
Attack/Release time constant
Low-frequency cutoff capacitor
Defines static state of inputs
Filters and bypass of power supply
Sets attack/release time for AGC
Provides additional pole for low-frequency
cutoff
C3
- 34 -
ISD2532/40/48/64
12. PACKAGE DRAWING AND DIMENSIONS
12.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)
28
1
26 25
3 4
23 22 21 20 19 18 17
15
16
27
2
24
5
6
7
9 10 11 12 13 14
8
A
G
C
B
D
F
E
H
INCHES
Nom
MILLIMETERS
Nom
Min
Max
0.711
0.104
0.299
0.0115
0.019
Min
17.81
2.46
7.42
0.127
0.35
Max
18.06
2.64
7.59
0.29
0.48
A
B
C
D
E
F
0.701
0.097
0.292
0.005
0.014
0.706
0.101
0.296
0.009
0.016
0.050
0.406
0.032
17.93
2.56
7.52
0.22
0.41
1.27
10.31
0.81
G
H
0.400
0.024
0.410
0.040
10.16
0.61
10.41
1.02
Note: Lead coplanarity to be within 0.004 inches.
Publication Release Date: June 2003
Revision 1.0
- 35 -
ISD2532/40/48/64
12.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)
INCHES
Nom
MILLIMETERS
Nom
Min
Max
Min
Max
A
B1
B2
C1
C2
D
1.445
1.450
0.150
0.070
1.455
36.70
36.83
3.81
1.78
36.96
0.065
0.600
0.530
0.075
0.625
0.550
0.19
1.65
15.24
13.46
1.91
15.88
13.97
4.83
0.540
13.72
D1
E
F
G
H
J
S
q
0.015
0.125
0.015
0.055
0.38
3.18
0.38
1.40
0.135
0.022
0.065
3.43
0.56
1.62
0.018
0.060
0.100
0.010
0.075
0.46
1.52
2.54
0.25
1.91
0.008
0.070
0°
0.012
0.080
15°
0.20
1.78
0°
0.30
2.03
15°
- 36 -
ISD2532/40/48/64
12.3. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1
1
28
2
2
7
3
26
25
4
F
5
24
6
23
7
22
8
21
20
9
19
10
18
11
17
12
16
13
15
14
I
Plastic Thin Small Outline Package (TSOP) Type 1 Dimensions
INCHES
MILLIMETERS
Min
Nom
0.528
0.465
0.315
Max
Min
13.20
11.70
7.90
0.05
0.17
Nom
13.40
11.80
8.00
Max
13.60
11.90
8.10
0.15
0.27
A
B
C
D
E
F
G
H
I
0.520
0.461
0.311
0.002
0.007
0.535
0.469
0.319
0.006
0.011
0.009
0.0217
0.039
0.22
0.55
1.00
0.037
0.041
0.95
1.05
00
30
60
00
30
60
0.020
0.022
0.028
0.50
0.55
0.70
J
0.004
0.008
0.10
0.21
Note: Lead coplanarity to be within 0.004 inches.
Publication Release Date: June 2003
Revision 1.0
- 37 -
ISD2532/40/48/64
12.4. DIE BONDING PHYSICAL LAYOUT [1]
ISD2532/40/48/64
VCCD
A3
A1
XCLK
P/R EOM
A2
A0
PD
o
Die Dimensions
X: 149.6 + 1 mils
Y: 206.3 + 1 mils
A4
CE
A5
A6
OVF
ISD2532/40/48/64
o
o
Die Thickness [2]
11.8 + .4 mils
Pad Opening
111 microns (4.4 mils)
≈
≈
NC
A7
A8
ANA OUT
ANA IN
AUX IN
VSSD
VSSA
SP+
SP- MIC
VCCA MIC REF
AGC
Notes:
[1]
The backside of die is internally connected to VSS. It MUST NOT be connected to any other potential or damage may
occur.
[2]
Die thickness is subject to change, please contact Winbond factory for status and availability.
- 38 -
ISD2532/40/48/64
ISD2532/40/48/64 PRODUCT PAD DESIGNATIONS
(with respect to die center)
Pad
Pad Name
X Axis (µm)
Y Axis (µm)
Overflow Output
1675.95
1779.38
OVF
Chip Enable Input
1728.08
2114.25
CE
PD
Power Down Input
End of Message
1731.83
1342.20
2383.88
2411.63
EOM
XCLK
No Connect (optional)
Playback/Record
987.83
808.58
2450.63
2453.25
P/R
VCCD
A0
A1
A2
A3
A4
A5
A6
VCC Digital Power Supply
Address 0
546.08
-896.55
-1114.05
-1329.68
-1542.68
-1639.05
-1696.80
-1696.80
-1729.80
-1729.80
-1729.80
-1408.80
-1111.43
-406.43
-46.05
2449.13
2425.13
2425.13
2425.13
2425.13
2178.75
1960.88
1731.38
-1875.75
-2061.00
-2343.38
-2408.25
-2388.75
-2431.13
-2360.25
-2360.25
-2403.00
-2438.63
-2438.63
-2422.88
-1946.63
-1703.63
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
NC
Address 7
NC
A7
A8
Address 8
AUX IN
VSSD
VSSA
SP+
SP-
VCCA
MIC
MIC REF
AGC
ANA IN
ANA OUT
Auxiliary Input
VSS Digital Power Supply
VSS Analog Power Supply
Speaker Output +
Speaker Output -
VCC Analog Power Supply
Microphone Input
Microphone Reference
Automatic Gain Control
Analog Input
388.20
747.83
1102.58
1296.08
1667.70
1729.95
1702.20
Analog Output
Publication Release Date: June 2003
Revision 1.0
- 39 -
ISD2532/40/48/64
13. ORDERING INFORMATION
Product Number Descriptor Key
ISD25
Special Temperature Field:
ISD2500 Series
Duration:
Blank = Commercial Packaged (0˚C to +70˚C)
or Commercial Die (0˚C to +50˚C)
32
40
48
64
=
=
=
=
32 seconds
40 seconds
48 seconds
64 seconds
Package Type:
P
=
28-Lead 600mil Plastic Dual Inline
Package (PDIP)
S
=
28-Lead 300mil Small Outline
Integrated Circuit (SOIC)
E
X
=
=
28-Lead 8x13.4 mm Thin Small
Outline Package (TSOP) Type 1
Die
When ordering ISD2532/40/48/64 products refer to the following part numbers which are supported in
volume for this product series. Consult the local Winbond Sales Representative or Distributor for
availability information.
Part Number
ISD2532P
ISD2532S
ISD2532E
ISD2532X
Part Number
ISD2540P
ISD2540S
ISD2540E
ISD2540X
Part Number
ISD2548P
Part Number
ISD2564P
ISD2548E
ISD2548X
ISD2564X
For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com
- 40 -
ISD2532/40/48/64
14. VERSION HISTORY
VERSION
DATE
Apr. 1998 Preliminary Specifications.
Reformat the document.
Jun. 2003
DESCRIPTION
0
1.0
Update TSOP description in pin configuration section.
Revise Table 1: Product Summary.
Update TSOP and SOIC package option.
Remove industrial temperature option.
Publication Release Date: June 2003
Revision 1.0
- 41 -
ISD2532/40/48/64
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond
makes no representation or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to specifications and product descriptions at
any time without notice. No license, whether express or implied, to any intellectual property or other right of
Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and
Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of
merchantability, fitness for a particular purpose or infringement of any Intellectual property.
Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other
applications intended to support or sustain life. Further more, Winbond products are not intended for applications
wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe
property or environmental injury could occur.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration
only and Winbond makes no representation or warranty that such applications shall be suitable for the use
specified.
ISD® and ChipCorder® are trademarks of Winbond Electronics Corporation.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as
published in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond.
Information contained in this ISD® ChipCorder® data sheet supersedes all data for the ISD ChipCorder products
published by ISD® prior to August, 1998.
This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information
in this, the information contained herein supersedes and governs such other information in its entirety.
Copyright© 2003, Winbond Electronics Corporation. All rights reserved. ISD® is a registered trademark of
Winbond. ChipCorder® is a trademark of Winbond. All other trademarks are properties of their respective
owners.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
CA 95134, U.S.A.
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.winbond-usa.com/
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 42 -
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