ISD4003-04MSI_技术文档

ISD4003 SERIES

SINGLE-CHIP, MULTIPLE-MESSAGES

VOICE RECORD/PLAYBACK DEVICES

4-, 5-, 6-, AND 8-MINUTE DURATION

Publication Release Date: January 2004

Revision 1.0

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ISD4003 SERIES

1. GENERAL DESCRIPTION

The ISD4003 ChipCorder^®series provides high-quality, 3-volt, single-chip record/playback solutions

for 4- to 8-minute messaging applications ideally for cellular phones and other portable products. The

CMOS-based devices include an on-chip oscillator, anti-aliasing filter, smoothing filter, AutoMute^®

feature, audio amplifier, and high density multilevel Flash memory array. The ISD4003 series is

designed to be used in a microprocessor- or microcontroller-based system. Address and control are

accomplished through a Serial Peripheral Interface (SPI) or Microwire Serial Interface to minimize pin

count.

Recordings are stored into the on-chip Flash memory cells, providing zero-power message storage.

This unique single-chip solution utilizes Winbond’s patented multilevel storage technology. Voice and

audio signals are directly stored onto memory array in their natural form, providing high-quality voice

reproduction.

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ISD4003 SERIES

2. FEATURES

• Single-chip voice record/playback solution

• Single 3 volt supply

• Low-power consumption

ꢀ

Operating current:

-

I

_{CC_Play}= 15 mA (typical)

_{CC_Rec}= 25 mA (typical)

ꢀ

Standby current:

_{CC_Standby}= 1 µA (typical)

-

I

• Duration: 4, 5, 6, and 8 minutes

• High-quality, natural voice/audio reproduction

• AutoMute feature provides background noise attenuation

• No algorithm development required

• Microcontroller SPI or Microwire™ Serial Interface

• Fully addressable to handle multiple messages

• Non-volatile message storage

• 100K record cycles (typical)

• 100-year message retention (typical)

• On-chip oscillator

• Power-down feature to reduce power consumption

• Available in die form, PDIP, SOIC, and TSOP

• Temperature:

-

Commercial (die): 0°C to +50°C

Commercial (packaged units): 0°C to +70°C

Extended: -20°C to +70°C

Industrial: -40°C to +85°C

Publication Release Date: January 2004

Revision 1.0

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ISD4003 SERIES

3. BLOCK DIAGRAM

Internal Clock

Timing

XCLK

Sampling Clock

ANA IN-

Amp

5-Pole Active

Antialiasing Filter

Analog Transceivers

ANA IN+

1920K Cell

Nonvolatile

Multilevel Storage

Array

5-Pole Active

Smoothing Filter

AutoMute^TM

Feature

Amp

AUDOUT

Power Conditioning

Device Control

V_CCAV_SSAV_SSAV_SSAV_SSDV_CCD

SCLK SS MOSI MISO INT RAC

AM CAP

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ISD4003 SERIES

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 3

3. BLOCK DIAGRAM .............................................................................................................................. 4

4. TABLE OF CONTENTS ...................................................................................................................... 5

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION.......................................................................................................... 12

7.1. Detailed Description.................................................................................................................... 12

7.2. Serial Peripheral Interface (SPI) Description.............................................................................. 13

7.2.1. OPCODES ........................................................................................................................... 14

7.2.2. SPI Diagrams....................................................................................................................... 15

7.2.3. SPI Control and Output Registers........................................................................................ 16

8. TIMING DIAGRAMS.......................................................................................................................... 18

9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20

9.1. Operating Conditions.................................................................................................................. 21

10. ELECTRICAL CHARACTERISTICS............................................................................................... 22

10.1. Parameters For Packaged Parts ........................................................................................ 22

10.2. Parameters For Die .............................................................................................................. 25

10.3. SPI AC Parameters .............................................................................................................. 26

11. TYPICAL APPLICATION CIRCUIT................................................................................................. 27

12. PACKAGING AND DIE INFORMATION......................................................................................... 30

12.1. 28-Lead 300-Mil Plastic Small Outline IC (SOIC)..................................................................... 30

12.2. 28-Lead 600-Mil Plastic Dual Inline Package (PDIP)............................................................... 31

12.3. 28-Lead 8x13.4mm Plastic Thin Small Outline Package (TSOP) Type 1................................ 32

12.4. Die Information ......................................................................................................................... 33

13. ORDERING INFORMATION........................................................................................................... 35

14. VERSION HISTORY ....................................................................................................................... 36

Publication Release Date: January 2004

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Revision 1.0

ISD4003 SERIES

5. PIN CONFIGURATION

1

2

3

4

28

27

26

25

SS

SCLK

V_CCD

XCLK

INT

MOSI

MISO

V_SSD

5

6

7

24

23

22

NC

RAC

V_SSA

NC

ISD4003

8

9

21

20

19

NC

10

11

12

18

17

V_SSA

V_CCA

ANA IN+

13

14

16

15

AUD OUT

AM CAP

ANA IN-

NC

SOIC / PDIP

V_SSA

NC

1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RAC

NC

V_CCA

NC

ANA IN+

ANA IN-

NC

INT

XCLK

V_CCD

AM CAP

NC

ISD4003

TSOP

SCLK

SS

AUD OUT

9

MOSI

NC

10

11

12

13

14

V_SSA

MISO

V_SSD

V_SSA

NC

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ISD4003 SERIES

6. PIN DESCRIPTION

PIN NAME

PIN NO.

FUNCTION

SOIC /

TSOP

PDIP

1

2

9

Slave Select: This input, when LOW, will select the

SS

ISD4003 device.

MOSI

10

Master Out Slave IN: This is the serial input to the

ISD4003 device when it is configured as slave. The master

microcontroller places data on the MOSI line one half-cycle

before the rising edge of SCLK for clocking into the device.

MISO

3

11

Master In Slave Out: This is the serial output (open drain)

of the ISD4003 device. This output goes into a high-

impedance state if the device is not selected.

V_SSA/ V_SSD

11, 12,

23 / 4

1, 17, 18 /

12

Ground: The ISD4003 series utilizes separate analog and

digital ground busses. The analog ground (V_SSA) pins

should be tied together as close as possible and connected

through a low-impedance path to power supply ground.

The digital ground (V_SSD) pin should be connected through

a separate low-impedance path to power supply ground.

These ground paths should be large enough to ensure that

the impedance between the V_SSApins and the V_SSDpin is

less than 3 Ω. The backside of the die is connected to V_SS

through the substrate. For chip-on-board design, the die

attach area must be connected to V_SSor left floating.

NC

5-10, 15,

19-22

3, 4, 13-

16, 19, 21,

23, 27, 28

Not connected

AUD OUT ^[1]

13

20

Audio Output: This pin provides an audio output of the

stored data and is recommended be AC coupled. It is

capable of driving a 5 KΩ impedance R_EXT

.

[1]

The AUD OUT pin is always at 1.2 volts when the device is powered up. When in playback, the output buffer

connected to this pin can drive a load as small as 5 KΩ. When in record, a built-in resistor connects AUD OUT to

the internal 1.2-volt analog ground supply. This resistor is approximately 850 KΩ, but will vary somewhat

according to the sample rate of the device. This relatively high impedance allows this pin to be connected to an

audio bus without loading it down.

Publication Release Date: January 2004

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Revision 1.0

ISD4003 SERIES

PIN NAME

PIN NO.

FUNCTION

SOIC /

TSOP

PDIP

AM CAP

14

22

AutoMute™ Feature: The AutoMute feature only applies

for playback operation and helps to minimize noise (with 6

dB of attenuation) when there is no signal (i.e. during

periods of silence). A 1 µF capacitor to ground is

recommended to connect to the AM CAP pin.

This capacitor becomes a part of an internal peak detector

which senses the signal amplitude. This peak level is

compared to an internally set threshold to determine the

AutoMute trip point. For large signals, the AutoMute

attenuation is set to 0 dB automatically but 6 dB of

attenuation occurs for silence. The 1 µF capacitor also

affects the rate at which the AutoMute feature changes with

the signal amplitude (or the attack time).

The AutoMute feature can be disabled by connecting the

AM CAP pin directly to V_CCA..

ANA IN-

16

24

Inverting Analog Input: This pin transfers the signal into

the device during recording via differential-input mode.

In this differential-input mode, a 16 mVp-p maximum input

signal should be capacitively coupled to ANA IN- for

optimal signal quality, as shown in Figure 1: ANA IN

Modes. This capacitor value should be equal to that used

on ANA IN+ pin. The input impedance at ANA IN- is

normally 56 KΩ.

In the single-ended mode, ANA IN- should be capacitively

coupled to V_SSAthrough a capacitor equal to that used on

the ANA IN+ pin.

ANA IN+

17

25

Non-Inverting Analog Input: This pin is the non-inverting

analog input that transfers the signal to the device for

recording. The analog input amplifier can be driven single

ended or differentially.

In the single-ended input mode, a 32 mVp-p (peak-to-peak)

maximum signal should be capacitively connected to this

pin for optimal signal quality. The external capacitor

associated with ANA IN+ together with the 3 KΩ input

impedance are selected to give cutoff at the low frequency

end of the voice passband.

In the differential-input mode, the maximum input signal at

ANA IN+ should be 16 mVp-p capacitively coupled for

optimal signal quality. The circuit connections for the two

modes are shown in Figure 1.

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ISD4003 SERIES

PIN NAME

PIN NO.

FUNCTION

SOIC /

TSOP

PDIP

V_CCA/ V_CCD

18 / 27

26 / 7

Supply Voltage: To minimize noises, the analog and digital

circuits in the ISD4003 devices use separate power

busses. These +3V busses are brought out to separate

pins and should be tied together as close to the supply as

possible. In addition, these supplies should be decoupled

as close to the package as possible.

RAC

24

2

Row Address Clock: This is an open drain output that

provides the signal of a ROW with a 200 ms period for 8

KHz sampling frequency. (This represents a single row of

memory.) This signal stays HIGH for 175 ms and stays

LOW for 25 ms when it reaches the end of a row.

The RAC pin stays HIGH for 109.37 µsec and stays LOW

for 15.63 µsec in Message Cueing mode (see Message

Cueing section for detailed description). Refer to the AC

Parameters table for RAC timing information at other

sample rates.

When a record command is first initiated, the RAC pin

remains HIGH for an extra T_RACLperiod. This is due to the

need of loading the internal sample and hold circuits in the

device. This pin can be used for message management

techniques.

A pull-up resistor is required to connect this pin to other

device.

25

5

Interrupt: This is an open drain output pin. This pin goes

LOW and stays LOW when an Overflow (OVF) or End of

Message (EOM) marker is detected. Each operation that

ends with an EOM or OVF will generate an interrupt. The

interrupt will be cleared the next time an SPI cycle is

initiated. The interrupt status can also be read by an R_INT

instruction.

INT

A pull-up resistor is required to connect this pin to other

device.

Overflow Flag (OVF) – The Overflow flag indicates that the

end of memory has been reached during a record or

playback operation.

End of Message (EOM) – The End of Message flag is set

only during playback operation when an EOM is found.

There are eight EOM flag position options per row.

Publication Release Date: January 2004

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Revision 1.0

ISD4003 SERIES

PIN NAME

PIN NO.

FUNCTION

SOIC /

TSOP

PDIP

XCLK

26

6

External Clock Input: The pin has an internal pull-down

device. The ISD4003 series is configured at the factory with

an internal sampling clock frequency centered to ±1

percent of specification. The frequency is then maintained

to a variation of ±2.25 percent over the entire commercial

temperature and operating voltage ranges. The internal

clock has a –6/+4 percent tolerance over the extended

temperature, industrial temperature and voltage ranges. A

regulated power supply is recommended for industrial

temperature range parts. If greater precision is required,

the device can be clocked through the XCLK pin as follows:

Part Number

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

Sample Rate

Required Clock

8.0 kHz

1024 kHz

6.4 kHz

819.2 kHz

682.7 kHz

512 kHz

5.3 kHz

4.0 kHz

These recommended clock rates should not be varied

because the anti-aliasing and smoothing filters are fixed.

Otherwise, aliasing problems can occur if the sample rate

differs from the one recommended. The duty cycle on the

input clock is not critical, as the clock is immediately

divided by two. If the XCLK is not used, this input must

be connected to ground.

SCLK

28

8

Serial Clock: This is the input clock to the ISD4003 device.

It is generated by the master device (typically

microcontoller) and is used to synchronize the data transfer

in and out of the device through the MOSI and MISO lines,

respectively. Data is latched into the ISD4003 on the rising

edge of SCLK and shifted out of the device on the falling

edge of SCLK.

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ISD4003 SERIES

Internal to the device

53K

Ω

0.1

F

ANA IN+

ANA IN-

3K

Ω

µ

Signal

32m Vp-p

-

To Filter

+

3K

Ω

53K

Ω

1.2V

Single-Ended Input Mode

Internal to the device

53K

Ω

0.1

F

ANA IN+

ANA IN-

3K

Ω

µ

Input Signal

16m Vp-p

-

To Filter

+

°

180

3K

Ω

53K

Ω

1.2V

Differential Input Mode

FIGURE 1: ISD4003 SERIES ANA IN MODES

T_RAC

(200 ms)

RAC

25 ms

T_RACL

FIGURE 2: RAC TIMING WAVEFORM DURING NORMAL OPERATION

(example of 8KHz sampling rate)

Publication Release Date: January 2004

Revision 1.0

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ISD4003 SERIES

7. FUNCTIONAL DESCRIPTION

7.1. DETAILED DESCRIPTION

Audio Quality

The Winbond’s ISD4003 ChipCorder^®series is offered at 8.0, 6.4, 5.3 and 4.0 kHz sampling

frequencies, allowing the user a choice of speech quality options. Increasing the sampling frequency

will produce better sound quality, but affects duration. Please refer to Table 1: Product Summary for

details.

Analog speech samples are stored directly into on-chip non-volatile memory without the digitization

and compression associated with other solutions. Direct analog storage provides higher quality

reproduction of voice, music, tones, and sound effects than other solid-state solutions.

Duration

The ISD4003 Series is a single-chip solution with 4-, 5-, 6-, and 8-minute duration.

TABLE 1: PRODUCT SUMMARY OF ISD4003 SERIES

Part Number

Duration

Sample Rate

Typical Filter Pass

(Minutes)

(kHz)

Band (kHz) *

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

4

5

6

8

8.0

6.4

5.3

4.0

3.4

2.7

2.3

1.7

* This is the –3dB point. This parameter is not checked during production testing and may vary due to process

variations and other factors. Therefore, the customer should not rely upon this value for testing purposes.

Flash Storage

The ISD4003 series utilizes on-chip Flash memory, providing zero-power message storage. The

message is retained for up to 100 years typically without power. In addition, the device can be re-

recorded typically over 100,000 times.

Memory Architecture

The ISD4003 series contains a total of 1,920K Flash memory cells, which is organized as 1,200 rows

of 1,600 cells each.

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ISD4003 SERIES

Microcontroller Interface

A four-wire (SCLK, MOSI, MISO & SS ) SPI interface is provided for controlling and addressing

functions. The ISD4003 is configured to operate as a peripheral slave device, with a microcontroller-

based SPI bus interface. Read and write operations are controlled through this SPI interface. An

interrupt signal (INT ) and internal read only Status Register are provided for handshake purposes.

Programming

The ISD4003 series is also ideal for playback-only applications, where single- or multiple-messages

playback is controlled through the SPI port. Once the desired message configuration is created,

duplicates can easily be generated via a programmer.

7.2. SERIAL PERIPHERAL INTERFACE (SPI) DESCRIPTION

The ISD4003 series operates via SPI serial interface with the following protocol.

First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on

the falling edge of the SCLK. However, for the ISD4003, the protocols are as follows:

1. All serial data transfers begin with the falling edge of SS pin.

2. SS is held LOW during all serial communications and held HIGH between instructions.

3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of

the SCLK signal, with LSB first.

4. Playback and record operations are initiated when the device is enabled by asserting the SS

pin LOW, shifting in an opcode and an address data to the ISD4003 device (refer to the

Opcode Summary in the following page).

5. The opcodes contain <11 address bits> and <5 control bits>.

6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt

will be cleared the next time a SPI cycle is initiated.

7. As Interrupt data is shifted out of the MISO pin, control and address data are simultaneously

shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible

with current system operation. Because it is possible to read an interrupt data and start a new

operation within the same SPI cycle.

8. An operation begins with the RUN bit set and ends with the RUN bit reset.

9. All operations begin after the rising edge of SS .

Publication Release Date: January 2004

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ISD4003 SERIES

7.2.1. OPCODES

The available Opcodes are summarized as follows:

TABLE 2: OPCODE SUMMARY

Instructions

OpCodes

Descriptions

Address (11 bits) Control bits (5 bits)

C0 C1 C2 C3 C4

POWERUP

0

1

0

Power-Up: Device will be ready for an operation after

T_PUD

.

SETPLAY

PLAY

SETREC

REC

0

1

0

1

0

1

Initiates playback from address <A0-A10>.

Playback from the current address (until EOM or OVF).

Initiates a record operation from address <A0-A10>.

Records from current address until OVF is reached or

Stop command is sent.

SETMC

MC ^[1]

1

0

1

Initiates Message Cueing (MC) from address <A0-

A10>.

Performs a Message Cueing from current location.

Proceeds to the end of message (EOM) or enters OVF

condition if no more messages are present.

STOP

0

X

1

0

X

0

Stops the current operation.

Stops the current operation and enters into standby

(power-down) mode.

STOPPWRDN <XXXXXXXXXXX>

RINT ^[2]

0

1

X

0

Read Interrupt status bits: Overflow and EOM.

Notes:

C0 = Message cueing

C1 = Ignore address bit

C2 = Master power control

C3 = Record or playback operation

C4 = Enable or disable an operation

^[1]Message Cueing can be selected only at the beginning of a playback operation.

[2]

As the Interrupt data is shifted out of the ISD4003, control and address data are being shifted in. Care should

be taken such that the data shifted in is compatible with current system operation. It is possible to read interrupt

data and start a new operation at the same time. See Figures 5 - 8 for references.

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ISD4003 SERIES

7.2.2. SPI Diagrams

MOSI

Input Shift Register

(Loaded to Row Counter

A0-A10

only if IAB = 0)

Select Logic

Row Counter

P0-P10

OVF EOM

MISO

Output Shift Register

FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM

The following diagram describes the SPI port and the control bits associated with it.

MISO

MOSI

OVF EOM P0

P1

A3

P2

A4

P3

A5

P4

A6

P5

A7

P6

A8

P7

P8

P9 P10

0

LSB

MSB

A0

A1

A2

A9 A10 C0

C1

C2

C3

C4

Message Cueing (MC)

Ignore Address Bit (IAB)

Power Up (PU)

Play/Record (P/R)

RUN

FIGURE 4: SPI PORT

Publication Release Date: January 2004

Revision 1.0

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ISD4003 SERIES

7.2.3. SPI Control and Output Registers

The SPI control register provides control of individual function such as play, record, message cueing,

power-up, power-down, start, stop and ignore address pointer operations.

TABLE 3: SPI CONTROL REGISTERS

Control Bit

C0

Control Register

MC

Bit

Device Function

Message Cueing function

=

1

0

Enable Message Cueing

Disable Message Cueing

Ignore Address bit

C1

C2

IAB ^[1]

PU

=

1

0

Ignore input address register (A0-A10)

Use the input address register (A0-A10)

Power Up

=

1

0

Power-Up

Power-Down

P/R

C3

C4

Playback or Record

Play

Record

=

1

0

RUN

Enable or Disable an operation

=

1

0

Start

Stop

Address Bits A0-A10

Input address register

TABLE 4: SPI OUTPUT REGISTERS

Output Bits Description

OVF

Overflow

EOM

End-of-Message

P0-P10

Output of the row pointer register

[1]

When IAB (Ignore Address Bit) is set to 0, a playback or record operation starts from address (A0-A10). For

consecutive playback or record, IAB should be changed to a 1 before the end of that row (see RAC timing).

Otherwise the ISD4003 will repeat the operation from the same row address. For memory management, the Row

Address Clock (RAC) signal and IAB can be used to move around the memory segments.

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ISD4003 SERIES

Message Cueing

Message cueing (MC) allows the user to skip through messages, without knowing the actual physical

location of the messages. It will stop when an EOM marker is reached. Then, the internal address

counter will point to the next message. Also, it will enter into OVF condition when it reaches the end of

memory. In this mode, the messages are skipped 1,600 times faster than the normal playback

mode.

Power-Up Sequence

The ISD4003 will be ready for an operation after power-up command is sent and followed by the T_PUD

timing (25 ms for 8 KHz sampling rate). Refer to the AC timing table for other T_PUDvalues with respect

to different sampling rates.

The following sequences are recommended for optimized Record and Playback operations.

Record Mode

1. Send POWERUP command.

2. Wait T_PUD(power-up delay).

3. Send POWERUP command.

4. Wait 2 x T_PUD(power-up delay).

5. a). Send SETREC command with address xx, or

b). Send REC command (recording from current location).

6. Send STOP command to stop recording.

7. Wait T_STOP/PAUSE.

For 3 & 4), please refer to Apps Brief 39A: recorded pop elimination in the ISD4000 series.

For 5.a), the device will start recording at address xx and will generate an interrupt when an overflow

(end of memory array) is reached, if no STOP command is sent before that. Then, it will automatic

stop recording operation.

Playback Mode

1. Send POWERUP command

2. Wait T_PUD(power-up delay)

3. a). Send SETPLAY command with address xx, or

b). Send PLAY command (playback from current location).

4. a). Send STOP command to halt the playback operation, or

b). Wait for playback operation to stop automatically, when an EOM or OVF is reached.

5. Wait T_STOP/PAUSE.

For 3.a), the device will start playback at address xx and it will generate an interrupt when an EOM or

OVF is reached. It will then stop playback operation.

Publication Release Date: January 2004

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Revision 1.0

ISD4003 SERIES

8. TIMING DIAGRAMS

T_SSH

SS

T_SSmin

T_SCKhi

T_SSS

SCLK

MOSI

T_DIH

T_SCKlow

T_DIS

T_PD

T_DF

(TRISTATE)

LSB

MISO

FIGURE 5: TIMING DIAGRAM

SS

SCLK

LSB

A8

A9

A10

C0

C1

C2

C3

C4

MOSI

LSB

OVF

EOM

P0

P1

P2

P3

P4

P5

MISO

FIGURE 6: 8-BIT COMMAND FORMAT

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ISD4003 SERIES

SS

SCLK

MOSI

LSB

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 C0 C1 C2 C3 C4

LSB

OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10

X

MISO

FIGURE 7: 16-BIT COMMAND FORMAT

SS

SCLK

MOSI

Stop

Play/Record

Data

MISO

T_STOP/PAUSE

(Rec)

ANA IN

T_STOP/PAUSE

(Play)

ANA OUT

FIGURE 8: PLAYBACK/RECORD AND STOP CYCLE

Publication Release Date: January 2004

Revision 1.0

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ISD4003 SERIES

9. ABSOLUTE MAXIMUM RATINGS

TABLE 5: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)

CONDITIONS

Junction temperature

VALUES

150°C

Storage temperature range

-65°C to +150°C

Voltage applied to any pin

(V_SS–0.3V) to (V_CC+0.3V)

(V_SS–1.0V) to (V_CC+1.0V)

(V_SS–1.0V) to 5.5V

Voltage applied to any pin (Input current limited to ±20mA)

Voltage applied to MOSI, SCLK, and SS pins

(Input current limited to ±20mA)

Lead temperature (soldering – 10 seconds)

V_CC– V_SS

300°C

-0.3V to +7.0V

TABLE 6: ABSOLUTE MAXIMUM RATINGS (DIE)

CONDITIONS

VALUES

150°C

Junction temperature

Storage temperature range

Voltage applied to any pad

-65°C to +150°C

(V_SS–0.3V) to (V_CC+0.3V)

(V_SS–1.0V) to (V_CC+1.0V)

(V_SS–1.0V) to 5.5V

Voltage applied to any pad (Input current limited to ±20 mA)

Voltage applied to MOSI, SCLK, and SS pins

(Input current limited to ±20mA)

V_CC– V_SS

-0.3V to +7.0V

Note: Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability and performance. Functional operation is not implied at these

conditions.

- 20 -

ISD4003 SERIES

9.1. OPERATING CONDITIONS

TABLE 7: OPERATING CONDITIONS (PACKAGED PARTS)

CONDITIONS

VALUES

0°C to +70°C

-20°C to +70°C

-40°C to +85°C

+2.7V to +3.3V

0V

Commercial operating temperature range (Case temperature)

Extended operating temperature (Case temperature)

Industrial operating temperature (Case temperature)

Supply voltage (V_CC) ^[1]

Ground voltage (V_SS) ^[2]

TABLE 8: OPERATING CONDITIONS (DIE)

CONDITIONS

Commercial operating temperature range

Supply voltage (V_CC) ^[1]

VALUES

0°C to +50°C

+2.7V to +3.3V

0V

Ground voltage (V_SS) ^[2]

[1]

V

= V_CCA= V_CCD

= V_SSA= V_SSD

CC

[2]

SS

Publication Release Date: January 2004

Revision 1.0

- 21 -

ISD4003 SERIES

10. ELECTRICAL CHARACTERISTICS

10.1. PARAMETERS FOR PACKAGED PARTS

TABLE 9: DC PARAMETERS

PARAMETERS

Input Low Voltage

Input High Voltage

Output Low Voltage

SYMBOLS

MIN^[2]

TYP^[1]

MAX^[2]

UNITS

CONDITIONS

V_IL

V_IH

V_OL

V_OL1

V_CCx 0.2

V

V_CCx 0.8

0.4

I_OL= 10 µA

I_OL= 1 mA

RAC, INT Output Low

Voltage

Output High Voltage

V_CCCurrent (Operating)

- Playback

- Record

V_CCCurrent (Standby)

Input Leakage Current

V_OH

I_CC

V_CC- 0.4

V

I_OH= -10 µA

15

25

1

30

40

10

mA

µA

R

_EXT= ∞ ^[3]

R_EXT= ∞ ^[3]

[3] [4]

I_SB

I_IL

µA

±1

MISO Tristate Current

I_HZ

1

10

µA

KΩ

dB

Output Load Impedance

ANA IN+ Input Resistance

ANA IN- Input Resistance

ANA IN+ or ANA IN- to AUD A_ARP

OUT Gain

R_EXT

R_{ANA IN+}

R_{ANA IN-}

5

2.2

40

3.0

56

23

3.8

71

32 mVpp 1 KHz

sinewave input ^[5]

Notes:

[1]

Typical values @ T_A= 25°C and V_CC= 3.0V.

All Min/Max limits are guaranteed by Winbond via electronical testing or characterization. Not all

specifications are 100 percent tested.

[2]

[3]

V_CCAand V_CCDconnected together.

[4]

[5]

SS = V_CCA= V_CCD, XCLK = MOSI = V_SSA= V_SSAand all other pins floating.

Measured with AutoMute feature disabled.

- 22 -

ISD4003 SERIES

TABLE 10: AC PARAMETERS (Packaged Parts)

CHARACTERISTIC

SYMBOLS

MIN^[2]

TYP^[1]

MAX^[2]

UNITS

CONDITIONS

Sampling Frequency

F_S

[5]

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

8.0

6.4

5.3

4.0

KHz

Filter Pass Band

F_CF

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

3.4

2.7

2.3

1.7

KHz

3 dB Roll-Off Point^[3][7]

Record Duration

T_REC

[6]

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

4

5

6

8

min

Playback Duration

T_PLAY

[6]

ISD4003-04M

ISD4003-05M

ISD4003-06M

ISD4003-08M

4

5

6

8

min

Power-Up Delay

T_PUD

ISD4003-04M

ISD4003-05M

25

31.25

37.5

50

msec

ISD4003-06M

ISD4003-08M

Stop or Pause in Record or Play

ISD4003-04M

T_STOPor T_PAUSE

50

62.5

75

msec

ISD4003-05M

ISD4003-06M

ISD4003-08M

100

RAC Clock Period

ISD4003-04M

T_RAC

[10]

200

250

300

400

msec

ISD4003-05M

ISD4003-06M

ISD4003-08M

RAC Clock Low Time

ISD4003-04M

T_RACL

25

31.25

37.5

50

msec

ISD4003-05M

ISD4003-06M

ISD4003-08M

RAC Clock Period in Message

Cueing Mode

T_RACM

ISD4003-04M

125

156.3

187.5

250

µsec

ISD4003-05M

ISD4003-06M

ISD4003-08M

RAC Clock Low Time in

Message Cueing Mode

ISD4003-04M

T_RACML

15.63

19.53

23.44

31.25

µsec

ISD4003-05M

ISD4003-06M

ISD4003-08M

Total Harmonic Distortion

ANA IN Input Voltage

THD

V_IN

1

2

%

32 mVpp 1 KHz

sinewave input ^[11]

32

mV

Peak-to-Peak ^{[4] [8] [9]}

Publication Release Date: January 2004

Revision 1.0

- 23 -

ISD4003 SERIES

Notes:

[1]

Typical values @ T_A= 25°C, V_CC= 3.0V and timing measurement at 50%.

[2]

All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

[3]

[4]

Low-frequency cutoff depends upon the value of external capacitors (see Pin Descriptions)

Single-ended input mode. In the differential input mode, V_INmaximum for ANA IN+ and ANA IN- is 16

mVp-p.

[5]

[6]

[7]

Sampling Frequency can vary as much as ±2.25 percent over the commercial temperature and voltage

ranges, and –6/+4 percent over the extended temperature, industrial temperature and voltage ranges.

For greater stability, an external clock can be utilized (see Pin Descriptions)

Playback and Record Duration can vary as much as ±2.25 percent over the commercial temperature and

voltage ranges, and –6/+4 percent over the extended temperature, industrial temperature and voltage

ranges. For greater stability, an external clock can be utilized (see Pin Descriptions)

Filter specification applies to the antialiasing filter and the smoothing filter. Therefore, from input to

output, expect a 6 dB drop by nature of passing through both filters.

The typical output voltage will be approximately 450 mVp-p with V_INat 32 mVp-p.

For optimal signal quality, this maximum limit is recommended.

When a record command is sent, T_RAC= T_RAC+ T_RACLon the first row address.

Measured with AutoMute feature disabled.

[8]

[9]

[10]

[11]

- 24 -

ISD4003 SERIES

10.2. PARAMETERS FOR DIE

TABLE 11: DC PARAMETERS

PARAMETERS ^[6]

SYMBOLS

MIN^[2]

TYP^[1]

MAX^[2]

UNITS

CONDITIONS

Input Low Voltage

Input High Voltage

Output Low Voltage

V_IL

V_IH

V_OL

V_OL1

V_CCx 0.2

V

V_CCx 0.8

0.4

I_OL= 10 µA

I_OL= 1 mA

RAC, INT Output Low

Voltage

Output High Voltage

Operating Current

-Playback

-Record

Standby Current

Total Harmonic Distortion

V_OH

I_CC

V_CC- 0.4

V

I_OH= -10 µA

15

25

1

30

40

10

2

mA

µA

%

R

_EXT= ∞ ^[3]

R_EXT= ∞ ^[3]

[3] [4]

I_SB

THD

1

32 mVpp 1 KHz

sinewave input ^[5]

32 mVpp 1 KHz

ANA IN+ or ANA IN- to AUD A_ARP

OUT Gain

23

dB

sinewave input ^[5]

Notes:

[1]

Typical values @ T_A= 25°C and V_CC= 3.0V. Sampling Frequency can vary as much as ±2.25 percent

over the commercial temperature and voltage ranges

[2]

All Min/Max limits are guaranteed by Winbond via electrical testing or characterization. Not all

specifications are 100 percent tested.

V_CCAand V_CCDconnected together.

[3]

[4]

SS = V_CCA= V_CCD, XCLK = MOSI = V_SSA= V_SSAand all other pins floating.

Measured with AutoMute feature disabled.

The test coverage for die is limited to room temperature testing. The test conditions may differ from that

of packaged parts.

[5]

[6]

Publication Release Date: January 2004

- 25 -

Revision 1.0

ISD4003 SERIES

10.3. SPI AC PARAMETERS

PARAMETER

TABLE 12: AC PARAMETERS^[1]

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

T_SSS

500

nsec

SS Setup Time

T_SSH

500

nsec

SS Hold Time

Data in Setup Time

Data in Hold Time

Output Delay

T_DIS

T_DIH

T_PD

T_DF

T_SSmin

200

nsec

µsec

500

Output Delay to HighZ ^[2]

1

SS HIGH

SCLK High Time

SCLK Low Time

CLK Frequency

T_SCKhi

T_SCKlow

F₀

400

nsec

KHz

1,000

Notes:

[1]

Typical values @ T_A= 25°C, V_CC= 3.0V and timing measurement at 50%.

Tri-state test condition.

[2]

V_CC

6.32K

Ω

MISO

10.91K

Ω

50pF (Includes scope and fixture capacitance)

- 26 -

ISD4003 SERIES

11. TYPICAL APPLICATION CIRCUIT

These application examples are for illustration purposes only. Winbond makes no representation or

warranty that such application will be suitable for production.

Make sure all bypass capacitors are as close as possible to the package.

C9

15-30 pF

C8

15-25 pF

V_CC

U₂

U₁

V_CCD

V_SSD

39

38

29

30

31

32

33

34

3

2

28

1

27

4

OCS1

OCS2

PD0/RDI

MISO

MOSI

SCLK

SS

R7

µ

C2 0.22

F

Ω

10 K

PD1/TD0

PD2/MISO

PD3/MOSI

PD4/SCK

PD5/SS

C1

47

1

2

RESET

IRQ

F

µ

18

23

12

11

13

V_CCA

V_SSA

µ

C3 0.22

37

35

28

27

26

25

24

23

22

21

TCAP

PC0

PC1

PC2

PC3

PC4

PC5

C4

C11

1 µF

µ

0.1

F

J1

16

3

2

4

5

1

ANA IN- AUD OUT

ISD4003

LINE OUT

C10

TCMP

R2

1M

µ

^F17

0.1

ANA IN+

V_CC

R1

10K

68HC705C8P^PC6

24

25

PC7

RAC

14

AM CAP

R4

R3 100

100K POT

12

13

14

15

16

17

18

19

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

INT

1

R6

3

C5

Ω

47 K

1µF

2

U₃

11

10

9

26

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PD7

XCLK

13

11

-IN

GAIN-OUT

V01

J4

3

2

4

5

1

10

14

+IN

EXT

8

SPEAKER

15

12

V02

V_DD

PDIP / SOIC

V_CC

5

BYPASS

7

6

7

HP-IN1

HP-IN2

C6

C7

µ

1

F

1

4

8

9

GND

µ

F

.1

5

4

3

2

HPSENSE

R5

Ω

47 K

SHUTDOWN

16

LM4860M

FIGURE 9: APPLICATION EXAMPLE USING SPI

Publication Release Date: January 2004

Revision 1.0

- 27 -

ISD4003 SERIES

V_CC

U₂

U₁

3

22

27

4

MISO

V_CCD

D3

23

24

GND

µ

C2 0.22

F

2

28

1

21

20

19

MOSI

SCLK

SS

D2

D1

D0

V_SSD

C1

47

F

µ

28

27

26

G3

G2

G1

18

23

V_CCA

V_SSA

RESET

C3 0.22µ

12

11

V_SSA

INT 25

3

C4

SI

SK

G7

SO

C9

µ

1

F

µ

0.1

F

J1

16

13

2

4

1

3

2

4

5

1

ANA IN-

AUD OUT

V_CC

COP 820C

LINE OUT

ISD4003

6

V_CC

R2

1M

C8

µ

0.1

L7

L6

L5

L4

^F17

24

18

17

16

ANA IN+

RAC

R1

10K

R7

R4

R3 100

Ω

3.3 K

14

100K POT

AM CAP

1

3

5

7

8

15

CLI

10

C5

2

U₃

14

13

L3

L2

L1

L0

25

26

1µ F

INT

13

11

-IN

GAIN-OUT

V01

11

J4

3

2

4

5

1

10

14

+IN

C10

82 pF

EXT

9

12

11

12

13

V_CC

SPEAKER

XCLK

V_CC

15

12

V02

V_DD

5

10

BYPASS

6

7

HP-IN1

HP-IN2

C6

R6

4.7 K

C7

µ

1

F

R5

4.7 K

Ω

1

4

8

9

GND

µ

F

.1

Ω

3

2

HPSENSE

PDIP / SOIC

SHUTDOWN

16

LM4860M

FIGURE 10: APPLICATION EXAMPLE USING MICROWIRE

- 28 -

ISD4003 SERIES

V_CC

U₂

U₁

3

22

27

4

MISO

V_CCD

D3

23

24

GND

µ

C2 0.22

F

2

28

1

21

20

19

MOSI

SCLK

SS

D2

D1

D0

V_SSD

C1

47

F

µ

28

27

26

G3

G2

G1

18

23

V_CCA

V_SSA

RESET

C3 0.22µ

12

11

V_SSA

INT 25

3

C4

SI

SK

G7

SO

C9

µ

1

F

µ

0.1

F

J1

16

13

2

4

1

3

2

4

5

1

ANA IN-

AUD OUT

V_CC

COP 820C

LINE OUT

ISD4003

6

V_CC

R2

1M

C8

µ

0.1

L7

L6

L5

L4

^F17

24

18

17

16

ANA IN+

RAC

R1

10K

R7

R4

R3 100

Ω

3.3 K

14

100K POT

AM CAP

1

3

5

7

8

15

CLI

10

C5

2

U₃

14

13

L3

L2

L1

L0

25

26

1µ F

INT

13

11

-IN

GAIN-OUT

V01

11

J4

3

2

4

5

1

10

14

+IN

C10

82 pF

EXT

9

12

11

12

13

V_CC

SPEAKER

XCLK

V_CC

15

12

V02

V_DD

5

10

BYPASS

6

7

HP-IN1

HP-IN2

C6

R6

4.7 K

C7

µ

1

F

R5

4.7 K

Ω

1

4

8

9

GND

µ

F

.1

Ω

3

2

HPSENSE

PDIP / SOIC

SHUTDOWN

16

LM4860M

FIGURE 11: APPLICATION EXAMPLE USING SPI PORT ON MICROCONTROLLER

Publication Release Date: January 2004

Revision 1.0

- 29 -

ISD4003 SERIES

12. PACKAGING AND DIE INFORMATION

12.1. 28-LEAD 300-MIL PLASTIC SMALL OUTLINE IC (SOIC)

28

1

26 25

23 22 21 20 19 18 17

15

16

27

2

24

5

3

4

6 7

9 10 11 12 13 14

8

A

G

C

B

D

F

E

H

INCHES

Nom

MILLIMETERS

Nom

Min

Max

0.711

0.104

0.299

0.0115

0.019

Min

17.81

2.46

7.42

0.127

0.35

Max

18.06

2.64

7.59

0.29

0.48

A

B

C

D

E

F

0.701

0.097

0.292

0.005

0.014

0.706

0.101

0.296

0.009

0.016

0.050

0.406

0.032

17.93

2.56

7.52

0.22

0.41

1.27

10.31

0.81

G

H

0.400

0.024

0.410

0.040

10.16

0.61

10.41

1.02

Note: Lead coplanarity to be within 0.004 inches.

- 30 -

ISD4003 SERIES

12.2. 28-LEAD 600-MIL PLASTIC DUAL INLINE PACKAGE (PDIP)

INCHES

MILLIMETERS

Min

1.445

Nom

1.450

0.150

0.070

Max

1.455

Min

36.70

Nom

36.83

3.81

Max

36.96

A

B1

B2

C1

C2

D

0.065

0.600

0.530

0.075

0.625

0.550

0.19

1.65

15.24

13.46

1.78

1.91

15.88

13.97

4.83

0.540

13.72

D1

E

F

G

H

J

S

q

0.015

0.125

0.015

0.055

0.38

3.18

0.38

1.40

0.135

0.022

0.065

3.43

0.56

1.62

0.018

0.060

0.100

0.010

0.075

0.46

1.52

2.54

0.25

1.91

0.008

0.070

0°

0.012

0.080

15°

0.20

1.78

0°

0.30

2.03

15°

Publication Release Date: January 2004

Revision 1.0

- 31 -

ISD4003 SERIES

12.3. 28-LEAD 8X13.4MM PLASTIC THIN SMALL OUTLINE PACKAGE (TSOP) TYPE 1

A

B

G

1

2288

2

7

3

26

3

25

4

F

5

24

5

23

6

23

6

22

7

22

7

21

C

8

21

8

20

9

19

10

18

11

18

11

17

12

17

12

13

16

13

15

14

15

14

E

D

J

H

J

H

I

INCHES

Nom

0.528

0.465

0.315

MILLIMETERS

Nom

Min

Max

Min

Max

13.60

11.90

8.10

0.15

0.27

A

0.520

0.461

0.311

0.002

0.007

0.535

0.469

0.319

0.006

0.011

13.20

11.70

7.90

0.05

0.17

13.40

11.80

8.00

B

C

D

E

F

G

H

I

0.009

0.0217

0.039

3°

0.22

0.55

1.00

3°

0.037

0°

0.041

6°

0.95

0°

1.05

6°

0.020

0.004

0.022

0.028

0.008

0.50

0.10

0.55

0.70

0.21

J

Note: Lead coplanarity to be within 0.004 inches.

- 32 -

ISD4003 SERIES

12.4. DIE INFORMATION

ISD4003 Series

o

Die Dimensions (with scribe line) ^[1]

V_CCD

MOSI

MISO

SCLK

SS

X: 166.6 ± 1 mils

Y: 274.9 ± 1 mils

V_SSD

INT

RAC

V_CCD

XCLK

V_SSA

o

Die Thickness ^[2]

11.5 ± 0.5 mils

Pad Opening

Single pad: 90 x 90 microns

Double pad: 180 x 90 microns

ISD4003

≈

[3]

V_SSA

V_CCA

AUD OUT

AM CAP

ANA IN-

ANA IN+

[3]

V_SSA

V_CCA

V_SSA

Notes:

[1]

The backside of die is internally connected to V_SS. It MUST NOT be connected to any other potential or

damage may occur.

[2]

[3]

Die thickness is subject to change, please contact Winbond as this thickness may change in the future.

Double bond is recommended if treated as one pad.

Publication Release Date: January 2004

- 33 -

Revision 1.0

ISD4003 SERIES

ISD4003 SERIES PAD COORDINATIONS

(with respect to die center)

Pad

Pad Description

Analog Ground

X Axis (µm)

1885.2

Y Axis (µm)

3273.7

V_SSA

RAC

Row Address Clock

Interrupt

1483.8

794.8

3273.7

INT

XCLK

V_CCD

SCLK

External Clock Input

Digital Power Supply

Slave Clock

564.8

384.9

169.5

-14.7

3273.7

Slave Select

-198.1

SS

MOSI

MISO

V_SSD

Master Out Slave In

Master In Slave Out

Digital Ground

Analog Ground

Audio Output

AutoMute

Inverting Analog Input

Noninverting Analog Input

Analog Power Supply

-1063.7

-1325.6

-1665.3

-1836.9

-1943.1

-1853.1

-1599.9

281.9

3273.7

-3272.4

[1]

V_SSA

[1]

AUD OUT

AM CAP

ANA IN-

ANA IN+

577.3

1449.3

1603.5

1853.7

1943.7

[1]

V_CCA

[1]

Note:

[1]

Double bond recommended if treated as one pad.

- 34 -

ISD4003 SERIES

13. ORDERING INFORMATION

ISD4003-

Product Family :

Special Temperature Field :

ISD4000 Family

Blank = Commercial Package (0°C to + 70°C)

or Commercial Die (0°C to + 50°C)

Product Series :

D

I

=

Extended (-20°C to + 70°C)

Industrial (-40°C to + 85°C)

03

=

Third Series (4-8 min)

Duration :

Packaged Units / Die :

X

P

=

Die

04M

05M

06M

08M

=

4 minutes

5 minutes

6 minutes

8 minutes

28-Lead 600-mil Plastic Dual Inline

Package (PDIP)

28-Lead 300-mil Plastic Small Outline

Package (SOIC)

28-Lead 8x13.4mm Plastic Thin Small

Outline Package (TSOP) Type 1

S

E

=

When ordering ISD4003 Series devices, please refer to the following valid part numbers.

Die / Package

Die

PDIP

Part Number

ISD4003-04MX

ISD4003-04MP

ISD4003-04MS

ISD4003-04MSI

ISD4003-04ME

ISD4003-05MX

ISD4003-06MX

ISD4003-06MP

ISD4003-06MS

ISD4003-06MSI

ISD4003-06ME

ISD4003-08MX

ISD4003-08MP

ISD4003-08MS

ISD4003-08MSI

ISD4003-08ME

ISD4003-05MP

ISD4003-05MS

ISD4003-05MSI

ISD4003-05ME

SOIC

TSOP

ISD4003-04MED ISD4003-05MED ISD4003-06MED ISD4003-08MED

ISD4003-04MEI ISD4003-05MEI ISD4003-06MEI ISD4003-08MEI

For the latest product information, access Winbond worldwide website at http://www.winbond-usa.com

Publication Release Date: January 2004

- 35 -

Revision 1.0

ISD4003 SERIES

14. VERSION HISTORY

VERSION

DATE

DESCRIPTION

0

1.0

June 2000 Initial version

Jan. 2004 Reformat the document.

Add note for typical filter pass band.

Add memory architecture description.

Remove all CSP info.

Revise RAC timing parameter for MC.

Revise AutoMute: playback only.

Revise SPI, opcodes sections, record & playback steps.

Rename T_RACLOto T_RACL

.

Revise A_ARPparameter.

Revise DC & AC parameters tables for die.

Revise die: (x,y) coordinates.

Figures 9-11: revise V_CCAand V_CCDpin #.

Revise Ordering Information.

- 36 -

ISD4003 SERIES

The contents of this document are provided only as a guide for the applications of Winbond products. Winbond

makes no representation or warranties with respect to the accuracy or completeness of the contents of this

publication and reserves the right to discontinue or make changes to specifications and product descriptions at

any time without notice. No license, whether express or implied, to any intellectual property or other right of

Winbond or others is granted by this publication. Except as set forth in Winbond's Standard Terms and

Conditions of Sale, Winbond assumes no liability whatsoever and disclaims any express or implied warranty of

merchantability, fitness for a particular purpose or infringement of any Intellectual property.

Winbond products are not designed, intended, authorized or warranted for use as components in systems or

equipments intended for surgical implantation, atomic energy control instruments, airplane or spaceship

instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other

applications intended to support or sustain life. Furthermore, Winbond products are not intended for applications

wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe

property or environmental injury could occur.

Application examples and alternative uses of any integrated circuit contained in this publication are for illustration

only and Winbond makes no representation or warranty that such applications shall be suitable for the use

specified.

ISD^®and ChipCorder^®are trademarks of Winbond Electronics Corporation.

The 100-year retention and 10K record cycle projections are based upon accelerated reliability tests, as published

in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product

incorporates SuperFlash^®technology licensed from SST.

Information contained in this ISD^®ChipCorder^®data sheet supersedes all data for the ISD ChipCorder products

published by ISD^®prior to August, 1998.

This data sheet and any future addendum to this data sheet is(are) the complete and controlling ISD^®ChipCorder^®

product specifications. In the event any inconsistencies exist between the information in this and other product

documentation, or in the event that other product documentation contains information in addition to the information

in this, the information contained herein supersedes and governs such other information in its entirety.

trademark of Winbond. All other trademarks are properties of their respective owners.

Headquarters

Winbond Electronics Corporation America

Winbond Electronics (Shanghai) Ltd.

No. 4, Creation Rd. III

Science-Based Industrial Park,

Hsinchu, Taiwan

2727 North First Street, San Jose,

CA 95134, U.S.A.

27F, 299 Yan An W. Rd. Shanghai,

200336 China

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62356998

TEL: 886-3-5770066

FAX: 1-408-5441797

FAX: 886-3-5665577

http://www.winbond-usa.com/

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

Winbond Electronics (H.K.) Ltd.

9F, No. 480, Pueiguang Rd.

Neihu District

7F Daini-ueno BLDG. 3-7-18

Shinyokohama Kohokuku,

Yokohama, 222-0033

TEL: 81-45-4781881

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

Taipei, 114 Taiwan

TEL: 886-2-81777168

FAX: 886-2-87153579

TEL: 852-27513100

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

Publication Release Date: January 2004

Revision 1.0

- 37 -


型号：	ISD4003-04MSI
厂家：	WINBOND
描述：	Speech Synthesizer With RCDG, 240s, CMOS, PDSO28, 0.1200 INCH, PLASTIC, SOIC-28 CD 光电二极管商用集成电路
文件：	总37页 (文件大小：335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISD4003-04MSI [WINBOND]

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