W19B160BBBBH [WINBOND]
Flash, 1MX16, 11ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48;
| 型号： | W19B160BBBBH |
| 厂家： | 
WINBOND |
| 描述： | Flash, 1MX16, 11ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, LEAD FREE, TFBGA-48 |
| 文件： | 总48页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W19B160BT/B DATA SHEET
-Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES................................................................................................................................. 4
PIN CONFIGURATIONS ............................................................................................................ 6
BLOCK DIAGRAM ...................................................................................................................... 7
PIN DESCRIPTION..................................................................................................................... 8
FUNCTIONAL DESCRIPTION ................................................................................................... 9
6.1
DEVICE BUS OPERATION............................................................................................ 9
6.1.1 Word/Byte Configuration...................................................................................................9
6.1.2 Reading Array Data..........................................................................................................9
6.1.3 Writing Commands/Command Sequences.......................................................................9
6.1.4 Program and Erase Operation Status...............................................................................9
6.1.5 Standby Mode ..................................................................................................................9
6.1.6 Automatic Sleep Mode ...................................................................................................10
6.1.7 #RESET: Hardware Reset Pin........................................................................................10
6.1.8 Output Disable Mode......................................................................................................10
6.1.9 Auto-select Mode............................................................................................................10
6.1.10 Sector Protection and Un-protection.............................................................................11
6.1.11 Temporary Sector Unprotect ........................................................................................11
6.1.12 Hardware Data Protection ............................................................................................11
6.1.13 Write Pulse “Glitch” Protection......................................................................................11
6.1.14 Logical Inhibit................................................................................................................11
6.1.15 Power-Up Write Inhibit..................................................................................................11
6.2
COMMAND DEFINITIONS........................................................................................... 12
6.2.1 Reading Array Data........................................................................................................12
6.2.2 Reset Command.............................................................................................................12
6.2.3 Auto-select Command Sequence...................................................................................12
6.2.4 Byte/Word Program Command Sequence......................................................................13
6.2.5 Chip Erase Command Sequence ...................................................................................13
6.2.6 Sector Erase Command Sequence ................................................................................13
6.2.7 Erase Suspend /Erase Resume Commands ..................................................................14
6.2.8 Unlock Bypass Command Sequence .............................................................................14
6.3
WRITE OPERATION STATUS..................................................................................... 15
6.3.1 DQ7: #Data Polling.........................................................................................................15
6.3.2 RY/#BY: Ready/#Busy....................................................................................................15
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6.3.3 DQ6: Toggle Bit..............................................................................................................16
6.3.4 DQ2: Toggle Bit II...........................................................................................................16
6.3.5 Reading Toggle Bits DQ6/DQ2.......................................................................................16
6.3.6 DQ3: Sector Erase Timer ...............................................................................................17
6.3.7 DQ5 : Exceeded Timing Limits .......................................................................................17
7.
8.
SPECIAL CHARACTERISTIC .................................................................................................. 17
TABLE OF OPERATION MODES ............................................................................................ 18
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Device Bus Operations................................................................................................. 18
Sector Address Table (Top Boot Block) ....................................................................... 19
Sector Address Table (Bottom Boot Block).................................................................. 20
CFI Query Identification String...................................................................................... 21
System Interface String ................................................................................................ 21
Device Geometry Definition.......................................................................................... 22
Primary Vendor-Specific Extended Query.................................................................... 23
Command Definitions ................................................................................................... 24
Write Operation Status ................................................................................................. 25
8.10 Temporary Sector Unprotect Algorithm........................................................................ 26
8.11 In-System Sector Protect/Unprotect Algorithms........................................................... 27
8.12 Program Algorithm........................................................................................................ 28
8.13 Erase Algorithm ............................................................................................................ 28
8.14 Data Polling Algorithm .................................................................................................. 29
8.15 Toggle Bit Algorithm ..................................................................................................... 30
ELECTRICAL CHARACTERISTICS......................................................................................... 31
9.
9.1
9.2
9.3
9.4
Absolute Maximum Ratings.......................................................................................... 31
Operating Ranges......................................................................................................... 31
DC CHARACTERISTICS.............................................................................................. 32
AC CHARACTERISTICS.............................................................................................. 33
9.4.1 Test Condition ................................................................................................................33
9.4.2 AC Test Load and Waveforms........................................................................................33
9.4.3 Read-Only Operations....................................................................................................34
9.4.4 Read-Only Operations....................................................................................................34
9.4.5 Hardware Reset (#RESET) ............................................................................................35
9.4.6 Word/Byte Configuration (#BYTE)..................................................................................35
9.4.7 Erase and Program Operation........................................................................................36
9.4.8 Temporary Sector Unprotect ..........................................................................................36
9.4.9 Alternate #CE Controlled Erase and Program Operation ...............................................37
10.
TIMING WAVEFORMS............................................................................................................. 38
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10.1 AC Read Waveform...................................................................................................... 38
10.2 Reset Waveform........................................................................................................... 38
10.3 #BYTE Waveform for Read Operation ......................................................................... 39
10.4 #BYTE Waveform for Write Operation ......................................................................... 39
10.5 Programming Waveform............................................................................................... 40
10.6 Chip/Sector Erase Waveform....................................................................................... 40
10.7 #Data Polling Waveform (During Embedded Algorithms)............................................ 41
10.8 Toggle Bit Waveform (During Embedded Algorithms) ................................................. 41
10.9 Temporary Sector Unprotect Timing Diagram.............................................................. 42
10.10
10.11
Sector Protect and Unprotect Timing Diagram ........................................................ 42
Alternate #CE Controlled Write (Erase/Program) Operation Timing ....................... 43
11.
12.
13.
14.
15.
LATCHUP CHARACTERISTICS .............................................................................................. 44
CAPACITANCE......................................................................................................................... 44
ORDERING INFORMATION .................................................................................................... 45
PACKAGE DIMENSIONS......................................................................................................... 46
VERSION HISTORY................................................................................................................. 48
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W19B160BT/B DATA SHEET
1. GENERAL DESCRIPTION
The W19B160B is a 16Mbit, 2.7~3.6 volt CMOS flash memory organized as 2M × 8 or 1M × 16 bits.
For flexible erase capability, the 16Mbits of data are divided into one 16Kbyte, two 8Kbyte, one
32Kbyte, and thirty-one 64Kbyte sectors. The word-wide (× 16) data appears on DQ15-DQ0, and
byte-wide (× 8) data appears on DQ7−DQ0. The device can be programmed and erased in-system
with a standard 2.7~3.6V power supply. A 12-volt VPP is not required. The unique cell architecture of
the W19B160B results in fast program/erase operations with extremely low current consumption. The
device can also be programmed and erased by using standard EPROM programmers.
2. FEATURES
Performance
•
•
2.7~3.6-volt write (program and erase) operations
Fast write operation
− Sector erase time: 0.7s (Typical)
− Chip erases time: 25 s (Typical)
− Byte/Word programming time: 5/7 µs (Typical)
Read access time: 70 ns
•
•
Typical program/erase cycles:
− 100K
•
•
Twenty-year data retention
Ultra low power consumption
− Active current (Read): 9mA (Typical)
− Active current (Program/erase): 20mA (Typical)
− Standby current: 0.2 μA (Typical)
Architecture
•
Sector erases architecture
− One 16Kbyte, two 8Kbyte, one 32Kbyte, and thirty-one 64Kbyte sectors
− Top or bottom boot block configurations available
− Supports full chip erase
•
•
•
JEDEC standard byte-wide and word-wide pin-outs TTL compatible I/O
Manufactured on WinStack-S 0.13µm process technology
Available packages: 48-pin TSOP and 48-ball TFBGA (6x8mm)
Software Features
•
Compatible with common Flash Memory Interface (CFI) specification
− Flash device parameters stored directly on the device
− Allows software driver to identify and use a variety of different current and future Flash products
End of program detection
•
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W19B160BT/B DATA SHEET
− Software method: Toggle bit/Data polling
•
•
Erase Suspend /Erase Resume
− Suspend an erase operation to read data or program data.
− Resume erase suspend operation.
Unlock bypass program command
− Allows the system to program bytes or words to device faster than standard program command.
Hardware Features
•
•
•
Ready/#Busy output (RY/#BY)
− Detect program or erase cycle completion
Hardware reset pin (#RESET)
− Reset the internal state machine to the read mode
Sector Protection
− Sectors can be locked in-system or via programmer
− Temporary Sector Unprotect allows changing data in protected sectors in-system
Temperature range
•
•
Extended temperature range (-20℃ to 85 ℃)
Industrial devices ambient temperature(-40℃ to +85℃)
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3. PIN CONFIGURATIONS
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4. BLOCK DIAGRAM
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5. PIN DESCRIPTION
SYMBOL
PIN NAME
Address Inputs
A0−A19
Data Inputs/Outputs
Word mode
DQ0−DQ14
DQ15 is Data Inputs/Outputs
A-1 is Address input
DQ15/A-1
Byte mode
#CE
Chip Enable
#OE
Output Enable
Write Enable
#WE
#BYTE
#RESET
RY/#BY
VDD
Byte Enable Input
Hardware Reset
Ready/Busy Status
Power Supply
Ground
VSS
NC
No Connection
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6. FUNCTIONAL DESCRIPTION
6.1 DEVICE BUS OPERATION
6.1.1 Word/Byte Configuration
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.
When the #BYTE pin is ‘1’, the device is in word configuration; DQ15-DQ0 are active and controlled
by #CE and #OE.
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ7-DQ0 are
active and controlled by #CE and #OE. The data I/O pins DQ8-DQ14 are tri-stated, and the DQ15 pin
is used as an input for the LSB (A-1) address function.
6.1.2 Reading Array Data
To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power
control and used to select the device. #OE is the output control gates array data to the output pins.
#WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in words or
bytes.
The internal state machine is set for reading array data when device power-up, or after hardware
reset. This ensures that no excess modification of the memory content occurs during the power
transition. In this mode there is no command necessary to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until the command register contents are
changed.
6.1.3 Writing Commands/Command Sequences
In writhing a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH.
For program operations, the #BYTE pin determines the device accepts program data whether in bytes
or in words. Refer to “Word/Byte Configuration” for more information.
The erase operation can erase a sector, multiple sectors, even the entire device. The “sector address”
is the address bits required to solely select a sector.
6.1.4 Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading
the status bits on DQ7 – DQ0. Refer to “Write Operation Status” and “AC Characteristics” for more
information.
6.1.5 Standby Mode
When the system is not reading or writing to the device, the device will be in a standby mode. In this
mode, current consumption is greatly reduced, and the outputs are in the high impedance state,
independent from the #OE input.
When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS
standby mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are
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held at VIH, but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current
will be greater. The device requires standard access time (tCE) for read access when the device is in
either of these standby modes, before it is ready to read data.
When the device is deselected during erasing or programming, the device initiates active current until
the operation is completed.
6.1.6 Automatic Sleep Mode
The automatic sleep mode minimizes device's energy consumption. When addresses remain stable
for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is
independent from the #CE #WE and #OE control signals. Standard address access timings provide
,
,
new data when addresses are changed. In sleep mode, output data is latched and always available to
the system.
6.1.7 #RESET: Hardware Reset Pin
The #RESET pin provides a hardware method to reset the device to reading array data. When the
#RESET pin is set to low for at least a period of tRP, the device will immediately terminate every
operations in progress, tri-states all output pins, and ignores all read/write commands for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data mode.
To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to
accept another command sequence.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at Vss ± 0.3V, the
device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within Vss ± 0.3V,
the standby current will be greater.
The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the
device, enabling the system to read the boot-up firmware from the device.
If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until
the internal reset operation is complete. If #RESET is asserted when a program or erase operation is
not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during
Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.
6.1.8 Output Disable Mode
When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high
impedance state.
6.1.9 Auto-select Mode
The auto select mode offers manufacturer and device identification, as well as sector protection
verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the auto select codes can also be accessed in-system through the
command register.
When using programming equipment , the auto select mode requires VID (8.5 V to 11.5 V) on address
pins A9. Address pins A6, A1, and A0 must be as shown in auto select table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
bits. When all necessary bits have been set as required, the programming equipment may then read
the corresponding identifier code on DQ7-DQ0.
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W19B160BT/B DATA SHEET
To access the auto select codes in-system, the host system can issue the auto select command
through the command register. This method does not require VID. Also refer to the auto select
Command Sequence section for more information.
6.1.10 Sector Protection and Un-protection
The sector protection feature will disable both program and erase operations in any sectors. The
sector un-protection feature will re-enables both program and erase operations in previously protected
sectors. Sector protection / un-protection can be implemented through two methods.
The primary method requires VID on the #RESET pin, and can be implemented either in-system or
through programming equipment. This method uses standard microprocessor bus cycle timing.
The alternate method intended only for programming equipment requires VID on address pin A9 and
#OE It is possible to determine whether a sector is protected or unprotected. See the auto select
Mode section for details.
6.1.11 Temporary Sector Unprotect
This feature allows temporary un-protection of previously protected sectors to change data in-system.
When the #RESET pin is set to VID, the Sector Unprotect mode is activated. During this mode,
formerly protected sectors can be programmed or erased by selecting the sector addresses. What if
VID is removed from the #RESET pin, all the previously protected sectors are protected again.
6.1.12 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
6.1.13 Write Pulse “Glitch” Protection
Noise pulses, which is less than 5nS (typical) on #OE, #CE or #WE, do not initiate a write cycle.
6.1.14 Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
6.1.15 Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
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6.2 COMMAND DEFINITIONS
The device operation can be initiated by writing specific address and data commands or sequences
into the command register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
6.2.1 Reading Array Data
After device power-up, it is automatically set to reading array data. There is no commands are
required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, the
device is ready to read array data.
The system must initiate the reset command to return the device to read mode if DQ5 goes high
during an active program or erase operation; otherwise, the device is in the auto select mode. See
Reset Command section and Requirements for Reading Array Data in the Device Bus Operations
section for more information.
6.2.2 Reset Command
The device will be to the read when writing the reset command. For this command, the address bits
are Don’t Care.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to which the system was writing to the read mode. Once
erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the device, to which the system was writing to the read mode.
The reset command may be written between the sequence cycles in an auto select command
sequence. When in the auto select mode, the reset command must be written to return to the read
mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the
device to the read mode.
6.2.3 Auto-select Command Sequence
The auto select command sequence provides the host system to access the manufacturer and device
codes, and determine whether a sector is protected or not. This is an alternative method, which is
intended for PROM programmers and requires VID on address pin A9. The auto select command
sequence may be written to an address within the device that is in the read mode. When the device is
actively programming or erasing, the auto select command may not be written.
The first writing two unlock cycles initiate the auto select command sequence. This is followed by a
third write cycle that contains the auto select command. The device then enters into the auto select
mode. The system may read at any address without initiating another auto select command sequence:
•
•
•
A read cycle at address XX00h returns the manufacturer code.
A read cycle at address XX01h in word mode (or XX02h in byte mode) returns the device code.
A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in
word mode (or the address 04h in byte mode) returns 01h if the sector is protected, or 00h if it is
unprotected.
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To return to read mode and exit the auto select mode, the system must write the reset command.
6.2.4 Byte/Word Program Command Sequence
The device can be programmed either by word or byte, which depending on the state of the #BYTE
pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by
writing two unlock write cycles, followed by the program setup command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The device automatically
provides internally generated program pulses and verifies the programmed cell margin.
Once the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please
note that a hardware reset will immediately stop the program operation. The program command
sequence should be reinitiated when the device has returned to the read mode, in order to ensure
data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that device to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can change “0” to “1.”
6.2.5 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7,
DQ6, or RY/#BY. Please refer to the Write Operation Status section for information on these status
bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when the device has returned to reading array data.
6.2.6 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase
command sequence, which is followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations is not required in system.
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As the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. Please refer to the Write Operation Status section for information on
these status bits.
However, a hardware reset shall terminate the erase operation immediately. If this occurs, to ensure
data integrity, the sector erase command sequence should be reinitiated once the device has returned
to reading array data.
6.2.7 Erase Suspend /Erase Resume Commands
The Erase Suspend Command allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected for erasure. This command is valid only during
the sector erase operation, including the 50us time out period during the sector erase command
sequence. The Erase Suspend Command is ignored if written during the chip erase operation or
embedded program algorithm. Writing the Erase Suspend Command during the Sector Erase time-out
immediately terminals the time-out period and suspends the erase operation. Addresses are as don’t
cares when writer the Erase Suspend Command.
When the Erase Suspend Command is written during a sector erase operation, the device requires a
maximum of 20us to suspend the erase operation. However, when the Erase Suspend Command is
written during the sector erase time-out, the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspended, the system can read array data from or program data
to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and writes timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation
Status for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using
the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for
more information.
The system may also write the auto-select command sequence when the device is in the erase
suspend mode. The device allows reading auto-select codes even at addresses within erasing
sectors, since the codes are not stored in the memory array. When the device exits the auto-select
mode, the device reverts to the erase suspend mode, and is ready for another valid operation. See
Auto-select Command Sequence for more information.
The system must write the erase resume command (address bits are don’t care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the resume command are
ignored. Another Erase Suspend Command can be written after the device has resumed erasing.
6.2.8 Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than
using the standard program command sequence. The unlock bypass command sequence is initiated
by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass
command, 20h. The device enters the unlock bypass command mode. A two-cycle unlock bypass
program command sequence is all that is required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses
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with the initial two unlock cycles required in the standard program command sequence, resulting in
faster total programming time. Command Definitions shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-pass Reset
commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock
bypass reset command sequence. The first cycle must contain the data 90h; the second cycle the
data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Program/Erase operation refer Program Algorithm and Erase Algorithm illustration.
6.3 WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ5, DQ6,
and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase
operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY,
to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1 DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the
command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the
data programmed to DQ7. The system must provide the program address to read valid status
information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is
active for about 1µS, and then the device returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7.Once the Embedded
Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the
sectors selected for erasure must be provided to read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100µS, and then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address
within a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the
DQ7 output, the system may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still
invalid. Valid data on DQ7-DQ0 will appear on successive read cycles.
6.3.2 RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is
in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the
Publication Release Date:Jan.04, 2008
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Revision A5
W19B160BT/B DATA SHEET
command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together
in parallel with a pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. When the output is high
(Ready), the device is in the read mode.
6.3.3 DQ6: Toggle Bit
Toggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete. Toggle Bit may be read at any address, and is valid after the rising edge of the final #WE
pulse in the command sequence (before the program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the
operation has completed, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100µS, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
If a program address falls within a protected sector, DQ6 toggles for about 1 μs after the program
command sequence is written, and then returns to reading array data.
6.3.4 DQ2: Toggle Bit II
When used with DQ6, the “Toggle Bit II” on DQ2 indicates whether a particular sector is actively
erasing (i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final #WE pulse in the command sequence.
DQ2 toggles as the system reads at addresses within those sectors that have been selected for
erasure. (The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot
distinguish that whether the sector is actively erasing or is erase-suspended. By comparison, DQ6
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Therefore, both status bits are required for sector and mode
information.
6.3.5 Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0−DQ7 at least twice in a
row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the
value of the toggle bit after the first read. While after the second read, the system would compare the
new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ0−DQ7 on the following read
cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is
high, the system should then determine again whether the toggle bit is toggling or not, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not
complete the operation, and the system must write the reset command to return to reading array data.
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W19B160BT/B DATA SHEET
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5 through successive read cycles, and
determines the status as described in the previous paragraph. Alternatively, the system may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
while it returns to determine the status of the operation.
6.3.6 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The
entire time-out applies after each additional sector erase command if additional sectors are selected
for erasure. Once the timeout period has completed, DQ3 switches from “0” to “1.” If the time between
additional sector erase commands from the system can be assumed to be less than 50 μS, the
system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase
Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (#Data Polling)
or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read
DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all further commands (except Erase
Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept
additional sector erase commands.
The system software should check the status of DQ3 before and following each subsequent sector
erase command to ensure the command has been accepted. If DQ3 is high on the second status
check, the last command might not have been accepted.
6.3.7 DQ5 : Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the
device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
7. SPECIAL CHARACTERISTIC
The W19B160B provides a good performance in the wireless products. It is concerned with access
speed. If the access speed is quick to meet the demand of specification (70nS), the system’s
application is widely and performance is better than other low speed products.
Publication Release Date:Jan.04, 2008
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Revision A5
W19B160BT/B DATA SHEET
8. TABLE OF OPERATION MODES
8.1 Device Bus Operations
DQ8-DQ15
DQ0-
MODE
#CE #OE #WE #RESET ADDRESS (1)
BYTE
=VIH
DQ7
BYTE =VIL
Read
Write
L
L
L
H
L
H
H
AIN
AIN
DOUT
DIN
DOUT DQ8-
DQ14=High-Z
H
DIN
DQ15=A-1
VDD ±
0.3V
VDD ±
0.3V
Standby
X
X
X
High-Z High-Z
High-Z
Output Disable
Reset
L
H
X
H
X
H
L
X
X
High-Z High-Z
High-Z High-Z
High-Z
High-Z
X
SA, A6=L,
A1=H, A0=L
Sector Protect (2)
L
L
X
H
H
X
L
L
X
VID
VID
VID
DIN
DIN
DIN
X
X
X
X
SA, A6=H,
A1=H, A0=L
Sector Unprotect (2)
Temporary Sector
Unprotect
AIN
DIN
High-Z
Legend： L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5-11.5V, X = Don’t Care, SA = Sector Address, AIN = Address In,
DIN = Data In, DOUT = Data Out
Notes：
1. Addresses are A19:A0 in word mode (#BYTE = VIH), A19:A-1 in byte mode (#BYTE = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
the” Sector Protection and Unprotect ion” section.Auto-select Codes (High Voltage Method)
A19 A11
A8
A5
DQ8
DESCRIPTION
#CE #OE #WE TO
TO
A9 TO A6 TO A1 A0 TO DQ7 TO DQ0
A12 A10
A7
A2
DQ15
Manufacturer ID:
Winbond
0
0
0
0
1
1
X
X
X
X
VID
VID
X
0
0
X
0
0
0
1
X
DAh
C4h
Device ID:
W19B160BT
(Top Boot Block)
22h
(Word
)
X
X
X
X
Device ID:
W19B160BB
(Bottom Boot
Block)
22h
(Word
)
0
0
0
0
1
1
X
X
X
VID
0
0
0
1
1
0
49h
01h
(protected)
00h
Sector Protection
Verification
SA
VID
X
X
X
(unprotected)
Legend : SA= Sector Address, X= Don't Care , VID = 8.5-11.5V , L = Logic 0 = VIL , H = Logic 1 = VIH.
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W19B160BT/B DATA SHEET
8.2 Sector Address Table (Top Boot Block)
SECTOR
ADDRESS
(X8)
(X16)
SECTOR SIZE
(KBYTES/KWORDS)
SECTOR
ADDRESS RANGE
ADDRESS RANGE
A19-A12
SA0
00000XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F9FFFh
1FA000h-1FBFFFh
1FC000h-1FFFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-FBFFFh
FC000h-FCFFFh
FD000h-FDFFFh
FE000h-FFFFFh
SA1
00001XXX
00010XXX
00011XXX
00100XXX
00101XXX
00110XXX
00111XXX
01000XXX
01001XXX
01010XXX
01011XXX
01100XXX
01101XXX
01110XXX
01111XXX
10000XXX
10001XXX
10010XXX
10011XXX
10100XXX
10101XXX
10110XXX
10111XXX
11000XXX
11001XXX
11010XXX
11011XXX
11100XXX
11101XXX
11110XXX
111110XX
11111100
11111101
1111111X
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
8/4
16/8
Note : The address range is [A19: A-1] in byte mode (#BYTE =VIL) or [A19:A0] in word mode (#BYTE =VIH ).
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
8.3 Sector Address Table (Bottom Boot Block)
SECTOR ADDRESS
A19-A12
(X8)
(X16)
SECTOR SIZE
(KBYTES/KWORDS)
SECTOR
ADDRESS RANGE
000000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
ADDRESS RANGE
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
80000h-87FFFh
88000h-8FFFFh
90000h-97FFFh
98000h-9FFFFh
A0000h-A7FFFh
A8000h-AFFFFh
B0000h-B7FFFh
B8000h-BFFFFh
C0000h-C7FFFh
C8000h-CFFFFh
D0000h-D7FFFh
D8000h-DFFFFh
E0000h-E7FFFh
E8000h-EFFFFh
F0000h-F7FFFh
F8000h-FFFFFh
SA0
0000000X
00000010
00000011
000001XX
00001XXX
00010XXX
00011XXX
00100XXX
00101XXX
00110XXX
00111XXX
01000XXX
01001XXX
01010XXX
01011XXX
01100XXX
01101XXX
01110XXX
01111XXX
10000XXX
10001XXX
10010XXX
10011XXX
10100XXX
10101XXX
10110XXX
10111XXX
11000XXX
11001XXX
11010XXX
11011XXX
11100XXX
11101XXX
11110XXX
11111XXX
16/8
SA1
8/4
SA2
8/4
SA3
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
Note: The address range is [A19:A-1] in byte mode (#BYTE =VIL) or [A19:A0] in word mode (#BYTE =VIH ).
- 20 -
W19B160BT/B DATA SHEET
8.4 CFI Query Identification String
ADDRESS
ADDRESS
DESCRIPTION
DATA
(WORD MODE)
(BYTE MODE)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Query-unique ASCII string "QRY"
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command Set (00h=none exists)
Address for Alternate OEM Extended Table (00h=none
exists)
8.5 System Interface String
ADDRESS
ADDRESS
DESCRIPTION
DATA
0027h
0036h
(WORD MODE)
(BYTE MODE)
VDD Min. (write/erase)
1Bh
1Ch
36h
38h
D7-D4: volt , D3-D0: 100 mV
VDD Max. (write/erase)
D7-D4: volt , D3-D0: 100 mV
VPP Min. voltage (00h=no Vpp pin present)
VPP Max. voltage (00h=no Vpp pin present)
Typical timeout per single byte/word write 2N ꢀS
1Dh
1Eh
1Fh
0000h
0000h
0004h
3Ah
3Ch
3Eh
Typical timeout for Min. size buffer write 2N ꢀS (00h=not
supported)
20h
21h
22h
0000h
000Ah
0000h
40h
42h
44h
Typical timeout per individual block erase 2N mS
Typical timeout for full chip erase 2N mS (00h=not
supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
23h
24h
25h
0005h
0000h
0004h
46h
48h
4Ah
Max. timeout per individual block erase 2N times typical
Max. timeout full chip erase 2N times typical ( 00h = not
supported)
26h
0000h
4Ch
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
8.6 Device Geometry Definition
ADDRESS
(WORD MODE)
27h
ADDRESS
(BYTE MODE)
4Eh
DESCRIPTION
DATA
Device size =2N bytes
0015h
0002h
0000h
0000h
0000h
0004h
0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
28h
50h
Flash device interface description (refer to CFI
publication 100)
29h
52h
Max. number of bytes in multi-byte write=2N (00h=not
supported)
2Ah
54h
2Bh
56h
Number Of Erase Block Regions Within Devices
2Ch
58h
2Dh
5Ah
Erase block region 1 information
2Eh
5Ch
(refer to the CFI specification or CFI publication 100 )
2Fh
5Eh
30h
60h
31h
62h
32h
64h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
33h
66h
34h
68h
35h
6Ah
36h
6Ch
37h
6Eh
38h
70h
39h
72h
3Ah
74h
3Bh
76h
3Ch
78h
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W19B160BT/B DATA SHEET
8.7 Primary Vendor-Specific Extended Query
ADDRESS
ADDRESS
DESCRIPTION
DATA
(WORD MODE)
( BYTE MODE)
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0030h
80h
82h
84h
86h
88h
Query-unique ASCII string "PRI"
Major version number, ASCII
Minor version number, ASCII
Address sensitive unlock
45h
46h
47h
48h
49h
4Ah
4Bh
0000h
0000h
0001h
0001h
0001h
0000h
0000h
8Ah
8Ch
8Eh
90h
92h
94h
96h
0 = Required, 1 = Not required
Erase Suspend
00 = Not supported, 01=Supported
Sector protect
0 = Not supported, X=number of sectors in per group
Sector Temporary Unprotect
00 = Not supported, 01=Supported
Sector protect/unprotect scheme
00 = Not supported, 01=Supported
Simultaneous operation
00 = Not supported, 01=Supported
Burst mode type
00 = Not supported, 01=Supported
Page mode type
4Ch
0000h
98h
00 = Not Supported, 01=4 Word Page, 02=8 Word
Page
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
8.8 Command Definitions
BUS CYCLES (2-5)
COMMAND
SEQUENCE
CYCLE
FIRST
SECOND
THIRD
FOURTH
FIFTH
SIXTH
(1)
ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA
Read (note 6)
Reset (note 7)
1
1
RA
RD
F0
XXX
555
Word
Byte
2AA
555
2AA
555
2AA
555
2AA
555
PA
555
AAA
555
Normal
Program
4
6
6
3
AA
AA
AA
AA
55
55
55
55
A0
80
80
20
PA
PD
AA
AA
AAA
555
Word
Byte
555
AAA
555
2AA
555
2AA
555
555
Chip Erase
Sector Erase
Unlock pass
55
55
10
30
AAA
555
AAA
555
AAA
Word
Byte
SA
AAA
555
AAA
555
AAA
Word
Byte
AAA
XXX
XXX
XXX
XXX
555
AAA
Unlock bypass program
Unlock bypass reset
Erase suspend
2
2
1
1
A0
90
B0
30
PD
F0
XXX
Erase resume
Word
Byte
2AA
555
2AA
555
555
AAA
555
Manufacturer
Code
4
4
AA
AA
55
55
90
90
X00
DA
AAA
555
Word
Byte
X01
x02
Device
Code
(note11
)
AAA
AAA
XX00
XX01
00
Word
Byte
555
2AA
555
555
(SA) X02
(SA) X04
Sector Protect
Verify (note 9)
4
1
AA
98
55
90
AAA
AAA
01
Common Flash
Interface (CFI)
Query (note 10)
Word
Byte
55
AA
Legend:
X = Don’t Care
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the #WE or #CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in auto select mode) or erased. Address bits A19-A12 uniquely select any sector.
Notes:
1. See Bus Operations Table for details.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the auto select command sequence, all bus cycles are write cycles.
4. Data bits DQ15-DQ8 are don’t care for unlock and command cycle.
5. Unless otherwise noted, address bits A19-A11 are don’t cares for unlock and command cycles.
6. No unlock or command cycles required when reading array data.
7. When device is in the auto select mode, the reset command is required to return to reading array data, or if DQ5 goes
high (while the device is providing status data).
- 24 -
W19B160BT/B DATA SHEET
8. The fourth cycle of the auto select command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector.
10. Command is valid when device is ready to read array data or when device is in auto select mode.
11. See Auto-select Codes table for device ID information.
8.9 Write Operation Status
DQ7
(NOTE 2)
DQ5
(NOTE1)
DQ2
(NOTE 2)
STATUS
DQ6
DQ3
RY/#BY
Embedded Program Algorithm
Embedded Erase Algorithm
#DQ7
Toggle
Toggle
0
0
0
N/A
1
No toggle
Toggle
0
0
1
Standard
Mode
0
1
Erase Suspended Sector
No toggle
N/A
Toggle
Erase-
Suspend-
Read
Erase
Suspend
Non-Erase Suspended
Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Erase-Suspend-Program
#DQ7
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 requires a valid address when reading status information. Please refer to related sections for details.
Publication Release Date:Jan.04, 2008
- 25 -
Revision A5
W19B160BT/B DATA SHEET
8.10 Temporary Sector Unprotect Algorithm
START
#RESET = V
ID
(Note 1)
Perform Erase or
Program Operations
#RESET = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again
- 26 -
W19B160BT/B DATA SHEET
8.11 In-System Sector Protect/Unprotect Algorithms
START
START
PLSCNT=1
Protect all sectors
The indicated portion
of the sector protect
algorithm must be
performed for all
PLSCNT=1
ID
#RESET=V ID
#RESET=V
unprotected sectors
prior to issuing the
first sector
s
Wait 1
μ
Wait 1
μ
s
unprotect address
No
First Write
Cycle=60h?
No
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
First Write
Cycle=60h?
Yes
Yes
Set up sector
address
All sector
protected?
No
Sector Protect:
Yes
Write 60h to sector
address with
A6=0,A1=1,A0=0
Set up first
sector address
μ
Wait 150
s
Sector Unrotect:
Write 60h to sector
address with
A6=1,A1=1,A0=0
Verity Sector
Protect:Write 40h
to sector address
Reset
PLSCNT=1
Increment
PLSCNT
Wait 15 mS
with A6=0,
Increment
PLSCNT
A1=1,A0=0
Verity Sector
Unprotect: Write 40h
to sector address
Read from
sector address
No
with A6=0,
A1=1,A0=0
with A6=1,
A1=1,A0=0
Read from
sector address
No
with A6=1,
PLSCNT
=25?
Data=01h?
A1=1,A0=0
Yes
No
Yes
Set up
next sector
address
PLSCNT
=1000?
No
Data=00h?
Yes
Protect another
sector?
Device failed
Yes
No
Yes
ID
Remove V
No
from #RESET
Last sector
verified?
Device failed
Write reset
command
Yes
Sector Protect
Algorithm
Sector Unprotect
Algorithm
ID
Remove V
from #RESET
Sector Protect
complete
Write reset
command
Sector Unprotectt
complete
Publication Release Date:Jan.04, 2008
Revision A5
- 27 -
W19B160BT/B DATA SHEET
8.12 Program Algorithm
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
No
Increment
Address
Last Address?
Yes
Programming
Completed
8.13 Erase Algorithm
STA RT
W rite Erase
Com mand Sequence
Data Poll from System
Embedded
Erase
algorithm
in progress
No
Data=FFh?
Yes
Erase Completed
- 28 -
W19B160BT/B DATA SHEET
8.14 Data Polling Algorithm
START
Read DQ7-DQ0
Addr=VA
Yes
DQ7=Data?
No
No
DQ5=1?
Yes
Read DQ7-DQ0
Addr=VA
Yes
DQ7=Data?
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the
sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
Publication Release Date:Jan.04, 2008
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Revision A5
W19B160BT/B DATA SHEET
8.15 Toggle Bit Algorithm
START
Read DQ7-DQ0
Read DQ7-DQ0
(Note 1)
No
Toggle Bit
=Toggle?
Yes
No
DQ5=1?
Yes
(Notes
1, 2)
Read DQ7-DQ0
Twice
No
Toggle Bit
=Toggle?
Yes
Program/Erase
Operation Not
Complete,Write
Reset Command
Program/Erase
Complete
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1.”
- 30 -
W19B160BT/B DATA SHEET
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
Voltage with Respect to Ground , VDD (Note1)
A9, #OE, and #RESET (Note 2)
All other pins (Note 1)
RATING
-65 to +150
-65 to +125
-0.5 to +4.0
-0.5 to VDD (Max.)
-0.5 to VDD +0.5
200
UNIT
°C
°C
V
V
V
Output Short Circuit Current (Note 3)
Notes:
mA
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -
2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions,
input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 ns.
2. Minimum DC input voltage on pins A9, #OE, and #RESET is -0.5 V. During voltage transitions, A9, #OE, and #RESET
may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on pin A9 is VDD (Max.) which may
overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage is +9.5 V which may overshoot to +12.0 V for
periods up to 20 nS.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those
indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
9.2 Operating Ranges
PARAMETER
Industrial (I) Devices
RATING
UNIT
-40 to +85
°C
Ambient Temperature (TA )
Commercial Devices
0 to +70
°C
V
Ambient Temperature (TA )
VDD Supply Voltages
2.7 to 3.6
VDD for standard voltage range
Operating ranges define those limits between which the functionality of the device is guaranteed.
Publication Release Date:Jan.04, 2008
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Revision A5
W19B160BT/B DATA SHEET
9.3 DC CHARACTERISTICS
LIMITS
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MIN.
TYP. MAX.
VIN = VSS to VDD, VDD = VDD
(Max.)
Input Load Current
ILI
-
-
-
-
-
-
± 1.0
35
μA
μA
μA
VDD = VDD (Max.), A9 = VID
(Max.)
A9 Input Load Current
Output Leakage Current
ILIT
ILO
VOUT = VSS to VDD , VDD = VDD
(Max.)
± 1.0
10 MHz
#CE = VIL , #OE = VIH
5 MHz
15
9
25
16
4
mA
mA
mA
mA
mA
mA
-
Byte Mode
VDD Active Read Current
(Note 1,2)
1 MHz
2
ICC1
10 MHz
#CE = VIL , #OE = VIH
5 MHz
18
9
25
16
4
Word Mode
1 MHz
2
VDD Active Current
(Note 2,3,4)
ICC2 #CE = VIL , #OE = VIH
-
-
20
30
5
mA
VDD Standby Current
(Note 2,5)
ICC3
0.2
#RESET , #CE = VDD ± 0.3V
#RESET = VSS ± 0.3V
μA
VDD Reset Current (Note 2,5) ICC4
-
-
0.2
0.2
5
μA
μA
V
Automatic Sleep Mode Current
(Note 2,4,5,6)
VIH = VDD ± 0.3V, VIL = VSS ±
0.3V
ICC5
5
Input Low Voltage
Input High Voltage
VIL
-0.5
-
-
0.8
VIH
0.7 x VDD
VDD+0.3 V
Voltage for Auto-select and
Temporary Sector Unprotected
VID
8.5
-
11.5
V
VDD =3.0V ± 10%
Output Low Voltage
VOL IOL = 4.0 mA, VDD = VDD (Min.)
VOH1 IOL = -2.0 mA, VDD = VDD (Min.)
-
-
-
-
0.45
V
V
V
2.4
-
-
Output High Voltage
VOH2
VDD -0.4
IOH = -100 μA, VDD = VDD (Min.)
Notes:
1. The ICC current is typically less than 2 mA/MHz, with #OE at VIH. Typical VDD is 3.0V.
2. Maximum ICC specifications are tested with VDD = VDD max.
3.
ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode
current is 200 nA.
5. For temperature >70 degree C, Vih(Max.)=Vdd+0.1V and Vil(Min)=Vss-0.1V.
6. Not 100% tested
- 32 -
W19B160BT/B DATA SHEET
9.4 AC CHARACTERISTICS
9.4.1 Test Condition
Test Condition
70nS
30
90nS
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
100
5
pF
ns
V
Input Pulse Levels
0 - 3.0
Input timing measurement reference levels
Output timing measurement reference levels
1.5
1.5
V
V
9.4.2 AC Test Load and Waveforms
+3.3V
W
2.7K
D
OUT
30 pF for 70nS
6.2KW
( Including Jig and Scope)
Input
3V
Output
1.5V
1.5V
0V
Test Point
Test Point
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
9.4.3 Read-Only Operations
70nS
90nS
PARAMETER
SYM. TEST Setup
TRC
Unit
Min. Max. Min. Max.
Read Cycle Time
70
-
-
90
-
-
ns
ns
#CE = VIL,
Address to Output Delay
TACC
70
90
#OE = VIL
Chip Enable to Output Delay
Output Enable Access Time
TCE
TOE
#OE = VIL
-
-
70
30
-
-
90
35
ns
ns
Chip Enable to Output High Z
Output Enable to Output High Z
TDF
TDF
-
-
25
25
-
-
30
30
ns
ns
Output Hold Time From Address. #OE or
#CE Whichever Occurs First
TOH
0
-
0
-
ns
Read
0
-
-
0
-
-
ns
ns
Output Enable Hold
TOEH
Toggle and #Data
Time
10
10
polling
Note : Not 100 % tested
9.4.4 Read-Only Operations
Test Condition
70nS
90nS
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
30
100
5
pF
ns
V
Input Pulse Levels
0 - 3.0
Input timing measurement reference levels
Output timing measurement reference levels
Note : Not 100 % tested
1.5
1.5
V
V
- 34 -
W19B160BT/B DATA SHEET
9.4.5 Hardware Reset (#RESET)
PARAMETER
SYM.
MIN.
MAX.
UNIT
#RESET PIN Low (During Embedded Algorithms) to
Read or Write
TREADY
-
20
us
#RESET Pin Low (Not During Embedded
Algorithms) to Read or Write
TREADY
-
500
ns
#RESET Pulse Width
TRp
TRH
TRPD
TRB
500
50
20
0
-
-
-
-
ns
ns
us
ns
#RESET High Time Before Read
#RESET Low to Standby Mode
RY/#BY Recovery Time
Note: Not 100 % tested
9.4.6 Word/Byte Configuration (#BYTE)
Test Condition
70nS
30
90nS
Unit
Output Load
1 TTL gate
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
100
pF
ns
V
5
0 - 3.0
1.5
Input Pulse Levels
Input timing measurement reference levels
Output timing measurement reference levels
V
1.5
V
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
9.4.7 Erase and Program Operation
70nS
90nS
PARAMETER
SYM.
Unit
Min. Typ. Max. Min.
Typ. Max.
Write Cycle Timing
Address setup Time
Address Hold Time
Data Setup Time
70
0
-
-
-
-
-
-
-
-
-
-
-
-
90
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TWC
TAS
45
35
0
45
45
0
TAH
TDS
TDH
TOES
Data Hold Time
Output Enable Setup Time
0
0
Read Recovery Time Before Write
(#OE High to #WE Low)
0
-
-
0
-
-
ns
TGHWL
#CE Setup Time
0
0
-
-
-
-
0
0
-
-
-
-
ns
ns
ns
ns
us
us
sec
us
ns
ns
TCS
TCH
#CE HOLD Time
Write Pulse Width
Write Pulse Width High
35
30
-
-
-
35
30
-
-
-
TWP
TWPH
TPB
-
-
-
-
Byte
5
7
0.7
-
150
210
10
-
5
7
0.7
-
150
210
10
-
Programming Time
Word
-
-
TPW
TSE
Sector Erase Time
-
-
VDD Setup Time (Note 1)
50
0
50
0
TVCS
TRB
Write Recovery Time from RY/#BY
Program/Erase Valid to RY/#BY Delay
-
-
-
-
30
-
90
-
-
90
TBUSY
Notes: Not 100 % tested
9.4.8 Temporary Sector Unprotect
PARAMETER
SYM.
TVIDR
TRSP
MIN.
MAX.
UNIT
VID Rise and Fall Time (See Note)
500
4
-
-
ns
us
#RESET setup Time for Temporary Sector Unprotect
#RESET Hold Time from RY/#BY High for Temporary
Sector Unprotect
TRRB
4
-
s
Note: Not 100 % tested
- 36 -
W19B160BT/B DATA SHEET
9.4.9 Alternate #CE Controlled Erase and Program Operation
70nS
90nS
Typ
PARAMETER
SYM.
Unit
Min
Typ
Max
Min
Max
(Note 3) (Note 4)
(Note 3) (Note 4)
Write Cycle Time (Note 1)
Address Setup Time
Address Hold Time
Data Setup Time
70
0
-
-
-
-
-
-
-
-
-
-
-
-
90
0
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
TWC
TAS
45
35
0
45
45
0
TAH
TDS
TDH
TOES
Data Hold Time
Output Enable Setup Time
0
0
Read Recover Time Before Write
(#OE High to #WE Low)
0
-
-
0
-
-
ns
TGHEL
#WE Setup Time
#WE Hold Time
0
0
-
-
-
-
-
-
-
0
0
-
-
-
-
-
-
-
ns
ns
ns
ns
TWS
TWH
TCP
#CE Pulse Width
#CE Pulse Width High
35
30
-
-
35
30
-
-
-
-
TCPH
TPB
Byte
5
5
Programming Time
us
(Note 6)
Word
-
-
-
-
7
-
-
-
-
-
-
-
-
7
-
-
-
-
TPW
Sector Erase Time (Note 2)
Chip Erase Time (Note 2)
0.7
25
11
0.7
25
11
sec
sec
TSE
TCE
Byte
TCPB
Chip Program Time
(Note 5)
sec
Word
-
7.2
-
-
7.2
-
TCPW
Notes :
1. Not 100 % tested.
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25℃,3.0 V VDD, 10,000 cycles .Additionally,
programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90℃, VDD =2.7V, 10,000 cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most
bytes program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 10,000 cycles.
Publication Release Date:Jan.04, 2008
- 37 -
Revision A5
W19B160BT/B DATA SHEET
10. TIMING WAVEFORMS
10.1 AC Read Waveform
RC
T
Addresses Stable
Address
#CE
TACC
OE
T
#OE
DF
T
T
OEH
#WE
TCE
TOH
High-Z
High-Z
Outputs
Output Vaild
#RESET
RY/#BY
0V
10.2 Reset Waveform
RY/#BY
#OE,#CE
#RESET
RH
T
T
RP
Ready
T
Reset Timing NOT during Embedded Algorithms
T
Ready
RY/#BY
T
RB
#OE,#CE
#RESET
TRP
Reset Timings during Embedded Algorithms
- 38 -
W19B160BT/B DATA SHEET
10.3 #BYTE Waveform for Read Operation
#CE
#OE
#BYTE
#BYTE
T
Switching
ELFL
Data Output
(DQ0-DQ14)
Data Output
(DQ0-DQ7)
DQ0-DQ14
DQ15/A-1
from word
to byte
mode
DQ15
Output
Address
Input
T
FLQZ
T
ELFH
#BYTE
#BYTE
Data Output
(DQ0-DQ7)
Data Output
(DQ0-DQ14)
DQ0-DQ14
Switching
from byte
to word
mode
Address
Input
DQ15
Output
DQ15/A-1
T
FHQV
10.4 #BYTE Waveform for Write Operation
#CE
The falling edge of the last #WE signal
#WE
#BYTE
T
SET
(T
)
AS
T
HOLD
(T
AH
)
Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications.
Publication Release Date:Jan.04, 2008
Revision A5
- 39 -
W19B160BT/B DATA SHEET
10.5 Programming Waveform
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
TWC
T
AS
PA
Address
PA
555h
PA
T
AH
#CE
#OE
T
CH
TWP
T
PW
TWPH
#WE
T
CS
T
DH
DS
T
D
Status
OUT
A0h
PD
Data
T
BUSY
T
RB
RY/#BY
VDD
T
VCS
Notes :
1. PA=program address ,PD=program data,DOUT is the true data at the program address
2. Illustration shows device in word mode
10.6 Chip/Sector Erase Waveform
Erase Command Sequence (last two cycles)
Read Status Data
VA
TWC
T
AS
VA
Address
2AAh
SA
555h for chip erase
TAH
#CE
#OE
T
CH
TWP
TWPH
TSE
#WE
TCS
TDS
T
DH
In
Complete
TRB
Data
30h
55h
Progress
10 for Chip Erase
T
BUSY
RY/#BY
TVCS
VDD
Notes :
1. SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write operation Status”).
2. These waveforms are for the word mode
- 40 -
W19B160BT/B DATA SHEET
10.7 #Data Polling Waveform (During Embedded Algorithms)
T
RC
Addresses
VA
VA
VA
ACC
T
T
CE
#CE
#OE
T
CH
T
OE
T
DF
TOEH
#WE
T
OH
High Z
High Z
Complement
Complement
Status Data
Valid Data
Valid Data
True
True
DQ7
Status Data
DQ0-DQ6
T
BUSY
RY/#BY
Note : VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
10.8 Toggle Bit Waveform (During Embedded Algorithms)
TRC
VA
VA
VA
VA
Addresses
#CE
T
ACC
CH
T
CE
T
OE
T
#OE
#WE
TOEH
TDF
TOH
High Z
Valid Status
(first read)
Valid Status
(second read)
Valid Status
Valid Status
DQ6
(stop toggling)
RY/#BY
TBUSY
Note : VA= Valid address;not requires for DQ6. Illustration shows status cycle after command sequence, last status read cycle,
and array data read cycle.
Publication Release Date:Jan.04, 2008
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Revision A5
W19B160BT/B DATA SHEET
10.9 Temporary Sector Unprotect Timing Diagram
12V
0 or 3V
#RESET
T
VIDR
TVIDR
Program or Erase Command Sequence
#CE
#WE
TRSP
RY/#BY
10.10 Sector Protect and Unprotect Timing Diagram
VID
V
IH
#RESET
SA,A6,
A1,A0
Valid*
Status
Valid*
Valid*
Verify
Sector Protect or Unprotect
60h
40h
60h
DATA
s,
Sector Protect:150μ
Sector Unprotect:15ms
μ
s
1
#CE
#WE
#OE
Note: For sector protect, A6=0, A1=1, A0=0.
For sector unprotect, A6=1, A1=1, A0=0.
- 42 -
W19B160BT/B DATA SHEET
10.11 Alternate #CE Controlled Write (Erase/Program) Operation Timing
#Data Polling
PA for program
555 for program
2AA for erase
SA for sector erase
PA
Address
555 for chip erase
TWC
T
AH
T
AS
TWH
#WE
#OE
#CE
T
GHEL
T
CP
TPW, TPB, ORT SE
TWS
T
CPH
T
DS
T
BUSY
T
DH
.
.
OUT
D
#DQ7
DATA
PD for program
30 for sector erase
10 for chip erase
A0 for program
T
RH
55 for erase
#RESET
RY/#BY
Notes :
1. Firgure indicates last two bus cycles of a program or erase operation.
2. PA= program address, SA= sector address, PD= program data.
3. #DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Publication Release Date:Jan.04, 2008
Revision A5
- 43 -
W19B160BT/B DATA SHEET
11. LATCHUP CHARACTERISTICS
PARAMETER
MIN
MAX
Input voltage with respect to Vss on all pins except I/O pins (including
A9, #OE, and #RESET)
-1.0 V
11.5 V
Input voltage with respect to Vss on all I/O pins
VDD Current
-1.0 V
VDD +1.0 V
+100 mA
-100 mA
Note : Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time.
12. CAPACITANCE
TEST
SETUP
PARAMETER
SYM.
TYP
MAX
UNIT
Input Capacitance
VIN
VOUT
VIN2
VIN = 0
6
7.5
12
9
pF
pF
pF
Output Capacitance
Control Pin Capacitance
Notes :
VOUT = 0
VIN = 0
8.5
7.5
1.
2.
Sampled, not 100 % tested.
Test condition TA = 25℃, f = 1.0 MHz.
- 44 -
W19B160BT/B DATA SHEET
13. ORDERING INFORMATION
W19B160B T T 7 H
Quality:Grade & Green
H: Extended ( -20℃~85 ℃)with Green package
M:Industrial ( -40℃~85 ℃)with Green package
SPEEDOPTION
7 : 70 ~ 79ns
8 : 80 ~ 89ns
9 : 90 ~ 99ns
A : 100 ~ 109ns
B : 110 ~ 119ns
PACKAGE TYPE
T = 48-Pin TSOP Package, 12 x 20mm
B = 48-Ball TFBGA, 0.80 mm pitch, 6 x 8 mm package
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
W19B160B
16 Megabit (2M x 8-Bit/ 1 M x 16-Bit) CMOS Flash Memory
Simultaneous Read/Write operations, 3.0 Volt-only Read, Program, and Erase
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
Publication Release Date:Jan.04, 2008
- 45 -
Revision A5
W19B160BT/B DATA SHEET
14. PACKAGE DIMENSIONS
TFBGA48ball (6X8 mm^2, Ø=0.40mm)
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W19B160BT/B DATA SHEET
48-Pin Standard Thin Small Outline Package (measured in millimeters)
1
48
e
E
b
c
D
H D
A2
A1
A
θ
L
L1
Y
MILLIMETER
INCH
NOM.
Symbol
MIN.
NOM.
MAX.
0.047
MAX.
1.20
MIN.
A
A1
0.05
0.95
18.3
19.8
11.9
0.002
0.037
0.720
0.780
0.468
A2
D
1.00
18.4
20.0
12.0
1.05
18.5
0.039
0.724
0.787
0.472
0.009
0.041
0.728
0.795
0.476
20.2
12.1
H D
E
0.011
0.008
0.17
0.10
0.22
0.27
0.21
0.007
0.004
b
c
0.020
0.50
e
0.024
0.031
0.50
0
L
0.60
0.80
0.70
0.020
0
0.028
L1
Y
0.004
5
0.10
5
θ
Publication Release Date:Jan.04, 2008
Revision A5
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W19B160BT/B DATA SHEET
15. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
April/12/2007
ALL
Initial Issued
48-Pin Standard Thin Small Outline Package/VID Spec to
11.5volt
A2
July/17/2007
ALL
1. Reduced TBUSY form 90nS to 30nS
2. Reduced ICC1 form 30/35mA to 25mA
3. Removed max of TCPB/ TCPW
4. Removed max of TPW
A3
Oct./01/2007
Oct./17/2007
34-38
26,46
A4
A5
Updated frame setting and package material as Green
Added note of ICC3-5, 90nS/Read only spec, and max. of
tPW/tPB
Jan./04/2008 32,36-41
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 48 -
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