W19B320SBB9B [WINBOND]
Flash, 2MX16, 90ns, PBGA48, TFBGA-48;
| 型号： | W19B320SBB9B |
| 厂家： | 
WINBOND |
| 描述： | Flash, 2MX16, 90ns, PBGA48, TFBGA-48 |
| 文件： | 总52页 (文件大小：1869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W19B(L)320ST/B Data Sheet
4M × 8/2M × 16 3V(3.3V) FLASH MEMORY
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES................................................................................................................................. 4
PIN CONFIGURATIONS ............................................................................................................ 5
BLOCK DIAGRAM ...................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION ................................................................................................... 6
6.1
Device Bus Operation..................................................................................................... 6
6.1.1 Word/Byte Configuration ..................................................................................................6
6.1.2 Reading Array Data..........................................................................................................6
6.1.3 Writing Commands/Command Sequences.......................................................................6
6.1.4 Standby Mode ..................................................................................................................7
6.1.5 Automatic Sleep Mode .....................................................................................................7
6.1.6 #RESET: Hardware Reset Pin..........................................................................................7
6.1.7 Output Disable Mode........................................................................................................8
6.1.8 Autoselect Mode...............................................................................................................8
6.1.9 Sector/Sector Block Protection and Unprotection.............................................................8
6.1.10 Write Protect ( ) .......................................................................................................8
#WP
6.1.11 Temporary Sector Unprotect ..........................................................................................9
6.1.12 Security Sector Flash Memory Region ...........................................................................9
6.1.13 Hardware Data Protection ............................................................................................10
Command Definitions ................................................................................................... 10
6.2.1 Reading Array Data........................................................................................................11
6.2.2 Reset Command.............................................................................................................11
6.2.3 Autoselect Command Sequence ....................................................................................11
6.2.4 Enter Security Sector/Exit Security Sector Command Sequence...................................12
6.2.5 Byte/Word Program Command Sequence......................................................................12
6.2.6 Unlock Bypass Command Sequence .............................................................................12
6.2.7 Chip Erase Command Sequence ...................................................................................13
6.2.8 Sector Erase Command Sequence ................................................................................13
6.2.9 Erase Suspend/Erase Resume Commands ...................................................................14
Write Operation Status ................................................................................................. 14
6.3.1 DQ7: #Data Polling.........................................................................................................14
6.3.2 RY/#BY: Ready/#Busy ...................................................................................................15
6.3.3 DQ6: Toggle Bit I............................................................................................................15
6.3.4 DQ2: Toggle Bit II...........................................................................................................16
6.2
6.3
Publication Release Date: March 23, 2004
- 1 -
Revision A2
W19B(L)320ST/B
6.3.5 Reading Toggle Bits DQ6/DQ2 ......................................................................................16
6.3.6 DQ5: Exceeded Timing Limits........................................................................................16
6.3.7 DQ3: Sector Erase Timer ...............................................................................................17
7.
TABLE OF OPERATION MODES ............................................................................................ 18
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Device Bus Operations................................................................................................. 18
Autoselect Codes (High Voltage Method) .................................................................... 19
CFI Query Identification String...................................................................................... 26
Command Definitions ................................................................................................... 29
Write Operation Status ................................................................................................. 30
Temporary Sector Unprotect Algorithm........................................................................ 31
In-System Sector Protect/Unprotect Algorithms........................................................... 32
Program Algorithm........................................................................................................ 33
Erase Algorithm ............................................................................................................ 33
7.10 Data Polling Algorithm .................................................................................................. 34
7.11 Toggle Bit Algorithm ..................................................................................................... 35
8.
ELECRICAL CHARACTERISTICS........................................................................................... 36
8.1
8.2
Absolute Maximum Ratings.......................................................................................... 36
Operating Ranges......................................................................................................... 36
1.1.1............................................................................................................................................36
1.1.1............................................................................................................................................36
DC Characteristics........................................................................................................ 37
8.3.1 CMOS Compatible..........................................................................................................37
AC Characteristics........................................................................................................ 38
8.4.1 Test Condition ................................................................................................................38
8.4.2 AC Test Load and Waveforms .......................................................................................38
8.4.3 Read-Only Operations....................................................................................................39
8.4.4 Hardware Reset (#RESET) ............................................................................................39
8.4.5 Word/Byte Configuration (#BYTE)..................................................................................39
8.4.6 Erase And Program Operation .......................................................................................40
8.4.7 Temporary Sector Unprotect ..........................................................................................40
8.4.8 Alternate #CE Controlled Erase and Program Operations..............................................41
8.3
8.4
9.
TIMING WAVEFORMS............................................................................................................. 42
9.1
9.2
9.3
9.4
9.5
9.6
AC Read Waveform...................................................................................................... 42
Reset Waveform........................................................................................................... 42
#BYTE Waveform for Read Operation ......................................................................... 43
#BYTE Waveform for Write Operation ......................................................................... 43
Programming Waveform............................................................................................... 44
Accelerated Programming Waveform........................................................................... 44
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W19B(L)320ST/B
9.7
9.8
9.9
Chip/Sector Erase Waveform....................................................................................... 45
#Data Polling Waveform (During Embedded Algorithms)............................................ 45
Toggle Bit Waveform (During Embedded Algorithms) ................................................. 46
9.10 DQ 2 vs. DQ6 Waveform.............................................................................................. 46
9.11 Temporary Sector Unprotect Timing Diagram.............................................................. 47
9.12 Sector/Sector Block Protect and Unprotect Timing Diagram ....................................... 47
9.13 Alternate #CE Controlled Write (Erase/Program) Operation Timing............................ 48
10.
11.
12.
13.
LATCHUP CHARACTERISTICS .............................................................................................. 49
CAPACITANCE......................................................................................................................... 49
ORDERING INFORMATION .................................................................................................... 50
PACKAGE DIMENSIONS......................................................................................................... 51
13.1 48-Ball TFBGA (measurements in millimeters)............................................................ 51
13.2 48-Pin Standard Thin Small Outline Package (measured in millimeters) .................... 51
14.
VERSION HISTORY................................................................................................................. 52
Publication Release Date: March 23, 2004
- 3 -
Revision A2
W19B(L)320ST/B
1. GENERAL DESCRIPTION
The W19B(L)320ST/B is a 32Mbit, 2.7−3.6(3.0−3.6) volt CMOS flash memory organized as 4M × 8 or
2M × 16 bits. For flexible erase capability, the 32 Mbits of data are divided into eight 8KB, and sixty-
three 64KB sectors. The word-wide (×16) data appears on DQ15−DQ0, and byte-wide (×8) data
appears on DQ7−DQ0. The device can be programmed and erased in-system with a standard
2.7−3.6V(3.0−3.6V) power supply. A 12-volt VPP is not required. The unique cell architecture of the
W19B320ST/B results in fast program/erase operations with extremely low current consumption
(compared to other comparable 3-volt flash memory products). The device can also be programmed
and erased by using standard EPROM programmers.
2. FEATURES
Performance
• 2.7~3.6-volt write (program and erase)
• TTL compatible I/O
operations (W19B320S)
• Manufactured on WinStack 0.18µm process
• 3.0~3.6-volt write (program and erase)
technology
operations (W19L320S)
• Available packages: 48-pin TSOP and 48-ball
• Fast write operation
TFBGA (8x11mm)
Software Features
− Sector erase time: 0.7 Sec (typ.)
− Chip erase time: 49 Sec (typ.)
− Byte programming time: 5 µS (typ.)
• Read access time: 90 nS
• Typical program/erase cycles:
− 100K
• Twenty-year data retention
• Ultra low power consumption
− Active current (Read): 10 mA (typ.) at 5 MHz
− Standby current: 0.2 µA (typ.)
• Compatible with common Flash Memory
Interface (CFI) specification
− Flash device parameters stored directly on
the device
− Allows software driver to identify and use a
variety of different current and future Flash
products
• Erase Suspend/Erase Resume
− Suspends erase operations to allow
programming in same bank
• End of program detection
Architecture
− Software method: Toggle bit/Data polling
• Sector erase architecture
− Eight 8KB, and sixty-three 64KB sectors
• Unlock Bypass Program command
− Reduces overall programming time when
issuing multiple program command
sequences
− Top or bottom boot block configurations
available
− Supports full chip erase
Hardware Features
• Security Sector Size: 256 Bytes
• Ready/#Busy output (RY/#BY)
− Detect program or erase cycle completion
• Hardware reset pin (#RESET)
− The Security Sector is an OTP; once the sector
is programmed, it cannot be erased
• JEDEC standard byte-wide and word-wide
− Reset the internal state machine to the read
pinouts
mode
- 4 -
W19B(L)320ST/B
• #WP/ACC input pin
• Sector Protection
− Write protect (#WP) function allows
protection of two outermost boot sectors,
regardless of sector protect status
− Sectors can be locked in-system or via
programmer
− Temporary Sector Unprotect allows changing
− Acceleration (ACC) function accelerates
data in protected sectors in-system
program timing
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
V
DD
V
SS
#CE
#OE
#WE
48-Ball TFBGA
(Top View, Balls Face Down)
DQ0
OUTPUT
BUFFER
CONTROL
.
#WP/ACC
#BYTE
.
A6
A13
B6
D6
A15
E6
A16
F6
#BYTE
C6
A14
G6
H6
Vss
DQ15/A-1
#RESET
A12
DQ15/A-1
A5
A9
B5
A8
D5
A11
E5
DQ7
F5
DQ14
C5
A10
G5
DQ13
H5
DQ6
DQ15/A-1
A0
.
A4
#WE
B4
D4
A19
E4
DQ5
F4
C4
NC
G4
V DD
H4
DQ4
#RESET
DQ12
.
.
DECODER
BANK
A3
RY/#BY
B3
D3
A20
E3
DQ2
F3
DQ10
C3
G3
DQ11
H3
DQ3
#WP/ACC A18
A20
A2
A7
B2
A17
D2
A5
E2
DQ0
F2
DQ8
C2
A6
G2
DQ9
H2
DQ1
A1
A3
B1
A4
D1
A1
E1
A0
F1
#CE
C1
A2
G1
#OE
H1
Vss
5. PIN DESCRIPTION
SYMBOL
A0−A20
DQ0−DQ14
PIN NAME
Address Inputs
Data Inputs/Outputs
48
A15
A14
A13
A12
A11
1
2
3
4
5
6
7
8
A16
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
#BYTE
Vss
DQ15/A-1
DQ7
DQ14
A10
Word
DQ15 is Data
DQ6
A9
mode
Inputs/Outputs
DQ13
DQ5
DQ15/A-1
A8
A19
A20
#WE
9
48-pin
TSOP
Byte mode A-1 is Address input
Chip Enable
Output Enable
DQ12
DQ4
10
11
12
13
14
15
16
17
18
19
20
#CE
#OE
#WE
DD
V
#RESET
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
NC
#WP/ACC
RY/#BY
Write Enable
A18
A17
Hardware Write Protect/
#WP/ACC
A7
A6
A5
A4
A3
A2
A1
Acceleration Pin
#BYTE
#RESET
RY/#BY
VDD
Byte Enable Input
Hardware Reset
Ready/Busy Status
Power Supply
Ground
#OE
21
Vss
22
23
24
#CE
A0
Vss
NC
No Connection
Publication Release Date: March 23, 2004
Revision A2
- 5 -
W19B(L)320ST/B
6. FUNCTIONAL DESCRIPTION
6.1 Device Bus Operation
6.1.1 Word/Byte Configuration
The #BYTE pin controls the device data I/O pins operate whether in the byte or word configuration.
When the #BYTE pin is ‘1’, the device is in word configuration; DQ0−DQ15 are active and controlled
by #CE and #OE.
When the #BYTE pin is ‘0’, the device is in byte configuration, and only data I/O pins DQ0−DQ7 are active
and controlled by #CE and #OE. The data I/O pins DQ8−DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
6.1.2 Reading Array Data
To read array data from the outputs, the #CE and #OE pins must be set to VIL. #CE is the power
control and used to select the device. #OE is the output control and gates array data to the output
pins. #WE should stay at VIH. The #BYTE pin determines the device outputs array data whether in
words or bytes.
The internal state machine is set for reading array data when device power-up, or after a hardware
reset. This ensures that no excess modification of the memory content occurs during the power
transition. In this mode there is no command necessary to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until the command register contents are
changed.
6.1.3 Writing Commands/Command Sequences
In writhing a command or command sequence (which includes programming data to the device and
erasing sectors of memory), the system must drive #WE and #CE to VIL, and #OE to VIH.
For program operations, the #BYTE pin determines the device accepts program data whether in bytes
or in words. Refer to “Word/Byte Configuration” for more information.
The Unlock Bypass mode of device is to facilitate a faster programming. When the device enters into
the Unlock Bypass mode, only two write cycles are required to program a word or byte. Please refer to
"Word/Byte Configuration” section for details on programming data to the device using both standard
and Unlock Bypass command sequences.
The erase operation can erase a sector, multiple sectors, even the entire device. The “sector address”
is the address bits required to solely select a sector.
Accelerated Program Operation
The device provides accelerated program operations through the ACC function. This is one of two
functions provided by the #WP/ACC pin. This function is primarily intended to allow a faster
manufacturing throughput in the factory.
If #WP/ACC pin is set at VHH, the device automatically enters into the Unlock Bypass mode. Then the
device will temporarily unprotect any protected sectors, and uses the higher voltage on this pin to
reduce the time required for program operations. The system would use a two-cycle program
command sequence required by the Unlock Bypass mode. When VHH is removed from the #WP/ACC
pin, the device is back to a normal operation.
- 6 -
W19B(L)320ST/B
Please note that the #WP/ACC pin can not be at VHH for operations excepts accelerated
programming; otherwise, the device will be damaged. In addition, the #WP/ACC pin can not be left
floating; otherwise, an unconnected inconsistent behavior will occur.
Autoselect Functions
When the system writes the autoselect command sequence, the device enters the autoselect mode.
The system can then read autoselect codes from the internal register (which is separate from the
memory array) on DQ0–DQ7. The standard read cycle timings is applied in this mode. Please refer to
the Autoselect Mode and Autoselect Command Sequence sections for more information.
6.1.4 Standby Mode
When the system is not reading or writing to the device, the device will be in a standby mode. In this
mode, current consumption is greatly reduced, and the outputs are in the high impedance state,
independent from the #OE input.
When the #CE and #RESET pins are both held at VDD ± 0.3V, the device enters into the CMOS standby
mode (note that this is a more restricted voltage range than VIH.) When #CE and #RESET are held at VIH,
but not within VDD ± 0.3V, the device will be in the standby mode, but the standby current will be greater.
The device requires standard access time (tCE) for read access when the device is in either of these standby
modes, before it is ready to read data.
When the device is deselected during erasing or programming, the device initiates active current until
the operation is completed.
6.1.5 Automatic Sleep Mode
The automatic sleep mode minimizes device's energy consumption. When addresses remain stable
for tACC +30 nS, the device will enable this mode automatically. The automatic sleep mode is
independent from the #CE #WE and #OE control signals. Standard address access timings provide
,
,
new data when addresses are changed. In sleep mode, output data is latched and always available to
the system.
6.1.6 #RESET: Hardware Reset Pin
The #RESET pin provides a hardware method to reset the device to reading array data. When the
#RESET pin is set to low for at least a period of tRP, the device will immediately terminate every
operations in progress, tri-states all output pins, and ignores all read/write commands for the duration
of the #RESET pulse. The device also resets the internal state machine to reading array data mode.
To ensure data integrity, the interrupted operation needs to be reinitiated when the device is ready to
accept another command sequence.
Current is reduced for the duration of the #RESET pulse. When #RESET is held at VSS ± 0.3V, the
device initiates the CMOS standby current (ICC4). If #RESET is held at VIL but not within VSS ± 0.3V,
the standby current will be greater.
The #RESET pin may be tied to the system-reset circuitry. Thus the system reset would also reset the
device, enabling the system to read the boot-up firmware from the device.
If #RESET is asserted during the program or erase operation, the RY/#BY pin will be at “0” (busy) until
the internal reset operation is complete. If #RESET is asserted when a program or erase operation is
not processing (RY/#BY pin is “1”), the reset operation is completed within a time of tREADY (not during
Embedded Algorithms). After the #RESET pin returns to VIH, the system can read data tRH.
Publication Release Date: March 23, 2004
- 7 -
Revision A2
W19B(L)320ST/B
6.1.7 Output Disable Mode
When the #OE input is at VIH, output from the device is disabled. The output pins are set in the high
impedance state.
6.1.8 Autoselect Mode
The autoselect mode offers manufacturer and device identification, as well as sector protection
verification, through identifier codes output on DQ0−DQ7. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (8.5 V to 12.5 V) on address
pins A9. Address pins A6, A1, and A0 must be as shown in table. In addition, when verifying sector
protection, the sector address must appear on the appropriate highest order address bits. When all
necessary bits have been set as required, the programming equipment may then read the
corresponding identifier code on DQ0−DQ7.
To access the autoselect codes in-system, the host system can issue the autoselect command
through the command register. This method does not require VID. Also refer to the Autoselect
Command Sequence section for more information.
6.1.9 Sector/Sector Block Protection and Unprotection
The hardware sector protection feature disables both program and erase operations in any sectors.
The hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors. Sector protection/unprotection can be implemented through two methods.
The primary method requires VID on the #RESET pin, and can be implemented either in-system or through
programming equipment. This method uses standard microprocessor bus cycle timing.
The alternate method intended only for programming equipment requires VID on address pin A9 and #OE It
is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for
details.
6.1.10 Write Protect (
#WP
)
The Write Protect function provides a hardware method to protect the certain boot sectors without
using VID. This function is one of two features provided by the #WP/ACC pin.
When the #WP/ACC pin is set at VIL, the device disables program and erase functions in the two
outermost 8 Kbyte boot sectors independently of whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block Protection and Unprotection.” The two outermost
8 Kbyte boot sectors are the two sectors containing either the lowest addresses in a bottom-boot-
configured device or the highest addresses in a top-boot-configured device.
When the #WP/ACC pin is set at VIH, the device reverts to the two outermost 8K Byte boot sectors
were last set either to be protected or unprotected. That is, sector protection or unprotection for these
two sectors depends on whether they were last protected or unprotected using the method described
in “Sector/Sector Block Protection and Unprotection”.
Please note that the #WP/ACC pin must not be left floating or unconnected; otherwise, the
inconsistent behavior of the device may occur.
- 8 -
W19B(L)320ST/B
6.1.11 Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system.
When the #RESET pin is set to VID (8.5V−12.5V), the Sector Unprotect mode is activated. During this
mode, formerly protected sectors can be programmed or erased by selecting the sector addresses.
What if VID is removed from the #RESET pin, all the previously protected sectors are protected again.
6.1.12 Security Sector Flash Memory Region
The Security Sector feature provides an OTP memory region that enables permanent device
identification through an Electronic Serial Number (ESN). The Security Sector uses a Security Sector
Indicator Bit (DQ7) to indicate whether the Security Sector is locked or not when shipped from the
factory. The DQ7 is permanently set when it is in the factory and cannot be changed, which prevents
copying of a factory locked device. This ensures the security of the ESN when the product is shipped
to the field. This issue should be considered during system design. Winbond offers the device with the
Security Sector either factory locked or customer lockable. The factory-locked version is always
protected when shipped from the factory, and has the Security Sector Indicator Bit permanently set to
“1.” The customer-lockable version is shipped with the Security Sector unprotected, which allowing
customers to utilize the sector in any ways they choose. The customer-lockable version has the
Security Sector Indicator Bit permanently set to “0.” Thus, the Security Sector Indicator Bit prevents
customer-lockable devices from being used to replace devices that are factory locked.
The system accesses the Security Sector through a command sequence (see “Enter Security
Sector/Exit Security Sector Command Sequence”). After the system has written the Enter Security
Sector command sequence, it may read the Security Sector by using the addresses normally
occupied by the boot sectors. This mode of operation continues until the system issues the Exit
Security Sector command sequence, or until power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending commands to the boot sectors.
Factory Locked: Security Sector Programmed and Protected At the Factory
The device Security Sector is protected when it is shipped from the factory, and it cannot be modified
in any way. The device is available to be preprogrammed by one of the following:
•
•
•
A random, secure ESN only
Customer code through the supplier's service
Both a random, secure ESN and customer code through supplier's service.
In devices with an ESN, the Bottom Boot device will be with the 16-byte ESN in the lowest
addressable memory area at addresses 000000h–000007h in word mode (or 000000h–00000Fh in
byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest
8 Kbyte boot sector at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h–3FE00Fh
in byte mode). Customers may choose have their code programmed by Winbond. Winbond can
program the customer’s code, with or without the random ESN. The devices are then shipped with the
Security Sector permanently locked.
Publication Release Date: March 23, 2004
- 9 -
Revision A2
W19B(L)320ST/B
Customer Lockable: Security Sector NOT Programmed or Protected At the Factory
If the security feature is not necessary, the Security Sector can be seen as an additional OTP memory
space. When in system design, this issue should be considered. The Security Sector can be read,
programmed, but cannot be erased. Please note that when programming the Security Sector, the
accelerated programming (ACC) and unlock bypass functions are not available. The Security Sector
area can be protected using one of the following procedures:
•
Write the three-cycle Enter Security Sector Region command sequence, and then follow the
in-system sector protect algorithm, except that #RESET may be at either VIH or VID. This
allows in-system protection of the Security Sector without raising any device pin to a high
voltage.
Please note that this method is only suitable for the Security Sector.
•
Write the three-cycle Enter Security Sector Region command sequence, and then use the
alternate method of sector protection described in the “Sector/ Sector Block Protection and
Unprotection” section. When the Security Sector is locked and verified, the system must write
the Exit Security Sector Region command sequence to return to reading and writing the
remainder of the array.
The Security Sector protection must be used with caution, since there is no procedure available for
unprotecting the Security Sector area and none of the bits in the Security Sector memory space can
be modified in any ways.
6.1.13 Hardware Data Protection
The command sequence requirements of unlock cycles for programming or erasing provides data
protection against negligent writes. In addition, the following hardware data protection measures
prevent inadvertent erasure or programming, which might be caused by spurious system level signals
during VDD power-up and power-down transitions, or from system noise.
Write Pulse “Glitch” Protection
Noise pulses, which is less than 5 nS (typical) on #OE, #CE or #WE, do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of #OE = VIL, #CE = VIH or #WE = VIH. #CE and #WE
must be a logical zero while #OE is a logical one to initiate a write cycle.
Power-Up Write Inhibit
During power up, if #WE = #CE = VIL and #OE = VIH, the device does not accept commands on the
rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up.
6.2 Command Definitions
The device operation can be initiated by writing specific address and data commands or sequences
into the command register. The device will be reset to reading array data when writing incorrect
address and data values or writing them in the improper sequence.
The addresses will be latched on the falling edge of #WE or #CE, whichever happens later; while the
data will be latched on the rising edge of #WE or #CE, whichever happens first. Please refer to timing
waveforms.
- 10 -
W19B(L)320ST/B
6.2.1 Reading Array Data
After device power-up, it is automatically set to reading array data. There is no commands are
required to retrieve data. After completing an Embedded Program or Embedded Erase algorithm, the
device is ready to read array data.
After the device accepts an Erase Suspend command, it enters the erase-suspend-read mode. After
this the system can read data from any non-erase-suspended sector. And then, after completing a
programming operation in the Erase Suspend mode, the system may once again read array data with
the same exception. Please refer to Erase Suspend/Erase Resume Commands section for detail
information.
The system must initiate the reset command to return the device to read (or erase-suspend-read)
mode if DQ5 goes high during an active program or erase operation; otherwise, the device is in the
autoselect mode. See Reset Command section and Requirements for Reading Array Data in the
Device Bus Operations section for more information.
6.2.2 Reset Command
The device will be to the read or erase-suspend-read mode when writing the reset command. For this
command, the address bits are Don’t Care.
The reset command may be written between the sequence cycles in an erase command sequence
before erasing begins. This resets the device to which the system was writing to the read mode. Once
erasure begins, however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence
before programming begins. This resets the device, to which the system was writing to the read mode.
If the program command sequence is written to the device, in the Erase Suspend mode, writing the
reset command returns the device to the erase-suspend-read mode. When programming begins, the
device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command
sequence. When in the autoselect mode, the reset command must be written to return to the read
mode. If the device entered into the autoselect mode while in the Erase Suspend mode, writing the
reset command returns the device to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device
to the read mode (or erase-suspend-read mode if the device was in Erase Suspend).
6.2.3 Autoselect Command Sequence
The autoselect command sequence provides the host system to access the manufacturer and device
codes, and determine whether a sector is protected or not. This is an alternative method, which is
intended for PROM programmers and requires VID on address pin A9. The autoselect command
sequence may be written to an address within the device that is either in the read or erase-suspend-
read mode. When the device is actively programming or erasing, the autoselect command may not be
written.
The first writing two unlock cycles initiate the autoselect command sequence. This is followed by a
third write cycle that contains the autoselect command. The device then enters into the autoselect
mode. The system may read at any address without initiating another autoselect command sequence:
•
A read cycle at address XX00h returns the manufacturer code.
•
A read cycle at address XX01h in word mode(or XX02h in byte mode) returns the device code.
Publication Release Date: March 23, 2004
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Revision A2
W19B(L)320ST/B
•
A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in
word mode (or the address 04h on A6-A-1 in byte mode) returns 01h if the sector is protected, or
00h if it is unprotected.
To return to read mode (or erase-suspend-read mode if the device was previously in Erase Suspend),
the system must write the reset command.
6.2.4 Enter Security Sector/Exit Security Sector Command Sequence
The Security Sector region provides a secured data area containing a random, sixteen-byte electronic
serial number (ESN). The system can access the Security Sector region by issuing the three-cycle
Enter Security Sector command sequence. The device continues to access the Security Sector region
until the system issues the four-cycle Exit Security Sector command sequence. The Exit Security
Sector command sequence returns the device to normal operation. See “Security Sector Flash
Memory Region” for further information.
6.2.5 Byte/Word Program Command Sequence
The device can be programmed either by word or byte, which depending on the state of the #BYTE
pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by
writing two unlock write cycles, followed by the program setup command. The program address and
data are written next, which in turn initiate the Embedded Program algorithm. The device automatically
provides internally generated program pulses and verifies the programmed cell margin.
Once the Embedded Program algorithm is complete, the device then returns to the read mode and
addresses are no longer latched. The system can determine the status of the program operation by
using DQ7, DQ6, or RY/#BY. Please refer to the Write Operation Status section for bits' information.
Any commands written to the device during the Embedded Program Algorithm are ignored. Please
note that a hardware reset will immediately stop the program operation. The program command
sequence should be reinitiated when the device has returned to the read mode, in order to ensure
data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from “0” back to “1.” If trying to do so may cause that device to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate that the operation is successful. However, a succeeding read will show that
the data is still “0.” Only erase operations can change “0” to “1.”
6.2.6 Unlock Bypass Command Sequence
The unlock bypass feature provides the system to program bytes or words to device which is faster
than using the standard program command sequence. The unlock bypass command sequence is
initiated by first writing two unlock cycles. And a third write cycle containing the unlock bypass
command, 20h, is followed. Then, the device enters into the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. In the same manner, additional data is programmed. This mode dispenses
with the initial two unlock cycles which required in the standard program command sequence,
resulting in faster total programming time.
All through the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset
commands are valid. The system must issue the two-cycle unlock bypass reset command sequence
to exit the unlock bypass mode. The first cycle must contain the data 90h. The second cycle need to
contain the data 00h. Then, the device returns to the read mode.
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W19B(L)320ST/B
The device offers accelerated program operations by the #WP/ACC pin. When the VHH is set at the
#WP/ACC pin, the device automatically enters into the Unlock Bypass mode. Then, the two-cycle
Unlock Bypass program command sequence may be written. To accelerate the operation, the device
must use the higher voltage on the #WP/ACC pin. Please note that the #WP/ACC pin must not be at
VHH in any operation other than accelerated programming; otherwise the device may be damaged. In
addition, the #WP/ACC pin must not be left floating or unconnected; otherwise the device inconsistent
behavior may occur.
6.2.7 Chip Erase Command Sequence
Chip erase is a six-bus cycle operation. Writing two unlock cycles initiates the chip erase command
sequence, which is followed by a set-up command. After chip erase command, two additional unlock
write cycles are then followed, which in turn invokes the Embedded Erase algorithm. The system
preprogram is not required prior to erase. Before electrical erase, the Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern. Any controls or
timings during these operations is not required in system.
As the Embedded Erase algorithm is complete, the device returns to the read mode and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7,
DQ6, DQ2, or RY/#BY. Please refer to the Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation will be ignored. However, a hardware reset
shall terminate the erase operation immediately. If this happens, to ensure data integrity, the chip
erase command sequence should be reinitiated when the device has returned to reading array data.
6.2.8 Sector Erase Command Sequence
Sector erase is a six-bus cycle operation. Writing two unlock cycles initiates the sector erase
command sequence, which is followed by a set-up command. Two additional unlock cycles are
written, and are then followed by the address of the sector to be erased, and the sector erase
command.
The device does not require the system to preprogram before erase. Before electrical erase, the
Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data
pattern. Any controls or timings during these operations is not required in system.
A sector erase time-out of 50 µS occurs after the command sequence is written. Additional sector
addresses and sector erase commands may be written during the time-out period. Loading the sector
erase buffer may be done in any sequence, and the number of sectors may be from one sector to all
sectors. The time between these additional cycles must be less than 50 µS; otherwise, erasure may
begin. Any sector erase address and command following the exceeded time-out may or may not be
accepted. To ensure all commands are accepted, processor interrupts be disabled during this time is
recommended. The interrupts can be re-enabled after the last Sector Erase command is written. Any
command other than Sector Erase or Erase Suspend during the time-out period resets the device to
the read mode. The system must rewrite the command sequence and any additional addresses and
commands.
The system can monitor DQ3 to determine whether or not the sector erase timer has timed out (See
the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final #WE
pulse in the command sequence.
Publication Release Date: March 23, 2004
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Revision A2
W19B(L)320ST/B
As the Embedded Erase algorithm is complete, the device returns to reading array data and
addresses are no longer latched. Please refer to the Write Operation Status section for information on
these status bits.
When the sector erase operation begins, only the Erase Suspend command is valid. All other
commands are ignored. However, a hardware reset shall terminate the erase operation immediately. If
this occurs, to ensure data integrity, the sector erase command sequence should be reinitiated once
the device has returned to reading array data.
6.2.9 Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. This command is valid only
during the sector erase operation, which includes the 50 µS time-out period during the sector erase
command sequence. If written during the chip erase operation or Embedded Program algorithm, the
Erase Suspend command is ignored.
As the Erase Suspend command is written during the sector erase operation, a maximum of 20 µs is
required to suspend the erase operation. However, while the Erase Suspend command is written
during the sector erase time-out, the device shall terminate the time-out period and suspends the
erase operation immediately.
The device enters into an erase-suspend-read mode after the erase operation has been suspended.
The system can read data from, or program data to, any sector not selected for erasure. (In device
“erase suspends” all sectors are selected for erasure.) The “reading at any address within erase-
suspended sectors produces status” information is on DQ0−DQ7. The system can use DQ7, or DQ6
and DQ2 together, to determine whether a sector is actively erasing or is erase-suspended. Please
refer to the Write Operation Status section for detail information on these status bits.
After an erase-suspended program operation is complete, the device returns to the erase-suspend-
read mode. Using the DQ7 or DQ6 status bits, the system can determine the status of the program
operation, just as in the standard Byte Program operation. Please refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the autoselect command sequence also can be issued. Please refer to
the Autoselect Mode and Autoselect Command Sequence sections for details.
The Erase Resume command must be written to resume the sector erase operation. Further writes of the
Resume command are ignored. After the chip has resumed erasing, another Erase Suspend command can
be written.
6.3 Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or
erase operation is complete or in progress. The device also offers a hardware-based output signal,
RY/#BY, to determine whether an Embedded Program or Erase operation is in progress or has been
completed.
6.3.1 DQ7: #Data Polling
The #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in
progress or completed, or whether or not the device is in Erase Suspend. Data Polling is valid after
the rising edge of the final #WE pulse in the command sequence.
- 14 -
W19B(L)320ST/B
During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. Once the
Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The
system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, #Data Polling on DQ7 is active for about 1µS, and then the
device returns to the read mode.
During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded
Erase algorithm has completed, or when the device enters the Erase Suspend mode, #Data Polling
produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to
read valid status information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, #Data
Polling on DQ7 is active for about 100 µS, and then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected. However, if the system reads DQ7 at an address
within a protected sector, the status may not be valid.
Just before the completion of an Embedded Program or Erase operation, DQ7 may change
asynchronously with DQ0−DQ6 while Output Enable (#OE) is set to low. That is, the device may
change from providing status information to valid data on DQ7. Depending on when it samples the
DQ7 output, the system may read the status or valid data. Even if the device has completed the
program or erase operation and DQ7 has valid data, the data outputs on DQ0−DQ6 may be still
invalid. Valid data on DQ0-DQ7 will appear on successive read cycles.
6.3.2 RY/#BY: Ready/#Busy
The RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is
in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the
command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together
in parallel with a pull-up resistor to VDD.
When the output is low (Busy), the device is actively erasing or programming. (This includes
programming in the Erase Suspend mode.) When the output is high (Ready), the device is in the read
mode, the standby mode is in the erase-suspend-read mode.
6.3.3 DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or
complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at
any address, and is valid after the rising edge of the final #WE pulse in the command sequence
(before the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either #OE or #CE to control the read cycles. Once the
operation has completed, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6
toggles for about 100 µS, and then returns to reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected
sectors which are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress),
Publication Release Date: March 23, 2004
- 15 -
Revision A2
W19B(L)320ST/B
DQ6 toggles. While if the device enters the Erase Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively,
the system can use DQ7 (see DQ7: #Data Polling).
If a program address falls within a protected sector, DQ6 toggles for about 1 µs after the program
command sequence is written, and then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling when the Embedded
Program algorithm is complete.
Please also refer to DQ2: Toggle Bit II.
6.3.4 DQ2: Toggle Bit II
When used with DQ6, the “Toggle Bit II” on DQ2 indicates whether a particular sector is actively
erasing (i.e., the Embedded Erase algorithm is in progress), or the sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final #WE pulse in the command sequence.
DQ2 toggles as the system reads at addresses within those sectors that have been selected for
erasure. (The system may use either #OE or #CE to control the read cycles.) But DQ2 cannot
distinguish that whether the sector is actively erasing or is erase-suspended. By comparison, DQ6
indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which
sectors are selected for erasure. Therefore, both status bits are required for sector and mode
information.
6.3.5 Reading Toggle Bits DQ6/DQ2
Whenever the system initially starts to read toggle bit status, it must read DQ0−DQ7 at least twice in a
row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the
value of the toggle bit after the first read. While after the second read, the system would compare the
new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed
the program or erase operation. The system can read array data on DQ0−DQ7 on the following read
cycle.
However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is
high, the system should then determine again whether the toggle bit is toggling or not, since the toggle
bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device
has successfully completed the program or erase operation. If it is still toggling, the device did not
completed the operation, and the system must write the reset command to return to reading array
data.
Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5 through successive read cycles, and
determines the status as described in the previous paragraph. Alternatively, the system may choose
to perform other system tasks. In this case, the system must start at the beginning of the algorithm
while it returns to determine the status of the operation.
6.3.6 DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not
successfully completed.
- 16 -
W19B(L)320ST/B
The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously
programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device
stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”
Under both these conditions, the system must write the reset command to return to the read mode (or
to the erase-suspend-read mode if the device was previously in the erase-suspend-program mode).
6.3.7 DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
erasure has begun or not. (The sector erase timer does not apply to the chip erase command.) The
entire time-out applies after each additional sector erase command if additional sectors are selected
for erasure. Once the timeout period has completed, DQ3 switches from “0” to “1.” If the time between
additional sector erase commands from the system can be assumed to be less than 50 µS, the
system need not monitor, DQ3 does not need to be monitored. Please also refer to Sector Erase
Command Sequence section.
After the sector erase command is written, the system should read the status of DQ7 (#Data Polling)
or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read
DQ3. If DQ3 is“1,” the Embedded Erase algorithm has begun; all further commands (except Erase
Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept
additional sector erase commands.
The system software should check the status of DQ3 before and following each subsequent sector
erase command to ensure the command has been accepted. If DQ3 is high on the second status
check, the last command might not have been accepted.
Publication Release Date: March 23, 2004
- 17 -
Revision A2
W19B(L)320ST/B
7. TABLE OF OPERATION MODES
7.1 Device Bus Operations
ADDRESSES
DQ8-DQ15
DQ0-DQ7
MODE
#CE
#OE #WE #RESET #WP/ACC
(Note2)
AIN
#BYTE =VIH #BYTE =VIL
Read
Write
L
L
L
L
H
H
H
L
L
H
H
H
L/H
(Note3)
VHH
DOUT
DOUT
DQ8-DQ14
= High-Z,
AIN
(Note 4)
(Note 4)
(Note 4)
(Note 4)
DQ15=A-1
Accelerated Program
AIN
VDD
VDD
Standby
X
X
H
X
High-Z
High-Z
High-Z
± 0.3V
± 0.3V
Output Disable
Reset
L
H
X
H
X
H
L
L/H
L/H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
SA, A6 = L,
Sector Protect (note2)
L
L
H
H
X
L
L
VID
VID
VID
L/H
(Note 4)
(Note 4)
(Note 4)
X
X
X
X
A1 = H, A0 = L
SA, A6 = H,
Sector Unprotect (note2)
(Note3)
(Note3)
A1 = H, A0 = L
Temporary Sector
Unprotect
X
X
AIN
(Note 4)
High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5-12.5V, VHH = 9.0±0.5V, X = Don’t Care, SA = Sector Address, AIN
= Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A20:A0 in word mode (#BYTE = VIH), A20: A-1 in byte mode (#BYTE = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the”
Sector/Sector Block Protection and Unprotect ion” section.
3. If #WP/ACC = VIL, the two outermost boot sectors remain protected. If #WP/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector
Block Protection and Unprotect ion”. If #WP/ACC = VHH, all sectors will be unprotected.
4. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
- 18 -
W19B(L)320ST/B
7.2 Autoselect Codes (High Voltage Method)
DQ8 TO
A20 A11
A8
A5
DQ7
A9
DQ15
DESCRIPTION
#CE #OE #WE TO
TO
TO A6 TO A1 A0
TO
#BYTE #BYTE
= VIH = VIL
A12 A10
A7
A2
DQ0
Manufacturer ID:
Winbond
VIL
VIL
VIL VIL
VIL VIL
VIH
VIH
X
X
X
X
VID
VID
X
X
VIL
VIL
X
X
DAh
BAh
Device ID:
W19B(L)320ST
(Top Boot Block)
X
X
X
X
VIL VIH 22h
VIL VIH 22h
X
Device ID:
W19B(L)320SB
(Bottom Boot Block)
VIL VIL
VIL VIL
VIH
VIH
X
X
X
VID
VID
VIL
VIL
X
2Ah
01h
(protected)
00h
Sector Protection
Verification
X
VIH VIL
X
X
X
SA
X
X
X
X
(unprotected)
99h
(factory
locked)
19h (not
factory
locked)
Security Indicator Bit
(DQ7)
VIL
VIL VIL
VIH
X
X
VID
VIH VIH
X
X
Legend: SA = Sector Address, X = Don't Care.
Publication Release Date: March 23, 2004
Revision A2
- 19 -
W19B(L)320ST/B
Sector Address Table (Top Boot Block)
SECTOR ADDRESS
A20-A12
(X8)
(X16)
SECTOR SIZE
SECTOR
(Kbytes/Kwords)
ADDRESS RANGE
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
ADDRESS RANGE
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
000000XXX
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
- 20 -
W19B(L)320ST/B
Sector Address Table (Top Boot Block), continued
SECTOR ADDRESS
(X8)
(X16)
SECTOR SIZE
SECTOR
(Kbytes/Kwords)
A20-A12
ADDRESS RANGE
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3F1FFFh
3F2000h-3F3FFFh
3F4000h-3F5FFFh
3F6000h-3F7FFFh
3F8000h-3F9FFFh
3FA000h-3FBFFFh
3FC000h-3FDFFFh
3FE000h-3FFFFFh
ADDRESS RANGE
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1F8FFFh
1F9000h-1F9FFFh
1FA000h-1FAFFFh
1FB000h-1FBFFFh
1FC000h-1FCFFFh
1FD000h-1FDFFFh
1FE000h-1FEFFFh
1FF000h-1FFFFFh
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
110000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE = VIH).
Security Sector Addresses for Top Boot Devices
SECTOR ADDRESS
A20-A12
(X 8)
(X 16)
ADDRESS RANGE
1FF000h-1FF07Fh
SECTOR SIZE
(bytes/words)
DEVICE
ADDRESS RANGE
3FE000h-3FE0FFh
W19B320ST
111111XXX
256/128
Publication Release Date: March 23, 2004
Revision A2
- 21 -
W19B(L)320ST/B
Sector Address Table (Bottom Boot Block)
SECTOR ADDRESS
A20-A12
(X8)
(X16)
SECTOR SIZE
SECTOR
(Kbytes/Kwords)
ADDRESS RANGE
000000h-001FFFh
002000h-003FFFh
004000h-005FFFh
006000h-007FFFh
008000h-009FFFh
00A000h-00BFFFh
00C000h-00DFFFh
00E000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
ADDRESS RANGE
000000h-000FFFh
001000h-001FFFh
002000h-002FFFh
003000h-003FFFh
004000h-004FFFh
005000h-005FFFh
006000h-006FFFh
007000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
000000000
000000001
000000010
000000011
000000100
000000101
000000110
000000111
000001XXX
000010XXX
000011XXX
000100XXX
000101XXX
000110XXX
000111XXX
001000XXX
001001XXX
001010XXX
001011XXX
001100XXX
001101XXX
001110XXX
001111XXX
010000XXX
010001XXX
010010XXX
010011XXX
010100XXX
010101XXX
010110XXX
010111XXX
011000XXX
011001XXX
011010XXX
011011XXX
011100XXX
011101XXX
011110XXX
011111XXX
100000XXX
100001XXX
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
- 22 -
W19B(L)320ST/B
Sector Address Table (Bottom Boot Block), continued
SECTOR ADDRESS
A20-A12
(X8)
(X16)
SECTOR SIZE
SECTOR
(Kbytes/Kwords)
ADDRESS RANGE
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
ADDRESS RANGE
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA65
SA67
SA68
SA69
SA70
100010XXX
100011XXX
100100XXX
100101XXX
100110XXX
100111XXX
101000XXX
101001XXX
101010XXX
101011XXX
101100XXX
101101XXX
101110XXX
101111XXX
111000XXX
110001XXX
110010XXX
110011XXX
110100XXX
110101XXX
110110XXX
110111XXX
111000XXX
111001XXX
111010XXX
111011XXX
111100XXX
111101XXX
111110XXX
111111XXX
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Note: The address range is [A20: A-1] in byte mode (#BYTE =VIL) or [A20:A0] in word mode (#BYTE =VIH).
Security Sector Addresses for Bottom Boot Devices
SECTOR ADDRESS
A20-A12
(X8)
(X16)
ADDRESS RANGE
000000h-00007Fh
SECTOR SIZE
(bytes/words)
DEVICE
ADDRESS RANGE
000000h-0000FFh
W19B320SB
000000XXX
256/128
Publication Release Date: March 23, 2004
Revision A2
- 23 -
W19B(L)320ST/B
Top Boot Sector/Sector Block Address for Protection/Unprotection)
SECTOR
A20-A12
SECTOR/SECTOR BLOCK SIZE
000000XXX
000001XXX
000010XXX
000011XXX
SA0-SA3
256(4x64) K bytes
SA4-SA7
SA8-SA11
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
111100XXX
111101XXX
111110XXX
SA60-SA62
192(3x64) K bytes
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
- 24 -
W19B(L)320ST/B
Bottom Boot Sector/Sector Block Address for Protection/Unprotection)
SECTOR
A20-A12
SECTOR/SECTOR BLOCK SIZE
111111XXX
111110XXX
111101XXX
111100XXX
SA70-SA67
256(4x64) K bytes
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
256(4x64) K bytes
000011XXX
000010XXX
000001XXX
SA10-SA8
192(3x64) K bytes
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
8 K bytes
Publication Release Date: March 23, 2004
Revision A2
- 25 -
W19B(L)320ST/B
7.3 CFI Query Identification String
ADDRESS
(Word Mode)
10h
ADDRESS
(Byte Mode)
20h
DESCRIPTION
DATA
0051h
0052h
0059h
0006h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Query-unique ASCII string "QRY"
11h
12h
22h
24h
13h
14h
26h
28h
Primary OEM Command Set
15h
16h
2Ah
2Ch
Address for Primary Extended Table
17h
18h
2Eh
30h
Alternate OEM Command set (00h = none exists)
Address for Alternate OEM Extended table (00h = none exists)
19h
1Ah
32h
34h
System Interface String
DESCRIPTION
ADDRESS
(Word Mode)
ADDRESS
(Byte Mode)
DATA
0027h
0036h
VDD Min. (write/erase)
D7-D4: volt, D3-D0: 100 mV
1Bh
1Ch
36h
38h
VDD Max. (write/erase)
D7-D4: volt, D3-D0: 100 mV
VPP Min. voltage (00h = no Vpp pin present)
1Dh
1Eh
1Fh
0000h
0000h
0004h
3Ah
3Ch
3Eh
VPP Max. voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2N µS
Typical timeout for Min. size buffer write 2N µS (00h = not
20h
0000h
40h
supported)
Typical timeout for individual block erase 2N mS
Typical timeout for full chip erase 2N mS (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
21h
22h
23h
24h
25h
000Ah
0000h
0005h
0000h
0004h
42h
44h
46h
48h
4Ah
Max. timeout per individual block erase 2N times typical
Max. timeout for full chip erase 2N times typical ( 00h = not
26h
0000h
4Ch
supported)
- 26 -
W19B(L)320ST/B
Device Geometry Definition
ADDRESS
(Write Mode)
27h
DATA
ADDRESS
(Byte Mode)
4Eh
DESCRIPTION
Device size =2N bytes
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
28h
29h
50h
52h
Flash device interface description (refer to CFI publication 100)
Max. number of bytes in multi-byte write=2N (00h = not
supported)
2Ah
2Bh
54h
56h
Number Of Erase Block Regions Within Devices
2Ch
58h
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
Erase block region 1 information
(refer to the CFI specification or CFI publication 100 )
31h
32h
33h
34h
62h
64h
66h
68h
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
Publication Release Date: March 23, 2004
Revision A2
- 27 -
W19B(L)320ST/B
Primary Vendor-Specific Extended Query
DESCRIPTION
ADDRESS
(Word Mode)
ADDRESS
(Byte Mode)
80h
DATA
40h
41h
42h
43h
44h
0050h
0052h
0049h
0031h
0031h
Query-unique ASCII string "PRI"
82h
84h
Major version number, ASCII
Minor version number, ASCII
86h
88h
Address sensitive unlock (Bits 1−0)
0 = required, 1 = not required
45h
0000h
8Ah
Silicon Revision Number (Bit 7-2)
Erase suspend
0 = Not supported, 1 = To read only; 2 = To read & write
Sector protect
0 = Note supported, 1 = Supported
Sector Temporary Unprotect
00 = Not supported, 01 = Supported
Sector protect/unprotect scheme
Simultaneous operation
46h
47h
0002h
0001h
8Ch
8Eh
48h
49h
4Ah
0001h
0004h
0000h
90h
92h
94h
00 = Not supported
Burst mode type
00 = Not supported, 01 = Supported
Page mode type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7−D4; Volt, D3−D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7−D4; Volt, D3−D0: 100 mV
Top/bottom boot Sector Flag
4Bh
4Ch
4Dh
4Eh
4Fh
0000h
0000h
0085h
0095h
000Xh
96h
98h
9Ah
9Ch
9Eh
02h=Bottom Boot Device, 03h = Top Boot Device
- 28 -
W19B(L)320ST/B
7.4 Command Definitions
BUS CYCLES (NOTE 2-5)
THIRD FOURTH
ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA
COMMAND SEQUENCE
CYCLE
FIRST
SECOND
FIFTH
SIXTH
(NOTE 1)
RA
XXX
555
AAA
555
RD
F0
Read (note 6)
Reset (note 7)
1
1
2AA
555
2AA
555
555
AAA
555
Word
Byte
Word
Byte
AA
AA
55
55
A0
20
PA
PD
Normal Program
4
Unlock Bypass
3
AAA
AAA
Unlock Bypass Program
XXX
XXX
A0
90
PA
PD
00
2
2
6
(Note 11)
Unlock Bypass Reset
(note12)
XXX
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
555
2AA
555
2AA
555
555
AAA
555
555
AAA
555
2AA
555
2AA
555
555
AAA
Word
Byte
AA
AA
55
55
80
80
AA
AA
55
55
10
30
Chip Erase
Word
Sector Erase
Byte
Erase Suspend (note 13)
Erase Resume (note 14)
SA
6
AAA
AAA
B0
30
1
1
2AA
555
2AA
555
2AA
555
AAA
55
AAA
555
Word
Byte
DA
Manufacturer
AA
AA
55
55
90
90
X00
4
Code
X01
X02
X03
Word
Device Code
Byte
(note 16)
99/19
4
Security Sector Word
AA
55
90
4
4
Factory Protect
AAA
555
AAA
X06
Byte
(Note 9)
Sector/Secto
Word
555
2AA
555
X02
r Block
AA
55
90
00/01
Protect
Verify (note
AAA
555
AAA
X04
10)
Byte
555
AAA
555
AAA
55
2AA
555
2AA
555
555
AAA
555
Word
Byte
Word
Byte
Enter Security
Sector Region
AA
AA
55
55
88
90
3
4
Exit Security
XXX
00
Sector Region
AAA
Common Flash
Interface (CFI)
Query (note 15)
Word
98
1
AA
Byte
Legend:
X = Don’t Care
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the #WE or #CE pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of #WE or #CE pulse, whichever happens first.
RD = Data read from location RA during read operation.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20-A12 uniquely select any sector.
Publication Release Date: March 23, 2004
- 29 -
Revision A2
W19B(L)320ST/B
Notes:
1. See Bus Operations Table for details.
2. All values are in hexadecimal
3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles.
4. Data bits DQ15−DQ8 are don’t care in command sequences, except for RD and PD.
5. Unless otherwise noted, address bits A20−A11 are don’t cares.
6. No unlock or command cycles required when device is in read mode.
7. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase
Suspend) when the device is in the autoselect mode, or if DQ5 goes high (while the device is providing status
information).
8. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15−DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
9. The data is 99h for factory locked and 19h for not factory locked.
10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
11. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
12. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass
mode.
13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
mode. The Erase Suspend command is valid only during a sector erase operation.
14. The Erase Resume command is valid only during the Erase Suspend mode.
15. Command is valid when device is ready to read array data or when device is in autoselect mode.
16. See Autoselect Codes table for device ID information
7.5 Write Operation Status
DQ7
DQ5
DQ2
STATUS
DQ6
DQ3
RY/#BY
(Note 2)
(Note1)
(Note 2)
Embedded Program Algorithm
Embedded Erase Algorithm
#DQ7
Toggle
Toggle
0
0
0
N/A
1
No toggle
Toggle
0
0
1
Standard
Mode
0
1
Erase Suspended Sector
No toggle
N/A
Toggle
Erase-
Suspend-
Read
Erase
Non-Erase Suspended
Sector
Suspend
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Mode
Erase-Suspend-Program
#DQ7
Toggle
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing
limits. Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 requires a valid address when reading status information. Please refer to related sections for details.
- 30 -
W19B(L)320ST/B
7.6 Temporary Sector Unprotect Algorithm
START
#RESET = V
(Note 1)ID
Perform Erase or
Program Operations
#RESET = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected (If #WP/ACC = VIL, outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Publication Release Date: March 23, 2004
Revision A2
- 31 -
W19B(L)320ST/B
7.7 In-System Sector Protect/Unprotect Algorithms
START
START
Protect all sectors
The indicated portion
PLSCNT=1
PLSCNT=1
#RESET=VID
Wait 1
of the sector protect
algorithm must be
performed for all
#RESET=VID
unprotected sectors
prior to issuing the
s
Wait 1 µ
µ
s
first sector
unprotect address
No
First Write
Cycle=60h?
No
Temporary Sector
Unprotect Mode
Temporary Sector
Unprotect Mode
First Write
Cycle=60h?
Yes
Yes
Set up sector
address
All sector
protected?
No
Sector Protect:
Write 60h to sector
Yes
address with
A6=0,A1=1,A0=0
Set up first
sector address
µ
Wait 150
s
Sector Unrotect:
Write 60h to sector
address with
A6=1,A1=1,A0=0
Verity Sector
Protect:Write 40h
Reset
PLSCNT=1
to sector address
Increment
PLSCNT
Wait 15 mS
with A6=0,
A1=1,A0=0
Increment
PLSCNT
Verity Sector
Unprotect:Write 40h
Read from
to sector address
sector address
No
with A6=0,
A1=1,A0=0
with A6=1,
A1=1,A0=0
Read from
No
sector address
with A6=1,
A1=1,A0=0
PLSCNT
=25?
Data=01h?
Yes
No
Yes
Set up
next sector
address
PLSCNT
=1000?
No
Data=00h?
Yes
Protect another
sector?
Device failed
Yes
No
Yes
Remove V
ID
No
from #RESET
Last sector
verified
Device failed
Write reset
command
Yes
Sector Protect
Algorithm
Sector Unprotect
Algorithm
Remove V
ID
from #RESET
Sector Protect
complete
Write reset
command
Sector Unprotectt
complete
- 32 -
W19B(L)320ST/B
7.8 Program Algorithm
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
Yes
No
No
Increment Address
Last Address?
Yes
Programming
Completed
7.9 Erase Algorithm
START
Write Program
Command Sequence
(Note1,2)
Data Poll to Erasing
Bank from System
Embedded
Erase
algorithm
No
in progress
Data=FFh?
Yes
Erase Completed
Notes:
1. See Command Definitions Table for erase command sequence details.
2. See DQ3 section for the sector erase timer details.
Publication Release Date: March 23, 2004
Revision A2
- 33 -
W19B(L)320ST/B
7.10 Data Polling Algorithm
START
Read DQ7-DQ0
Addr=VA
Yes
DQ7=Data?
No
No
DQ5=1?
Yes
Read DQ7-DQ0
Addr=VA
Yes
DQ7=Data?
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector erase operation; a valid address is any sector address within the
sector being erased. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
- 34 -
W19B(L)320ST/B
7.11 Toggle Bit Algorithm
START
Read DQ7-DQ0
Read DQ7-DQ0
No
Toggle Bit
=Toggle?
Yes
No
DQ5=1?
Yes
Read DQ7-DQ0
Twice
No
Toggle Bit
=Toggle?
Yes
Program/Erase
Operation Not
Program/Erase
Complete
Complete,Write
Reset Command
Note: The system should recheck the toggle bit even if DQ5 =”1” because the toggle bit may stop toggling as DQ5 changes to
“1”. See the subsections on DQ6 and DQ2 for more information
Publication Release Date: March 23, 2004
- 35 -
Revision A2
W19B(L)320ST/B
8. ELECRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER
Storage Temperature Plastic Packages
Ambient Temperature with Power Applied
Voltage with Respect to Ground VDD (Note 1)
A9, #OE, and #RESET (Note 2)
#WP/ACC
All other pins (Note 1)
Output Short Circuit Current (Note 3)
Notes:
RATING
-65 to +150
-65 to +125
-0.5 to +4.0
-0.5 to +12.5
-0.5 to +10.5
-0.5 to VDD +0.5
200
UNIT
°C
°C
V
V
V
V
mA
1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to
-2.0 V for periods of up to 20 nS. Maximum DC voltage on input or I/O pins is VDD +0.5 V. During voltage transitions,
input or I/O pins may overshoot to VDD +2.0 V for periods up to 20 nS.
2. Minimum DC input voltage on pins A9, #OE, #RESET, and #WP/ACC is -0.5 V. During voltage transitions, A9, #OE,
#WP/ACC, and #RESET may overshoot VSS to -2.0 V for periods of up to 20 nS. Maximum DC input voltage on pin A9
is +12.5 V which may overshoot to +14.0 V for periods up to 20 nS. Maximum DC input voltage on #WP/ACC is +9.5 V
which may overshoot to +12.0 V for periods up to 20 nS.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than
one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the device at these or any other conditions above those
indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
8.2 Operating Ranges
PARAMETER
RATING
-40 to +85
0 to +70
-20 to +85
2.7 to 3.6
3.0 to 3.6
UNIT
Industrial
Commercial
Extend
W19B320S
W19L320S
Ambient Temperature (TA)
°C
VDD Supply Voltages
V
Operating ranges define those limits between which the functionality of the device is guaranteed.
- 36 -
W19B(L)320ST/B
8.3 DC Characteristics
8.3.1 CMOS Compatible
LIMITS
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MIN. TYP. MAX.
Input Load Current
ILI VIN =VSS to VDD, VDD = VDD (Max.)
ILIT VDD = VDD (Max.), A9 = 12.5 V
-
-
-
-
-
-
-
±3.0
35
35
±1.0
16
4
µA
µA
A9 Input Load Current
#RESET Input Load Current
Output Leakage Current
ILR VDD = VDD (Max.), #RESET = 12.5 V
ILO VOUT =VSS to VDD, VDD =VDD (Max.)
-
µA
-
µA
5 MHz
1 MHz
5 MHz
1 MHz
10
2
mA
mA
mA
mA
mA
#CE = VIL, #OE = VIH
Byte Mode
VDD Active Read Current (Note 1, 2)
ICC1
10
2
16
4
#CE = VIL, #OE = VIH
Word Mode
VDD Active Write Current (Note 2, 3)
VDD Standby Current (Note 2)
VDD Reset Current (Note 2)
ICC2
ICC3
ICC4
-
-
-
15
0.2
0.2
45
5
#CE = VIL, #OE = VIH, #WE = VIL
#CE, #RESET = VDD ±0.3V
#RESET = VSS ±0.3V
µA
µA
5
Automatic Sleep Mode Current
(note 2, 4)
Input Low Voltage
ICC5
-
0.2
5
VIH = VDD ±0.3V, VIL = VSS ± 0.3V
µA
V
VIL
-
-
-0.5
-
-
0.8
0.7 x
VDD
VDD
Input High Voltage
VIH
V
+0.3
Voltage for Autoselect and Temporary
VDD = 3.0V ±10% (W19B320S) or
VDD = 3.3V ±10% (W19L320S)
Sector protect/ Unprotect and Program VHH
Acceleration
8.5
-
9.5
V
Voltage for Autoselect and Temporary
VDD = 3.0V ±10% (W19B320S) or
VDD = 3.3V ±10% (W19L320S)
VID
8.5
-
-
-
-
12.5
0.45
-
V
V
V
Sector Unprotected
Output Low Voltage
VOL IOL = 4.0 mA, VDD = VDD (Min.)
0.85 x
VDD
VOH1 IOH = -2.0 mA, VDD = VDD (Min.)
Output High Voltage
VDD-
0.4
VOH2
-
-
IOH = -100 µA, VDD = VDD (Min.)
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with #OE at VIH.
2. Maximum ICC specifications are tested with VDD = VDD max.
3.
ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 nS. Typical sleep mode
current is 200 nA.
Publication Release Date: March 23, 2004
- 37 -
Revision A2
W19B(L)320ST/B
8.4 AC Characteristics
8.4.1 Test Condition
TEST CONDITION
90 nS
1 TTL gate
UNIT
Output Load
Output Load Capacitance, CL (including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input Timing Measurement Reference Levels
Output Timing Measurement Reference Levels
100
5
pF
nS
V
V
V
0 − 3.0
1.5
1.5
8.4.2 AC Test Load and Waveforms
+3.3V
2.7K
Ω
DOUT
6.2K
Ω
100 pF
(Including Jig and Scope)
Input
Output
3V
1.5V
1.5V
0V
Test Point
Test Point
- 38 -
W19B(L)320ST/B
8.4.3 Read-Only Operations
PARAMETER
90 nS
UNIT
SYM.
TEST SETUP
MIN.
MAX.
-
Read Cycle Time
TRC
TACC
TCE
TOE
TDF
90
-
-
-
-
nS
nS
nS
nS
nS
nS
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
Output Enable to Output High Z
#CE, #OE =VIL
#OE, = VIL
90
90
40
16
16
TDF
-
Output Hold Time From Address. #OE or
#CE Whichever Occurs First
TOH
0
0
-
-
-
nS
nS
nS
Read
Toggle and
Output Enable Hold Time
TOEH
10
#Data polling
Note: Not 100 % tested
8.4.4 Hardware Reset (#RESET)
PARAMETER
SYM.
MIN.
MAX.
UNIT
#RESET PIN Low (During Embedded Algorithms) to Read
Mode
#RESET Pin Low (Not During Embedded Algorithms) to
Read Mode
TReady
TReady
-
20
µS
-
500
nS
#RESET Pulse Width
TRP
TRH
500
50
20
0
-
-
-
-
nS
nS
µS
nS
Reset High Time Before Read
#RESET Low to Standby Mode
RY/#BY Recovery Time
Note: Not 100 % tested
TRPD
TRB
8.4.5 Word/Byte Configuration (#BYTE)
90 nS
PARAMETER
SYM.
UNIT
MIN.
MAX.
#CE to #BYTE Switching Low or High
#BYTE Switching Low to Output High Z
#BYTE Switching High to Output Active
TELFL/TELFH
TFLQZ
TFHQV
-
-
90
5
16
-
nS
nS
nS
Publication Release Date: March 23, 2004
Revision A2
- 39 -
W19B(L)320ST/B
8.4.6 Erase And Program Operation
PARAMETER
90 nS
UNIT
SYM.
MIN.
90
0
TYP. MAX.
Write Cycle Timing
Address setup Time
TWC
TAS
-
-
-
-
nS
nS
nS
Address Setup Timing to #OE low during toggle bit polling TASO
15
-
-
Address Hold Time
TAH
45
0
-
-
-
-
nS
nS
Address Hold Time From #CE or #OE high during toggle
TAHT
bit polling
Data Setup Time
Data Hold Time
Output Enable High During toggle bit polling
TDS
TDH
TOEPH
45
0
20
-
-
-
-
-
-
nS
nS
nS
Read Recovery Time Before Write (#OE High to #WE
TGHWL
0
-
-
nS
Low)
#CE Setup Time
#CE HOLD Time
Write Pulse Width
Write Pulse Width High
Latency Between Read and Write Operation
TCS
TCH
TWP
TWPH
TSR/W
TPB
0
0
35
30
0
-
-
-
-
-
-
-
5
7
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
µS
µS
Byte
Programming Time
Word
TPW
Byte
Accelerated Programming Time
Word
TACCP
-
4
-
µS
Sector Erase Time
VDD Setup Time (Note 1)
Write Recovery Time from RY/#BY
Program/Erase Valid to RY/#BY Delay
Note: Not 100 % tested
TSE
TVCS
TRB
-
50
0
0.7
-
-
-
-
sec
µS
nS
nS
-
-
-
TBUSY
90
8.4.7 Temporary Sector Unprotect
PARAMETER
VID Rise and Fall Time (See Note)
VHH Rise and Fall Time (See Note)
#RESET setup Time for Temporary Sector Unprotect
SYM.
TVIDR
TVHH
TRSP
MIN.
MAX.
UNIT
nS
nS
500
250
4
-
-
-
µS
#RESET Hold Time from RY/#BY High for Temporary
TRRB
4
-
µS
Sector Unprotect
Note: Not 100 % tested
- 40 -
W19B(L)320ST/B
8.4.8 Alternate #CE Controlled Erase and Program Operations
90 nS
UNIT
PARAMETER
SYM.
TYP.
MAX.
MIN.
(Note3)
(Note4)
Write Cycle Time (Note 1)
TWC
TAS
TAH
TDS
TDH
90
0
45
45
0
-
-
-
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recover Time Before Write (#OE High to #WE
Low)
TGHEL
0
-
-
nS
#WE Setup Time
#WE Hold Time
#CE Pulse Width
#CE Pulse Width High
TWS
TWH
TCP
TCPH
TPB
0
0
35
30
-
-
-
-
-
5
7
-
-
-
nS
nS
nS
nS
-
Byte
150
210
Programming Time (Note 6)
Word
Byte
Accelerated Programming Time (Note 6)
Word
µS
µS
TPW
-
TACCP
-
4
120
Sector Erase Time (Note 2)
Chip Erase Time (Note 2)
TSE
TCE
TCPB
TCPW
-
-
-
-
0.7
49
21
14
15
-
63
42
Sec
Sec
Byte
Chip Program Time (Note 5)
Word
Sec
Notes:
1. Not 100 % tested.
2. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
3. Typical program and erase time assume the following conditions :25°C, 3.0 V VDD, 10,000 or 100,000
cycles .Additionally, programming typicals assume checkerboard pattern.
4. Under worst case conditions of 90°C, VDD = 2.7V for W19B320S or VDD = 3.0V for W19L320S, 10,000 or 100,000
cycles.
5. The typical chip programming time is considerably less than the maximun chip programming time listed,since most
bytes program faster than maximun program times listed.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.
7. The device has a minimum erase and program cycle endurance of 10,000 or100,000 cycles.
Publication Release Date: March 23, 2004
- 41 -
Revision A2
W19B(L)320ST/B
9. TIMING WAVEFORMS
9.1 AC Read Waveform
TRC
Address
Addresses Stable
TACC
#CE
TRH
TRH
TOE
#OE
#WE
TDF
TOEH
High-Z
TCE
TOH
High-Z
Outputs
Output Vaild
#RESET
RY/#BY
0V
9.2 Reset Waveform
RY/#BY
#OE,#CE
RH
T
#RESET
T
RP
Ready
T
Reset Timing NOT during Embedded Algorithms
T
Ready
RY/#BY
T
RB
#OE,#CE
#RESET
TRP
Reset Timings during Embedded Algorithms
- 42 -
W19B(L)320ST/B
9.3 #BYTE Waveform for Read Operation
#CE
#OE
#BYTE
#BYTE
T
ELFL
Switching
Data Output
(DQ0-DQ14)
Data Output
(DQ0-DQ7)
from word
DQ0-DQ14
DQ15/A-1
to byte
mode
DQ15
Output
Address
Input
TFLQZ
T
ELFH
#BYTE
#BYTE
Data Output
(DQ0-DQ7)
Data Output
(DQ0-DQ14)
DQ0-DQ14
Switching
from byte
to word
mode
Address
Input
DQ15
DQ15/A-1
Output
T
FHQV
9.4 #BYTE Waveform for Write Operation
#CE
The falling edge of the last #WE signal
#WE
#BYTE
T
SET
(T
)
AS
T
HOLD
(T
AH
)
Note: Refer to the Erase /Program Operations table for TAS and TAH Specifications.
Publication Release Date: March 23, 2004
Revision A2
- 43 -
W19B(L)320ST/B
9.5 Programming Waveform
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
TWC
T
AS
PA
Address
PA
555h
PA
T
AH
#CE
#OE
T
CH
TWP
T
PW
TWPH
T
DH
#WE
T
CS
DS
T
D
Status
OUT
A0h
PD
Data
T
BUSY
T
RB
RY/#BY
VDD
T
VCS
Notes:
1. PA = program address, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
9.6 Accelerated Programming Waveform
V
HH
V
or
IL
V
IH
V
or
IL
V
IH
#WP/ACC
T
VHH
T
VHH
- 44 -
W19B(L)320ST/B
9.7 Chip/Sector Erase Waveform
Erase Command Sequence (last two cycles)
Read Status Data
TWC
T
AS
VA
VA
Address
2AAh
SA
555h for chip erase
T
AH
#CE
#OE
T
CH
TWP
TWPH
TSE
#WE
TCS
TDS
T
DH
In
Complete
TRB
Data
30h
55h
Progress
10 for Chip Erase
T
BUSY
RY/#BY
TVCS
VDD
Notes:
1. SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write operation Status”).
2. These waveforms are for the word mode
9.8 #Data Polling Waveform (During Embedded Algorithms)
T
RC
Addresses
VA
VA
VA
ACC
T
T
CE
#CE
#OE
T
CH
T
OE
T
DF
TOEH
#WE
T
OH
Complement
Status Data
High Z
High Z
Complement
Status Data
Valid Data
Valid Data
True
True
DQ7
DQ0-DQ6
T
BUSY
RY/#BY
Note: VA= Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Publication Release Date: March 23, 2004
- 45 -
Revision A2
W19B(L)320ST/B
9.9 Toggle Bit Waveform (During Embedded Algorithms)
TAHT
TAS
Addresses
TAHT
TASO
#CE
TCEPH
T
OEH
#WE
TOEPH
#OE
TDH
TOE
Valid
Valid
Valid
Valid Data
Status
Valid Data
DQ6/DQ2
RY/#BY
Status
Status
(stop toggling)
(first read)
(second read)
Note: VA = Valid address;not requires for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
9.10 DQ 2 vs. DQ6 Waveform
Enter
Enter Erase
Erase
Embedded
Erasing
Erase
Suspend
Suspend Program
Resume
#WE
DQ6
Erase
Erase
Erase
Erase Suspend
Read
Erase Suspend
Read
Complete
Erase
Suspend
Program
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The sysytem may use #OE or #CE to
toggle DQ2 and DQ6.
- 46 -
W19B(L)320ST/B
9.11 Temporary Sector Unprotect Timing Diagram
V
ID
V
ID
VSS
VSS
,
VIL
,
VIL
,
,
or
or
V
V
IH
IH
#RESET
T
VIDR
TVIDR
Program or Erase Command Sequence
#CE
#WE
TRSP
RRB
T
RY/#BY
9.12 Sector/Sector Block Protect and Unprotect Timing Diagram
VID
V
IH
#RESET
SA,A6,
Valid*
Status
Valid*
Valid*
Verify
A1,A0
Sector/sector Block Protect or Unprotect
60h
60h
40h
μ
DATA
Sector/Sector Block Protect:150 s,
Sector/Sector Block Unprotect:15ms
μ
s
1
#CE
#WE
#OE
*For sector protect,A6=0,A1=1,A0=0.For sector unprotect ,A6=1,A1=1,A0=0
Publication Release Date: March 23, 2004
Revision A2
- 47 -
W19B(L)320ST/B
9.13 Alternate #CE Controlled Write (Erase/Program) Operation Timing
#Data Polling
PA for program
SA for sector erase
555 for chip erase
555 for program
2AA for erase
PA
Address
TWC
TWH
t GHEL
T
AH
T
AS
#WE
#OE
#CE
T
CP
TPB,TPW, TACCP, or
TSE
T
T
CPH
TWS
DS T
T
BUSY
DH
.
.
OUT
D
#DQ7
DATA
PD for program
30 for sector erase
10 for chip erase
A0 for program
55 for erase
T
RH
#RESET
RY/#BY
Notes:
1. Firgure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. #DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
- 48 -
W19B(L)320ST/B
10. LATCHUP CHARACTERISTICS
PARAMETER
MIN.
MAX.
Input voltage with respect to Vss on all pins except I/O pins
(including A9, #OE, and #RESET)
-1.0V
12.5 V
Input voltage with respect to Vss on all I/O pins
VDD Current
-1.0V
-100 mA
VDD +1.0V
+100 mA
Note: Includes all pins except VDD. Test conditions: VDD = 3.0 V, one pin at a time.
11. CAPACITANCE
TSOP
TYP. MAX.
TFBGA
PARAMETER
SYM.
TEST SETUP
UNIT
TYP.
MAX.
5.0
Input Capacitance
Output Capacitance
Control Pin Capacitance
CIN
COUT
CIN2
VIN = 0
VOUT = 0
VIN = 0
6
7.5
12
9
4.2
5.4
3.9
pF
pF
pF
8.5
7.5
6.5
4.7
Notes:
1. Sampled, not 100 % tested.
2. Test condition TA = 25°C, f = 1.0 MHz.
Publication Release Date: March 23, 2004
Revision A2
- 49 -
W19B(L)320ST/B
12. ORDERING INFORMATION
W AA X YY Y Z P Q S T
Cycling
Winbond Standard Product
C:100K, 0~+70C
G:100K, -20~+85C
L:100K, -40~+85C
B:10K, 0~+70C
F:10K, -20~+85C
K:10K, -40~+85C
W: Winbond standard quality
Product Line
Access Time
9: 90ns
19:WinStack Flash Memory
Product Category Mark
Package
B:2.7~3.6V
L:3.0~3.6V
Density
B: TFBGA
T: TSOP
Product Characteristic
32:32M
T: TOP BOOT
Mulitiple Bank Architectures
0: Single Bank
B: BOTTOM BOOT
Bank Category
S: Single Bank
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
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W19B(L)320ST/B
13. PACKAGE DIMENSIONS
13.1 48-Ball TFBGA (measurements in millimeters)
CONTROL DIMENSIONS ARE IN MILLIMETERS
MILLIMETER
INCH
SYMBOL
MIN NOM MAX MIN NOM MAX
1.20
A
0.048
A1
D
0.30 0.008
0.012
0.20
0.433 0.435
0.431
10.95
11.00 11.05
D2
E
0.220
5.6 BASIC
0.317
0.315
8.05 0.313
7.95 8.00
4.0 BASIC
0.10 BASIC
E2
0.157 BASIC
0.004 BASIC
0.016 0.018 0.020
0.031
y
b
0.45
0.40
0.50
e
0.80 BASIC
13.2 48-Pin Standard Thin Small Outline Package (measured in millimeters)
1
48
MILLIMETER
INCH
NOM.
Sym.
MIN.
NOM.
MAX.
0.047
MAX. MIN.
1.20
e
A
A1
0.05
0.002
A2 0.95 1.00 1.05 0.037 0.039 0.041
E
18.4 18.5
0.724 0.728
18.3
19.8
11.9
0.720
0.780
0.468
D
b
0.795
0.476
20.0 20.2
0.787
0.472
0.009
HD
E
12.1
12.0
0.011
0.008
0.17 0.22 0.27 0.007
b
c
0.10
0.004
0.21
c
0.020
0.50
D
e
0.024
0.031
0.50
L
0.60 0.70 0.020
0.80
0.028
HD
A2
A1
L1
Y
0.004
5
0.10
A
θ
L
θ
0
0
5
L1
Y
Publication Release Date: March 23, 2004
Revision A2
- 51 -
W19B(L)320ST/B
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
Jan. 29, 2004
-
Initial Issued
Change Typical Program/ Erase Cycle from
10K/100K to 100K
A2
Mar. 23, 2004
4
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 52 -
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