W24010CS70LE [WINBOND]
Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 0.450 INCH, SOP-32;
| 型号： | W24010CS70LE |
| 厂家： | 
WINBOND |
| 描述： | Standard SRAM, 128KX8, 100ns, CMOS, PDSO32, 0.450 INCH, SOP-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：203K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary W24010C
128K ´ 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24010C is a normal-speed, very low-power CMOS static RAM organized as 131072 ´ 8 bits
that operates on a wide voltage range from 2.7V to 5.5V power supply. This device is manufactured
using Winbond's high performance CMOS technology.
FEATURES
· Low power consumption:
- Active: 350 mW (max.)
- Standby: 15 mW (max.) /3V
50 mW (max.) /5V
· Access time: 70 nS (max.) /5V
100 nS (max.) /3V
· All inputs and outputs directly TTL compatible
· Three-state outputs
· Battery back-up operation capability
· Data retention voltage: 2V (min.)
· Packaged in 32-pin 450 mil SOP, standard
type one TSOP (8 mm ´ 20 mm), and small
type one TSOP (8 mm ´ 13.4 mm)
· Single 3V/5V power supply
· Fully static operation
PIN CONFIGURATIONS
BLOCK DIAGRAM
PRECHARGE CKT.
CLK GEN.
A16
A14
32
31
V
DD
NC
A16
A14
1
A12
A4
R
O
W
2
A15
CORE CELL ARRAY
1024 ROWS
30
CS2
3
A3
D
E
C
O
D
E
R
128 X 8 COLUMNS
A2
A7
A6
A5
A9
A12
A7
4
29
28
27
26
25
24
23
22
21
20
19
18
17
WE
A13
A8
5
A6
6
A5
A9
7
I/O1
:
I/O8
I/O CKT.
A11
A4
A3
A2
A1
A0
DATA
CNTRL.
8
COLUMN DECODER
9
OE
CLK
GEN.
A10
10
11
12
13
14
15
16
A15
A8
A0
A1 A11A10
A13
WE
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
CS1
CS2
OE
I/O1
I/O2
I/O3
PIN DESCRIPTION
V
SS
SYMBOL
DESCRIPTION
Address Inputs
A0- A16
A11
A9
A8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Data Inputs/Outputs
Chip Select Input
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
I/O1- I/O8
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A13
CS1, CS2
WE
WE
CS2
A15
Write Enable Input
Output Enable Input
Power Supply
Ground
V
DD
32-pin
TSOP
NC
A16
A14
A12
A7
A6
A5
A4
V
S
I/O3
I/O2
I/O1
A0
A1
A2
OE
VDD
VSS
NC
A3
No Connection
Publication Release Date: December 1998
Revision A1
- 1 -
Preliminary W24010C
TRUTH TABLE
CS2
CS1
MODE
Not Selected
Not Selected
Output Disable
Read
VDD CURRENT
ISB, ISB1
ISB, ISB1
IDD
I/O1-I/O8
OE
X
WE
X
H
X
L
L
L
X
L
High Z
High Z
High Z
X
X
H
H
H
H
L
H
H
Data Out
Data In
IDD
X
L
Write
IDD
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Supply Voltage to VSS Potential
Input/Output to VSS Potential
Allowable Power Dissipation
Storage Temperature
RATING
UNIT
V
-0.5 to +7.0
-0.5 to VDD +0.5
1.0
V
W
-65 to +150
0 to 70
°C
°C
Operating Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
Operating Characteristics
(VDD = 5V ±10%; VDD = 3V ±10%; VSS = 0V; TA = 0 to 70°C)
PARAMETER
SYM. TEST CONDITIONS
5V
3V
UNIT
MIN. TYP.* MAX.
MIN.
-0.5
TYP.* MAX.
Input Low Voltage
Input High Voltage
VIL
-
-
-0.5
-
-
+0.8
-
-
+0.6
V
V
VIH
+2.2
VDD
+2.0
VDD
+0.5
+0.5
Input Leakage
Current
ILI
VIN = VSS to VDD
-1
-1
-
-
+1
-1
-1
-
-
+1
mA
mA
VI/O = VSS to VDD,
Output Leakage
Current
ILO
+1
+1
= VIH (min.)
CS1
or CS2 = VIL (max.)
or OE = VIH (min.)
or WE = VIL (max.)
IOL = +2.1 mA
Output Low Voltage
VOL
VOH
-
-
-
0.4
-
-
-
-
0.4
-
V
V
Output High
Voltage
IOH = -1.0 mA
2.4
2.2
- 2 -
Preliminary W24010C
Operating Characteristics, continued
PARAMETER
SYM. TEST CONDITIONS
5V
3V
UNIT
MIN. TYP.* MAX. MIN. TYP.* MAX.
Operating Power
Supply Current
IDD
-
-
70
-
-
30
mA
= VIL (max.)
and CS2 = VIH (min.),
I/O = 0 mA,
CS1
Cycle = min.
Duty = 100%
Standby Power
Supply Current
ISB
-
-
-
3
-
-
-
1
5
mA
= VIH (min.) or
CS2 = VIL (max.),
Cycle = min.
CS1
Duty = 100%
ISB1
1.0
10
0.5
mA
³ VDD -0.2V or
CS1
CS2 £ 0.2V
Note: Typical parameter is measured under ambient temperature TA = 25° C and VDD = 5V/ 3V
CAPACITANCE
(VDD = 5 V, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYM.
CIN
CONDITIONS
VIN = 0V
MAX.
UNIT
pF
6
8
CI/O
VOUT = 0V
pF
Note: These parameters are sampled but not 100% tested.
AC Characteristics
AC Test Conditions
PARAMETER
CONDITIONS
Input Pulse Levels
3V
5V
0V to 2.4V
0V to 3.0V
5 nS
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
1.5V
See the drawing below
AC Test Loads and Waveform
1 TTL
1 TTL
OUTPUT
OUTPUT
100 pF
Including
Jig and
Scope
5 pF
Including
Jig and
Scope
(For TCLZ, TOLZ, TCHZ, TOHZ, TWHZ, TOW)
90%
2.4 V / 3.0 V
0 V
90%
10%
5 nS
10%
5 nS
Publication Release Date: December 1998
Revision A1
- 3 -
Preliminary W24010C
AC Characteristics, continued
(VDD = 5 V ±10%; VDD = 3 V ±10%; VSS = 0 V; TA =0 to 70°C)
Read Cycle
PARAMETER
SYM.
5 V
3 V
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
TRC
70
-
-
100
-
100
100
50
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
Address Access Time
TAA
70
70
35
-
-
-
Chip Select Access Time
TACS
TAOE
TCLZ*
TOLZ*
TCHZ*
TOHZ*
TOH
-
Output Enable to Output Valid
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
* These parameters are sampled but not 100% tested
-
-
10
5
15
5
-
-
-
-
30
30
-
35
35
-
-
-
10
15
Write Cycle
PARAMETER
SYM.
5 V
3 V
UNIT
MIN.
70
50
50
0
MAX.
MIN.
MAX.
Write Cycle Time
TWC
TCW
TAW
TAS
-
-
-
-
-
-
100
70
70
0
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
TWP
TWR
50
0
70
0
Write Recovery Time
CS1, CS2, WE
Data Valid to End of Write
TDW
30
0
-
-
-
50
0
-
-
nS
nS
nS
nS
nS
Data Hold from End of Write
Write to Output in High Z
TDH
TWHZ*
TOHZ*
TOW
25
25
-
-
30
30
-
Output Disable to Output in High Z
Output Active from End of Write
-
-
5
10
* These parameters are sampled but not 100% tested
- 4 -
Preliminary W24010C
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
TRC
Address
AA
T
OH
T
OH
T
OUT
D
Read Cycle 2
(Chip Select Controlled)
CS1
CS2
T
ACS
T
CHZ
T
CLZ
D
OUT
Read Cycle 3
(Output Enable Controlled)
TRC
Address
OE
T
AA
T
OH
TAOE
OLZ
T
CS1
CS2
T
OHZ
TACS
CHZ
T
T
CLZ
D
OUT
Publication Release Date: December 1998
Revision A1
- 5 -
Preliminary W24010C
Timing Waveforms, continued
Write Cycle 1
T
WC
Address
OE
T
WR
T
CW
CS1
CS2
WE
T
AW
T
WP
T
AS
T
OHZ
(1, 4)
D
OUT
T
T
DH
DW
D
IN
Write Cycle 2
(OE = VIL Fixed)
T
WC
Address
CS1
T
WR
T
CW
CS2
WE
T
AW
T
T
OH
WP
T
AS
(2)
(3)
T
WHZ
T
OW
(1, 4)
D
OUT
T
DH
T
DW
D
IN
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
- 6 -
Preliminary W24010C
DATA RETENTION CHARACTERISTICS
(TA =0 to 70°C)
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP. MAX. UNIT
VDD for Data Retention
VDR
2.0
-
-
V
CS1 ³ VDD -0.2V or
CS2 £ 0.2V
Data Retention Current
IDDDR
-
-
5
mA
CS1 ³ VDD -0.2V or
CS2 £ 0.2V, VDD = 3V
Chip Deselect to Data
Retention Time
TCDR
TR
See data retention waveform
0
-
-
-
-
nS
nS
Operation Recovery Time
TRC*
* Read Cycle Time
DATA RETENTION WAVEFORM
DD
V
DD
0.9 x V
DD
0.9 x
V
R
>
DR
>
V
1.5V
=
TCDR
T
DD
V
CS1
-
0.2V
CS1
CS2
=
<
<
0.2V
0V CS2
=
=
Publication Release Date: December 1998
Revision A1
- 7 -
Preliminary W24010C
ORDERING INFORMATION
PART NO.
ACCESS
TIME (nS)
OPERATING
VOLTAGE (V)
OPERATING
TEMPERATURE (
PACKAGE
450 mil SOP
°C)
W24010CS70LL
W24010CT70LL
W24010CQ70LL
W24010CS70LE
W24010CT70LE
W24010CQ70LE
Notes:
70
70
5V
5V
0 to 70
0 to 70
Standard type one TSOP
Small type one TSOP
450 mil SOP
70
5V
0 to 70
70/100
70/100
70/100
5V/3V
5V/3V
5V/3V
0 to 70
0 to 70
Standard type one TSOP
Small type one TSOP
0 to 70
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 8 -
Preliminary W24010C
PACKAGE DIMENSIONS
32-pin SOP Wide Body
Dimension in Inches
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
3.00
0.118
17
32
0.004
0.101
0.10
2.57
0.36
0.15
A
A
b
1
e1
0.106
0.111
0.020
0.012
0.817
2.69
0.41
2.82
0.51
2
0.014 0.016
0.006 0.008
0.805
0.20
0.31
c
D
E
e
20.75
11.43
1.42
20.45
11.30
1.27
E HE
11.18
1.12
0.445
0.450
0.056
0.440
0.044 0.050
q
0.556
0.039
0.546 0.556
0.023 0.031
13.87
0.58
1.19
14.12 14.38
HE
L
0.79
1.40
0.99
L
0.047
0.063
0.036
0.055
1.60
0.91
L
E
Detail F
1
16
b
S
y
0.10
10
0.004
10
0
0
q
Notes:
1. Dimensions D Max. & S include mold flash
or tie bar burrs.
e1
D
2. Dimension b does not include dambar
protrusion/intrusion.
c
3. Dimensions D & E include mold mismatch
.
A
A2
and determined at the mold parting line.
4. Controlling dimension: Inches
5. General appearance spec should be based
on final visual inspection spec.
e
S
y
LE
A1
See Detail F
Seating Plane
32-pin Standard Type One TSOP
H D
D
Dimension in Inches
Dimension in mm
Max.
Symbol
Min. Nom.
Min. Nom.
Max.
__
__
__
__
A
1.20
0.15
1.05
0.23
0.047
0.006
c
__
__
0.002
0.037
0.05
0.95
A 1
1
2
0.041
0.009
1.00
0.20
0.15
A
0.039
M
e
b
c
0.007 0.008
0.17
0.12
E
0.005 0.006
0.720 0.724
0.17
0.007
0.728
0.10(0.004)
D
18.30 18.40 18.50
b
0.311 0.315
0.780 0.787
7.90
8.00
8.10
E
0.319
19.80
__
20.00 20.20
0.795
__
HD
e
__
__
0.020
0.50
0.016 0.020
0.40
__
0.50
0.60
__
0.024
__
L
__
L
1
0.031
0.80
__
A
__
0.000
0.004
5
0.10
5
0.00
1
Y
A2
A1
1
3
3
q
q
L
Y
L1
Controlling dimension: Millimeters
Publication Release Date: December 1998
Revision A1
- 9 -
Preliminary W24010C
Package Dimensions, continued
32-pin Small Type One TSOP
D
H
D
Dimension in Inches
Dimension in mm
Symbol
Min.
Max.
Nom.
Min. Nom.
Max.
c
A
0.049
0.006
1.25
0.15
0.002
0.05
0.95
A
1
2
1
0.039
0.041
0.037
0.007
A
b
c
1.00 1.05
e
0.008 0.009 0.17 0.20 0.27
E
0.0056 0.0059 0.0062 0.14 0.15 0.16
D
E
0.461
0.311
0.520
0.469 11.70 11.80 11.90
0.319 7.90 8.00 8.10
0.536 13.20 13.40 13.60
0.50
0.465
0.315
b
0.528
0.020
0.020
H
e
D
L
0.50
0.012
0.028
0.70
0.30
0.675
L1 0.027
2
A
A
0.000
0.004 0.00
0.10
5
Y
q
A
q
1
L
0
3
5
0
3
Y
L1
Controlling dimension: Millimeters
- 10 -
Preliminary W24010C
VERSION HISTORY
VERSION
DATE
Dec. 1998
PAGE
DESCRIPTION
A1
-
Initial Issued
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: December 1998
Revision A1
- 11 -
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