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W24L11S-70LL [WINBOND]

128K X 8 High Speed CMOS Static RAM; 128K ×8高速CMOS静态RAM
W24L11S-70LL
型号： W24L11S-70LL
厂家： WINBOND    WINBOND
描述：

128K X 8 High Speed CMOS Static RAM
128K ×8高速CMOS静态RAM

存储 内存集成电路 静态存储器 光电二极管
文件： 总11页 (文件大小：172K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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Preliminary W24L11  
128K ´ 8 CMOS STATIC RAM  
GENERAL DESCRIPTION  
´
The W24L11 is a normal-speed, very low-power CMOS static RAM organized as 131072 8 bits that  
operates on a wide voltage range from 3.0V to 3.6V power supply. This device is manufactured using  
Winbond's high performance CMOS technology.  
FEATURES  
·
·
·
·
·
Low power consumption:  
Three-state outputs  
-
Active: 144 mW (max.)  
Battery back-up operation capability  
Data retention voltage: 2V (min.)  
Packaged in 600 mil DIP, 450 mil SOP,  
standard type one, TSOP (8 mm 20 mm) ,  
small type one and TSOP (8 mm 13.4 mm)  
·
·
·
·
Access time: 70 nS  
Single 3.3V power supply  
Fully static operation  
´
´
All inputs and outputs directly TTL compatible  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
PRECHARGE CKT.  
A16  
A14  
32  
31  
V
DD  
NC  
A16  
A14  
1
A4  
A3  
2
A15  
30  
CS2  
3
A7  
A6  
4
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A12  
A7  
WE  
A13  
A8  
5
A6  
A5  
A4  
A3  
A2  
A1  
A0  
6
A9  
A9  
7
I/O1  
:
A11  
8
9
OE  
A0  
A13  
A1  
A10  
10  
11  
12  
13  
14  
15  
16  
A10  
WE  
CS1  
CS1  
I/O8  
I/O7  
I/O6  
I/O5  
I/O4  
OE  
I/O1  
I/O2  
I/O3  
PIN DESCRIPTION  
V
SS  
SYMBOL  
DESCRIPTION  
Address Inputs  
A0- A16  
A11  
A9  
A8  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
Data Inputs/Outputs  
Chip Select Input  
-
I/O1 I/O8  
A13  
I/O8  
WE  
CS2  
A15  
CS1  
, CS2  
V
DD  
32-pin  
NC  
V
SS  
A16  
A14  
A12  
A7  
A6  
A5  
Write Enable Input  
WE  
Output Enable Input  
Power Supply  
Ground  
OE  
A4  
DD  
V
SS  
V
NC  
No Connection  
Publication Release Date: October 1999  
Revision A1  
- 1 -  
Preliminary W24L11  
TRUTH TABLE  
CS2  
CS1  
MODE  
Not Selected  
Not Selected  
Output Disable  
Read  
VDD CURRENT  
I/O1-I/O8  
OE  
X
WE  
X
SB SB1  
H
X
L
L
L
X
L
High Z  
High Z  
High Z  
I
I
I
I
I
, I  
SB SB1  
X
X
, I  
DD  
DD  
DD  
H
H
H
H
L
H
H
Data Out  
Data In  
X
L
Write  
DC CHARACTERISTICS  
Absolute Maximum Ratings  
PARAMETER  
RATING  
UNIT  
SS  
Supply Voltage to V Potential  
-0.5 to +4.6  
V
V
SS  
DD  
Input/Output to V Potential  
-0.5 to V +0.5  
Allowable Power Dissipation  
Storage Temperature  
1.0  
W
°C  
°C  
-65 to +150  
0 to 70  
Operating Temperature  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the  
device.  
Operating Characteristics  
(VDD = 3.0V to 3.6V; VSS = 0V; TA ( C) = 0 to 70)  
°
PARAMETER  
Input Low Voltage  
SYM.  
VIL  
TEST CONDITIONS  
MIN.  
-0.5  
+2.0  
-1  
MAX.  
+0.6  
UNIT  
V
-
-
Input High Voltage  
VIH  
ILI  
VDD +0.5  
+1  
V
Input Leakage Current  
Output Leakage Current  
VIN = VSS to VDD  
A
m
ILO  
VI/O = VSS to VDD  
,
-1  
+1  
A
m
CS1 = VIH (min.) or  
CS2 = VIL (max.) or  
= VIH (min.) or  
OE  
WE = VIL (max.)  
IOL = +2.1 mA  
IOH = -1.0 mA  
Output Low Voltage  
Output High Voltage  
VOL  
VOH  
IDD  
-
2.2  
-
0.4  
-
V
V
Operating Power Supply  
Current  
40  
mA  
= VIL (max.) and  
CS1  
CS2 = VIH (min.), I/O = 0 mA,  
Cycle = min. Duty = 100%  
- 2 -  
Preliminary W24L11  
Operating Characteristics, continued  
PARAMETER  
SYM.  
TEST CONDITIONS  
MIN.  
MAX.  
UNIT  
mA  
Standby Power Supply  
Current  
-
1
ISB  
= VIH (min.) or  
CS1  
CS2 = VIL (max.)  
Cycle = min. Duty = 100%  
A
m
LL  
L
-
-
50  
ISB1  
CS1 VDD -0.2V or  
³
CS2 0.2V  
£
100  
Note: Typical parameter is measured under ambient temperature TA = 25 C and VDD = 3.3V  
°
CAPACITANCE  
(VDD = 3.3 V, TA = 25 C, f = 1 MHz)  
°
PARAMETER  
Input Capacitance  
SYM.  
CONDITIONS  
MAX.  
UNIT  
pF  
IN  
C
IN  
V
= 0V  
6
8
I/O  
C
OUT  
V
Input/Output Capacitance  
= 0V  
pF  
Note: These parameters are sampled but not 100% tested.  
AC characteristics  
AC Test Conditions  
PARAMETER  
Input Pulse Levels  
CONDITIONS  
0V to 3.0V  
5 nS  
Input Rise and Fall Times  
Input and Output Timing Reference Level  
Output Load  
1.5V  
See the drawing below  
AC Test Loads and Waveform  
1 TTL  
1 TTL  
OUTPUT  
OUTPUT  
100 pF  
Including  
Jig and  
Scope  
5 pF  
Including  
Jig and  
Scope  
(For T  
T
T
CHZ,  
T
T
T
)
CLZ, OLZ,  
OHZ, WHZ, OW  
90%  
10%  
3.0 V  
90%  
10%  
0 V  
5 nS  
5 nS  
Publication Release Date: October 1999  
Revision A1  
- 3 -  
Preliminary W24L11  
AC Characteristics, continued  
(VDD = 3.0V to 3.6 V; VSS = 0V; TA ( C) = 0 to 70)  
°
Read Cycle  
PARAMETER  
SYMBOL  
W24L11-70L/LL  
UNIT  
MIN.  
MAX.  
RC  
Read Cycle Time  
T
70  
-
-
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
AA  
T
Address Access Time  
70  
70  
35  
-
ACS  
T
Chip Select Access Time  
-
AOE  
T
Output Enable to Output Valid  
Chip Selection to Output in Low Z  
Output Enable to Output in Low Z  
Chip Deselection to Output in High Z  
Output Disable to Output in High Z  
Output Hold from Address Change  
-
CLZ  
T
T
T
T
T
*
10  
5
OLZ  
*
-
CHZ  
*
-
30  
30  
-
OHZ  
*
-
OH  
10  
These parameters are sampled but not 100% tested  
*
Write Cycle  
PARAMETER  
SYMBOL  
W24L11-70L/LL  
UNIT  
MIN.  
70  
55  
55  
0
MAX.  
WC  
Write Cycle Time  
T
-
-
-
-
-
-
nS  
nS  
nS  
nS  
nS  
nS  
CW  
T
Chip Selection to End of Write  
Address Valid to End of Write  
Address Setup Time  
AW  
T
AS  
T
WP  
T
Write Pulse Width  
50  
0
WR  
T
Write Recovery Time  
CS1  
WE  
, CS2,  
DW  
Data Valid to End of Write  
Data Hold from End of Write  
Write to Output in High Z  
T
45  
0
-
-
-
nS  
nS  
nS  
nS  
nS  
DH  
T
WHZ  
T
T
T
*
25  
25  
-
OHZ  
OW  
Output Disable to Output in High Z  
Output Active from End of Write  
*
-
5
These parameters are sampled but not 100% tested  
*
- 4 -  
Preliminary W24L11  
TIMING WAVEFORMS  
Read Cycle 1  
(Address Controlled)  
TRC  
Address  
AA  
T
OH  
T
OH  
T
OUT  
D
Read Cycle 2  
(Chip Select Controlled)  
CS1  
CS2  
T
ACS  
T
CHZ  
T
CLZ  
D
OUT  
Read Cycle 3  
(Output Enable Controlled)  
T
RC  
Address  
OE  
T
AA  
T
T
OH  
AOE  
T
OLZ  
CS1  
CS2  
T
T
OHZ  
ACS  
T
CHZ  
T
CLZ  
D
OUT  
Publication Release Date: October 1999  
Revision A1  
- 5 -  
Preliminary W24L11  
Timing Waveforms, continued  
Write Cycle 1  
T
WC  
Address  
OE  
T
WR  
T
CW  
CS1  
CS2  
WE  
T
AW  
T
WP  
T
AS  
T
OHZ  
(1, 4)  
DOUT  
T
DW  
T
DH  
D
IN  
Write Cycle 2  
(OE = VIL Fixed)  
T
WC  
Address  
CS1  
T
WR  
T
CW  
CS2  
WE  
T
AW  
T
OH  
T
WP  
T
AS  
(2)  
(3)  
T
WHZ  
T
OW  
(1, 4)  
D
OUT  
T
DW  
T
DH  
D
IN  
Notes:  
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.  
OUT  
IN  
are the same as the data written to D during the write cycle.  
2. The data output from D  
OUT  
3. D  
provides the read data for the next address.  
4. Transition is measured 500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.  
±
- 6 -  
Preliminary W24L11  
DATA RETENTION CHARACTERISTICS  
(TA ( C) = 0 to 70)  
°
PARAMETER  
for Data Retention  
SYM.  
TEST CONDITIONS  
MIN. TYP. MAX. UNIT  
DD  
V
DR  
V
2.0  
-
-
V
DD  
V
³
CS1  
-0.2V or  
£
CS2 0.2V  
DDDR  
I
Data Retention Current  
-
-
50  
m
A
DD  
V
CS1 ³  
-0.2V or  
DD  
£
CS2 0.2V, V = 3V  
CDR  
Chip Deselect to Data  
Retention Time  
T
T
See data retention waveform  
0
-
-
-
-
nS  
nS  
R
RC  
Operation Recovery Time  
T
*
Read Cycle Time  
*
DATA RETENTION WAVEFORM  
V
DD  
0.9V  
DD  
0.9  
V
DD  
>
=
2V  
V
DR  
T
CDR  
T
R
>
V
CS1  
-
DD 0.2V  
CS1  
CS2  
=
<
<
0V CS2 0.2V  
=
=
Publication Release Date: October 1999  
Revision A1  
- 7 -  
Preliminary W24L11  
ORDERING INFORMATION  
PART NO.  
ACCESS OPERATING  
OPERATING  
STANDBY  
PACKAGE  
TIME  
(nS)  
VOLTAGE  
TEMPERATURE CURRENT  
MAX.( A)  
m
(V)  
(°C)  
W24L11-70LL  
W24L11S-70LL  
W24L11T-70LL  
70  
70  
70  
3.0V to 3.6V  
3.0V to 3.6V  
3.0V to 3.6V  
0 to 70  
0 to 70  
0 to 70  
50  
50  
50  
600 mil DIP  
450 mil SOP  
Standard type one  
TSOP  
W24L11Q-70LL  
W24L11-70L  
70  
70  
70  
70  
3.0V to 3.6V  
3.0V to 3.6V  
3.0V to 3.6V  
3.0V to 3.6V  
0 to 70  
0 to 70  
0 to 70  
0 to 70  
50  
Small type one TSOP  
600 mil DIP  
100  
100  
100  
W24L11S-70L  
W24L11T-70L  
450 mil SOP  
Standard type one  
TSOP  
W24L11Q-70L  
70  
3.0V to 3.6V  
0 to 70  
100  
Small type one TSOP  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications  
where personal injury might occur as a consequence of product failure.  
- 8 -  
Preliminary W24L11  
PACKAGE DIMENSIONS  
32-pin P-DIP  
Dimension in inches  
Min. Nom. Max. Min. Nom. Max.  
Dimension in mm  
Symbol  
A
5.33  
0.210  
0.010  
0.25  
A
A
B
1
0.150 0.155 0.160 3.81  
0.016 0.018 0.022 0.41  
3.94  
0.46  
1.27  
0.25  
4.06  
0.56  
1.37  
0.36  
2
0.050  
1.22  
0.048  
0.008  
0.054  
B1  
c
D
E
0.010 0.014 0.20  
1.650 1.660  
D
17  
32  
41.91 42.16  
15.49  
14.10  
2.79  
3.56  
15  
0.610  
0.555  
0.110  
15.24  
13.84 13.97  
0.590 0.600  
14.99  
0.545  
0.550  
E
1
0.090 0.100  
0.120 0.130  
0
2.29  
3.05  
0
2.54  
3.30  
e
L
a
1
E1  
0.140  
15  
0.630  
0.670 16.00  
0.085  
17.02  
2.16  
0.650  
16.51  
eA  
S
16  
1
Notes:  
E
S
1. Dimensions D Max. & S include mold flash or  
tie bar burrs.  
c
2. Dimension E1 does not include interlead flash.  
3. Dimensions D & E1 include mold mismatch and  
are determined at the mold parting line.  
4. Dimension B1 does not include dambar  
protrusion/intrusion.  
2
A
A
L
A1  
Base Plane  
Seating Plane  
5. Controlling dimension: Inches  
6. General appearance spec. should be based on  
final visual inspection spec.  
B
e1  
eA  
a
B1  
32-pin SOP Wide Body  
Dimension in mm  
Min. Nom. Max. Min. Nom. Max.  
Dimension in Inches  
Symbol  
3.00  
0.118  
A
17  
32  
0.004  
0.101 0.106 0.111  
0.10  
2.57  
0.36  
0.15  
A1  
A2  
b
e1  
2.69  
0.41  
2.82  
0.51  
0.014 0.016  
0.006 0.008  
0.020  
0.012  
0.20  
0.31  
c
20.75  
11.43  
1.42  
0.805 0.817  
20.45  
11.30  
1.27  
D
E
e
E H  
E
11.18  
1.12  
0.440 0.445 0.450  
0.056  
0.044 0.050  
q
0.546 0.556 0.556 13.87 14.12 14.38  
HE  
L
L E  
0.023  
0.039  
0.031  
0.79  
1.40  
0.99  
0.58  
1.19  
L
0.063  
0.036  
0.047 0.055  
1.60  
0.91  
Detail F  
1
16  
S
y
b
0.10  
10  
0.004  
10  
0
0
q
Notes:  
1. Dimensions D Max. & S include mold flash  
or tie bar burrs.  
e1  
D
2. Dimension b does not include dambar  
protrusion/intrusion.  
c
3. Dimensions D & E include mold mismatch  
.
A
2
A
and determined at the mold parting line.  
4. Controlling dimension: Inches  
5. General appearance spec should be based  
on final visual inspection spec.  
e
S
y
L
E
A
1
See Detail F  
Seating Plane  
Publication Release Date: October 1999  
Revision A1  
- 9 -  
Preliminary W24L11  
Package Dimensions, continued  
32-pin Standard Type One TSOP  
H D  
D
Dimension in Inches  
Min. Nom. Max.  
Dimension in mm  
Symbol  
Min.  
__  
Max.  
Nom.  
__  
__  
__  
A
1.20  
0.15  
1.05  
0.23  
c
0.047  
__  
__  
A 1  
A 2  
b
0.002  
0.037  
0.006 0.05  
1
0.95  
0.041  
0.009  
1.00  
0.039  
M
e
0.007 0.008  
0.17 0.20  
0.12 0.15  
E
c
0.005 0.006  
0.720 0.724  
0.17  
0.007  
0.728  
0.10(0.004)  
D
18.30 18.40 18.50  
b
E
0.311 0.315  
0.780 0.787  
7.90 8.00  
8.10  
0.319  
19.80  
__  
20.00 20.20  
HD  
e
0.795  
__  
__  
__  
0.020  
0.50  
0.016 0.020  
0.40 0.50  
0.60  
__  
L
0.024  
__  
__  
__  
L
1
0.031  
0.80  
A
__  
__  
0.000  
0.004  
5
0.10  
5
0.00  
Y
A2  
A1  
1
3
1
3
q
q
L
Y
L1  
Controlling dimension: Millimeters  
32-pin Small Type One TSOP  
D
H
D
Dimension in Inches  
Min. Nom. Max.  
Dimension in mm  
Symbol  
Nom.  
Min.  
Max.  
A
c
0.049  
1.25  
0.15  
0.006  
0.002  
A
1
2
0.05  
0.95  
1
0.039  
0.041  
A
b
c
0.037  
0.007  
1.00 1.05  
e
0.008 0.009 0.17 0.20 0.27  
E
0.00560.00590.0062 0.14 0.15 0.16  
D
E
0.461  
0.311  
0.520  
0.469 11.70 11.80 11.90  
0.465  
0.315  
0.528  
b
0.319 7.90 8.00 8.10  
H
e
D
0.536 13.20 13.40 13.60  
0.020  
0.020  
0.50  
0.50  
L
0.012  
0.027  
0.000  
0
0.028  
0.70  
0.30  
L1  
0.675  
2
A
A
0.004 0.00  
0.10  
5
Y
q
A
q
1
L
3
5
0
3
Y
1
L
Controlling dimension: Millimeters  
- 10 -  
Preliminary W24L11  
VERSION HISTORY  
VERSION  
DATE  
Oct. 1999  
PAGE  
DESCRIPTION  
A1  
-
Initial Issued  
Winbond Electronics (H.K.) Ltd.  
Winbond Electronics North America Corp.  
Winbond Memory Lab.  
Winbond Microelectronics Corp.  
Winbond Systems Lab.  
2727 N. First Street, San Jose,  
CA 95134, U.S.A.  
Headquarters  
Rm. 803, World Trade Square, Tower II,  
123 Hoi Bun Rd., Kwun Tong,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5796096  
http://www.winbond.com.tw/  
TEL: 408-9436666  
FAX: 408-5441798  
Voice & Fax-on-demand: 886-2-27197006  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-27190505  
FAX: 886-2-27197502  
Note: All data and specifications are subject to change without notice.  
Publication Release Date: October 1999  
Revision A1  
- 11 -  

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WINBOND

W24L11T-70LE

 Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32

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WINBOND

W24L11T-70LL

 128K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257

 32K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257A

 32K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257A-12

 32K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257A-15

 32K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257A-20

 32K X 8 High Speed CMOS Static RAM

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WINBOND

W24L257ACJ-12

 Standard SRAM, 32KX8, 12ns, CMOS, PDSO28, 0.300 INCH, SOJ-28

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WINBOND
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