W25P243AD-6 [WINBOND]
64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM; 64K ×64连拍PIPELINED高速CMOS静态RAM
| 型号： | W25P243AD-6 |
| 厂家： | 
WINBOND |
| 描述： | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总18页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W25P243A
64K ´ 64 BURST PIPELINED HIGH-SPEED
CMOS STATIC RAM
GENERAL DESCRIPTION
The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM
´
organized as 65,536 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst
ä
address counter supports both Pentium burst mode and linear burst mode. The mode to be
LBO
executed is controlled by the
pin. Pipelining or non-pipelining of the data outputs is controlled by
pin. A snooze mode can reduce power dissipation.
FT
the
W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the
device is deselected by CE2/CE3 .
This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.
FEATURES
·
·
·
·
·
·
·
·
·
·
Synchronous operation
Pipelined data output capability
High-speed access time: 4.5/5/6 nS (max.)
Single +3.3V power supply
Supports snooze mode (low-power state)
Internal burst counter supports Intel burst
(Interleaved) mode & linear burst mode
Individual byte write capability
3.3V LVTTL compatible I/O
·
·
Support 2T/1T mode
Clock-controlled and registered input
Asynchronous output enable
Packaged in 128-pin QFP and TQFP
BLOCK DIAGRAM
INPUT
A(15:0)
REGISTER
64K X 64
CORE
ARRAY
CLK
CE(3:1)
GW
BWE
CONTROL
LOGIC
BW(8:1)
DATA I/O
REGISTER
I/O(64:1)
REGISTER
OE
ADSC
ADSP
ADV
LBO
ZZ
Publication Release Date: August 1999
Revision A3
- 1 -
W25P243A
PIN CONFIGURATION
/
/
/
V
S
S
Q
V
D
D
Q
/
/
/
/
/
/
A
D
S
C
/
/ /
/
A
D
S
P
C
E
2
C
E
3
/ B
C W
E 8
B /
B /
B
W
2
A
D
V
V V
S D
S D
B
W
6
C
B
W
7
B B V
WWS
4 3 S
B
W
1
V
D
D
N
C
N
C
WO WG
5 E E W
L
K
1
2
7
1
1
1 1
2 2
1
1
3
1
1
2
1
0
1 1 1
0 0 0
1
2
1 1 1
2 2 2
1 1 1
1 1 1
9 8 7
1
1 1 1
1 1 0
1
2
0
1 1
1
0
7
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VSSQ
VDDQ
0
3
2
1 1 1
6 5 4
2
I/O33
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
VSSQ
VDDQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
VSSQ
VDDQ
I/O11
I/O10
I/O9
6
4
8
6 5 4 3 2 1
1 0 9 8
5
3
I/O34
4
I/O35
5
I/O36
6
I/O37
7
I/O38
8
I/O39
9
I/O40
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
I/O41
I/O42
I/O43
VDDQ
VSSQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VDDQ
VSSQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
I/O60
I/O61
I/O62
I/O63
I/O64
VDDQ
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
4
0
5
VSSQ
3
9
4 4
2 3
5
4 5
5
9
6
2
4
1
4 4 4
4 5 6
4 4 5
8 9 0
5
3
5 5
7 8
6
4
4
7
5 5
1 2
5
6
6 6
0 1
6
3
A
1
0
A R
8 S
V
A
1
4
V
S
A
1
1
A
9
A A A
5 4 3
A A
2 1
Z
Z
V N
S C
S
A
1
5
A V
1 D
A
1
A
7
V V
D S
D S
V
D
D
Q
/
A
6
A
0
L
3 D S 2
B
O
Q
- 2 -
W25P243A
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
Input, Synchronous
I/O, Synchronous
Input, Clock
Host address
-
A0 A15
Data Inputs/Outputs
Processor host bus clock
Chip enables
I/O1- I/O64
CLK
Input, Synchronous
CE1
, CE2, CE3
GW
Input, Synchronous
Input, Synchronous
Input, Synchronous
Input, Asynchronous
Input, Synchronous
Input, Synchronous
Input, Synchronous
Global write
Byte write enable from cache controller
BWE
BW1-
BWE
BW8
Host bus byte enables used with
Output enable input
OE
Internal burst address counter advance
Address status from Chip Set
Address status from CPU
ADV
ADSC
ADSP
ZZ
Input, Asynchronous
Input, Static
Snooze pin for low-power state, internal pull low
Lower address burst order
LBO
SS
Connected to V : Device is in linear mode.
DD
Connected to V or unconnected: Device is in non-
linear mode.
DDQ
V
I/O power supply
I/O ground
SSQ
V
DD
V
Power supply
SS
V
Ground
RSV
NC
Reserved pin, don't use these pins
No connection
Publication Release Date: August 1999
- 3 -
Revision A3
W25P243A
FUNCTIONAL DESCRIPTION
The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
ä
computers. It supports two burst address sequences for Intel systems (Interleaved mode) and linear
LBO
ADSP
ADSC
mode, which can be controlled by the
pin. The burst cycles are initiated by
or
ADV
and the burst counter is incremented whenever
is sampled low.
BURST ADDRESS SEQUENCE
LBO
DD
LBO
SS
= V )
INTEL SYSTEM (
= V
)
LINEAR MODE (
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
A[1:0]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
External Start Address
Second Address
Third Address
01
00
11
10
01
10
11
00
10
11
00
01
10
11
00
01
Fourth Address
11
10
01
00
11
00
01
10
BWE
BW
The device supports several types of write mode operations.
BE
and
[8:1] support individual
GW
signal is
BW
byte writes. The
[7:0] signals can be directly connected to the SRAM
[8:1]. The
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
ADDRESS
USED
CYCLE
CE2
DATA
WRITE*
OE
CE1
CE3
ADSP
ADSC
ADV
Unselected
No
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
X
0
X
1
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
Hi-Z
Hi-Z
X
Unselected
No
X
Unselected
No
X
1
Hi-Z
X
Unselected
No
X
0
Hi-Z
X
Unselected
No
X
0
Hi-Z
X
Begin Read
External
External
Next
1
Hi-Z
X
Begin Read
1
0
Hi-Z
Read
Read
Read
Read
Read
Read
Read
Read
Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hi-Z
Next
D-Out
Hi-Z
Next
Next
D-Out
Hi-Z
Current
Current
Current
Current
D-Out
Hi-Z
D-Out
- 4 -
W25P243A
Truth Table, continued
ADDRESS
USED
CYCLE
CE2
DATA WRITE*
OE
CE1
CE3
ADSP
ADSC
ADV
Begin Write
Current
Current
External
Next
X
1
0
X
1
X
1
X
X
1
X
X
0
1
X
1
1
1
0
1
1
1
1
1
1
X
0
0
1
1
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
Write
Write
Write
Write
Write
Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
X
X
X
X
X
X
X
X
1
Next
X
1
Current
Current
X
Notes:
1. For a detailed definition of read/write, see the Write Table below.
2. An "X" means don't care, "1" means logic high, and "0" means logic low.
3. The pin enables the data output and is not sampled with the clock. All signals of the SRAM are sampled synchronously
OE
with the bus clock except for the
pin.
OE
4. On a write cycle that follows a read cycle,
must be inactive prior to the start of write cycle to allow write data to setup to
OE
the SRAM.
are met.
must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM data hold timings
OE
WRITE TABLE
READ/WRITE FUNCTION
GW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BW8
X
1
BW7
X
1
BW6
X
1
BW5
X
1
BW4
X
1
BW3
X
1
BW2
X
1
BW1
X
1
BWE
1
Read
Read
0
0
1
1
1
1
1
1
1
0
Write byte 1 I/O1- I/O8
Write byte 2 I/O9- I/O16
Write byte 2, byte 1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
1
1
Write byte 3 I/O17 I/O24
-
Write byte 3, byte 1
0
1
1
1
1
1
0
1
0
Write byte 3, byte 2
0
1
1
1
1
1
0
0
1
Write byte 3, byte 2, byte 1
Write byte 4, I/O25- I/O32
Write byte 4, byte 1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
Write byte 4, byte 2
0
1
1
1
1
0
1
0
1
Write byte 4, byte 2, byte 1
Write byte 4, byte 3
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
Write byte 4, byte 3, byte 1
Write byte 4, byte 3, byte 2
Write byte 4, byte 3, byte 2, byte 1
Write byte 5, I/O33- I/O40
Write byte 5, byte 1
0
1
1
1
1
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
0
0
0
0
0
1
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
Publication Release Date: August 1999
Revision A3
- 5 -
W25P243A
Write Table, continued
READ/WRITE FUNCTION
GW
1
BW8
1
BW7
1
BW6
1
BW5
0
BW4
1
BW3
1
BW2
0
BW1
1
BWE
0
Write byte 5, byte 2
Write byte 5, byte 2, byte 1
Write byte 5, byte 3
1
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
1
0
1
1
Write byte 5, byte 3, byte 1
Write byte 5, byte 3, byte 2
Write byte 5, byte 3, byte 2, byte 1
Write byte 5, byte 4
1
0
1
1
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
1
1
0
1
1
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
Write byte 5, byte 4, byte 1
Write byte 5, byte 4, byte 2
Write byte 5, byte 4, byte 2, byte 1
Write byte 5, byte 4, byte 3
Write byte 5, byte 4, byte 3, byte 1
Write byte 5, byte 4, byte 3, byte 2
1
0
1
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
0
1
Write byte 5, byte 4, byte 3, byte 2,
byte 1
1
0
1
1
1
0
0
0
0
0
Write byte 6
1
1
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
Write byte 6, byte 1
Write byte 6, byte 2
Write byte 6, byte 2, byte 1
..... and so on .....
1
0
1
1
0
1
1
1
0
1
1
0
1
1
0
1
1
1
0
0
...
1
...
0
...
0
...
0
...
0
...
0
...
0
...
1
...
0
...
0
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 2, byte 1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 1
Write byte 8, byte 7, byte 6, byte 5,
byte 4, byte 3, byte 2
Write all bytes
Write all bytes
1
0
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
Power Down Mode
The ZZ state is a low-power state in which the device consumes less power than in the unselected
mode. Enabling the ZZ pin for a fixed period of time will force the SRAM into the ZZ state. Pulling the
ZZ pin low for a set period of time will wake up the SRAM again. While the SRAM is in ZZ mode, data
retention is guaranteed, but the chip will not monitor any input signals except for the ZZ pin. In the
unselected mode, on the other hand, all the input signals are monitored.
- 6 -
W25P243A
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Core Supply Voltage to Vss
I/O Supply Voltage to Vss
SSQ
RATING
-0.5 to 4.6
-0.5 to 4.6
UNIT
V
V
SSQ
V
DDQ
-0.5 to V +0.5
1.0
Input/Output to V
Potential
V
Allowable Power Dissipation
Storage Temperature
W
-65 to 150
0 to +70
°
°
C
C
Operating Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
DD DDQ
(V /V
SS SSQ A
= 0V, T = 0 to 70 C)
°
= 3.15V to 3.6V, V /V
PARAMETER
SYM.
TEST CONDITIONS
MIN. TYP.
MAX.
UNIT
V
IL
Input Low Voltage
Input High Voltage
V
-
-
-0.5
-
-
+0.8
IH
V
DD
V
+2.0
V
+0.3
+10
LI
IN
SSQ
SSQ
DDQ
Input Leakage Current
I
V
= V
to V
-10
-10
-
-
m
A
LO
I/O
V
DDQ,
Output Leakage
Current
I
= V
to V
and data
+ 10
mA
I/O pins in high-Z state defined
in truth table
OL
OL
Output Low Voltage
Output High Voltage
Operating Current
Standby Current
V
I
I
= +8.0 mA
= -4.0 mA
-
2.4
-
-
-
-
-
0.4
-
V
OH
OH
V
V
DD
I
350
80
mA
mA
CYC
T
³
min. , I/O = 0 mA
SB
I
Unselected mode defined in
truth table,
-
IN IO
IH
IL
V , V = V (min.) /V (max.)
CYC
T
³
min.
ZZ
ZZ Mode Current
I
-
-
5
mA
CYC
³
ZZ mode, T
min.
Note: Typical characteristics are measured at VDD = 3.3V, TA = 25 C.
°
CAPACITANCE
DD
A
(V
= 3.3V, T = 25 C, f = 1 MHz)
°
PARAMETER
SYM.
CONDITIONS
MAX.
UNIT
IN
IN
Input Capacitance
C
V
= 0V
6
8
pF
pF
I/O
OUT
V = 0V
Input/Output Capacitance
C
Note: These parameters are sampled but not 100% tested.
Publication Release Date: August 1999
Revision A3
- 7 -
W25P243A
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
2 nS
1.5V
L
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
OH OL
C = 30 pF, I /I = -4 mA/8 mA
AC Test Loads and Waveform
R1 320 ohm
3.3V
RL = 50 ohm
VL = 1.5V
OUTPUT
R2
5 pF
OUTPUT
350 ohm
30 pF
Including
Jig and
Scope
Zo = 50 ohm
Including
Jig and
Scope
T
T
(For T
T
KLZ,
measurement)
OHZ, OLZ,
KHZ,
3.0V
0V
90%
90%
10%
10%
2 nS
2 nS
AC Timing Characteristics
(VDD/VDDQ = 3.15V to 3.6V, VSS/VSSQ = 0V, TA = 0 to 70 C, all timings measured in pipelined mode)
°
PARAMETER
SYM.
W25P243A-4A
W25P243A-5
W25P243A-6
UNIT
NOTE
nS
nS
nS
nS
nS
nS
MIN.
2.0
1.0
2.0
1.0
2.0
MAX.
MIN.
2.0
1.0
2.0
1.0
2.0
MAX.
MIN.
2.0
1.0
2.0
1.0
2.0
MAX.
AS
Address Setup Time
Address Hold Time
Write Data Setup Time
Write Data Hold Time
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AH
T
T
T
T
DS
DH
ADVS
ADV
ADV
Setup Time
Hold Time
nS
ADVH
T
1.0
-
1.0
-
1.0
-
- 8 -
W25P243A
AC Timing Characteristics, continued
NOTE
PARAMETER
SYM. W25P243A-4A W25P243A-5 W25P243A-6
MIN. MAX. MIN. MAX. MIN. MAX.
ADSS
UNIT
T
T
T
T
T
T
T
2.0
1.0
2.0
1.0
2.0
1.0
2.0
-
-
-
-
-
-
-
2.0
1.0
2.0
1.0
2.0
1.0
2.0
-
-
-
-
-
-
-
2.0
1.0
2.0
1.0
2.0
1.0
2.0
-
-
-
-
-
-
-
nS
nS
nS
nS
nS
nS
nS
ADSP
ADSP
ADSC
ADSC
Setup Time
Hold Time
Setup Time
Hold Time
ADSH
ADCS
ADCH
CES
CE1
CE1
CE3
CE3
, CE2,
, CE2,
Setup Time
Hold Time
CEH
WS
GW BWE BWEx
,
,
Setup
Time
WH
T
1.0
-
1.0
-
1.0
-
nS
GW BWE BWEx
,
,
Hold Time
CYC
KH
-
-
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
Clock Cycle Time
T
T
T
T
T
T
T
T
T
T
T
T
10
4
-
-
12
5
-
-
13.3
6
Clock High Pulse Width
Clock Low Pulse Width
Clock Access Time
KL
4
-
5
-
6
KQ
-
4.5
-
5
-
6
13.3
1
1.5
0
1
1
1
KHZ
KLZ
KX
Clock High to Output High-Z
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable to Output Valid
Output Disable to Output High-Z
Output Enable to Output Low-Z
ZZ Standby Time
1.5
0
10
1.5
0
12
-
-
-
-
1.5
1.5
1.5
-
OE
-
-
4.5
4.5
-
-
-
5
5
-
-
6
6
OHZ
OLZ
ZZS
ZZR
1
1
2
3
0
0
-
0
-
-
100
-
-
100
-
-
100
-
ZZ Recover Time
100
100
100
Notes:
1. These parameters are sampled but not 100% tested
2. In the ZZ mode, the SRAM will enter a low-power state. In this mode, data retention is guaranteed and the clock is active.
3. and should not be accessed for at least 100 nS after chip leaves ZZ mode.
ADSC
ADSP
4. Configuration signals
and
are static and should not be changed during operation.
FT
LBO
Publication Release Date: August 1999
Revision A3
- 9 -
W25P243A
TIMING WAVEFORMS
Read Cycle Timing
Pipelined Read
Single Read
Burst Read
Unselected
TCYC
CLK
TKH
TKL
TADSS
TADSH
ADSP is blocked by CE1 inactive
ADSP
ADSC
TADCH
TADCS
ADSC initiated read
TADVS
TADVH
Suspend Burst
ADV
TAS
TAH
RD1
A[15:0]
RD3
RD2
TWS
TWH
GW
TWS
TWH
BWE
BW[8:1]
TCES
TCES
TCES
TCEH
CE1 masks ADSP
CE1
CE2
TCEH
CE2 / CE3 only sampled with ADSP or ADSC
Unselected with CE2
TCEH
CE3
TOHZ
TOE
OE
TKX
2a
TOLZ
Data-Out
3a
High-Z
High-Z
1a
2b
2d
2c
TKLZ
TKHZ
TKQ
TKQ
Data-In
DON'T CARE
UNDEFINED
- 10 -
W25P243A
Timing Waveforms, continued
Write Cycle Timing
Burst Write
Write
Unselected
Single Write
TCYC
TKL
CLK
TKH
TADSS
TADSH
ADSP is blocked by CE1 inactive
ADSP
TADCH
TADCS
ADSC initiated write
ADSC
TADVS
TADVH
ADV
ADV must be inactive for ADSP write
WR2
TAS
WR1
TAH
A[15:0]
WR3
GWE allows processor address (and BE=BW)
to be pipelined during a writeback
TWH
TWS
TWS
TWS
GW
TWH
BWE
TWH
WR1
WR2
BW[8:1]
WR3
TCES
TCEH
CE1 masks ADSP
CE1
CE2
TCES
TCEH
TCEH
Unselected with CE2
CE2 / CE3 only sampled with ADSP or ADSC
TCES
CE3
OE
Data-Out
High-Z
High-Z
TDS TDH
BW[4:1] are applied only to first cycle of WR2
2a
2b
2c
1a
2d
3a
Data-In
DON'T CARE
UNDEFINED
Publication Release Date: August 1999
Revision A3
- 11 -
W25P243A
Timing Waveforms, continued
Read/Write Cycle Timing
Single Write
TCYC
Burst Read
Unselected
Single Read
CLK
TKH
TKL
TADSS
TADSH
ADSP is blocked by CE1 inactive
ADSP
ADSC
TADCH
TADCS
ADSC initiated read
TADVS
TADVH
Suspend Burst
ADV
TAS
TAH
A[15:0]
RD2
WR1
RD1
TWH
TWS
GW
TWS
TWH
BWE
TWS
TWH
WR1
BW[8:1]
TCES
TCES
TCES
TCEH
CE1 masks ADSP
CE1
CE2
TCEH
CE2 / CE3 only sampled with ADSP or ADSC
TCEH
Unselected with CE3
CE3
TOE
TOHZ
OE
TKX
TOH
TOLZ
1a
Data-Out
High-Z
High-Z
2d
2c
2b
2a
TKLZ
TDSTDH
1a
TKQ
TKHZ
Data-In
DON'T CARE
UNDEFINED
- 12 -
W25P243A
Timing Waveforms, continued
ZZ and RD Timing
Read
Single Read
TADSH
Snooze -with Data Retention
TCYC
CLK
TKH
TKL
TADSS
ADSP
ADSC
ADV
TADVS
TADVH
TAS
TAH
A[15:0]
RD1
RD2
TWS
TWH
GW
TWS
TWH
BWE
TWS
TWH
RD
BW[8:1]
RD
RD
TCES
TCES
TCES
TCEH
TCEH
TCEH
CE1
CE2
CE3
TOE
TOHZ
OE
TOLZ
Data-Out
High-Z
High-Z
1a
TKX
TKLZ
TKHZ
TKQ
Data-In
ZZ
TZZS
TZZR
DON'T CARE
UNDEFINED
Publication Release Date: August 1999
Revision A3
- 13 -
W25P243A
Timing Waveforms, continued
Dual Bank Burst Read Cycle
CLK
Select Bank 0
Select Bank 1
Select Bank 0
ADSP
ADSC
ADV
Read 2
Read 3
Read 1
A[31:3]
GW
BWE
BW[8:1]
CE1
CE[3:2]
Bank 0
Non-
Active
Active
Active
Non-
CE[3:2]
Bank 1
Non-
Activ
Active
Active
OE
D[63:0]
Bank 0
1b
1a
1c
1d
D[63:0]
Bank 1
2b
2a
2c
2d
DON'T CARE
UNDEFINED
- 14 -
W25P243A
ORDERING INFORMATION
PART NO.
ACCESS
TIME (nS)
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
W25P243AF-4A
W25P243AF-5
W25P243AF-6
W25P243AD-4A
W25P243AD-5
W25P243AD-6
4.5
5
350
350
350
350
350
350
80
80
80
80
80
80
128-pin QFP
128-pin QFP
128-pin QFP
128-pin TQFP
128-pin TQFP
128-pin TQFP
6
4.5
5
6
Notes
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Publication Release Date: August 1999
- 15 -
Revision A3
W25P243A
PACKAGE DIMENSIONS
128-pin QFP
HD
D
128
103
1
102
E
H
E
38
65
39
64
e
b
c
A
q
2
A
1
A
L
See Detail F
Seating Plane
y
L 1
Detail F
Dimension in inches
Dimension in mm
Symbol
Nom.
Nom.
Min.
Max.
Min.
Max.
3.40
0.134
A
A1
0.004
0.10
0.101 0.107 0.113 2.57
2.87
0.25
2.72
0.20
2
A
0.006
0.004
0.008 0.010 0.15
b
c
D
E
e
0.006
0.10
13.90
19.90
0.15
0.25
0.010
14.00
20.00
0.50
0.547 0.551 0.555
0.783 0.787 0.791
0.020
14.10
20.10
0.669
0.905
0.685
0.921
0.039
0.071
0.677
0.913
0.031
0.063
17.00 17.20 17.40
D
H
23.20 23.40
23.00
0.60
1.40
E
H
0.80
1.60
1.00
1.80
0.023
0.055
L
1
L
0.004
12
y
0.10
12
0
0
q
- 16 -
W25P243A
Package Dimensions, continued
128-pin TQFP
HD
D
128
103
1
102
E
E
H
38
65
39
64
e
b
c
A
2
q
A
L
1
See Detail F
Seating Plane
A
y
L 1
Detail F
Dimension in inches
Dimension in mm
Symbol
Nom.
Nom.
Min.
Max.
Min.
Max.
1.60
0.063
A
A1
A2
b
c
0.002
0.05
0.053 0.055 0.057 1.35
1.45
0.27
1.40
0.20
0.006
0.004
0.008 0.011 0.15
0.006
0.10
0.15
0.25
0.010
14.00
20.00
0.50
13.90
19.90
0.547 0.551 0.555
0.783 0.787 0.791
0.020
14.10
20.10
D
E
e
0.626
0.862
0.018
0.634
0.870
0.030
0.630
0.866
0.024
0.039
15.90 16.00 16.10
22.00 22.10
H
HE
L
D
21.90
0.45 0.60
1.00
0.75
1
L
y
0.004
12
0.10
12
0
0
q
Publication Release Date: August 1999
Revision A3
- 17 -
W25P243A
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Nov. 1997
Feb. 1998
Initial Issued
1 to 5, 8 to 12, 14
Eliminate the CE2 and CE3 functionality
A3
Aug. 1999
1, 8, 9, 15
9
Support 83, 75 MHz
OHZ
T
: Change from "Output Enable" to "
Output Disable"
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Headquarters
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5796096
http://www.winbond.com.tw/
TEL: 408-9436666
FAX: 408-5441798
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 18 -
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