W25Q64JVXGIMTR [WINBOND]
3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI & DTR;
| 型号： | W25Q64JVXGIMTR |
| 厂家： | 
WINBOND |
| 描述： | 3V 64M-BIT SERIAL FLASH MEMORY WITH DUAL/QUAD SPI & QPI & DTR |
| 文件： | 总101页 (文件大小：2877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W25Q64JV-DTR
3V 64M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI & DTR
For Industrial & Industrial Plus Grade
Publication Release Date: March 27, 2018
Revision J
W25Q64JV-DTR
Table of Contents
1.
2.
GENERAL DESCRIPTIONS.............................................................................................................4
FEATURES.......................................................................................................................................4
NOTE: 1. HARDWARE /RESET PIN IS ONLY AVAILABLE ON TFBGA OR SOIC16 PACKAGES ...........4
3. PACKAGE TYPES AND PIN CONFIGURATIONS ..........................................................................5
3.1
3.2
3.3
3.4
3.5
3.1
3.2
Pin Configuration SOIC 208-mil ...........................................................................................5
Pad Configuration WSON 6x5-mm / 8x6-mm, XSON 4x4-mm............................................5
Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm, XSON 4x4-mm.........................5
Pin Configuration SOIC 300-mil ...........................................................................................6
Pin Description SOIC 300-mil...............................................................................................6
Ball Configuration TFBGA 8x6-mm......................................................................................7
Ball Description TFBGA 8x6-mm .........................................................................................7
4.
PIN DESCRIPTIONS........................................................................................................................8
4.1
4.2
4.3
4.4
4.5
4.6
Chip Select (/CS)..................................................................................................................8
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ....................................8
Write Protect (/WP)...............................................................................................................8
HOLD (/HOLD) .....................................................................................................................8
Serial Clock (CLK)................................................................................................................8
Reset (/RESET)....................................................................................................................8
5.
6.
BLOCK DIAGRAM............................................................................................................................9
FUNCTIONAL DESCRIPTIONS.....................................................................................................10
6.1
SPI / QPI Operations..........................................................................................................10
Standard SPI Instructions .....................................................................................................10
Dual SPI Instructions ............................................................................................................10
Quad SPI Instructions...........................................................................................................11
QPI Instructions ....................................................................................................................11
SPI / QPI DTR Read Instructions..........................................................................................11
Hold Function........................................................................................................................11
Software Reset & Hardware /RESET pin..............................................................................12
Write Protection..................................................................................................................13
Write Protect Features..........................................................................................................13
6.2
7.
STATUS AND CONFIGURATION REGISTERS............................................................................14
7.1
Status Registers .................................................................................................................14
Erase/Write In Progress (BUSY) – Status Only.................................................................14
Write Enable Latch (WEL) – Status Only...........................................................................14
Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable.................................14
Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable........................................15
Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable........................................15
Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................15
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W25Q64JV-DTR
Status Register Protect (SRP, SRL) – Volatile/Non-Volatile Writable................................16
Erase/Program Suspend Status (SUS) – Status Only .......................................................17
Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable...........17
Quad Enable (QE) – Volatile/Non-Volatile Writable.........................................................17
Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ......................................18
Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ..........................18
/HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable...............18
Reserved Bits – Non Functional ......................................................................................19
Status Register Memory Protection (WPS = 0, CMP = 0)...................................................20
Status Register Memory Protection (WPS = 0, CMP = 1)...................................................21
Individual Block Memory Protection (WPS=1) ....................................................................22
INSTRUCTIONS.............................................................................................................................23
8.
8.1
Device ID and Instruction Set Tables.................................................................................23
Manufacturer and Device Identification.................................................................................23
Instruction Set Table 1 (Standard SPI Instructions)(1) ...........................................................24
Instruction Set Table 2 (Dual/Quad SPI Instructions)(1).........................................................25
Instruction Set Table 3 (QPI Instructions)(11).........................................................................26
Instruction Set Table 4 (DTR with SPI Instructions)..............................................................27
Instruction Set Table 5 (DTR with QPI Instructions) .............................................................27
Instruction Descriptions ......................................................................................................29
Write Enable (06h)................................................................................................................29
Write Enable for Volatile Status Register (50h).....................................................................29
Write Disable (04h)...............................................................................................................30
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)...............30
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ...............32
Read Data (03h) ...................................................................................................................35
Fast Read (0Bh) ...................................................................................................................36
DTR Fast Read (0Dh)...........................................................................................................38
Fast Read Dual Output (3Bh) ...............................................................................................40
Fast Read Quad Output (6Bh)............................................................................................41
Fast Read Dual I/O (BBh)...................................................................................................42
DTR Fast Read Dual I/O (BDh) ..........................................................................................44
Fast Read Quad I/O (EBh)..................................................................................................46
DTR Fast Read Quad I/O (EDh).........................................................................................48
Set Burst with Wrap (77h)...................................................................................................52
Page Program (02h) ...........................................................................................................53
Quad Input Page Program (32h).........................................................................................55
Sector Erase (20h)..............................................................................................................56
32KB Block Erase (52h)......................................................................................................57
64KB Block Erase (D8h).....................................................................................................58
Chip Erase (C7h / 60h).......................................................................................................59
Erase / Program Suspend (75h) .........................................................................................60
Erase / Program Resume (7Ah)..........................................................................................62
8.2
Publication Release Date: March 27, 2018
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W25Q64JV-DTR
Power-down (B9h) ..............................................................................................................63
Release Power-down / Device ID (ABh).............................................................................64
Read Manufacturer / Device ID (90h) .................................................................................66
Read Manufacturer / Device ID Dual I/O (92h) ...................................................................67
Read Manufacturer / Device ID Quad I/O (94h)..................................................................68
Read Unique ID Number (4Bh)...........................................................................................69
Read JEDEC ID (9Fh) ........................................................................................................70
Read SFDP Register (5Ah).................................................................................................71
Erase Security Registers (44h)...........................................................................................72
Program Security Registers (42h).......................................................................................73
Read Security Registers (48h)............................................................................................74
Set Read Parameters (C0h) ...............................................................................................75
Burst Read with Wrap (0Ch)...............................................................................................76
DTR Burst Read with Wrap (0Eh).......................................................................................77
Enter QPI Mode (38h).........................................................................................................78
Exit QPI Mode (FFh)...........................................................................................................79
Individual Block/Sector Lock (36h)......................................................................................80
Individual Block/Sector Unlock (39h) ..................................................................................81
Read Block/Sector Lock (3Dh)............................................................................................82
Global Block/Sector Lock (7Eh)..........................................................................................83
Global Block/Sector Unlock (98h).......................................................................................83
Enable Reset (66h) and Reset Device (99h) ......................................................................84
ELECTRICAL CHARACTERISTICS...............................................................................................85
(1)
9.
9.1
9.2
9.3
9.4
9.5
9.6
Absolute Maximum Ratings
..........................................................................................85
Operating Ranges ..............................................................................................................85
Power-Up Power-Down Timing and Requirements ...........................................................86
DC Electrical Characteristics-.............................................................................................87
AC Measurement Conditions .............................................................................................88
AC Electrical Characteristics (6) ..........................................................................................89
Serial Output Timing.............................................................................................................91
Serial Input Timing..............................................................................................................91
/HOLD Timing.....................................................................................................................91
/WP Timing.........................................................................................................................91
9.7
9.8
9.9
10.
PACKAGE SPECIFICATIONS .......................................................................................................92
10.1 8-Pin SOIC 208-mil (Package Code SS)............................................................................92
10.3 8-Pad WSON 6x5-mm (Package Code ZP).......................................................................93
10.4 8-Pad WSON 8x6-mm (Package Code ZE).......................................................................94
10.6 8-Pad XSON 4x4x0.45-mm (Package Code XG) ..............................................................95
10.7 16-Pin SOIC 300-mil (Package Code SF)..........................................................................96
10.8 Ordering Information...........................................................................................................97
10.9 Valid Part Numbers and Top Side Marking........................................................................99
REVISION JISTORY.....................................................................................................................100
11.
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W25Q64JV-DTR
1. GENERAL DESCRIPTIONS
The W25Q64JV (64M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices.
They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing
voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current consumption
as low as 1µA for power-down. All devices are offered in space-saving packages.
The W25Q64JV array is organized into 32,768 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q64JV has
2,048 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See Figure 2)
The W25Q64JV support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI Quad Peripheral
Interface (QPI) as well as Double Transfer Rate(DTR) : Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 133MHz are supported allowing
equivalent clock rates of 266MHz (133MHz x 2) for Dual I/O and 532MHz (133MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O and QPI instructions. These 3transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and
SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
2. FEATURES
New Family of SpiFlash Memories
– 64M-bit /8M-byte
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Program 1 to 256 byte per programmable page
– Erase/Program Suspend & Resume
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– SPI/QPI DTR (Double Transfer Rate) Read
– Software & Hardware Reset(1)
Advanced Security Features
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– Top/Bottom, Complement array protection
– Individual Block/Sector array protection
– 64-Bit Unique ID for each device
Highest Performance Serial Flash
–133MHz Single, Dual/Quad SPI clocks
– 266/532MHz equivalent Dual/Quad SPI
– 66MB/S continuous data transfer rate
– Min. 100K Program-Erase cycles per sector
– More than 20-year data retention
– Discoverable Parameters (SFDP) Register
– 3X256-Bytes Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
Efficient “Continuous Read”
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Quad Peripheral Interface (QPI) reduces
instruction overhead
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 6x5-mm / 8x6-mm
– 8-pad XSON 4x4-mm
– 16-pin SOIC 300-mil (additional /RESET pin)
– 24-ball TFBGA 8x6-mm (5x5-1 ball array)
– Contact Winbond for KGD and other options
Note: 1. Hardware /RESET pin is only available on
TFBGA or SOIC16 packages
–<1µA Power-down (typ.)
– -40°C to +85°C operating range
– -40°C to +105°C operating range
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
3. PACKAGE TYPES AND PIN CONFIGURATIONS
3.1 Pin Configuration SOIC 208-mil
Top View
/CS
DO (IO1)
/WP (IO2)
GND
1
2
3
4
8
7
6
5
VCC
/HOLD or /RESET
(IO3)
CLK
DI (IO0)
Figure 1a. W25Q64JV Pin Assignments, 8-pin SOIC 208-mil (Package Code SS)
3.2 Pad Configuration WSON 6x5-mm / 8x6-mm, XSON 4x4-mm
Top View
/CS
DO (IO1)
/WP (IO2)
GND
1
2
3
4
8
7
6
5
VCC
/HOLD or /RESET
(IO3)
CLK
DI (IO0)
Figure 1b. W25Q64JV Pad Assignments, 8-pad WSON 6x5-mm / 8x6-mm (Package Code ZP / ZE)
3.3 Pin Description SOIC 208-mil, WSON 6x5-mm / 8x6-mm, XSON 4x4-mm
PIN NO.
PIN NAME
/CS
I/O
I
FUNCTION
1
2
3
4
5
6
Chip Select Input
DO (IO1)
/WP (IO2)
GND
I/O
I/O
Data Output (Data Input Output 1)(1)
Write Protect Input ( Data Input Output 2)(2)
Ground
DI (IO0)
CLK
I/O
I
Data Input (Data Input Output 0)(1)
Serial Clock Input
/HOLD or /RESET
(IO3)
7
8
I/O
Hold or Reset Input (Data Input Output 3)(2)
Power Supply
VCC
Notes: 1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual
SPI.
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W25Q64JV-DTR
3.4 Pin Configuration SOIC 300-mil
Top View
/HOLD (IO3)
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
DI (IO0)
NC
/RESET
NC
NC
NC
NC
NC
NC
/CS
GND
/WP (IO2)
DO (IO1)
Figure 1c. W25Q64JV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
3.5 Pin Description SOIC 300-mil
PIN NO.
PIN NAME
/HOLD (IO3)
VCC
I/O
FUNCTION
Hold Input (Data Input Output 3)(2)
Power Supply
1
2
I/O
3
/RESET
N/C
I
Reset Input(3)
4
No Connect
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO (IO1)
/WP (IO2)
GND
I/O
I/O
Data Output (Data Input Output 1)(1)
Write Protect Input (Data Input Output 2)(2)
Ground
9
10
11
12
13
14
15
16
N/C
No Connect
N/C
No Connect
N/C
No Connect
N/C
No Connect
DI (IO0)
CLK
I/O
I
Data Input (Data Input Output 0)(1)
Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD (or /RESET) functions are only available for Standard/Dual SPI.
3. The /RESET pin on SOIC-16 package is independent of the HOLD/RST bit and QE bit settings in the Status Register. This pin
can be left floating, if Rest function is not needed.
Publication Release Date: March 27, 2018
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Revision J
W25Q64JV-DTR
3.1 Ball Configuration TFBGA 8x6-mm
Top View
A2
NC
A3
NC
A4
A5
NC
/RESET
B1
NC
B2
B3
B4
B5
NC
CLK
GND
VCC
C1
NC
C2
C3
NC
C4
C5
NC
/CS
/WP (IO2)
D1
NC
D2
D3
D4
D5
NC
DO(IO1)
DI(IO0) /HOLD(IO3)
E1
NC
E2
NC
E3
NC
E4
NC
E5
NC
Package Code TB
Figure 1d. W25Q64JV Ball Assignments, 24-ball TFBGA 8x6-mm, 5X5 (Package Code TB)
3.2 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
/RESET
CLK
I/O
FUNCTION
A4
B2
I
I
Reset Input(3)
Serial Clock Input
Ground
B3
GND
B4
VCC
Power Supply
Chip Select Input
C2
/CS
I
C4
/WP (IO2)
DO (IO1)
DI (IO0)
/HOLD (IO3)
NC
I/O
I/O
I/O
I/O
Write Protect Input (Data Input Output 2)(2)
Data Output (Data Input Output 1)(1)
Data Input (Data Input Output 0)(1)
Hold or Reset Input (Data Input Output 3)(2)
No Connect
D2
D3
D4
Multiple
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions.
3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states.
If the hardware reset function is not used, this pin can be left floating or connected to VCC in the system
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W25Q64JV-DTR
4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure 58).
If needed a pull-up resister on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q64JV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. When
QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be hardware
protected. The /WP pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the /WP pin
function is not available since this pin is used for IO2. See Figure 1a-e for the pin configuration of Quad I/O
operation.
4.4 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be useful
when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the QE bit of
Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is used for IO3.
See Figure 1a-e for the pin configuration of Quad I/O operation.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
4.6 Reset (/RESET)
The /RESET pin allows the device to be reset by the controller. For 8-pin packages, when QE=0, the IO3
pin can be configured either as a /HOLD pin or as a /RESET pin depending on Status Register setting.
When QE=1, the /HOLD or /RESET function is not available for 8-pin configuration. On the 16-pin SOIC
package, a dedicated /RESET pin is provided and it is independent of QE bit setting.
Publication Release Date: March 27, 2018
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Revision J
W25Q64JV-DTR
5. BLOCK DIAGRAM
Figure 2. W25Q64JV Serial Flash Memory Block Diagram
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W25Q64JV-DTR
6. FUNCTIONAL DESCRIPTIONS
6.1 SPI / QPI Operations
Power Up
Device Initialization
& Status Register Refresh
(Non-Volatile Cells)
Standard SPI
Dual SPI
Hardware
Reset
SPI Reset
(66h + 99h)
Quad SPI
Enable QPI (38h)
Disable QPI (FFh)
Hardware
Reset
QPI Reset
(66h + 99h)
QPI
Figure 3. W25Q64JV Serial Flash Memory Operation Diagram
Standard SPI Instructions
The W25Q64JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
Dual SPI Instructions
The W25Q64JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
Publication Release Date: March 27, 2018
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W25Q64JV-DTR
Quad SPI Instructions
The W25Q64JV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)” and “Fast Read Quad I/O (EBh)”. These instructions allow data to be transferred to or from the
device four to six times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant
improvement in continuous and random access transfer rates allowing fast code-shadowing to RAM or
execution directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI
instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
QPI Instructions
The W25Q64JV supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI
protocol requires that the byte-long instruction code being shifted into the device only via DI pin in eight
serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks
are required. This can significantly reduce the SPI instruction overhead and improve system performance
in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can
be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between
these two modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state
of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit
(QE) in Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. See Figure 3
for the device operation modes.
SPI / QPI DTR Read Instructions
To effectively improve the read operation throughput without increasing the serial clock frequency,
W25Q64JV introduces multiple DTR (Double Transfer Rate) Read instructions that support
Standard/Dual/Quad SPI and QPI modes. The byte-long instruction code is still latched into the device on
the rising edge of the serial clock similar to all other SPI/QPI instructions. Once a DTR instruction code is
accepted by the device, the address input and data output will be latched on both rising and falling edges
of the serial clock.
Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q64JV operation to be paused
while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can
save the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation,
not during Quad SPI or QPI. The Quad Enable Bit QE in Status Register-2 is used to determine if the pin
is used as /HOLD pin or data I/O pin. When QE=0 (factory default), the pin is /HOLD, when QE=1, the pin
will become an I/O pin, /HOLD function is no longer available.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising
edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition
will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS)
signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal
logic state of the device.
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W25Q64JV-DTR
Software Reset & Hardware /RESET pin
The W25Q64JV can be reset to the initial power-on state by a software Reset sequence, either in SPI mode
or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h).
If the command sequence is successfully accepted, the device will take approximately 30uS (tRST) to reset.
No command will be accepted during the reset period.
For the WSON-8 package type, W25Q64JV can also be configured to utilize a hardware /RESET pin. The
HOLD/RST bit in the Status Register-3 is the configuration bit for /HOLD pin function or RESET pin function.
When HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described above; when HOLD/RST=1,
the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset
the device to its initial power-on state. Any on-going Program/Erase operation will be interrupted and data
corruption may happen. While /RESET is low, the device will not accept any command input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the four data
I/O pins.
For the SOIC-16 package, W25Q64JV provides a dedicated /RESET pin in addition to the /HOLD (IO3) pin
as illustrated in Figure 1b. Drive the /RESET pin low for a minimum period of ~1us (tRESET*) will reset the
device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will not affect the
function of this dedicated /RESET pin.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a minimum
period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status of
other SPI signals (/CS, CLK, IOs, /WP and/or /HOLD).
Note:
1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended
to ensure reliable operation.
2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 and TFBGA package. If the reset function is not
needed, this pin can be left floating in the system.
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W25Q64JV-DTR
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q64JV
provides several means to protect the data from inadvertent writes.
Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Status Registers
Additional Individual Block/Sector Locks for array protection
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q64JV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 58). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP, SRL) and Block Protect (CMP, SEC, TB, BP[2:0]) bits. These settings allow
a portion or the entire memory array to be configured as read only. Used in conjunction with the Write
Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware control. See
Status Register section for further information. Additionally, the Power-down instruction offers an extra level
of write protection as all instructions are ignored except for the Release Power-down instruction.
The W25Q64JV also provides another Write Protect method using the Individual Block Locks. Each 64KB
block (except the top and bottom blocks, total of 126 blocks) and each 4KB sector within the top/bottom
blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the
corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program
commands issued to the corresponding sector or block will be ignored. When the device is powered on, all
Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An
“Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, SEC, TB, BP[2:0] bits to protect specific areas of
the array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
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W25Q64JV-DTR
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for W25Q64JV.The Read Status Register-1/2/3
instructions can be used to provide status on the availability of the flash memory array, whether the device
is write enabled or disabled, the state of write protection, Quad SPI setting, Security Register lock status,
Erase/Program Suspend status, output driver strength, and power-up. The Write Status Register instruction
can be used to configure the device write protection features, Quad SPI setting, Security Register OTP locks,
Hold/Reset functions, and output driver strength. Write access to the Status Register is controlled by the state
of the non-volatile Status Register Protect bits (SRP, SRL), the Write Enable instruction, and during
Standard/Dual SPI operations, the /WP pin.
7.1 Status Registers
Figure 4a. Status Register-1
Erase/Write In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE
in AC Characteristics). When the program, erase or write status/security register instruction has completed,
the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
Block Protect Bits (BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
Publication Release Date: March 27, 2018
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W25Q64JV-DTR
protected from Program and Erase instructions (see Status Register Memory Protection table). The factory
default setting for the Block Protection Bits is 0, none of the array protected.
Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top
(TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The
factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending
on the state of the SRP, SRL and WEL bits.
Sector/Block Protect Bit (SEC) – Volatile/Non-Volatile Writable
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
Complement Protect (CMP) – Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For instance,
when CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top
64KB block will become unprotected while the rest of the array become read-only. Please refer to the Status
Register Memory Protection table for details. The default setting is CMP=0.
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W25Q64JV-DTR
Status Register Protect (SRP, SRL) – Volatile/Non-Volatile Writable
The Status Register Protect bits (SRP) are non-volatile read/write bits in the status register (S7).
The SRP bit controls the method of write protection: software protection or hardware protection.
The Status Register Lock bits (SRL) are non-volatile/volatile read/write bits in the status register
(S8). The SRL bit controls the method of write protection: temporary lock-down or permanently
one time program.
Status
Register
SRL
SRP
0
/WP
X
Description
Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0
Hardware
Protected
When /WP pin is low the Status Register locked and cannot be
written to.
0
1
0
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
0
1
1
Power Supply Status Register is protected and cannot be written to again
Lock-Down
1
X
X
until the next power-down, power-up cycle.(1)
One Time
Program(2)
Status Register is permanently protected and cannot be written
to. (enabled by adding prefix command AAh, 55h)
1
X
X
Note:
1. When SRL =1, a power-down, power-up cycle will change SRL =0 state.
2. Please contact Winbond for details regarding the special instruction sequence.
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Revision J
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W25Q64JV-DTR
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
(R)
S9
S8
SUS
CMP
QE
SRL
Suspend Status
(Status-Only)
Complement Protect
(Volatile/Non-Volatile Writable)
Security Register Lock Bits
(Volatile/Non-Volatile OTP Writable)
Reserved
Quad Enable
(Volatile/Non-Volatile Writable)
Status Register Lock
(Volatile/Non-Volatile Writable)
Figure 4b. Status Register-2
Erase/Program Suspend Status (SUS) – Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
Quad Enable (QE) – Volatile/Non-Volatile Writable
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default for part numbers with ordering options
“IM” & “JM”), the /WP pin and /HOLD are enabled. When the QE bit is set to a 1(factory default for Quad
Enabled part numbers with ordering option “IQ” & “JQ”),, the Quad IO2 and IO3 pins are enabled, and /WP
and /HOLD functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enter QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,
QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a
“1” to a “0”.
.
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W25Q64JV-DTR
S23
S22
S21
S20
S19
(R)
S18
S17
R
S16
R
HOLD
/RST
DRV 1 DRV0 (R)
WPS
/HOLD or /RESET Function
( Volatile/Non- Volatile Writable)
Output Driver Strength
( Volatile/Non- Volatile Writable)
Reserved
Write Protect Selection
( Volatile/Non- Volatile Writable)
Reserved
Reserved
Figure 4c. Status Register-3
Write Protect Selection (WPS) – Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the device will
use the combination of CMP, SEC, TB, BP[2:0] bits to protect a specific area of the memory array. When
WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks. The
default value for all Individual Block Lock bits is 1 upon device power on or after reset.
Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
100%
0, 0
0, 1
1, 0
1, 1
75%
50%
25% (default)
/HOLD or /RESET Pin Function (HOLD/RST) – Volatile/Non-Volatile Writable
The HOLD/RST bit is used to determine whether /HOLD or /RESET function should be implemented on the
hardware pin for 8-pin packages. When HOLD/RST=0 (factory default), the pin acts as /HOLD; when
HOLD/RST=1, the pin acts as /RESET. However, /HOLD or /RESET functions are only available when
QE=0. If QE is set to 1, the /HOLD and /RESET functions are disabled, the pin acts as a dedicated data
I/O pin.
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W25Q64JV-DTR
Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written
as “0”, but there will not be any effects.
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W25Q64JV-DTR
Status Register Memory Protection (WPS = 0, CMP = 0)
Status Register(1)
W25Q64JV (64M-bit) Memory Protection(3)
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED PROTECTED
DENSITY
SEC
TB BP2 BP1 BP0
PORTION(2)
X
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NONE
126 and 127
124 thru 127
120 thru 127
112 thru 127
96 thru 127
64 thru 127
0 and 1
NONE
NONE
NONE
7E0000h – 7FFFFFh
7C0000h – 7FFFFFh
780000h – 7FFFFFh
700000h – 7FFFFFh
600000h – 7FFFFFh
400000h – 7FFFFFh
000000h – 01FFFFh
000000h – 03FFFFh
000000h – 07FFFFh
000000h – 0FFFFFh
000000h – 1FFFFFh
000000h – 3FFFFFh
000000h – 7FFFFFh
128KB
256KB
512KB
1MB
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
2MB
4MB
128KB
256KB
512KB
1MB
0 thru 3
0 thru 7
0 thru 15
0 thru 31
2MB
0 thru 63
4MB
0 thru 127
8MB
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
X
1
0
1
X
127
127
127
127
0
7FF000h – 7FFFFFh
7FE000h – 7FFFFFh
7FC000h – 7FFFFFh
7F8000h – 7FFFFFh
000000h – 000FFFh
000000h – 001FFFh
000000h – 003FFFh
000000h – 007FFFh
4KB
8KB
U – 1/2048
U – 1/1024
U – 1/512
U – 1/256
L – 1/2048
L – 1/1024
L – 1/512
L – 1/256
16KB
32KB
4KB
0
8KB
0
16KB
32KB
0
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command
will be ignored.
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Revision J
W25Q64JV-DTR
Status Register Memory Protection (WPS = 0, CMP = 1)
Status Register(1) W25Q64JV (64M-bit) Memory Protection(3)
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
SEC
TB SEC
TB
SEC
X
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
1
1
1
1
1
1
X
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 thru 127
0 thru 125
0 thru 123
0 thru 119
0 thru 111
0 thru 95
000000h – 7FFFFFh
000000h – 7DFFFFh
000000h – 7BFFFFh
000000h – 77FFFFh
000000h – 6FFFFFh
000000h – 5FFFFFh
000000h – 3FFFFFh
020000h – 7FFFFFh
040000h – 7FFFFFh
080000h – 7FFFFFh
100000h – 7FFFFFh
200000h – 7FFFFFh
400000h – 7FFFFFh
NONE
8MB
8,064KB
7,936KB
7,680KB
7MB
ALL
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
Lower 3/4
Lower 1/2
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
Upper 3/4
Upper 1/2
NONE
5MB
0 thru 63
4MB
2 thru 127
4 thru 127
8 thru 127
16 thru 127
32 thru 127
64 thru 127
NONE
8,064KB
7,936KB
7,680KB
7MB
5MB
4MB
NONE
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
X
1
0
1
X
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
0 thru 127
000000h – 7FEFFFh
000000h – 7FDFFFh
000000h – 7FBFFFh
000000h – 7F7FFFh
001000h – 7FFFFFh
002000h – 7FFFFFh
004000h – 7FFFFFh
008000h – 7FFFFFh
8,188KB
8,184KB
8,176KB
8,160KB
8,188KB
8,184KB
8,176KB
8,160KB
L – 2047/2048
L – 1023/1024
L – 511/512
L – 255/256
L – 2047/2048
L – 1023/1024
L – 511/512
L – 255/256
Notes:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this command
will be ignored.
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W25Q64JV-DTR
Individual Block Memory Protection (WPS=1)
Figure 4d. Individual Block/Sector Locks
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
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Revision J
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W25Q64JV-DTR
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q64JV consists of 48 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1-2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
The QPI instruction set of the W25Q64JV consists of 35 basic instructions that are fully controlled through
the SPI bus (see Instruction Set Table 3). Instructions are initiated with the falling edge of Chip Select (/CS).
The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four IO pins are
sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions, addresses,
data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial clocks
(CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through
57. All read instructions can be completed after any clocked bit. However, all instructions that Write,
Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked)
otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes.
Additionally, while the memory is being programmed or erased, or when the Status Register is being written,
all instructions except for Read Status Register will be ignored until the program or erase cycle has
completed.
8.1 Device ID and Instruction Set Tables
Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
EFh
(ID15 - ID0)
9Fh
Device ID
(ID7 - ID0)
ABh, 90h, 92h, 94h
16h
Instruction
W25Q64JV-IM/JM
7017
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W25Q64JV-DTR
Instruction Set Table 1 (Standard SPI Instructions)(1)
Data Input Output
Byte 1
Byte 2
8
Byte 3
8
Byte 4
8
Byte 5
8
Byte 6
8
Byte 7
8
Number of Clock(1-1-1)
Write Enable
8
06h
50h
04h
Volatile SR Write Enable
Write Disable
Release Power-down / ID
Manufacturer/Device ID
JEDEC ID
ABh
90h
9Fh
4Bh
Dummy
Dummy
Dummy
Dummy
Dummy
00h
(ID7-ID0)(2)
(MF7-MF0)
(ID7-ID0)
(UID63-0)
(MF7-MF0)
Dummy
(ID15-ID8)
Dummy
(ID7-ID0)
Dummy
Read Unique ID
Dummy
Read Data
03h
0Bh
02h
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
Dummy
D7-D0
Fast Read
(D7-D0)
D7-D0(3)
Page Program
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Chip Erase
20h
52h
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
D8h
C7h/60h
Read Status Register-1
Write Status Register-1(4)
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Read SFDP Register
Erase Security Register(5)
Program Security Register(5)
Read Security Register(5)
Global Block Lock
05h
01h
35h
31h
15h
11h
5Ah
44h
42h
48h
7Eh
98h
3Dh
36h
39h
75h
7Ah
B9h
38h
66h
99h
(S7-S0)(2)
(S7-S0)(4)
(S15-S8)(2)
(S15-S8)
(S23-S16)(2)
(S23-S16)
00h
00h
A7–A0
A7-A0
A7-A0
A7-A0
dummy
(D7-0)
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
D7-D0(3)
Dummy
(D7-D0)
Global Block Unlock
Read Block Lock
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(L7-L0)
Individual Block Lock
Individual Block Unlock
Erase / Program Suspend
Erase / Program Resume
Power-down
Enter QPI Mode
Enable Reset
Reset Device
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
Instruction Set Table 2 (Dual/Quad SPI Instructions)(1)
Data Input Output
Number of Clock(1-1-2)
Byte 1
8
Byte 2
8
Byte 3
8
Byte 4
8
Byte 5
4
Byte 6
4
Byte 7
4
Byte 8
4
Byte 9
4
Fast Read Dual Output
Number of Clock(1-2-2)
Fast Read Dual I/O
3Bh
8
A23-A16
4
A15-A8
4
A7-A0
4
Dummy
4
Dummy
4
(D7-D0)(7)
…
4
4
4
2
BBh
92h
8
A23-A16(6)
A23-A16(6)
8
A15-A8(6)
A15-A8(6)
8
A7-A0(6)
00(6)
8
M7-M0
(D7-D0)(7)
…
Mftr./Device ID Dual I/O
Number of Clock(1-1-4)
Quad Input Page Program
Fast Read Quad Output
Number of Clock(1-4-4)
Dummy(14) (MF7-MF0) (ID7-ID0)(7)
2
2
2
2
32h
6Bh
8
A23-A16
A23-A16
2(8)
A15-A8
A15-A8
2(8)
A7-A0
A7-A0
2(8)
(D7-D0)(9)
Dummy
2
(D7-D0)(3)
Dummy
2
…
Dummy
Dummy
(D7-D0)(10)
2
2
2
Mftr./Device ID Quad I/O
Fast Read Quad I/O
Set Burst with Wrap
94h
EBh
77h
A23-A16
A23-A16
Dummy
A15-A8
A15-A8
Dummy
00
Dummy(14)
M7-M0
Dummy
Dummy
Dummy
Dummy
(MF7-MF0)
(D7-D0)
(ID7-ID0)
A7-A0
Dummy
…
W7-W0
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W25Q64JV-DTR
Instruction Set Table 3 (QPI Instructions)(11)
Data Input Output
Byte 1
Byte 2
2
Byte 3
2
Byte 4
2
Byte 5
2
Byte 6
2
Byte 7
2
Number of Clock (4-4-4)
2
Write Enable
06h
50h
04h
Volatile SR Write Enable
Write Disable
Release Power-down / ID
Manufacturer/Device ID
JEDEC ID
ABh
90h
9Fh
C0h
Dummy
Dummy
Dummy
Dummy
Dummy
00h
(ID7-ID0)(2)
(MF7-MF0)
(ID7-ID0)
(MF7-MF0)
P7-P0
(ID15-ID8)
(ID7-ID0)
Set Read Parameters
Fast Read
0Bh
0Ch
EBh
02h
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
Dummy(12)
Dummy(12)
M7-M0(12)
D7-D0(9)
(D7-D0)
(D7-D0)
(D7-D0)
D7-D0(3)
…
…
…
…
Burst Read with Wrap(13)
Fast Read Quad I/O
Page Program
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Chip Erase
20h
52h
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
D8h
C7h/60h
Read Status Register-1
Write Status Register-1
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Global Block Lock
05h
01h
35h
31h
15h
11h
7Eh
98h
3Dh
36h
39h
75h
7Ah
B9h
66h
99h
FFh
(S7-S0)(2)
(S7-S0)(4)
(S15-S8)(2)
(S15-S8)
(S23-S16)(2)
(S23-S16)
Global Block Unlock
Read Block Lock
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(L7-L0)
Individual Block Lock
Individual Block Unlock
Erase / Program Suspend
Erase / Program Resume
Power-down
Enable Reset
Reset Device
Exit QPI Mode
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
Instruction Set Table 4 (DTR with SPI Instructions)
Data Input Output
Number of Clock(1-1-1)
DTR Fast Read
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
8
0Dh
8
4
A23-A16
2
4
A15-A8
2
4
A7-A0
2
6
Dummy
6
4
(D7-D0)
2
4
…
2
Number of Clock(1-2-2)
M7-M0
Dummy
DTR Fast Read Dual I/O
Number of Clock(1-4-4)
DTR Fast Read Quad
BDh
8
A23-A16
1
A15-A8
1
A7-A0
1
(D7-D0)
1
….
1
8
M7-M0
Dummy
EDh
A23-A16
A15-A8
A7-A0
(D7-D0)
….
Instruction Set Table 5 (DTR with QPI Instructions)
Data Input Output
Number of Clock (4-4-4)
DTR Read with Wrap(13)
DTR Fast Read
Byte 1
2
Byte 2
1
Byte 3
1
Byte 4
1
Byte 5
8
Byte 6
1
Byte 7
1
0Eh
0Dh
A23-A16
A23-A16
A15-A8
A15-A8
A7-0
A7-A0
Dummy
Dummy
(D7-D0)
(D7-D0)
…
…
M7-M0
Dummy
DTR Fast Read
EDh
A23-A16
A15-A8
A7-A0
(D7-D0)
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W25Q64JV-DTR
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.5.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
Set Burst with Wrap input format:
IO0 = x, x, x, x, x, x, W4, x
IO1 = x, x, x, x, x, x, W5, x
IO2 = x, x, x, x, x, x, W6, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
IO3 = x, x, x, x, x, x, x,
x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. QPI Command, Address, Data input/output format:
CLK # 0
1
2
3
4
5
6
7
8
9
10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
12. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is
controlled by read parameter P7 – P4.
13. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.
14. The first dummy is M7-M0 should be set to Fxh.
Publication Release Date: March 27, 2018
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Revision J
W25Q64JV-DTR
8.2 Instruction Descriptions
Write Enable (06h)
The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase,
Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable
instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on
the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instruction
06h
CLK
IO0
IO1
IO2
IO3
Instruction (06h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for
Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid
for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instruction
50h
CLK
IO0
IO1
IO2
IO3
Instruction (50h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)
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W25Q64JV-DTR
Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a
0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI
pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instruction
04h
CLK
IO0
IO1
IO2
IO3
Instruction (04h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2
or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure
8. Refer to section 7.1 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle
is complete and if the device can accept another instruction. The Status Register can be read continuously,
as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (05h/35h/15h)
High Impedance
DI
(IO0)
Status Register-1/2/3 out
Status Register-1/2/3 out
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
*
*
*
Figure 8a. Read Status Register Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
CLK
Instruction
05h/35h/15h
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
SR-1/2/3
out
SR-1/2/3
out
Figure 8b. Read Status Register Instruction (QPI Mode)
- 31 -
W25Q64JV-DTR
Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register
bits include: SRP, SEC, TB, BP[2:0] in Status Register-1; CMP, LB[3:1], QE, SRL in Status Register-2;
HOLD/RST, DRV1, DRV0, and WPS in Status Register-3. All other Status Register bit locations are read-
only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once
it is set to 1, it cannot be cleared to 0.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code
“01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
SRL and LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon
power off or the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost,
and the non-volatile Status Register bit values will be restored.
During non-volatile Status Register write operation (06h combined with 01h/31h/11h), after /CS is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See AC
Characteristics). While the Write Status Register cycle is in progress, the Read Status Register instruction
may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status
Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. After the
Write Status Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be
cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after /CS is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter
and operate in the QPI mode.
Refer to section 7.1 for Status Register descriptions.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Register-1/2/3 in
Mode 3
Mode 0
CLK
Instruction
(01h/31h/11h)
DI
(IO0)
7
6
5
4
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 9a. Write Status Register-1/2/3 Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
Mode 3
Mode 0
CLK
Instruction
01/31/11h
SR1/2/3
in
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
Figure 9b. Write Status Register-1/2/3 Instruction (QPI Mode)
- 33 -
W25Q64JV-DTR
The W25Q64JV is also backward compatible to Winbond’s previous generations of serial flash memories,
in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)” command.
To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth
bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after the eighth clock, the Write
Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not
be affected (Previous generations will clear CMP and QE bits).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
CLK
Instruction (01h)
Status Register 1 in
Status Register 2 in
DI
(IO0)
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
*
*
High Impedance
DO
(IO1)
= MSB
*
Figure 9c. Write Status Register-1/2 Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
Mode 3
Mode 0
CLK
Instruction
01h
SR1 in
SR2 in
4
5
6
7
0
1
2
3
12
8
9
IO0
IO1
IO2
IO3
13
14 10
15 11
Figure 9d. Write Status Register-1/2 Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as the
clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR
(see AC Electrical Characteristics).
The Read Data (03h) instruction is only supported in Standard SPI mode.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (03h)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
Data Out 1
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
= MSB
*
*
Figure 14. Read Data Instruction (SPI Mode only)
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W25Q64JV-DTR
Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24-bit address as shown in Figure 16. The dummy clocks allow the devices internal circuits
additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is
a “don’t care”.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (0Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
DI
(IO0)
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 16a. Fast Read Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
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W25Q64JV-DTR
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range
of applications with different needs for either maximum Fast Read frequency or minimum data access
latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be
configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset
instruction is 2.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
CLK
Instruction
0Bh
IOs switch from
Input to Output
A23-16
A15-8
A7-0
Dummy*
20 16 12
21 17 13
8
9
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
* "Set Read Parameters" instruction (C0h) can set
the number of dummy clocks.
Figure 16b. Fast Read Instruction (QPI Mode)
- 37 -
W25Q64JV-DTR
DTR Fast Read (0Dh)
The DTR Fast Read instruction is similar to the Fast Read instruction except that the 24-bit address input
and the data output require DTR (Double Transfer Rate) operation. This is accomplished by adding six
“dummy” clocks after the 24-bit address as shown in Figure 17. The dummy clocks allow the devices internal
circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO
pin is a “don’t care”.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
17 18 19
CLK
Instruction (0Dh)
24-Bit Address
DI
23 22 21 20 19 18
5
4
3
2
1
0
(IO0)
*
High Impedance
DO
(IO1)
= MSB
*
/CS
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
CLK
6 Dummy Clocks
DI
0
(IO0)
Data Out 1
Data Out 2
Data Out 3
High Impedance
DO
(IO1)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
*
*
*
Figure 17a. DTR Fast Read Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 38 -
W25Q64JV-DTR
DTR Fast Read (0Dh) in QPI Mode
The DTR Fast Read instruction is also supported in QPI mode.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
11 12
13
14
CLK
Instruction
0Dh
8 Dummy
Clocks
IOs switch from
Input to Output
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
7
7
7
*
*
Byte 1
*
Byte 2
*
Byte 3
= MSB
*
Figure 17b. DTR Fast Read Instruction (QPI Mode)
- 39 -
W25Q64JV-DTR
Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to
RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24-bit address as shown in Figure 18. The dummy clocks allow the device's internal circuits
additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”.
However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (3Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
IO0 switches from
Dummy Clocks
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
High Impedance
DO
(IO1)
7
5
3
1
7
7
7
Data Out 1
Data Out 2
Data Out 3
Data Out 4
*
*
*
*
Figure 18. Fast Read Dual Output Instruction (SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 40 -
W25Q64JV-DTR
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Quad Enable (QE) bit in Status Register-
2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read
Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in Figure 20. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
IO0
Instruction (6Bh)
24-Bit Address
23 22 21
3
2
1
0
*
High Impedance
High Impedance
High Impedance
IO1
IO2
IO3
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CLK
IO0 switches from
Dummy Clocks
Input to Output
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
High Impedance
High Impedance
High Impedance
Byte 1
Byte 2
Byte 3
Byte 4
Figure 20. Fast Read Quad Output Instruction (SPI Mode only)
- 41 -
W25Q64JV-DTR
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution
(XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 22a. The upper nibble of
the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 22b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return
the device to normal operation.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (BBh)
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 22a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 10, SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 42 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 22b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)
- 43 -
W25Q64JV-DTR
DTR Fast Read Dual I/O (BDh)
The DTR Fast Read Dual I/O (BDh) instruction allows for improved random access while maintaining two
IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to
input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
DTR Fast Read Dual I/O with “Continuous Read Mode”
The DTR Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 23a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 23b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh/FFFFFh on IO0 for the next instruction (16/20 clocks), to ensure M4 = 1
and return the device to normal operation.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CLK
Instruction (BDh)
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
15
16
17
18
19
20
21
22
23
24
25
26
27
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
DO
(IO1)
7
3
1
7
7
7
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 23a. DTR Fast Read Dual I/O (Initial instruction or previous M5-410, SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 44 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
CLK
A23-16
A15-8
A7-0
M7-0
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
6
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
7
5
3
*
*
= MSB
*
/CS
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
DO
(IO1)
7
3
1
7
7
7
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 23b. DTR Fast Read Dual I/O (Previous instruction set M5-4=10, SPI Mode only)
- 45 -
W25Q64JV-DTR
Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clocks
are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit
(QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 24a. The upper nibble of
the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 24b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the
device to normal operation.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy
Dummy
Instruction (EBh)
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
5
6
7
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
Byte 3
Figure 24a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, SPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 46 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy
Dummy
20 16 12
8
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
21 17 13
9
5
6
7
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
Byte 3
Figure 24b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can either
enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. Refer to section 8.2.37 for detail descriptions.
- 47 -
W25Q64JV-DTR
DTR Fast Read Quad I/O (EDh)
The DTR Fast Read Quad I/O (EDh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
DTR Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23/A31-0), as shown in Figure 27a. The upper nibble
of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or
exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However,
the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 27b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFh/3FFh on IO0 for the next instruction (8/10 clocks), to ensure M4 = 1 and
return the device to normal operation.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
17 18
19
20
CLK
IOs switch from
Input to Output
7 Dummy
Clocks
A23-16
A15-8
A7-0
M7-0
Instruction (EDh)
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO0
IO1
IO2
IO3
5
6
7
5
6
22 18 14 10
23 19 15 11
7
7
7
7
= MSB
*
*
*
Byte 1
*
Byte 2
*
Byte 3
*
Figure 27a. DTR Fast Read Quad I/O (Initial instruction or previous M5-410, SPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 48 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
10
11
12
CLK
IOs switch from
Input to Output
7 Dummy
Clocks
A23-16
A15-8
A7-0
M7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO0
IO1
IO2
IO3
5
6
7
5
6
22 18 14 10
23 19 15 11
7
7
7
7
*
*
*
Byte 1
*
Byte 2
*
Byte 3
= MSB
*
Figure 27b. Fast Read Quad I/O (Previous instruction set M5-4=10, SPI Mode)
DTR Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EDh. The “Set Burst with Wrap” (77h) command can either
enable or disable the “Wrap Around” feature for the following EDh commands. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. Refer to section 8.2.37 for detail descriptions.
- 49 -
W25Q64JV-DTR
DTR Fast Read Quad I/O (EDh) in QPI Mode
The DTR Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. In QPI
mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting,
the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 8.3.37 for details.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
11 12
13
14
CLK
Instruction
EDh
7 Dummy
Clocks
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO0
IO1
IO2
IO3
5
6
7
5
6
22 18 14 10
23 19 15 11
7
7
7
7
*
*
*
Byte 1
*
Byte 2
*
Byte 3
= MSB
*
Figure 27c. DTR Fast Read Quad I/O (Initial instruction or previous M5-410, QPI Mode)
3
Publication Release Date: March 27, 2018
Revision J
- 50 -
W25Q64JV-DTR
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 27d. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction
to accommodate a wide range of applications with different needs for either maximum Fast Read frequency
or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of
dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power
up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered
as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits
immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 8.2.37 for details.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
Instruction
EBh
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0*
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
5
6
7
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
Byte 3
* "Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Figure 27d. Fast Read Quad I/O Instruction (Initial instruction or previous M5-410, QPI Mode)
- 51 -
W25Q64JV-DTR
Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read
Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within
a 256-byte page. Certain applications can benefit from this feature and improve the overall system code
execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure 28. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
Wrap Around
W4 =1 (DEFAULT)
W6, W5
Wrap Length
Wrap Around
Wrap Length
0
0
Yes
8-byte
No
N/A
0
1
1
1
0
1
Yes
Yes
Yes
16-byte
32-byte
64-byte
No
No
No
N/A
N/A
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” instructions
will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around”
function and return to normal read operation, another Set Burst with Wrap instruction should be issued to
set W4 = 1. The default value of W4 upon power on or after a software/hardware reset is 1.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation
with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode
and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 8.1.39 and 8.1.40 for
details.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
CLK
don't
care
don't
care
don't
care
Wrap Bit
Instruction (77h)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
w4
w5
w6
X
X
X
X
X
IO0
IO1
IO2
IO3
X
X
X
X
X
X
X
X
X
Figure 28. Set Burst with Wrap Instruction (SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 52 -
W25Q64JV-DTR
Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least
one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction while
data is being sent to the device. The Page Program instruction sequence is shown in Figure 29.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks cannot exceed the remaining page
length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page
and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block
Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (02h)
24-Bit Address
Data Byte 1
DI
(IO0)
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
*
*
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
CLK
Data Byte 2
Data Byte 3
Data Byte 256
DI
(IO0)
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
*
Figure 29a. Page Program Instruction (SPI Mode)
- 53 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13
Mode 3
Mode 0
CLK
Instruction
02h
A23-16
A15-8
A7-0
Byte1
Byte 2
Byte 3
Byte 255 Byte 256
20 16 12
21 17 13
8
9
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
5
6
7
5
6
7
5
6
7
22 18 14 10
23 19 15 11
Figure 29b. Page Program Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 54 -
W25Q64JV-DTR
Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable (QE) bit in Status Register-2 must be set to 1. A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must
be held low for the entire length of the instruction while data is being sent to the device. All other functions
of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction
sequence is shown in Figure 30.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
IO0
Instruction (32h)
24-Bit Address
23 22 21
3
2
1
0
*
IO1
IO2
IO3
= MSB
*
/CS
31 32 33 34 35 36 37
Mode 3
Mode 0
CLK
Byte
253
Byte
254
Byte
255
Byte
256
Byte 1
Byte 2
Byte 3
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
5
6
5
6
7
7
7
7
7
7
7
*
*
*
*
*
*
*
Figure 30. Quad Input Page Program Instruction (SPI Mode only)
- 55 -
W25Q64JV-DTR
Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0). The Sector Erase
instruction sequence is shown in Figure 31a & 31b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction
will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (20h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 31a. Sector Erase Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction
20h
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Figure 31b. Sector Erase Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 56 -
W25Q64JV-DTR
32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase instruction
sequence is shown in Figure 32a & 32b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (52h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 32a. 32KB Block Erase Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction
52h
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Figure 32b. 32KB Block Erase Instruction (QPI Mode)
- 57 -
W25Q64JV-DTR
64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 33a & 33b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (D8h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 33a. 64KB Block Erase Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction
D8h
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Figure 33b. 64KB Block Erase Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 58 -
W25Q64JV-DTR
Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 34.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence
for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress, the Read
Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1
during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept other
instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the Status
Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is protected
by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Instruction
C7h/60h
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
IO0
IO1
IO2
IO3
Instruction (C7h/60h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 34. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)
- 59 -
W25Q64JV-DTR
Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other sectors or
blocks. The Erase/Program Suspend instruction sequence is shown in Figure 35a & 35b.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status
Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program
Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program
operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will
be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the
erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS
”
and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend.
For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is
not issued earlier than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block
that was being suspended may become corrupted. It is recommended for the user to implement system
design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.
/CS
tSUS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (75h)
High Impedance
DI
(IO0)
DO
(IO1)
Accept instructions
Figure 35a. Erase/Program Suspend Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 60 -
W25Q64JV-DTR
/CS
tSUS
Mode 3
Mode 0
0
1
Mode 3
CLK
Mode 0
Instruction
75h
IO0
IO1
IO2
IO3
Accept instructions
Figure 35b. Erase/Program Suspend Instruction (QPI Mode)
- 61 -
W25Q64JV-DTR
Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals
to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1
within 200ns and the Sector or Block will complete the erase operation or the page will complete the
program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will
be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 36a & 36b.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “tSUS” following a previous Resume instruction.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (7Ah)
DI
(IO0)
Resume previously
suspended Program or
Erase
Figure 36a. Erase/Program Resume Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
CLK
Instruction
7Ah
IO0
IO1
IO2
IO3
Resume previously
suspended Program or
Erase
Figure 36b. Erase/Program Resume Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 62 -
W25Q64JV-DTR
Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction
especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The
instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure
37a & 37b.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down /
Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for
securing maximum write protection. The device always powers-up in the normal operation with the standby
current of ICC1.
/CS
tDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (B9h)
DI
(IO0)
Stand-by current
Power-down current
Figure 37a. Deep Power-down Instruction (SPI Mode)
/CS
tDP
Mode 3
Mode 0
0
1
Mode 3
Mode 0
CLK
Instruction
B9h
IO0
IO1
IO2
IO3
Stand-by current
Power-down current
Figure 37b. Deep Power-down Instruction (QPI Mode)
- 63 -
W25Q64JV-DTR
Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low, shifting
the instruction code “ABh” and driving /CS high as shown in Figure 38a & 38b. Release from power-down
will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation
and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID
bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID value
for the W25Q64JV is listed in Manufacturer and Device Identification table. The Device ID can be read
continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is the
same as previously described, and shown in Figure 38c & 38d, except that after /CS is driven high it must
remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will
resume normal operation and other instructions will be accepted. If the Release from Power-down / Device
ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1) the
instruction is ignored and will not have any effects on the current cycle.
/CS
tRES1
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (ABh)
DI
(IO0)
Power-down current
Stand-by current
Figure 38a. Release Power-down Instruction (SPI Mode)
/CS
tRES1
Mode 3
Mode 0
0
1
Mode 3
Mode 0
CLK
Instruction
ABh
IO0
IO1
IO2
IO3
Power-down current
Stand-by current
Figure 38b. Release Power-down Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 64 -
W25Q64JV-DTR
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
tRES2
CLK
Instruction (ABh)
3 Dummy Bytes
DI
(IO0)
23 22
2
1
0
Device ID
*
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
*
= MSB
Power-down current
Stand-by current
*
Figure 38c. Release Power-down / Device ID Instruction (SPI Mode)
/CS
tRES2
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
Mode 3
Mode 0
CLK
Instruction
ABh
IOs switch from
Input to Output
3 Dummy Bytes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
Device ID
Power-down current Stand-by current
Figure 38d. Release Power-down / Device ID Instruction (QPI Mode)
- 65 -
W25Q64JV-DTR
Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and
the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 39. The Device ID values for the W25Q64JV are listed in Manufacturer and Device Identification
table. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (90h)
Address (000000h)
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Mode 3
Mode 0
CLK
DI
(IO0)
0
DO
(IO1)
7
6
5
4
3
2
1
0
Manufacturer ID (EFh)
Device ID
*
Figure 39. Read Manufacturer / Device ID Instruction (SPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 66 -
W25Q64JV-DTR
Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The
instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24-bit
address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock. After
which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on the
falling edge of CLK with most significant bits (MSB) first as shown in Figure 40. The Device ID values for
the W25Q64JV are listed in Manufacturer and Device Identification table. The Manufacturer and Device
IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS
high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
A23-16
A15-8
A7-0 (00h)
M7-0
Instruction (92h)
High Impedance
DI
(IO0)
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
DO
(IO1)
7
5
3
7
5
3
7
5
3
7
5
3
= MSB
*
*
*
*
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
CLK
IOs switch from
Input to Output
DI
(IO0)
0
1
6
4
5
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
DO
(IO1)
7
3
1
7
7
7
MFR ID
(repeat)
Device ID
(repeat)
*
*
*
*
MFR ID
Device ID
Figure 40. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
- 67 -
W25Q64JV-DTR
Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x
speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a
four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input
the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID
are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown
in Figure 41. The Device ID values for the W25Q64JV are listed in Manufacturer and Device Identification
table. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
A7-0
(00h)
IOs switch from
Input to Output
A23-16
A15-8
M7-0
Dummy
Dummy
Instruction (94h)
4
5
6
7
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
High Impedance
High Impedance
High Impedance
5
6
7
5
6
7
5
6
7
MFR ID Device ID
/CS
23 24 25 26 27 28 29 30
Mode 3
Mode 0
CLK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
MFR ID Device ID MFR ID Device ID
(repeat) (repeat) (repeat) (repeat)
Figure 41. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
Publication Release Date: March 27, 2018
- 68 -
Revision J
W25Q64JV-DTR
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each W25Q64JV device. The ID number can be used in conjunction with user software methods to help
prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin
low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64-
bit ID is shifted out on the falling edge of CLK as shown in Figure 42.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (4Bh)
Dummy Byte 1
Dummy Byte 2
DI
(IO0)
High Impedance
DO
(IO1)
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Mode 3
Mode 0
CLK
Dummy Byte 3
Dummy Byte 4
DI
(IO0)
High Impedance
DO
(IO1)
63 62 61
2
1
0
= MSB
64-bit Unique Serial Number
*
*
Figure 42. Read Unique ID Number Instruction (SPI Mode only)
- 69 -
W25Q64JV-DTR
Read JEDEC ID (9Fh)
For compatibility reasons, the W25Q64JV provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low
and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and
two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling
edge of CLK with most significant bit (MSB) first as shown in Figure 43a & 43b. For memory type and
capacity values refer to Manufacturer and Device Identification table.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK
Instruction (9Fh)
High Impedance
DI
(IO0)
Manufacturer ID (EFh)
DO
(IO1)
= MSB
*
/CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3
Mode 0
CLK
DI
(IO0)
Memory Type ID15-8
Capacity ID7-0
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
Figure 43a. Read JEDEC ID Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
Mode 3
Mode 0
CLK
Instruction
9Fh
IOs switch from
Input to Output
12
8
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
13
9
14 10
15 11
ID15-8
EFh
ID7-0
Figure 43b. Read JEDEC ID Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 70 -
W25Q64JV-DTR
Read SFDP Register (5Ah)
The W25Q64JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains
information about device configurations, available instructions and other features. The SFDP parameters
are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified,
but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP
standard initially established in 2010 for PC and other applications, as well as the JEDEC standard
JESD216-serials that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011
(date code 1124 and beyond) support the SFDP feature as specified in the applicable datasheet.
The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required before the
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB)
first as shown in Figure 44. For SFDP register values and descriptions, please refer to the Winbond
Application Note for SFDP Definition Table.
Note 1: A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (5Ah)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(IO0)
0
7
6
5
4
3
2
1
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
*
*
*
Figure 44. Read SFDP Register Instruction Sequence Diagram
- 71 -
W25Q64JV-DTR
Erase Security Registers (44h)
The W25Q64JV offers three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
ADDRESS
A23-16
A15-12
A11-8
A7-0
Security Register #1
Security Register #2
Security Register #3
00h
00h
00h
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
Don’t Care
Don’t Care
Don’t Care
The Erase Security Register instruction sequence is shown in Figure 45. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1
during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register
will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to
section 7.1.8 for detail descriptions).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (44h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 45. Erase Security Registers Instruction (SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 72 -
W25Q64JV-DTR
Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations.
A Write Enable instruction must be executed before the device will accept the Program Security Register
Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin.
The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.
ADDRESS
A23-16
00h
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-8
0 0 0 0
0 0 0 0
0 0 0 0
A7-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00h
00h
The Program Security Register instruction sequence is shown in Figure 46. The Security Register Lock Bits
(LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to
1, the corresponding security register will be permanently locked, Program Security Register instruction to
that register will be ignored (See 7.1.8, 8.2.25 for detail descriptions).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (42h)
24-Bit Address
Data Byte 1
DI
(IO0)
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
*
*
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
CLK
Data Byte 2
Data Byte 3
Data Byte 256
DI
(IO0)
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
*
Figure 46. Program Security Registers Instruction (SPI Mode only)
- 73 -
W25Q64JV-DTR
Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight
“dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin.
After the address is received, the data byte of the addressed memory location will be shifted out on the DO
pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically
incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches
the last byte of the register (byte address FFh), it will reset to address 00h, the first byte of the register, and
continue to increment. The instruction is completed by driving /CS high. The Read Security Register
instruction sequence is shown in Figure 47. If a Read Security Register instruction is issued while an Erase,
Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on
the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR
(see AC Electrical Characteristics).
ADDRESS
A23-16
00h
A15-12
0 0 0 1
0 0 1 0
0 0 1 1
A11-8
0 0 0 0
0 0 0 0
0 0 0 0
A7-0
Security Register #1
Security Register #2
Security Register #3
Byte Address
Byte Address
Byte Address
00h
00h
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (48h)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(IO0)
0
7
6
5
4
3
2
1
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 47. Read Security Registers Instruction (SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 74 -
W25Q64JV-DTR
Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to
configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read
with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read
with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for
various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the Instruction
Table 1-2 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)” instruction.
This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy
clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast Read Quad
I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the device is switched
from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to any 0Bh, EBh or
0Ch instructions.
MAXIMUM
READ FREQ.
(Vcc=2.7-3.0V)
MAXIMUM
READ FREQ.
(Vcc=3.0-3.6V)
DUMMY
CLOCKS
WRAP
LENGTH
P5 – P4
P1 – P0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
2
4
6
8
33MHz
50MHz
80MHz
104MHz
50MHz
80MHz
8-byte
16-byte
32-byte
64-byte
104MHz
133MHz
Note: 4-bytes address alignment for QPI Read: read address start from A1,A0=0,0
/CS
Mode 3
Mode 0
0
1
2
3
Mode 3
Mode 0
CLK
Instruction
C0h
Read
Parameters
P4 P0
IO0
IO1
IO2
IO3
P5 P1
P6 P2
P7 P3
Figure 48. Set Read Parameters Instruction (QPI Mode only)
- 75 -
W25Q64JV-DTR
Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode,
except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap
Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters
(C0h)” instruction.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
CLK
Instruction
0Ch
IOs switch from
Input to Output
A23-16
A15-8
A7-0
Dummy*
20 16 12
21 17 13
8
9
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
Byte 3
* "Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Figure 49. Burst Read with Wrap Instruction (QPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 76 -
W25Q64JV-DTR
DTR Burst Read with Wrap (0Eh)
The “DTR Burst Read with Wrap (0Eh)” instruction provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI mode,
except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap
Length” once the ending boundary is reached.
The “Wrap Length” can be configured by the “Set Read Parameters (C0h)” instruction.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
11 12
13
14
CLK
Instruction
0Eh
8 Dummy
Clocks
IOs switch from
Input to Output
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
7
7
7
*
*
Byte 1
*
Byte 2
*
Byte 3
= MSB
*
Figure 50. DTR Burst Read with Wrap Instruction (QPI Mode only)
- 77 -
W25Q64JV-DTR
Enter QPI Mode (38h)
The W25Q64JV support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad Peripheral
Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time. “Enter QPI (38h)”
instruction is the only way to switch the device from SPI mode to QPI mode.
Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full
backward compatibility with earlier generations of Winbond serial flash memories. See Instruction Set Table
1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable (QE) bit
in Status Register-2 must be set to 1 first, and an “Enter QPI (38h)” instruction must be issued. If the Quad
Enable (QE) bit is 0, the “Enter QPI (38h)” instruction will be ignored and the device will remain in SPI mode.
See Instruction Set Table 3 for all the commands supported in QPI mode.
When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (38h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 51. Enter QPI Instruction (SPI Mode only)
Publication Release Date: March 27, 2018
Revision J
- 78 -
W25Q64JV-DTR
Exit QPI Mode (FFh)
In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”
instruction must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL) and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
CLK
Instruction
FFh
IO0
IO1
IO2
IO3
Figure 52. Exit QPI Instruction (QPI Mode only)
- 79 -
W25Q64JV-DTR
Individual Block/Sector Lock (36h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0]
bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To lock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Lock command must
be issued by driving /CS low, shifting the instruction code “36h” into the Data Input (DI) pin on the rising
edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must be
executed before the device will accept the Individual Block/Sector Lock Instruction (Status Register bit
WEL= 1).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (36h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 53a. Individual Block/Sector Lock Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction
36h
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Figure 53b. Individual Block/Sector Lock Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 80 -
W25Q64JV-DTR
Individual Block/Sector Unlock (39h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0]
bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To unlock a specific block or sector as illustrated in Figure 4d, an Individual Block/Sector Unlock command
must be issued by driving /CS low, shifting the instruction code “39h” into the Data Input (DI) pin on the
rising edge of CLK, followed by a 24-bit address and then driving /CS high. A Write Enable instruction must
be executed before the device will accept the Individual Block/Sector Unlock Instruction (Status Register
bit WEL= 1).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (39h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 54a. Individual Block Unlock Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction
39h
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Figure 54b. Individual Block Unlock Instruction (QPI Mode)
- 81 -
W25Q64JV-DTR
Read Block/Sector Lock (3Dh)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, SEC, TB, BP[2:0]
bits in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To read out the lock bit value of a specific block or sector as illustrated in Figure 4d, a Read Block/Sector
Lock command must be issued by driving /CS low, shifting the instruction code “3Dh” into the Data Input
(DI) pin on the rising edge of CLK, followed by a 24-bit address. The Block/Sector Lock bit value will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure
55. If the least significant bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the
corresponding block/sector is unlocked, Erase/Program operation can be performed.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
Mode 0
CLK
Instruction (3Dh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
Lock Value Out
High Impedance
DO
(IO1)
X
X
X
X
X
X
X
0
= MSB
*
*
Figure 55a. Read Block Lock Instruction (SPI Mode)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
Mode 3
Mode 0
CLK
Instruction
3Dh
IOs switch from
Input to Output
A23-16
A15-8
A7-0
20 16 12
21 17 13
8
9
4
0
1
2
3
X
X
X
X
0
X
X
X
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Lock
Value
Figure 55b. Read Block Lock Instruction (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 82 -
W25Q64JV-DTR
Global Block/Sector Lock (7Eh)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The command must
be issued by driving /CS low, shifting the instruction code “7Eh” into the Data Input (DI) pin on the rising
edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the device will
accept the Global Block/Sector Lock Instruction (Status Register bit WEL= 1).
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Instruction
7Eh
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
IO0
IO1
IO2
IO3
Instruction (7Eh)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 56. Global Block Lock Instruction for SPI Mode (left) or QPI Mode (right)
Global Block/Sector Unlock (98h)
All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The command
must be issued by driving /CS low, shifting the instruction code “98h” into the Data Input (DI) pin on the
rising edge of CLK, and then driving /CS high. A Write Enable instruction must be executed before the
device will accept the Global Block/Sector Unlock Instruction (Status Register bit WEL= 1).
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
/CS
CLK
Instruction
98h
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
IO0
IO1
IO2
IO3
Instruction (98h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 57. Global Block Unlock Instruction for SPI Mode (left) or QPI Mode (right)
- 83 -
W25Q64JV-DTR
Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the W25Q64JV provide a software
Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going
internal operations will be terminated and the device will return to its default power-on state and lose all the
current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL) status,
Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit setting (M7-
M0) and Wrap Bit setting (W6-W4).
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To
avoid accidental reset, both instructions must be issued in sequence. Any other commands other than
“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
command is accepted by the device, the device will take approximately tRST=30us to reset. During this
period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and the
SUS bit in Status Register before issuing the Reset command sequence.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (66h)
High Impedance
Instruction (99h)
DI
(IO0)
DO
(IO1)
Figure 58a. Enable Reset and Reset Instruction Sequence (SPI Mode)
/CS
Mode 3
Mode 0
0
1
Mode 3
Mode 0
0
1
Mode 3
Mode 0
CLK
Instruction
66h
Instruction
99h
IO0
IO1
IO2
IO3
Figure 58b. Enable Reset and Reset Instruction Sequence (QPI Mode)
Publication Release Date: March 27, 2018
Revision J
- 84 -
W25Q64JV-DTR
9. ELECTRICAL CHARACTERISTICS
(1)
9.1 Absolute Maximum Ratings
PARAMETERS
SYMBOL
VCC
CONDITIONS
RANGE
UNIT
V
Supply Voltage
–0.6 to 4.6
–0.6 to VCC+0.4
Voltage Applied to Any Pin
VIO
Relative to Ground
V
<20nS Transient
Relative to Ground
Transient Voltage on any Pin
VIOT
–2.0V to VCC+2.0V
V
Storage Temperature
TSTG
TLEAD
VESD
–65 to +150
°C
°C
V
Lead Temperature
See Note (2)
Electrostatic Discharge Voltage
Human Body Model(3) –2000 to +2000
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the
European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
SPEC
PARAMETER
SYMBOL CONDITIONS
UNIT
MIN
3.0
MAX
3.6
FR = 133MHz,
VCC
fR = 50MHz
fR = 50MHz
V
V
Supply Voltage(1)
FR = 104MHz,
2.7
3.0
Industrial
TA
–40
–40
+85
+105
°C
°C
Ambient Temperature,
Operating
Industrial Plus
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of
the programming (erase/write) voltage.
- 85 -
W25Q64JV-DTR
9.3 Power-Up Power-Down Timing and Requirements
SPEC
PARAMETER
SYMBOL
UNIT
MIN
20
5
MAX
VCC (min) to /CS Low
tVSL(1)
tPUW(1)
VWI(1)
µs
ms
V
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
1.0
2.0
Note:
1. These parameters are characterized only.
VCC
VCC (max)
Program, Erase and Write Instructions are ignored
/CS must track VCC
VCC (min)
VWI
Read Instructions
Allowed
Device is fully
Accessible
tVSL
Reset
State
tPUW
Time
Figure 58a. Power-up Timing and Voltage Levels
/CS must track VCC
during VCC Ramp Up/Down
VCC
/CS
Time
Figure 58b. Power-up, Power-Down Requirement
Publication Release Date: March 27, 2018
Revision J
- 86 -
W25Q64JV-DTR
9.4 DC Electrical Characteristics-
SPEC
UNIT
PARAMETER
SYMBOL CONDITIONS
MIN
TYP
MAX
(1)
(1)
Input Capacitance
Output Capacitance
Input Leakage
6
pF
pF
µA
µA
CIN
VIN = 0V
(1)
(1)
8
Cout
ILI
VOUT = 0V
±2
±2
I/O Leakage
ILO
/CS = VCC,
VIN = GND or VCC
Standby Current
ICC1
ICC2
10
1
50
15
15
18
20
µA
µA
/CS = VCC,
VIN = GND or VCC
Power-down Current
Current Read Data /
C = 0.1 VCC / 0.9 VCC
DO = Open
ICC3
ICC3
ICC3
8
mA
mA
mA
(2)
Dual /Quad 50MHz
Current Read Data /
Dual /Quad 80MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
10
12
(2)
Current Read Data /
Dual /Quad 104MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
(2)
Current Write Status
Register
ICC4
ICC5
ICC6
/CS = VCC
/CS = VCC
/CS = VCC
/CS = VCC
20
20
20
20
25
25
25
mA
mA
mA
Current Page Program
Current Sector/Block
Erase
Current Chip Erase
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ICC7
VIL
25
mA
V
–0.5
VCC x 0.3
VCC + 0.4
0.2
VIH
VCC x 0.7
V
VOL
VOH
IOL = 100 µA
V
IOH = –100 µA
VCC – 0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V.
2. Checker Board Pattern.
- 87 -
W25Q64JV-DTR
9.5 AC Measurement Conditions
SPEC
UNIT
MAX
PARAMETER
SYMBOL
MIN
Load Capacitance
CL
TR, TF
VIN
30
5
pF
ns
V
Input Rise and Fall Times
Input Pulse Voltages
0.1 VCC to 0.9 VCC
0.3 VCC to 0.7 VCC
0.5 VCC to 0.5 VCC
Input Timing Reference Voltages
Output Timing Reference Voltages
IN
V
OUT
V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Input and Output
Timing Reference Levels
Input Levels
0.9 VCC
0.5 VCC
0.1 VCC
Figure 59. AC Measurement I/O Waveform
Publication Release Date: March 27, 2018
Revision J
- 88 -
W25Q64JV-DTR
9.6 AC Electrical Characteristics (6)
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
TYP
MAX
Clock frequency except for Read Data (03h) &
DTR instructions (3.0V-3.6V)
FR
FR
fC1
fC2
D.C.
133
MHz
MHz
Clock frequency except for Read Data (03h) &
DTR instructions( 2.7V-3.0V)
D.C.
104
FR
FR
fC3
fC4
D.C.
D.C.
D.C.
66
52
50
MHz
MHz
MHz
Clock frequency DTR instructions(3.0V-3.6V)
Clock frequency DTR instructions ( 2.7V-3.0V)
Clock frequency for Read Data instruction (03h)
fR
tCLH,
tCLL
Clock High, Low Time
for all instructions except for Read Data (03h)
45%
PC
ns
ns
(1)
Clock High, Low Time
for Read Data (03h) instruction
tCRLH,
45%
PC
(1)
tCRLL
(2)
Clock Rise Time peak to peak
Clock Fall Time peak to peak
0.1
0.1
V/ns
V/ns
tCLCH
(2)
tCHCL
/CS Active Setup Time relative to CLK
/CS Not Active Hold Time relative to CLK
Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL1
tSHSL2
tCSS
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDSU
tDH
1
Data In Hold Time
2
/CS Active Hold Time relative to CLK
/CS Not Active Setup Time relative to CLK
/CS Deselect Time (for Read)
3
3
tCSH
tCSH
tDIS
10
50
/CS Deselect Time (for Erase or Program or Write)
Output Disable Time
(2)
7
6
tSHQZ
Clock Low to Output Valid
tCLQV
tCLQX
tHLCH
tCHHH
tV
ns
ns
ns
ns
Output Hold Time
tHO
1.5
5
/HOLD Active Setup Time relative to CLK
/HOLD Active Hold Time relative to CLK
5
Continued – next page AC Electrical Characteristics (cont’d)
- 89 -
W25Q64JV-DTR
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
5
TYP
MAX
/HOLD Not Active Setup Time relative to CLK
/HOLD Not Active Hold Time relative to CLK
/HOLD to Output Low-Z
tHHCH
tCHHL
ns
ns
ns
5
(2)
tLZ
7
tHHQX
(2)
/HOLD to Output High-Z
tHZ
12
ns
ns
ns
tHLQZ
(3)
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
20
tWHSL
(3)
100
tSHWL
(2)
/CS High to Power-down Mode
3
3
µs
µs
µs
tDP
(2)
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
tRES1
(2)
1.8
tRES2
(2)
/CS High to next Instruction after Suspend
20
30
µs
tSUS
(2)
/CS High to next Instruction after Reset
/RESET pin Low period to reset the device
Write Status Register Time
µs
µs
tRST
1(4)
(2)
tRESET
tW
10
15
3
ms
ms
Page Program Time
tPP
0.4
Sector Erase Time (4KB)
tSE
45
400
ms
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
tBE1
tBE2
tCE
120
150
20
1,600
2,000
100
ms
ms
s
Notes:
1. Clock high or Clock low must be more than or equal to 45%Pc. Pc=1/fc(max)
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when SRP = 1.
4. It’s possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to ensure
reliable operation.
5. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V, 25% driver
strength.
6. 4-bytes address alignment for QPI/Quad Read: And read address start from Addr [1:0]=(0,0).
Publication Release Date: March 27, 2018
- 90 -
Revision J
W25Q64JV-DTR
Serial Output Timing
/CS
tCLH
CLK
tCLQV
tCLQX
tCLQV
tCLL
tSHQZ
tCLQX
IO
output
MSB OUT
LSB OUT
9.7 Serial Input Timing
/CS
tSHSL
tCHSL
tSLCH
tCHSH
tSHCH
CLK
tDVCH
tCHDX
tCLCH
tCHCL
IO
input
MSB IN
LSB IN
9.8 /HOLD Timing
/CS
tHLCH
tCHHL
tHHCH
CLK
tCHHH
/HOLD
tHLQZ
tHHQX
IO
output
IO
input
9.9 /WP Timing
/CS
tWHSL
/WP
tSHWL
CLK
IO
input
Write Status Register is allowed
Write Status Register is not allowed
- 91 -
W25Q64JV-DTR
10.PACKAGE SPECIFICATIONS
10.1 8-Pin SOIC 208-mil (Package Code SS)
Millimeters
Symbol
Inches
Nom
Min
Nom
Max
Min
Max
A
A1
A2
b
C
D
D1
E
E1
e
H
L
1.75
0.05
1.70
0.35
0.19
5.18
5.13
5.18
5.13
1.95
0.15
1.80
0.42
0.20
5.28
5.23
5.28
5.23
1.27 BSC
7.90
0.65
---
2.16
0.25
1.91
0.48
0.25
5.38
5.33
5.38
5.33
0.069
0.002
0.067
0.014
0.007
0.204
0.202
0.204
0.202
0.077
0.006
0.071
0.017
0.008
0.208
0.206
0.208
0.206
0.050 BSC
0.311
0.026
---
0.085
0.010
0.075
0.019
0.010
0.212
0.210
0.212
0.210
7.70
0.50
---
8.10
0.80
0.10
8°
0.303
0.020
---
0.319
0.031
0.004
8°
y
θ
0°
---
0°
---
Publication Release Date: March 27, 2018
Revision J
- 92 -
W25Q64JV-DTR
10.3 8-Pad WSON 6x5-mm (Package Code ZP)
Millimeters
Symbol
Inches
Min
0.70
0.00
Nom
Max
0.80
0.05
Min
0.028
0.000
Nom
0.030
0.001
Max
0.031
0.002
A
0.75
A1
0.02
b
C
0.35
---
0.40
0.20 REF
6.00
0.48
---
0.014
---
0.016
0.008 REF
0.236
0.019
---
D
5.90
3.35
4.90
4.25
6.10
3.45
5.10
4.35
0.232
0.132
0.193
0.167
0.240
0.136
0.201
0.171
D2
E
3.40
0.134
5.00
0.197
E2
e
4.30
0.169
1.27 BSC
0.050 BSC
L
y
0.55
0.00
0.60
---
0.65
0.022
0.000
0.024
---
0.026
0.003
0.075
Note:
The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be
left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.
- 93 -
W25Q64JV-DTR
10.4 8-Pad WSON 8x6-mm (Package Code ZE)
MILLIMETERS
SYMBOL
INCHES
Min
0.70
0.00
0.35
---
Nom
0.75
Max
0.80
0.05
0.48
---
Min
0.028
0.000
0.014
---
Nom
0.030
Max
0.031
0.002
0.019
---
A
A1
b
0.02
0.001
0.40
0.016
C
0.20 Ref.
8.00
0.008 Ref.
0.315
D
7.90
3.35
5.90
4.25
8.10
3.45
6.10
4.35
0.311
0.132
0.232
0.167
0.319
0.136
0.240
0.171
D2
E
3.40
0.134
6.00
0.236
E2
e
4.30
0.169
1.27 BSC
0.50
0.050 BSC
0.020
L
0.45
0.00
0.55
0.05
0.018
0.000
0.022
0.002
y
---
---
Note:
The metal pad area on the bottom center of the package is not connected to any internal electrical signals. It can be
left floating or connected to the device ground (GND pin). Avoid placement of exposed PCB vias under the pad.
Publication Release Date: March 27, 2018
- 94 -
Revision J
W25Q64JV-DTR
10.6 8-Pad XSON 4x4x0.45-mm (Package Code XG)
- 95 -
W25Q64JV-DTR
10.7 16-Pin SOIC 300-mil (Package Code SF)
Millimeters
Symbol
Inches
Min
2.36
0.10
---
Nom
2.49
---
Max
2.64
0.30
---
Min
0.093
0.004
---
Nom
0.098
---
Max
0.104
0.012
---
A
A1
A2
b
2.31
0.41
0.23
10.31
10.31
7.49
1.27 BSC
0.81
---
0.091
0.016
0.009
0.406
0.406
0.295
0.050 BSC
0.032
---
0.33
0.18
10.08
10.01
7.39
0.51
0.28
10.49
10.64
7.59
0.013
0.007
0.397
0.394
0.291
0.020
0.011
0.413
0.419
0.299
C
D
E
E1
e
L
0.38
---
1.27
0.076
8°
0.015
---
0.050
0.003
8°
y
θ
0°
---
0°
---
Publication Release Date: March 27, 2018
Revision J
- 96 -
W25Q64JV-DTR
10.9 24-Ball TFBGA 8x6-mm (Package Code TB, 5x5 Ball Array)
Note:
Ball land: 0.45mm. Ball Opening: 0.35mm
PCB ball land suggested <= 0.35mm
Millimeters
Inches
Nom
Symbol
Min
---
Nom
---
Max
1.20
0.36
---
Min
---
Max
0.047
0.014
---
A
A1
A2
b
---
0.26
---
0.31
0.010
---
0.012
0.85
0.033
0.35
7.90
0.40
0.45
8.10
0.014
0.311
0.016
0.018
0.319
D
8.00
0.315
D1
E
4.00 BSC
6.00
0.157 BSC
0.236
5.90
6.10
0.10
0.232
0.240
E1
SE
SD
e
4.00 BSC
1.00 TYP
1.00 TYP
1.00 BSC
---
0.157 BSC
0.039 TYP
0.039 TYP
0.039 BSC
---
ccc
---
---
0.0039
- 97 -
W25Q64JV-DTR
10.10 Ordering Information
(1)
(2)
W 25Q 64J V xx I
W
= Winbond
25Q
64J
= SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O
=
64M-bit
V
= 2.7V to 3.6V
SS = 8-pin SOIC 208-mil
ZE = WSON8 8x6-mm
SF = 16-pin SOIC 300-mil
XG = XSON 4x4x0.45-mm
ZP = WSON8 6x5-mm
TB = TFBGA 8x6-mm (5x5 ball array)
I
=
Industrial (-40°C to +85°C)
J
=
Industrial Plus (-40°C to +105°C)
(3,4)
M
=
Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
Notes:
1. The “W” prefix is not included on the part marking.
2. Only the 2nd letter is used for the part marking; WSON package type ZP & ZE are not used for the part marking.
3. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and
Reel (shape T) or Tray (shape S), when placing orders.
4. For shipments with OTP feature, please contact Winbond for details.
Publication Release Date: March 27, 2018
- 98 -
Revision J
W25Q64JV-DTR
10.11 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25Q64JV SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit
Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses
an abbreviated 10-digit number.
PACKAGE TYPE
DENSITY
64M-bit
64M-bit
PRODUCT NUMBER
TOP SIDE MARKING
SS
W25Q64JVSSIM
W25Q64JVSSJM
W25Q64JVSFIM
W25Q64JVSFJM
25Q64JVSIM
25Q64JVSJM
25Q64JVFIM
25Q64JVFJM
SOIC-8 208-mil
SF
SOIC-16 300-mil
ZP
W25Q64JVZPIM
W25Q64JVZPJM
25Q64JVIM
25Q64JVJM
64M-bit
64M-bit
64M-bit
WSON-8 6x5-mm
ZE(1)
WSON-8 8x6-mm
W25Q64JVZEIM
W25Q64JVZEJM
25Q64JVIM
25Q64JVJM
XG
W25Q64JVXGIM
W25Q64JVXGJM
Q64JVXGIM
Q64JVXGJM
XSON-8 4x4-mm
TB(2)
TFBGA-24 8x6-mm
(5x5 Ball Array)
64M-bit
W25Q64JVTBIM
25Q64JVBIM
Note:
1. For WSON packages, the package type ZP and ZE is not used in the top side marking.
2. These package types are special order, please contact Winbond for more information.
- 99 -
W25Q64JV-DTR
11. REVISION JISTORY
VERSION
DATE
PAGE
DESCRIPTION
New Create Preliminary
Removed Preliminary
A
B
C
D
06/11/2013
04/12/2016
05/24/2016
06/14/2016
29,89
9
Updated dummy notice and alignment notice.
Updated block diagram(Removed SFDP)
Updated SRP table
Updated instruction table setting
Removed tSLCH1(DTR)
16
25-28
87
E
2016/10/24
Removed PDIP-8 information & VSOP8 208mil
F
G
H
I
2016/12/21
2017/02/07
2017/02/17
2017/10/02
8,23,69
96
Updated SFDP table
Updated top side marking
Updated USON 4X4 information
Updated TFBGA 5X5 information
4-5,94,96-97
7,97-99
14
Updated SR1 Figure
J
2018/01/12
87,89-90
4,98-99
Updated ICC3, tPP, tSLCH, tCHSL, tDVCH, tCHDX
Added industrial plus information
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems
or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur. Winbond customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document
and the products and services described herein at any time, without notice.
Publication Release Date: March 27, 2018
- 100 -
Revision J
相关型号：
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