W26A02H-70LI [WINBOND]

Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, TSOP2-44;


型号：	W26A02H-70LI
厂家：	WINBOND
描述：	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, TSOP2-44 静态存储器光电二极管内存集成电路
文件：	总11页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary W26A02

´ 16 CMOS STATIC RAM

128K

GENERAL DESCRIPTION

The W26A02 is a normal-speed, very low-power CMOS static RAM organized as 131072 x 16 bits that

operates on a wide voltage range from 1.65V to 1.95V power supply. The W26A02, W26A02-LE and

W26A02-LI, can meet the requirement of various operating temperature. This device is manufactured

using Winbond’s high performance CMOS technology.

FEATURES

· Low power consumption

· Access time: 70 nS

· 1.65V to 1.95V supply voltage

· Fully static operation

· Battery back-up operation capability

· Data retention voltage: 1.0V (min.)

· Data byte control

#LB (I/O1 - I/O8), #UB (I/O9 - I/O16)

· All inputs and outputs directly TTL compatible

· Three-state outputs

· Available packages: 44-pin type two TSOP,

and TFBGA

PIN CONFIGURATIONS

BLOCK DIAGRAM

PRECHARGE CKT.

CLK GEN.

A15

CORE CELL ARRAY

1024 ROWS

#CS

I/O1

I/O2

I/O3

I/O4

VDD

#OE

#UB

#LB

I/O16

I/O15

I/O14

I/O13

V_SS

A14

A16

128 X 16 COLUMNS

A13

I/O1

I/O16

I/O CKT.

COLUMN DECODER

DATA

CNTRL.

CLK

GEN.

VDD

A7 A6 A5

A9 A10 A11 A12

I/O5

I/O6

I/O12

I/O11

I/O10

I/O9

A10

A11

44-pin

TSOP

#WE

#CS

#UB

I/O7

I/O8

#WE

A16

A15

A14

#LB

#OE

A13

A12

PIN DESCRIPTION

SYMBOL

DESCRIPTION

TFBGA TOP VIEW

Address Inputs

Data Inputs/Outputs

A0 - A16

I/O1 - I/O16

#CS

#LB

I/O9

I/O1

#OE

#UB

I/O11

Chip Select Input

Write Enable Input

Lower byte select

Upper byte select

Output Enable Input

Power Supply

#CS

#WE

I/O3

V_DD

V_SS

I/O10

V_SS

V_DD

I/O2

I/O4

I/O5

I/O6

#WE

A16

I/O12

I/O13

I/O14

#LB

#UB

I/O15

A14

I/O7

I/O8

A15

A13

A10

I/O16

A12

#OE

A11

VDD

VSS

Ground

No Connection

Publication Release Date: May 6, 2002

Revision A1

- 1 -

Preliminary W26A02

TRUTH TABLE

VDD

#CS #OE #WE #LB #UB

MODE

I/O1

I/O8

I/O9 - I/O16

CURRENT

ISB, ISB1

IDD

Not Selected

Output Disable

2 Bytes Read

High Z

DOUT

High Z

DOUT

IDD

Lower Byte

Read

DOUT

High Z

IDD

Upper Byte

Read

High Z

DIN

DOUT

DIN

IDD

2 Bytes Write

Lower Byte

Write

DIN

High Z

Upper Byte

Write

High Z

DIN

IDD

Not Selected

High Z

ISB, ISB1

- 2 -

Preliminary W26A02

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

Supply Voltage to VSS Potential

Input/Output to VSS Potential

Allowable Power Dissipation

Storage Temperature

RATING

-0.5 to +2.6

-0.5 to VDD +0.3

1.0

UNIT

-65 to +150

-20 to 85

°C

Operating Temperature

°C

-40 to 85

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

Operating Characteristics

(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)

TEST

W26A02

MAX.

PARAMETER

SYM.

UNIT

CONDITIONS

MIN.

1.65

-0.2

+1.4

-1

Operating Power Voltage

Input Low Voltage

VDD

VIL

VIH

ILI

1.95

+0.4

Input High Voltage

VDD +0.2

Input Leakage Current

VIN = VSS to VDD

VI/O = VSS to VDD; #CS = VIH

(min.) or #OE = VIH (min.)

or #WE = VIL (max.)

Output Leakage Current

ILO

-1

Output Low Voltage

Output High Voltage

VOL

VOH

IOL = +0.1 mA

IOH = -0.1 mA

0.2

1.4

Operating Power Supply

Current

#CS = VIL (max.), I/O = 0 mA;

Cycle = min. Duty = 100%

IDD

ISB

#CS = VIH (min.)

0.3

Standby Power Supply

Current

ISB1

#CS

VDD -0.2V

Publication Release Date: May 6, 2002

Revision A1

- 3 -

Preliminary W26A02

CAPACITANCE

(TA = 25° C, f = 1 MHz)

PARAMETER

SYM.

CIN

CONDITIONS

VIN = 0V

MAX.

UNIT

Input Capacitance

Input/Output Capacitance

CI/O

VOUT = 0V

Note: These parameters are sampled but not 100% tested.

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

CONDITIONS

0V to 1.6V

Input Rise and Fall Times

Input and Output Timing Reference Level

Output Load

5 nS

0.9V

See the drawing below

AC Test Loads and Waveform

1 TTL

OUTPUT

5 pF

30 pF

Including

Jig and

Scope

Including

Jig and

Scope

(For T

)

CLZ, OLZ, CHZ, OHZ, WHZ, OW

1.6V

90%

10%

90%

10%

5 nS

- 4 -

Preliminary W26A02

AC Characteristics, continued

(VSS = 0V; TA (°C) = -20 to 85 for LE, -40 to 85 for LI)

Read Cycle

W26A02

UNIT

PARAMETER

SYMBOL

MIN.

MAX.

Read Cycle Time

TRC

Address Access Time

TAA

Chip Select Access Time

TACS

TAOE

TBA

Output Enable to Output Valid

#UB, #LB Access Tim

Chip Selection to Output in Low Z

Output Enable to Output in Low Z

#UB, #LB Enable to Output in Low Z

Chip Deselection to Output in High Z

Output Disable to Output in High Z

#UB, #LB Disable to Output in High Z

Output Hold from Address Change

*These parameters are sampled but not 100% tested

TCLZ*

TOLZ*

TBLZ*

TCHZ*

TOHZ*

TBHZ*

TOH

Write Cycle

W26A02

PARAMETER

SYMBOL

UNIT

MIN.

MAX.

Write Cycle Time

TWC

TCW

TAW

TBW

TAS

Chip Selection to End of Write

Address Valid to End of Write

#UB, #LB Select to End of Write

Address Setup Time

Write Pulse Width

TWP

TWR

TDW

TDH

Write Recovery Time

#CS, #WE

Data Valid to End of Write

Data Hold from End of Write

Write to Output in High Z

TWHZ*

TOHZ*

TOW

Output Disable to Output in High Z

Output Active from End of Write

*These parameters are sampled but not 100% tested

Publication Release Date: May 6, 2002

Revision A1

- 5 -

Preliminary W26A02

TIMING WAVEFORMS

Read Cycle 1

(Address Controlled)

Address

TAA

TOH

OUT

Read Cycle 2

(Chip Select Controlled, #OE = VIL, #WE= VIH)

Address

#CS

ACS

CHZ

CLZ

#OE

AOE

OHZ

OLZ

#UB / #LB

BHZ

BLZ

HIGH-Z

OUT

- 6 -

Preliminary W26A02

Timing Waveforms, continued

Read Cycle 3

(Output Enable

Controlled)

Address

#OE

TAOE

TOLZ

#CS

OHZ

TACS

TCLZ

CHZ

OUT

Write Cycle 1

(#OE Clock)

Address

#OE

TWR

#CS

#UB/#LB

#WE

TAW

OUT

Publication Release Date: May 6, 2002

Revision A1

- 7 -

Preliminary W26A02

Timing Waveforms, continued

Write Cycle 2

(#OE = VIL Fixed)

Address

#CS

#UB/#LB

#WE

TWP

(2)

(3)

WHZ (1, 4)

OUT

Notes:

1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.

2. The data output from DOUT are the same as the data written to DIN during the write cycle.

3. DOUT provides the read data for the next address.

4. Transition is measured ±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.

- 8 -

Preliminary W26A02

DATA RETENTION CHARACTERISTICS

(TA (°C) = -20 to 85 for LE; -40 to 85 for LI)

PARAMETER

VDD for Data Retention

Data Retention Current

SYM.

VDR

TEST CONDITIONS

#CS ³ VDD -0.2V

MIN.

1.0

TYP. MAX. UNIT

IDDDR

#CS ³ VDD -0.2V, VDD = 1.8V

Chip Deselect to Data

Retention Time

TCDR

See data retention waveform

Operation Recovery Time

TRC*

* Read Cycle Time

DATA RETENTION WAVEFORM

0.9 x VDD

1.0V

VDR

CDR

#CS

VDD -0.2V

#CS

ORDERING INFORMATION

OPERATING

ACCESS

TIME

(nS)

OPERATING VOLTAGE (V)

TEMPERATURE

PART NO.

PACKAGE

TFBGA

STANDBY CURRENT (mA)

(

W26A02B-70LE

W26A02H-70LE

W26A02B-70LI

W26A02H-70LI

Notes:

-20 to 85

-40 to 85

1.8V/5 mA

TSOP(II)

TFBGA

TSOP(II)

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications

where personal injury might occur as a consequence of product failure.

Publication Release Date: May 6, 2002

- 9 -

Revision A1

Preliminary W26A02

PACKAGE DIMENSIONS

44-pin Standard Type Two TSOP

Dimension in inches

Min. Nom. Max. Min. Nom. Max.

Dimension in mm

Symbol

A ²

0.047

1.20

0.002

0.05

0.037 0.039 0.041

0.010 0.014 0.018

0.95

0.25

0.12

1.00 1.05

0.35 0.45

0.005 0.006 0.007

0.15 0.17

0.721 0.725 0.729 18.31 18.41 18.51

0.396 0.400 0.404 10.06 10.16 10.26

0.455 0.463 0.471 11.56 11.76 11.96

0.031

0.016 0.020 0.024 0.40 0.50

0.031 0.80

0.80

0.10 (0.004)

0.60

L ₁

0.004

0.10

TFBGA

- 10 -

Preliminary W26A02

VERSION HISTORY

VERSION

DATE

May 6, 2002

PAGE

DESCRIPTION

Initial Issued

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

2727 North First Street, San Jose,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5665577

200336 China

CA 95134, U.S.A.

TEL: 1-408-9436666

FAX: 1-408-5441798

TEL: 86-21-62365999

FAX: 86-21-62365998

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu Chiu, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

FAX: 81-45-4781800

TEL: 852-27513100

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: May 6, 2002

Revision A1

- 11 -

相关型号：