概述
规格参数
数据手册W27E520S-70 概述
64K X 8 ELECTRICALLY ERASABLE EPROM 64K ×8的电可擦除EPROM EEPROM
W27E520S-70 规格参数
| 是否Rohs认证： | 不符合 | 生命周期： | Obsolete |
| 零件包装代码： | SOIC | 包装说明： | 0.300 INCH, SOP-20 |
| 针数： | 20 | Reach Compliance Code： | not_compliant |
| ECCN代码： | 3A991.B.1.B.2 | HTS代码： | 8542.32.00.51 |
| 风险等级： | 5.92 | 最长访问时间： | 70 ns |
| 命令用户界面： | NO | 数据轮询： | NO |
| JESD-30 代码： | R-PDSO-G20 | JESD-609代码： | e0 |
| 长度： | 12.8 mm | 内存密度： | 524288 bit |
| 内存集成电路类型： | EEPROM | 内存宽度： | 8 |
| 功能数量： | 1 | 端子数量： | 20 |
| 字数： | 65536 words | 字数代码： | 64000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 70 °C |
| 最低工作温度： | 组织： | 64KX8 | |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP20,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 并行/串行： | PARALLEL |
| 峰值回流温度（摄氏度）： | 240 | 电源： | 5 V |
| 编程电压： | 5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 2.67 mm | 最大待机电流： | 0.0001 A |
| 子类别： | EEPROMs | 最大压摆率： | 0.02 mA |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 4.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | COMMERCIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 30 | 切换位： | NO |
| 宽度： | 7.5 mm | Base Number Matches： | 1 |
W27E520S-70 数据手册
通过下载W27E520S-70数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载W27E520
´ 8 ELECTRICALLY ERASABLE EPROM
64K
GENERAL DESCRIPTION
The W27E520 is a high speed, low power Electrically Erasable and Programmable Read Only
´
Memory organized as 65,536 8 bits. It includes latches for the lower 8 address lines to multiplex
with the 8 data lines. To cooperate with the MCU, this device could save the external TTL
component, also cost and space. It requires only one supply in the range of 4.5V to 5.5V in normal
read mode. The W27E520 provides an electrical chip erase function. It will be a great convenient
when you need to change/update the contents in the device.
FEATURES
· High speed access time: 70/90 nS (max.)
· Read operating current: 20 mA (max.)
· Erase/Programming operating current
· High Reliability CMOS Technology
-
-
2K V ESD Protection
200 mA Latchup Immunity
· Fully static operation
30 mA (max.)
m
· Standby current: 100 A (max.)
· All inputs and outputs directly TTL/CMOS
compatible
· Unregulated battery power supply range,
4.5V to 5.5V
· Three-state outputs
· +13V erase and programming voltage
· Available packages: 20-pin TSSOP and 20-pin
SOP
PIN CONFIGURATIONS
BLOCK DIAGRAM
ALE
OE / V
OUTPUT
BUFFER
1
A10
A12
A14
ALE
20
19
18
17
16
15
14
13
12
11
A8
CONTROL
2
AD1
AD3
AD5
AD7
GND
PP
3
4
L
A
T
5
V
DD
TSSOP
Top View
C
H
E
S
AD7 - AD0
6
OE/VPP
A15
MEMORY
ARRAY
DECODER
7
AD6
AD4
AD2
AD0
8
A15 - A8
V
A13
9
A11
10
DD
A9
GND
1
VDD
ALE
A14
A12
A10
A8
OE/VPP
A15
20
19
18
17
2
PIN DESCRIPTION
3
A13
SYMBOL
DESCRIPTION
4
A11
A9
Address/Data Inputs/Outputs
Address Inputs
-
AD0 AD7
5
SOP
Top View
16
15
14
13
12
11
6
-
A8 A15
AD0
7
AD1
AD2
AD4
ALE
Address Latch Enable
Output Enable, Program/Erase
Supply Voltage
8
AD3
AD5
AD7
PP
OE
/V
9
AD6
10
GND
DD
V
Power Supply
GND
Ground
Publication Release Date: September 2000
Revision A2
- 1 -
W27E520
FUNCTIONAL DESCRIPTION
Read Mode
CE
OE
Unlike conventional UVEPROMs, which has
and
two control functions, the W27E520
PP
and one ALE (address_latch_enable) control functions. The ALE makes lower
OE
has one
/V
address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be
used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.
PP
OE
/V controls the output buffer to gate data to the output pins. When addresses are stable, the
ACC
CE
address access time (T
) is equal to the delay from ALE to output (T ), and data are available at
OE
PP
/V , if T
ACC CE
and T timings are met.
OE
the outputs T after the falling edge of
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E520 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
PP
PE
DD
DE
OE
There are two ways to enter Erase mode. One is to raise
/V to V (13V), V
= V (6.5V),
HH
A9 = V (13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed
low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =
2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is
50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when
PP
PP
DD
DP
OE
/V is raised to V (13V), V = V (6.5V), the address pins equal the desired addresses, and
the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down
the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
PP
/V pins, the W27E520 may have common inputs.
OE
ALE and
Standby Mode
DD
PP
/V
OE
The standby mode significantly reduces V current. This mode is entered when ALE and
keep high. In standby mode, all outputs are in a high impedance state.
- 2 -
W27E520
System Considerations
An EPROM's power switching characteristics require careful device decoupling. System designers are
SB
DD
interested in three supply current issues: standby current levels (I ), active current levels (I ), and
transient current peaks produced by the falling and rising edges of ALE Transient current magnitudes
depend on the device output's capacitive and inductive loading. Proper decoupling capacitor selection
m
will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected
DD
between its V and GND. This high frequency, low inherent-inductance capacitor should be placed
m
as close as possible to the device. Additionally, for every eight devices, a 4.7 F electrolytic capacitor
DD
should be placed at the array's power supply connection between V and GND. The bulk capacitor
will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
(VPP = 13V, VPE = 13V, VHH = 12V, VDP = 6.5V, VDE = 6.5V, VDD = 5.0V, VDI = 5.0V, X = VIH or VIL)
MODE
PIN
ALE
OTHER ADDRESS
VDD
AD[7:0]
OE/VPP
IH
IH
IN
DD
Address Latch Enable
Read
V
V
A
V
A[7:0]
IL
V
IL
V
IN
DD
V
OUT
A
D
IL
V
IH
V
DD
V
Output Disable
X
High Z
IH
/V
IH
IH
DD
Standby
Program
Erase 1
V
V
X
V
A[7:0]
IH
V
PP
V
IN
DP
V
IN
A
D
IH
V
PE
V
IL
PE
DE
V
A8&A11 = V , A9 = V
,
X
IH
A10 = V , Others = X
IH
PE
DE
Erase 2
V
V
First command:
Addr. = 5555 (hex)
V
AA(hex)
10(hex)
DA(Hex)
1F(Hex)
DE
V
Second command:
Addr. = 2AAA (hex)
IL
V
IL
IL
HH
DI
V
Product Identifier-
manufacturer
V
A8 = V , A9 = V , Others = X
IL
V
IL
IH
HH
DI
V
Product Identifier-device
V
A8 = V , A9 = V , Others = X
Publication Release Date: September 2000
Revision A2
- 3 -
W27E520
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
-55 to +125
-65 to +150
-2.0 to +7.0
UNIT
Ambient Temperature with Power Applied
Storage Temperature
°
°
C
C
Voltage on all Pins with Respect to Ground Except
V
PP,
DD
OE
/V
A9 and V Pins
-2.0 to +7.0
V
PP
OE
Voltage on
/V Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground
-2.0 to +7.0
V
V
DD
Voltage V Pin with Respect to Ground
-2.0 to +14.0
Notes:
1. Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
2. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 nS. Maximum output pin voltage is
DD
V
+0.75V DC which may overshoot to +7.0V for pulses of less than 20 nS.
DC Erase Characteristics
(TA = 25 C 5 C, VDD = 6.5V 0.25V)
°
± °
±
PARAMETER
SYM.
CONDITIONS
LIMITS
MIN. TYP.
UNIT
MAX.
10
LI
IN
V
IL
IH
Input Load Current
I
= V or V
-10
-
-
-
m
A
DD
V
CP
Erase Current
I
30
mA
IH,
ALE = V
PP
/V = V
PE
OE
IL
PE
,
A8 & A11 = V , A9 = V
IH
A10 = V , Others = X
PP
V
PP
Erase Current
I
-
-
30
mA
IH,
ALE = V
PP PE
/V = V
OE
IL
PE
,
A8 & A11 = V , A9 = V
IH
A10 = V , Others = X
IL
Input Low Voltage
Input High Voltage
V
-
-0.3
2.4
-
-
-
-
0.8
V
V
V
IH
DD
+0.3
V
-
V
OL
OL
Output Low Voltage
(Verify)
V
I
= 2.1 mA
OH
= -0.4 mA
0.45
OH
Output High Voltage
(Verify)
V
I
2.4
-
-
-
HH
A9 SID Voltage
V
11.5
12.75
12.75
6.25
12
13
13
6.5
12.5
13.25
13.25
6.75
V
V
V
V
DD
V
= 5V ±10%
PE
A9 Erase Voltage
V
-
-
-
PP
V
PE
Erase Voltage
V
DD
V
DE
Supply Voltage (Erase
V
& Erase Verify)
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
- 4 -
W27E520
CAPACITANCE
(VDD = 4.5V to 5.5V, TA = 25 C, f = 1 MHz)
°
PARAMETER
Input Capacitance
SYMBOL
MAX.
6
UNIT
pF
IN
C
IN
V = 0V
OUT
C
OUT
V = 0V
Output Capacitance
12
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V/3V
10 nS
Input Rise and Fall Times
Input and Output Timing Reference Level
Output Load
1.5V/1.5V
L
OH OL
C = 100 pF, I /I = -0.4 mA/2.1 mA
AC Test Load and Waveforms
+1.3V
(IN914)
3.3K ohm
D
OUT
100 pF (Including Jig and Scope)
Input
Output
Test Points
Test Points
3V
0V
1.5V
1.5V
Publication Release Date: September 2000
Revision A2
- 5 -
W27E520
READ OPERATION DC CHARACTERISTICS
(VDD = 4.5V to 5.5V, TA = 0 to 70 C)
°
PARAMETER
SYM.
CONDITIONS
LIMITS
MIN. TYP. MAX.
UNIT
LI
IN
DD
Input Load Current
I
I
I
V
V
= 0V to V
-5
-5
-
-
-
-
5
5
m
A
LO
SB
OUT
DD
= 0V to V
Output Leakage Current
m
A
DD
Standby V Current
100
m
A
DD
PP
±
OE
/V
ALE = V
DD
0.3V,
=
(CMOS input)
±
V
0.3V All others inputs
DD
= GND/ V
±
0.3V
DD
DD
IL
IL OUT
ALE = V , I = 0 mA
f = 5 MHz
V
Operating Current
I
-
-
20
mA
Input Low Voltage
Input High Voltage
V
V
-
-0.6
2.0
-
-
0.8
V
V
IH
DD
V
-
+0.3
0.4
-
OL
OL
Output Low Voltage
Output High Voltage
V
I
I
= 2.1 mA
-
-
-
V
V
OH
V
OH
= -0.4 mA
2.4
READ OPERATION AC CHARACTERISTICS
DD
A
(V = 4.5V to 5.5V, T = 0 to 70 C)
°
PARAMETER
SYM.
W27E520-70
W27E520-90
UNIT
MIN.
MAX.
MIN.
MAX.
CE
Address Latch Enable Access Time
Address Latch Enable Width
Address Access Time
T
-
45
-
70
-
-
45
-
90
-
nS
nS
nS
nS
nS
nS
nS
ALE
T
ACC
T
70
-
90
-
AS
T
Address Setup Time
15
15
-
15
15
-
AH
T
Address Hold Time
-
-
OE
T
Output Enable Access Time
35
25
35
25
DF
T
-
-
PP
OE
/V High to High-Z Output
OH
T
Output Hold from Address Change
0
-
0
-
nS
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
- 6 -
W27E520
DC PROGRAMMING CHARACTERISTICS
(VDD = 6.5V 0.25V, TA = 25 C 5 C)
±
°
± °
PARAMETER
SYM.
CONDITIONS
LIMITS
UNIT
MAX.
MIN.
-10
-
TYP.
LI
IN
V
IL
IH
PP
PP
Input Load Current
I
= V or V
-
-
10
30
mA
DD
CP
IH
V
Program Current
I
ALE = V ,
mA
OE PP
/V = V
PP
PP
IH
V
Program Current
I
ALE = V ,
-
-
30
mA
OE PP
/V = V
IL
Input Low Voltage
Input High Voltage
V
-
-
-0.3
2.4
-
-
0.8
V
V
V
V
V
V
V
IH
V
DD
+0.5
V
OL
V
OL
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Silicon I.D. Voltage
PP
I
= 2.1 mA
-
-
0.45
-
OH
V
OH
I
= -0.4 mA
2.4
-
HH
V
11.5
12.75
6.25
12.0
13.0
6.5
12.5
DD
V
= 5V ±10%
PP
V
V
V
Program Voltage
-
-
13.25
6.75
DD
DP
V
Supply Voltage (Program)
AC PROGRAMMING/ERASE CHARACTERISTICS
(VDD = 6.5V 0.25V, TA = 25 C 5 C)
±
°
± °
PARAMETER
SYM.
LIMITS
TYP.
-
UNIT
MIN.
MAX.
PRT
T
50
-
nS
nS
OE PP
/V Pulse Rise Time
Address Latch Enable Width
ALE Program Pulse Width
ALE
T
T
T
T
T
T
T
T
T
T
500
47.5
95
-
50
100
50
100
-
-
PPW
EPW
EPW1
EPW2
LAS
52.5
S
m
ALE Erase Pulse Width
ALE Erase Pulse Width 1
ALE Erase Pulse Width 2
Latched Address Setup Time
Latched Address Hold Time
Address Setup Time
105
mS
47.5
95
52.5
S
m
105
mS
nS
nS
mS
mS
mS
100
100
2.0
0
-
-
-
-
-
LAH
-
AS
-
AH
Address Hold Time
-
OES
2.0
-
OE PP
/V Setup Time
OEH
T
2.0
-
-
mS
mS
OE PP
/V Hold Time
DS
Data Setup Time
Data H old Time
T
T
T
2.0
2.0
-
-
-
-
-
-
DH
mS
nS
EOE
150
OE PP
Data Valid from
Data Valid from
/V Low during Erase Verify
POE
DFP
VS
T
T
T
T
-
-
-
-
-
150
nS
nS
mS
mS
OE PP
/V Low during Program Verify
0
130
OE PP
/V High to Output High Z
2.0
2.0
-
-
OE PP
/V High Voltage Delay After ALE Low
VR
OE PP
/V Recovery Time
DD
PP
PP
Note: V must be applied simultaneously or before V and removed simultaneously or after V .
Publication Release Date: September 2000
Revision A2
- 7 -
W27E520
TIMING WAVEFORMS
AC Read Waveform
V
IH
Address Valid
A8-A15
ALE
V
IL
ALE
T
V
IH
V
IL
CE
T
V
IH
TOE
OE/Vpp
DF
T
V
IL
AS
T
AH
T
OH
T
High Z
High Z
Data
AD0-AD7
Address
ACC
T
Programming Waveform
PROGRAM
PROGRAM (VERIFY)
TAS
TAH
VIH
A[15:8]
Address Stable
VIL
TRPT
13V
VIH
OE/Vpp
TOES
TOEH
VIL
TVR
TVS
VIH
ALE
VIL
TALE
TALE
TPPW
TDFP
TDH
TDS
TPOE
TLAH
TLAS
VIH
AD[7:0]
Add
Data out
Add
Data in
VIL
- 8 -
W27E520
Timing Waveforms, continued
Erase Waveform 1
Read
Device
SID
Read
Company
SID
Chip Erase
Erase (Verify)
VDD = 6.5V
VDD = 6.5V
A9 = 13.0V
V
DD
= 5.0V
A9 = 12.0V
Others = V or V
IL
IH
Others = V
ILor V
IH
VIH
A[15:8]
VIL
A8, A11 = V
IL
Address Valid
A10 = V
A8 = V
IH
A8 = V
IL
IH
VIH
AD[7:0]
Add
TVR
DA
DOUT
1F
TPRT
V IL
13.0V
VIH
TEOE
OE/Vpp
VIL
TOEH
TOES
VIH
ALE
VIL
TEPW
Erase Waveform 2
Read
Device
SID
Read
Chip Erase
Company
Command 1
VDD =6.5V
Command 2
VDD =6.5V
Erase Verify
VDD =6.5V
SID
DD
V
=5.0V
A9=12.0
V
Others=VILor VIH
TAS
VIH
V IL
A[15:8] = 55
A[15:8] = 2A
A[15:8]
OE/Vpp
Address Valid
A8=VIL
IH
A8=V
TRPT
VIH
V IL
TOES
OEH
T
VS
T
TPRT
TEOE
VIH
V IL
ALE
T
EPW1
T
EPW2
T
TOES
LAH
T
TDS
TDH
TLAS
VIH
V IL
AD[7:0]
55
AA
10
AA
DA
1F
Add
DOUT
Note: First command Address = 5555(hex) with Data = AA(hex)
Second command Address = 2AAA(hex) with Data = 10(hex)
Publication Release Date: September 2000
Revision A2
- 9 -
W27E520
SMART PROGRAMMING ALGORITHM 1
Start
Address = First Location
V
DD
= 6.5V
OE/Vpp = 13V
m
Program One 50 S Pulse
Last
Address ?
Increment
Address
No
Yes
Address = First Location
Increment
Address
X = 0
No
Fail
Verify
Byte
Pass
Last
Address ?
Increment X
Yes
No
m
X = 25 ?
Program One 50 S Pulse
Power
Down
V
DD
= 5.0V
OE/Vpp = VIL
Yes
Compare
All Bytes to
Original
Data
Fail
Device
Failed
Pass
Device
Passed
- 10 -
W27E520
SMART PROGRAMMING ALGORITHM 2
Start
Address = First Location
V
DD
= 6.5V
X = 0
m
Program One 50 S Pulse
OE/Vpp = 13V
Increment X
Yes
X = 25?
No
Fail
Fail
Verify One Byte
OE/Vpp = V IL
Verify One Byte
OE/Vpp = V IL
Pass
Pass
No
Increment
Address
Last Address
?
Yes
Power
Down
V
=5.0V
DD
Fail
Compare
All Bytes to
Original
Data
Pass
Device
Device
Failed
Passed
Publication Release Date: September 2000
Revision A2
- 11 -
W27E520
SMART ERASE ALGORITHM 1
Start
X = 0
V = 6.5V
DD
OE/Vpp = 13V
A9 = 13V; A8&A11 = V
IL
A10 = V
IH
Chip Erase 100 mS Pulse
Address = First Location
Increment X
DD
V
= 6.5V
OE/Vpp = VIL
No
X = 20?
Fail
Erase
Verify
Pass
Yes
No
Last
Address?
Increment
Address
Yes
Power
Down
V
DD
= 5.0V
OE/Vpp = V
IL
Compare
All Bytes to
FFs (HEX)
Fail
Pass
Pass
Device
Fail
Device
- 12 -
W27E520
SMART ERASE ALGORITHM 2
Start
X = 0
V
DD
= 6.5V
OE/Vpp = 13V
Program One 50 S Pulse
m
with Address = 5555(Hex) Data = AA(Hex)
Program One 100 mS Pulse
with Address = 2AAA(Hex) Data = 10(Hex)
Increment X
V
DD
= 6.5V
OE/Vpp = V
IL
No
X = 20?
Fail
Erase
Verify
Pass
Last
Yes
No
Increment
Address
Address?
Yes
Power
Down
V
DD
= 5.0V
OE/Vpp = V
IL
Compare
All Bytes to
FFs (HEX)
Fail
Pass
Fail
Device
Pass
Device
Publication Release Date: September 2000
Revision A2
- 13 -
W27E520
ORDERING INFORMATION
PART NO.
ACCESS
TIME
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (mA)
PACKAGE
(nS)
W27E520W-70*
W27E520W-90*
W27E520S-70*
W27E520S-90*
70
90
70
90
20
20
20
20
100
100
100
100
173mil TSSOP
173mil TSSOP
300mil SOP
300mil SOP
Notes:
1. The Part No is preliminary and might be changed after project is consoled.
2. Winbond reserves the right to make changes to its products without prior notice.
3. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 14 -
W27E520
PACKAGE DIMENSIONS
20-pin TSSOP
c
L
b
Dimension in Inches
Dimension in mm
Min. Nom. Max.
1.10
Symbol
Min. Nom. Max.
0.043
A
0.002
0.006
0.05
0.50
6.40
6.25
0.15
1
A
1
E
E
0.020
0.252
0.246
0.169
0.007
0.028
0.70
6.60
6.50
4.48
0.30
0.18
L
0.260
0.256
D
E
0.176 4.30
0.18
1
E
q
e
0.012
0.007 0.09
b
c
e
q
D
0.003
0.65 BSC
0.256 BSC
A
8
0
8
0
1
A
20-pin SOP
c
L
b
Dimension in mm
Dimension in Inches
Min. Nom. Max.
Symbol
Min. Nom. Max.
0.105
0.092
0.003
2.34
2.67
A
0.305
0.076
0.381
12.6
0.012
0.035
0.513
1
A
1
E
E
0.015
0.497
0.393
0.291
0.013
0.889
13.0
L
D
E
0.420 9.98
0.299 7.39
10.7
7.60
1
E
q
e
0.330
0.020
0.013 0.229
1.27 BSC
0.508
0.330
b
c
e
q
D
0.009
0.50 BSC
A
8
0
8
0
1
A
Publication Release Date: September 2000
Revision A2
- 15 -
W27E520
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Jun. 2000
Sep. 2000
-
Initial Issued
Correct Erase Waveform
Modify Address Latch Enable Mode: X -> Ain;
9
3
IL
IL IH
Modify Output Disable Mode: V -> V /V ;
Modify Standby Mode: Ain -> X;
Typo Correction
1
Modify Feature description: LVTTL -> TTL
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
FAX: 886-3-5796096
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change withou t notice.
- 16 -
W27E520S-70 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| W27E520S-90 | WINBOND | 64K X 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27E520W-70 | WINBOND | 64K X 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27E520W-90 | WINBOND | 64K X 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L01 | WINBOND | 128K X 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L01-90 | WINBOND | EEPROM, 128KX8, 90ns, Parallel, CMOS, PDIP32, 0.600 INCH, PLASTIC, DIP-32 | 获取价格 |
|
| W27L010 | WINBOND | 128K ⅴ 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L010-12 | WINBOND | 128K ⅴ 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L010-90 | WINBOND | 128K ⅴ 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L010P-12 | WINBOND | 128K ⅴ 8 ELECTRICALLY ERASABLE EPROM | 获取价格 |
|
| W27L010P-15 | WINBOND | EEPROM, 128KX8, 150ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 | 获取价格 |
|
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