W27L02 [WINBOND]
256K X 8 ELECTRIC ALLY ERASABLE EPROM; 256K ×8 ALLY电可擦除EPROM
| 型号： | W27L02 |
| 厂家： | 
WINBOND |
| 描述： | 256K X 8 ELECTRIC ALLY ERASABLE EPROM |
| 文件： | 总15页 (文件大小：354K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W27L02
256K × 8 ELECTRICALLY ERASABLE EPROM
1. GENERAL DESCRIPTION
The W27L02 is a high speed, low power consumption Electrically Erasable and Programmable Read
Only Memory organized as 262,144 x 8 bits. It requires only one supply in the range of 3.3V ±10% in
normal read mode. The W27L02 provides an electrical chip erase function.
2. FEATURES
• +12V erase/programming voltage
• Fully static operation
• Wide range for power supply voltage:
3.3V ±10%
• High speed access time: 70/90 nS (max.)
• Read operating current: 15 mA (max.)
• All inputs and outputs directly TTL/CMOS
compatible
• Three-state outputs
• Erase/Programming operating current:
30 mA (max.)
• Available packages: 32-lead PLCC and 32-lead
STSOP
• Standby current: 20 µA (max.)
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
VDD
Vss
V
PP
Q0
.
#PGM
#CE
OUTPUT
BUFFER
CONTROL
DECODER
.
#
Q7
#OE
A
1
A
1
6
A
1
2
A
1
5
V
p
p
V
D
D
P
G
M 7
3
2
3
4
3
2
1
3
1
0
A0
.
5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
29
28
27
26
25
24
23
22
21
A14
A13
6
CORE
ARRAY
7
A8
8
A9
32-lead PLCC
9
A11
#OE
A10
#CE
Q7
.
10
11
12
13
A17
1
8
1
9
2
1
7
1
1
5
1
6
0
4
Q
1
Q
2
V
s
Q
3
Q
Q
5
Q
6
4
s
5. PIN DESCRIPTION
1
2
3
4
5
6
7
8
32
A11
A9
A8
A13
A14
A17
#PGM
VDD
VPP
A16
A15
A12
A7
A6
A5
A4
#OE
A10
#CE
Q7
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SYMBOL
A1 − A17
Q0 − Q7
#CE
DESCRIPTION
Q6
Address Inputs
Q5
Q4
Q3
32-lead STSOP
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
V
9
10
SS
Q2
Q1
Q0
11
12
13
14
15
16
A0
A1
A2
A3
#OE
#PGM
VPP
VDD
Vss
Ground
NC
No Connection
Publication Release Date: February 20, 2003
Revision A3
- 1 -
W27L02
6. FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L02 has two control functions and both of these produce data at
the outputs.
#CE is for power control and chip select. #OE controls the output buffer to gate data to the output pins.
When addresses are stable, the address access time (TACC) is equal to the delay from #CE to output
(TCE), and data are available at the outputs TOE after the falling edge of #OE, if TACC and TCE timings
are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an
hour), the W27L02 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an
EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise VPP to VPE (12V), VDD = VCE (5V), #CE low,
#OE high, A9 = VHH (12V), and all other address pins are kept at fixed low or high. Pulsing #PGM low
starts the erase operation. The other way is somewhat like flash, by programming two consecutive
commands into the device and then enter Erase mode. The two commands are loading Data = AA(hex)
to Addr. = 5555(hex) and Data = 10(hex) to Addr. = 2AAA(hex). Be careful to note that the #PGM pulse
widths of these two commands are different: One is 100 µS, while the other is 100 mS. Please refer to
the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase
margin. This mode will be entered after the erase operation if VDD = VPE (5V), #CE low, and #OE low,
#PGM high.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V),
VDD = VCP (5V), #CE low, #OE high, the address pins equal the desired addresses, and the input pins
equal the desired inputs. Pulsing #PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed
with the desired data or not. Hence, after each byte is programmed, a program verify operation should
be performed. The program verify mode automatically ensures a substantial program margin. This mode
will be entered after the program operation if VPP = VPP (12V), #CE low, #OE low, and #PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When #CE high , erasing or programming of non-target chips is inhibited, so that except for the
#CE, the W27L02 may have common inputs.
- 2 -
W27L02
Standby Mode
The standby mode significantly reduces VDD current. This mode is entered when #CE high. In standby
mode, all outputs are in a high impedance state, independent of #OE and #PGM.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L02 provides two control inputs for
multiple memory connections. Two-line control provides for lowest possible memory power dissipation
and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are
concerned with three supply current issues: standby current levels (ISB), active current levels (ICC), and
transient current peaks produced by the falling and rising edges of #CE. Transient current magnitudes
depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling
capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic
capacitor connected between its VDD and Vss. This high frequency, low inherent-inductance capacitor
should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array's power supply connection between VDD and Vss.
The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
Table of Operating Modes
VDD = 3.3V ±10%, Vpp = VpE = VHH = 12V, VCP = VPE = VCE = 5V, X = VIH or VIL
PINS
MODE
OTER
ADDR
#CE
#OE #PGM A0
A9
VDD
VPP
OUTPUTS
Read
VIL
VIL
VIH
VIL
VIH
X
X
X
X
X
X
X
X
X
X
X
X
X
VDD
VDD DOUT
Output Disable
Standby (TTL)
VDD VDD High Z
VDD VDD High Z
VDD
±0.3V
VIL
Standby (CMOS)
X
X
X
X
X
VDD VDD High Z
Program
VIH
VIL
X
VIL
VIH
X
X
X
X
X
X
X
X
X
X
VCP
VCP
VCP
VPP DIN
Program Verify
Program Inhibit
Erase1
VIL
VPP DOUT
VPP High Z
VIH
VIL
VIH
VIL
VIL
VPE
First command:
VCE VPE FF (Hex)
VIL
VIH
VIL
VCE VCP AA (Hex)
Addr. = 5555 (hex)
Erase2
Second command:
VCE VCP 10 (Hex)
Addr. = 2AAA (hex)
Erase Verify
Erase Inhibit
VIL
VIH
VIL
X
VIH
X
X
X
X
X
X
X
VPE
VCE
VPP DOUT
VPE High Z
Product Identifier -
VIL
VIL
X
VIL
VHH
X
VDD VDD DA (Hex)
Manufacturer
Product Identifier -
Device
VIL
VIL
X
VIH
VHH
X
VDD VDD 85 (Hex)
Publication Release Date: February 20, 2003
Revision A3
- 3 -
W27L02
8. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
Operation Temperature
RATING
0 to +70
UNIT
°C
Storage Temperature
-65 to +125
°C
V
Voltage on all Pins with Respect to Ground Except VDD, VPP and A9 Pins -0.5 to VDD +0.5
Voltage on VDD Pin with Respect to Ground
Voltage on VPP Pin with Respect to Ground
Voltage on A9 Pin with Respect to Ground
-0.5 to +7.0
-0.5 to +14.5
-0.5 to +14.5
V
V
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Capacitance
(VDD = 3.3V ±10%, TA = 25° C, f = 1 MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CIN
COUT
CONDITIONS
VIN = 0V
VOUT = 0V
MAX.
6
12
UNIT
pF
pF
Read Operation DC Characteristics
(VDD = 3.3V ±10%, TA = 0 to 70° C)
LIMITS
TYP.
PARAMETER
SYM.
CONDITIONS
UNIT
MIN.
-5
-10
MAX.
5
10
Input Load Current
Output Leakage Current
ILI
ILO
VIN = 0V to VDD
VOUT = 0V to VDD
-
-
µA
µA
Standby VDD Current
ISB
#CE = VIH
-
-
-
-
-
200
20
µA
µA
(TTL input)
Standby VDD Current
(CMOS input)
ISB1
ICC
#CE = VDD ±0.2V
#CE = VIL, IOUT = 0 mA,
f = 5 MHz
VDD Operating Current
-
15
mA
VPP Operating Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VPP Operating Voltage
IPP
VIL
VIH
VOL
VOH
VPP
VPP = VDD
-
-0.3
2.0
-
-
-
-
-
-
10
0.6
VDD +0.5
0.4
µA
V
V
V
V
-
-
IOL = 1.6 mA
IOH = -0.1 mA
-
-
2.4
VDD -0.7
-
VDD
V
- 4 -
W27L02
Electrical Chericteristics, continued
Program/Erase DC Characteristics
(TA = 25° C , VDD = 3.3V ±10%, VHH = 12V)
LIMITS
TYP. MAX.
PARAMETER
Input Load Current
SYM.
CONDITIONS
UNIT
MIN.
-10
ILI
VIN = VIL or VIH
-
10
µA
#CE = VIL, #OE = VIH,
#PGM = VIL
#CE = VIL, #OE = VIH,
#PGM = VIL, A9 = VHH
#CE = VIL, #OE = VIH,
#PGM = VIL
#CE = VIL, #OE = VIH,
#PGM = VIL, A9 = VHH
VDD Program Current
ICP
-
-
-
-
-
30
mA
VDD Erase Current
VPP Program Current
VPP Erase Current
ICE
IPP
IPE
-
-
-
30
30
30
mA
mA
mA
Input Low Voltage
Input High Voltage
VIL
-
-
-0.3
2.4
-
-
-
-
0.8
5.5
0.45
-
12.5
14.25
12.25
14.25
V
V
V
V
V
V
V
V
VIH
VOL
VOH
VID
VID
VPP
VPE
Output Low Voltage (Verify)
Output High Voltage (Verify)
A9 Silicon I.D. Voltage
A9 Erase Voltage
VPP Program Voltage
VPP Erase Voltage
IOL = 2.1 mA
IOH = -0.4 mA
2.4
-
-
-
-
-
11.5
11.75
11.75
11.75
12.0
12.0
12.0
12.0
VDD Supply Voltage
(Program)
VDD Supply Voltage (Erase)
VDD Supply Voltage (Erase
Verify)
VCP
VCE
VPE
-
-
-
4.5
4.5
-
5.0
5.0
5.0
5.5
5.5
-
V
V
V
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
Publication Release Date: February 20, 2003
Revision A3
- 5 -
W27L02
Electrical Chericteristics, continued
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise and Fall Times
CONDITIONS
0V to 3.0V
5 nS
Input and Output Timing Reference Level
1.5V/1.5V
CL = 100 pF, IOH/IOL = -0.1 mA/1.6 mA for Read
IOH/IOL = -0.4 mA/2.1 mA for Program/Erase
Output Load
AC Test Load and Waveforms
+1.3V
(IN914)
3.3K ohm
D
OUT
100 pF (Including Jig and Scope)
Output
Input
Test Points
Test Points
3.0V
0V
1.5V
1.5V
- 6 -
W27L02
Electrical Chericteristics, continued
Read Operation AC Characteristics
(VDD = 3.3V ±10%, TA = 0 to 70° C)
W27L02-70
MIN. MAX.
W27L02-90
PARAMETER
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
#OE High to High-Z Output
Output Hold from Address Change
SYM.
UNIT
MIN.
90
-
MAX.
-
TRC
TCE
TACC
TOE
TDF
TOH
70
-
-
nS
nS
nS
nS
nS
nS
70
70
30
25
-
90
90
40
25
-
-
-
-
-
-
0
-
0
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
AC Programming/Erase Characteristics
(VDD = 3.3V ±10%, TA = 25° C )
LIMITS
PARAMETER
SYM.
UNIT
MIN.
2.0
2.0
2.0
95
95
2.0
2.0
-
TYP.
-
MAX.
VPP Setup Time
TVPS
TAS
-
µS
µS
µS
µS
mS
µS
µS
nS
nS
µS
µS
µS
Address Setup Time
-
-
Data Setup Time
TDS
-
-
#PGM Program Pulse Width
#PGM Erase Pulse Width
Data Hold Time
TPWP
TPWE
TDH
100
105
100
105
-
-
-
-
-
-
-
-
#OE Setup Time
TOES
TOEV
TDFP
TAH
-
Data Valid from #OE
150
130
#OE High to Output High Z
Address Hold Time after #PGM High
Address Hold Time (Erase)
#CE Setup Time
0
0
-
-
-
TAHE
TCES
2.0
2.0
Note: VDD must be applied simultaneously or before VPP and removed simultaneously or after VPP.
Publication Release Date: February 20, 2003
Revision A3
- 7 -
W27L02
9. TIMING WAVEFORMS
AC Read Waveform
V
IH
Address
#CE
Address Valid
V
IL
V
IH
V
IL
TCE
V
IH
#OE
T
DF
V
IL
T
OE
T
OH
T
ACC
High Z
Outputs
Valid Output
High Z
Program Waveform
Program
Verify
Read
Verify
Program
V
IH
Address Stable
Address Valid
Address Stable
Address
Data
V
IL
T
DFP
T
AS
T
ACC
D
D
OUT
D
OUT
OUT
Data In Stable
T
AH
T
DS
T
DH
12.0V
PP
V
5.0V
5.0V
T
VPS
T
CES
V
IH
V
IL
#CE
T
OE
V
IH
#OE
V
IL
T
OES
T
OEV
V
IH
T
PWP
#PGM
V
IL
- 8 -
W27L02
Timing Waveforms, Continued
Erase Waveform 1
Read
Read
Manufacturer
Device
Blank Check
Read Verify
Erase Verify
SID
SID
Chip Erase
A9 = 12.0V
A9 = 12.0V
Others = V
IL
Others = V
IL
V
IH
Address
Stable
A0=V
IH
Address
Stable
Address
Stable
Address
Data
A0 = V
IL
Others=
IL
V
IL
T
AS
T
T
T
AHC
AS
AS
T
ACC
T
DFP
D
OUT
D
85
OUT
D
OUT
DA
Data All One
T
T
DH
T
DS
AH
12.0V
5.0V
T
= VDD
VPS
V
PP
T
CE
V
IH
#CE
V
IL
T
OES
T
OE
T
OE
T
OE
V
IH
#OE
V
IL
T
OEV
T
PWE
T
CES
#PGM
Erase Waveform 2
Read
Read
Manufacturer
SID
Device
Blank Check
Read Verify
Erase Verify
Chip Erase
SID
A9 = 12.0V
Command 1
5555
Command 2
2AAA
Others = V
IL
V
IH
A0=V
IH
Address
Data
Address
Stable
Address
Stable
Address
Stable
A0 = V
IL
Others=
IL
V
IL
T
AS
T
T
AHC
AS
TAS
T
ACC
T
DFP
10
85
AA
D
OUT
D
DA
OUT
D
OUT
T
DH
T
DS
T
AH
12.0V
5.0V
T
VPS
= VDD
V
PP
T
CE
V
IH
#CE
V
IL
T
OES
T
OE
T
OE
T
OE
V
IH
#OE
V
IL
T
CES
T
OEV
T
PWP
T
PWP
#PGM
Publication Release Date: February 20, 2003
Revision A3
- 9 -
W27L02
10. SMART PROGRAMMING ALGORITHM
Start
Address = First Location
VDD = 5V
Vpp = 12V
X = 0
Program One 100 S Pulse
µ
Increment X
Yes
X = 25?
No
Fail
No
Verify
Fail
Verify
One Byte
One Byte
Pass
Pass
Last
Increment
Address
Address?
Yes
VDD = 5V
Vpp = 5V
Compare
Fail
All Bytes to
Original Data
Pass
Fail
Pass
Device
Device
- 10 -
W27L02
11. SMART ERASE ALGORITHM 1
Start
X = 0
VDD = 5V
Vpp = 12V
A9 = 12V; A0 = VIL
Chip Erase 100 mS Pulse
Address = First Location
VDD = 3.0V
Vpp = 3.0V
Increment X
No
Compare
All Bytes to
FFs (HEX)
Fail
X = 20?
Yes
Pass
Pass
Fail
Device
Device
Publication Release Date: February 20, 2003
Revision A3
- 11 -
W27L02
12. SMART ERASE ALGORITHM 2
Start
X = 0
VDD = 5V
Vpp = 12V
Command 100uS Pulse
with Address = 5555(Hex)
Data = AA(Hex)
Command 100mS Pulse
with Address =2AAA(Hex)
Data = 10(Hex)
Address = First Location
VDD = 3.0V
Vpp = 3.0V
Increment X
No
Compare
All Bytes to
FFs (HEX)
Fail
X = 20?
Yes
Pass
Pass
Fail
Device
Device
- 12 -
W27L02
13. ORDERING INFORMATION
PART NO.
ACCESS
POWER SUPPLY
CURRENT MAX.
(mA)
STANDBY VDD
CURRENT MAX.
(µA)
PACKAGE
TIME
(nS)
W27L02P-70
W27L02P-90
W27L02Q-70
W27L02Q-90
70
90
70
90
15
15
15
15
20
20
20
20
32-Lead PLCC
32-Lead PLCC
32-Lead STSOP
32-Lead STSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
Publication Release Date: February 20, 2003
Revision A3
- 13 -
W27L02
14. PACKAGE DIMENSIONS
32-Lead PLCC
H E
E
4
1
32
30
Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Dimension in Inches
Symbol
0.140
A
3.56
5
29
0.020
0.50
A
A
b
1
2
1
0.105
0.026
0.016
0.008
0.110
0.028
0.018
0.010
0.115
0.032
0.022
0.014
2.67
0.66
0.41
0.20
2.80
0.71
2.93
0.81
0.56
0.35
0.46
b
c
D
E
e
0.25
D
G
D
H
0.547
0.447
0.044
0.553
0.453
0.056
13.89
11.35
1.12
14.05
11.51
1.42
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
13.97
11.43
1.27
D
D
0.490
0.390
0.585
0.485
0.530
0.430
0.595
0.495
12.45
9.91
12.95
10.41
14.99
12.45
2.29
13.46
10.92
15.11
12.57
G
G
H
H
L
E
D
E
14.86
12.32
21
13
0.075
0.095
0.004
10
1.91
2.41
0.10
10
y
θ
14
20
c
0
0
Notes:
L
2
A
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based onfinal
visual inspection sepc.
A
1
A
θ
e
b
b 1
Seating Plane
y
G
E
32-Lead STSOP (8 x 14 mm)
Dimension in Inches Dimension in mm
Symbol
HD
D
Max.
1.20
Min. Nom. Max. Min. Nom.
0.047
A
c
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
0.15
1
A
0.040
1.00
0.22
2
A
1.05
0.27
0.007 0.009 0.010
e
b
c
0.004
0.008
-----
12.40
8.00
0.21
-----
0.488
D
E
H
E
0.315
0.551
0.020
b
14.00
D
0.50
0.60
0.80
e
0.50
0.70
0.020 0.024 0.028
0.031
L
1
L
θ
0.000
0.10
5
0.004
5
0.00
0
Y
1 A
2
A
A
L
Y
0
3
3
θ
L
1
- 14 -
W27L02
15. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
Oct. 19, 2001
May 30, 2002
-
10
Initial Issue
Modify Erase Waveform
Correct the Vcv(VPP) as VPE(VPP) under Erase Inhibit
Mode
2, 3, 4, 6
Modify the Pin of VPP from VPE to VPP In the Erase Verify
Mode
3
All
Delete VDD = 5.0V ±10%
A3
Feb. 20, 2003
1, 13, 14 Delete DIP package
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Publication Release Date: February 20, 2003
Revision A3
- 15 -
相关型号：
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