W28F641B_技术文档

W28F641B/T

64MBIT (4MBIT × 16)

PAGE MODE DUAL WORK FLASH MEMORY

Table of Contents-

1. GENERAL DESCRIPTION.................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. PIN CONFIGURATION ....................................................................................................................... 3

4. ELECTRICAL CHARACTERISTICS................................................................................................. 16

Absolute Maximum Ratings* ............................................................................................................ 16

Operating Conditions........................................................................................................................ 16

(1)

Capacitance .................................................................................................................................. 17

AC Input/Output Test Conditions...................................................................................................... 17

DC Characteristics............................................................................................................................ 18

AC Characteristics - Read-only Operations(1)................................................................................. 20

(1, 2)

AC Characteristics - Write Operations

...................................................................................... 23

Reset Operations.............................................................................................................................. 25

Reset AC Specifications................................................................................................................... 25

(3)

Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance ............. 26

5. ADDITIONAL INFORMATION........................................................................................................... 27

Recommended Operating Conditions .............................................................................................. 27

At Device Power-Up ................................................................................................................... 27

Glitch Noises .............................................................................................................................. 28

6. ORDERING INFORMATION............................................................................................................. 29

7. PACKAGE DIMENSIONS ................................................................................................................. 30

48-pin Standard Thin Small Outline Package (measured in millimeters)......................................... 30

48-ball TFBGA (8 mm x 11 mm) (measurements in millimeters)..................................................... 30

8. VERSION HISTORY ......................................................................................................................... 31

Publication Release Date: March 27, 2003

- 1 -

Revision A3

W28F641B/T

1. GENERAL DESCRIPTION

The W28F641, a 4-Plane Page Mode Dual Work (Simultaneous Read while Erase/Program) Flash

memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide

range of applications. The product can be operated at VDD = 2.7V to 3.6V and VPP = 1.65V to 3.6V or

11.7V to 12.3V. Its low voltage operation capability greatly extends battery life for portable

applications.

The W28F641 provides high performance asynchronous page mode. It allows code execution directly

from Flash, thus eliminating time-consuming wait states. Furthermore, the configurative partitioning

architecture allows flexible dual work operation.

The memory array block architecture utilizes Enhanced Data Protection features, and provides

separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and

data storage.

Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP

(One Time Program) block provides an area to store permanent code such as a unique number.

2. FEATURES

• 64M Density with 16Bit I/O Interface

• High-Performance Reads

− One hundred and twenty-seven 32k-word

Main Blocks

− Top or Bottom Parameter Location

− 80/35 nS 8-Word Page Mode

• Configurative 4-Plane Dual Work

− Flexible Partitioning

• Enhanced Data Protection Features

− Individual Block Lock and Block Lock-Down

with Zero-Latency

− Read operations during Block Erase or (Page

− All blocks are locked at power-up or device

Buffer) Program

reset

− Status Register for Each Partition

− Absolute Protection with V_PP≤ V_PPLK

• Low Power Operation

− Block Erase, Full Chip Erase, (Page Buffer)

Word Program Lockout during Power

Transitions

− 2.7V Read and Write Operations

− VDDQ for Input/Output Power Supply Isolation

− Automatic Power Savings Mode Reduces

• Automated Erase/Program Algorithms

ICCR in Static Mode

− 3.0V Low-Power 11 µS/ Word (Typ.)

• Enhanced Code + Data Storage

− 5 µS Typical Erase/Program Suspends

• OTP (One Time Program) Block

− 4-Word Factory-Programmed Area

− 4-Word User-Programmable Area

• High Performance Program with Page Buffer

− 16-Word Page Buffer

− 5 µS/ Word (Typ.) at 12V V_PP

• Operating Temperature

− -40°C to +85°C

• CMOS Process (P-type silicon substrate)

• Flexible Blocking Architecture

− Eight 4k-word Parameter Blocks

Programming

− 12V No Glue Logic 9 µS/ Word (Typ.)

Production Programming and 0.5s Erase

(Typ.)

• Cross-Compatible Command Support

− Common Flash Interface (CFI)

− Basic Command Set

• Extended Cycling Capability

− Minimum 100,000 Block Erase Cycles

• Chip-Size Packaging

− 0.75 mm pitch 48-Ball TFBGA and 48-Pin

TSOP

• ETOX™ Flash Technology

- 2 -

W28F641B/T

* ETOX is a trademark of Intel Corporation.

• No designed or rated as radiation hardened

3. PIN CONFIGURATION

H

C

G

F

E

D

B

A

A19

A4

V_PP

A11

A7

1

2

A8

#WP

A13

A10

A14

#WE

A18

#RESET

A17

A6

A5

A3

A2

A1

0.75 mm pitch

48-Ball TFBGA

Pinout

A12

A9

A20

A21

A15

A16

3

DQ14

DQ5

DQ2

DQ8

DQ9

#CE

A0

DQ11

4

DDQ

V

DQ6

DQ0

DQ1

Vss

5

DQ15

DQ7

DQ12

DQ4

DQ3

#OE

Vss

DQ10

V

DD

DQ13

6

A16

48

A15

A14

A13

A12

A11

A10

1

V

47

46

DDQ

2

Vss

3

DQ15

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

4

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

8 x 11 mm

TOP VIEW

5

6

7

A9

A8

8

A21

A20

9

10

11

12

13

14

15

16

17

18

19

20

48-pin TSOP

#WE

V

Standard Pinout

12mm X 20mm

Top View

DD

#RESET

VPP

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

#WP

A19

A18

A17

A7

A6

A5

A4

A3

A2

A1

#OE

Vss

#CE

A0

21

22

23

24

Figure 1. 0.75 mm pitch TFBGA 48-Ball and 48-Lead TSOP (Normal Bend) Pinout

Publication Release Date: March 27, 2003

Revision A3

- 3 -

W28F641B/T

Table 1. Pin Descriptions

SYMBOL

TYPE

NAME AND FUNCTION

INPUT

A0 − A21

ADDRESS INPUTS: Inputs for addresses. 64M: A0 − A21.

DATA INPUT/OUTPUTS: Inputs data and commands during CUI (Command User

Interface) write cycles, outputs data during memory array, status register, query code,

identifier code and partition configuration register code reads. Data pins float to high

impedance (High Z) when the chip or outputs are deselected. Data is internally

latched during an erase or program cycle.

INPUT/

DQ0 − DQ15

OUTPUT

CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. #CE-high (V_IH) deselects the device and reduces power

consumption to standby levels.

#CE

INPUT

RESET: When low (V_IL), #RESET resets internal automation and inhibits write

operations, which provides data protection. #RESET-high (V_IH) enables normal

operation. After power-up or reset mode, the device is automatically set to read array

mode. #RESET must be low during power-up/down.

#RESET

#OE

#WE

INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data

INPUT

are latched on the rising edge of #CE or #WE (whichever goes high first).

WRITE PROTECT: When #WP is V_IL, locked-down blocks cannot be unlocked. Erase

#WP

INPUT

or program operation can be executed to the blocks which are not locked and not

locked-down. When #WP is V_IH, lock-down is disabled.

MONITORING POWER SUPPLY VOLTAGE: V_PPis not used for power supply pin.

With V_PP≤ V_PPLK, block erase, full chip erase, (page buffer) program or OTP program

cannot be executed and should not be attempted.

Applying 12V ±0.3V to V_PPprovides fast erasing or fast programming mode. In this

mode, V_PPis power supply pin. Applying 12V ±0.3V to V_PPduring erase/program can

only be done for a maximum of 1,000 cycles on each block. V_PPmay be connected to

12V ±0.3V for a total of 80 hours maximum. Use of this pin at 12V beyond these

limits may reduce block cycling capability or cause permanent damage.

V_PP

DEVICE POWER SUPPLY: With V_DD≤ V_LKO, all write attempts to the flash memory

are inhibited. Device operations at invalid V_DDvoltage (see DC Characteristics)

produce spurious results and should not be attempted.

V_DD

SUPPLY

INPUT/OUTPUT POWER SUPPLY (2.7V to 3.6V): Power supply for all input/output

V_DDQ

V_SS

pins.

SUPPLY GROUND: Do not float any ground pins.

- 4 -

W28F641B/T

Table 2. Simultaneous Operation Modes Allowed with Four Planes^(1,2)

THEN THE MODES ALLOWED IN THE OTHER PARTITION IS:

Page

Full

Chip

Erase

Block

Erase

IF ONE

Read Read Read Read

Word

OTP

Block

Program

Suspend

Buffer

PARTITION IS: Array ID/OTP Status Query Program

Program Erase

Program

Suspend

Read Array

X

Read ID/OTP

Read Status

Read Query

Word Program

X

Page Buffer

Program

X

OTP Program

Block Erase

X

Full Chip Erase

Program

Suspend

X

Block Erase

Suspend

X

Notes:

1. "X" denotes the operation available.

2. Configurative Partition Dual Work Restrictions:

Status register reflects partition state, not WSM (Write State Machine) state - this allows a status register for each partition.

Only one partition can be erased or programmed at a time - no command queuing.

Commands must be written to an address within the block targeted by that command.

Publication Release Date: March 27, 2003

- 5 -

Revision A3

W28F641B/T

BLOCK NUMBER

ADDRESS RANGE

1F8000H - 1FFFFFH

1F0000H - 1F7FFFH

1E8000H - 1EFFFFH

1E0000H - 1E7FFFH

1D8000H - 1DFFFFH

1D0000H - 1D7FFFH

1C8000H - 1CFFFFH

1C0000H - 1C7FFFH

1B8000H - 1BFFFFH

1B0000H - 1B7FFFH

1A8000H - 1AFFFFH

1A0000H - 1A7FFFH

198000H - 19FFFFH

190000H - 197FFFH

188000H - 18FFFFH

180000H - 187FFFH

178000H - 17FFFFH

170000H - 177FFFH

168000H - 16FFFFH

160000H - 167FFFH

158000H - 15FFFFH

150000H - 157FFFH

148000H - 14FFFFH

140000H - 147FFFH

138000H - 13FFFFH

130000H - 137FFFH

128000H - 12FFFFH

120000H - 127FFFH

118000H - 11FFFFH

110000H - 117FFFH

108000H - 10FFFFH

100000H - 107FFFH

BLOCK NUMBER ADDRESS RANGE

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

32K-WORD

134 4K-WORD

133 4K-WORD

132 4K-WORD

131 4K-WORD

130 4K-WORD

129 4K-WORD

128 4K-WORD

127 4K-WORD

126 32K-WORD

125 32K-WORD

124 32K-WORD

123 32K-WORD

122 32K-WORD

121 32K-WORD

120 32K-WORD

119 32K-WORD

118 32K-WORD

117 32K-WORD

116 32K-WORD

115 32K-WORD

114 32K-WORD

113 32K-WORD

112 32K-WORD

111 32K-WORD

110 32K-WORD

109 32K-WORD

108 32K-WORD

107 32K-WORD

106 32K-WORD

105 32K-WORD

104 32K-WORD

103 32K-WORD

102 32K-WORD

101 32K-WORD

100 32K-WORD

3FF000H - 3FFFFFH

3FE000H - 3FEFFFH

3FD000H - 3FDFFFH

3FC000H - 3FCFFFH

3FB000H - 3FBFFFH

3FA000H - 3FAFFFH

3F9000H - 3F9FFFH

3F8000H - 3F8FFFH

3F0000H - 3F7FFFH

3E8000H - 3EFFFFH

3E0000H - 3E7FFFH

3D8000H - 3DFFFFH

3D0000H - 3D7FFFH

3C8000H - 3CFFFFH

3C0000H - 3C7FFFH

3B8000H - 3BFFFFH

3B0000H - 3B7FFFH

3A8000H - 3AFFFFH

3A0000H - 3A7FFFH

398000H - 39FFFFH

390000H - 397FFFH

388000H - 38FFFFH

380000H - 387FFFH

378000H - 37FFFFH

370000H - 377FFFH

368000H - 36FFFFH

360000H - 367FFFH

358000H - 35FFFFH

350000H - 357FFFH

348000H - 34FFFFH

340000H - 347FFFH

338000H - 33FFFFH

330000H - 337FFFH

328000H - 32FFFFH

320000H - 327FFFH

318000H - 31FFFFH

310000H - 317FFFH

308000H - 30FFFFH

300000H - 307FFFH

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32K-WORD

0F8000H - 0FFFFFH

0F0000H - 0F7FFFH

0E8000H - 0EFFFFH

0E0000H - 0E7FFFH

0D8000H - 0DFFFFH

0D0000H - 0D7FFFH

0C8000H - 0CFFFFH

0C0000H - 0C7FFFH

0B8000H - 0BFFFFH

0B0000H - 0B7FFFH

0A8000H - 0AFFFFH

0A0000H - 0A7FFFH

098000H - 09FFFFH

090000H - 097FFFH

088000H - 08FFFFH

080000H - 087FFFH

078000H - 07FFFFH

070000H - 077FFFH

068000H - 06FFFFH

060000H - 067FFFH

058000H - 05FFFFH

050000H - 057FFFH

048000H - 04FFFFH

040000H - 047FFFH

038000H - 03FFFFH

030000H - 037FFFH

028000H - 02FFFFH

020000H - 027FFFH

018000H - 01FFFFH

010000H - 017FFFH

008000H - 00FFFFH

000000H - 007FFFH

99

98

97

96

32K-WORD

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

32K-WORD

2F8000H - 2FFFFFH

2F0000H - 2F7FFFH

2E8000H - 2EFFFFH

2E0000H - 2E7FFFH

2D8000H - 2DFFFFH

2D0000H - 2D7FFFH

2C8000H - 2CFFFFH

2C0000H - 2C7FFFH

2B8000H - 2BFFFFH

2B0000H - 2B7FFFH

2A8000H - 2AFFFFH

2A0000H - 2A7FFFH

298000H - 29FFFFH

290000H - 297FFFH

288000H - 28FFFFH

280000H - 287FFFH

278000H - 27FFFFH

270000H - 277FFFH

268000H - 26FFFFH

260000H - 267FFFH

258000H - 25FFFFH

250000H - 257FFFH

248000H - 24FFFFH

240000H - 247FFFH

238000H - 23FFFFH

230000H - 237FFFH

228000H - 22FFFFH

220000H - 227FFFH

218000H - 21FFFFH

210000H - 217FFFH

208000H - 20FFFFH

200000H - 207FFFH

8

7

6

5

4

3

2

1

0

Figure 2.1 Top Parameter Memory Map

- 6 -

W28F641B/T

BLOCK NUMBER

ADDRESS RANGE

3F8000H - 3FFFFFH

3F0000H - 3F7FFFH

3E8000H - 3EFFFFH

3E0000H - 3E7FFFH

3D8000H - 3DFFFFH

3D0000H - 3D7FFFH

3C8000H - 3CFFFFH

3C0000H - 3C7FFFH

3B8000H - 3BFFFFH

3B0000H - 3B7FFFH

3A8000H - 3AFFFFH

3A0000H - 3A7FFFH

398000H - 39FFFFH

390000H - 397FFFH

388000H - 38FFFFH

380000H - 387FFFH

378000H - 37FFFFH

370000H - 377FFFH

368000H - 36FFFFH

360000H - 367FFFH

358000H - 35FFFFH

350000H - 357FFFH

348000H - 34FFFFH

340000H - 347FFFH

338000H - 33FFFFH

330000H - 337FFFH

328000H - 32FFFFH

320000H - 327FFFH

318000H - 31FFFFH

310000H - 317FFFH

308000H - 30FFFFH

300000H - 307FFFH

BLOCK NUMBER

ADDRESS RANGE

1F8000H - 1FFFFFH

1F0000H - 1F7FFFH

1E8000H - 1EFFFFH

1E0000H - 1E7FFFH

1D8000H - 1DFFFFH

1D0000H - 1D7FFFH

1C8000H - 1CFFFFH

1C0000H - 1C7FFFH

1B8000H - 1BFFFFH

1B0000H - 1B7FFFH

1A8000H - 1AFFFFH

1A0000H - 1A7FFFH

198000H - 19FFFFH

190000H - 197FFFH

188000H - 18FFFFH

180000H - 187FFFH

178000H - 17FFFFH

170000H - 177FFFH

168000H - 16FFFFH

160000H - 167FFFH

158000H - 15FFFFH

150000H - 157FFFH

148000H - 14FFFFH

140000H - 147FFFH

138000H - 13FFFFH

130000H - 137FFFH

128000H - 12FFFFH

120000H - 127FFFH

118000H - 11FFFFH

110000H - 117FFFH

108000H - 10FFFFH

100000H - 107FFFH

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

32K-WORD

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

32K-WORD

102 32K-WORD

101 32K-WORD

100 32K-WORD

2F8000H - 2FFFFFH

2F0000H - 2F7FFFH

2E8000H - 2EFFFFH

2E0000H - 2E7FFFH

2D8000H - 2DFFFFH

2D0000H - 2D7FFFH

2C8000H - 2CFFFFH

2C0000H - 2C7FFFH

2B8000H - 2BFFFFH

2B0000H - 2B7FFFH

2A8000H - 2AFFFFH

2A0000H - 2A7FFFH

298000H - 29FFFFH

290000H - 297FFFH

288000H - 28FFFFH

280000H - 287FFFH

278000H - 27FFFFH

270000H - 277FFFH

268000H - 26FFFFH

260000H - 267FFFH

258000H - 25FFFFH

250000H - 257FFFH

248000H - 24FFFFH

240000H - 247FFFH

238000H - 23FFFFH

230000H - 237FFFH

228000H - 22FFFFH

220000H - 227FFFH

218000H - 21FFFFH

210000H - 217FFFH

208000H - 20FFFFH

200000H - 207FFFH

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

32K-WORD

4K-WORD

0F8000H - 0FFFFFH

0F0000H - 0F7FFFH

0E8000H - 0EFFFFH

0E0000H - 0E7FFFH

0D8000H - 0DFFFFH

0D0000H - 0D7FFFH

0C8000H - 0CFFFFH

0C0000H - 0C7FFFH

0B8000H - 0BFFFFH

0B0000H - 0B7FFFH

0A8000H - 0AFFFFH

0A0000H - 0A7FFFH

098000H - 09FFFFH

090000H - 097FFFH

088000H - 08FFFFH

080000H - 087FFFH

078000H - 07FFFFH

070000H - 077FFFH

068000H - 06FFFFH

060000H - 067FFFH

058000H - 05FFFFH

050000H - 057FFFH

048000H - 04FFFFH

040000H - 047FFFH

038000H - 03FFFFH

030000H - 037FFFH

028000H - 02FFFFH

020000H - 027FFFH

018000H - 01FFFFH

010000H - 017FFFH

008000H - 00FFFFH

007000H - 007FFFH

006000H - 006FFFH

005000H - 005FFFH

004000H - 004FFFH

003000H - 003FFFH

002000H - 002FFFH

001000H - 001FFFH

000000H - 000FFFH

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

32K-WORD

8

7

6

5

4

3

2

1

0

Figure 2.2 Bottom Parameter Memory Map

Publication Release Date: March 27, 2003

Revision A3

- 7 -

W28F641B/T

Table 3. Identifier Codes and OTP Address for Read Operation

ADDRESS

[A15 − A0]

DATA

NOTES

CODE

[DQ15 − DQ0]

Manufacture Code

Device Code

Manufacture Code

Top Parameter

0000H

00B0H

00B1H

DQ0 = 0

DQ0 = 1

DQ1 = 0

DQ1 = 1

PCRC

1

1, 2

3

0001H

Bottom Parameter

Block is Unlocked

Block is Locked

3

Block Address

+2

Block Lock Configuration Code

Block is not Locked-Down

Block is Locked-Down

Partition Configuration register

OTP Lock

3

Device Configuration Code

OTP

0006H

0080H

1, 4

1, 5

1, 6

OTP-LK

OTP

0081-0088H

Notes:

1. The address A21 − A16 are shown in below table for reading the manufacturer code, device code, device configuration code

and OTP data.

2. Bottom parameter device has its parameter blocks in the plane0 (The lowest address).

Top parameter device has its parameter blocks in the plane3 (The highest address).

3. Block Address = The beginning location of a block address within the partition to which the Read Identifier Codes/OTP

command (90H) has been written.

DQ15 − DQ2 are reserved for future implementation.

4. PCRC = Partition Configuration Register Code.

5. OTP-LK = OTP Block Lock configuration.

6. OTP = OTP Block data.

Table 4. Identifier Codes and OTP Address for Read Operation on Partition Configuration⁽¹⁾

(2)

PARTITION CONFIGURATION REGISTER

ADDRESS (64M-bit device)

[A21 − A16]

PCR.10

PCR.9

PCR.8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

00H

00H or 10H

00H or 20H

00H or 30H

00H or 10H or 20H

00H or 20H or 30H

00H or 10H or 30H

00H or 10H or 20H or 30H

Notes:

1. The address to read the identifier codes or OTP data is dependent on the partition which is selected when writing the Read

Identifier Codes/OTP command (90H).

2. Refer to Table 12 for the partition configuration register.

- 8 -

W28F641B/T

[A21-A0]

000088H

Customer Programmable Area

Factory Programmed Area

000085H

000084H

000081H

000080H

Reserved for Future Implementation

(DQ15-DQ2)

Customer programmable Area Lock Bit (DQ1)

Factory programmed Area Lock Bit (DQ0)

Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.)

(1, 2)

Table 5. Bus Operations

MODE

Read Array

NOTE #RESET #CE

#OE

V_IL

V_IH

X

#WE

V_IH

X

ADDRESS

V_PP

X

DQ0 − 15

DOUT

6

V_IH

V_IL

V_IH

X

Output Disable

Standby

X

High Z

X

Reset

3

6

X

Read Identifier

Codes/OTP

See

V_IH

V_IL

V_IH

X

Table 3, 4

See

Read Query

Write

6,7

V_IH

V_IL

V_IH

V_IL

X

Appendix

4,5,6

X

DIN

Notes:

1. Refer to DC Characteristics. When V_PP≤ V_PPLK, memory contents can be read, but cannot be altered.

2. X can be V_ILor V_IHfor control pins and addresses, and V_PPLKor V_PPH1/2for V_PP. See DC Characteristics for V_PPLKand V_PPH1/2

voltages.

3. #RESET at V_SS±0.2V ensures the lowest power consumption.

4. Command writes involving block erase, (page buffer) program or OTP program are reliably executed when V_PP= V_PPH1/2and

V_DD= 2.7V to 3.6V.

Command writes involving full chip erase are reliably executed when V_PP= V_PPH1and V_DD= 2.7V to 3.6V.

5. Refer to Table 6 for valid DIN during a write operation.

6. Never hold #OE low and #WE low at the same timing.

7. Refer to Appendix for more information about query code.

Publication Release Date: March 27, 2003

- 9 -

Revision A3

W28F641B/T

Table 6. Command Definitions⁽¹¹⁾

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

COMMAND

NOTE

CYCLES

REQ’D.

(1)

(2)

(1)

(2)

(3)

Oper

Addr

Data Oper

Addr

Data

Read Array

Read Identifier Codes/OTP

Read Query

Read Status Register

Clear Status Register

Block Erase

1

≥ 2

2

1

2

Write

PA

FFH

4

PA

BA

X

90H

98H

70H

50H

20H

30H

Read IA or OA ID or OD

Read

QA

PA

QD

SRD

5

5, 9

Write

BA

X

D0H

Full Chip Erase

2

40H or

Program

2

≥ 4

1

5, 6

5, 7

8, 9

Write

WA

PA

Write

WA

WD

N-1

10H

Page Buffer Program

E8H

B0H

Block Erase and (Page Buffer)

Program Suspend

Block Erase and (Page Buffer)

Program Resume

1

8, 9

Write

PA

D0H

Set Block Lock Bit

Clear Block Lock Bit

Set Block Lock-down Bit

OTP Program

2

Write

BA

OA

60H

C0H

Write

BA

OA

01H

D0H

2FH

OD

10

9

Set Partition configuration

2

Write

PCRC

60H

Write

PCRC

04H

Register

Notes:

1. Bus operations are defined in Table 5.

2. All address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.

X = Any valid address within the device.

PA = Address within the selected partition.

IA = Identifier codes address (See Table 3 and Table 4).

QA = Query codes address. Refer to Appendix for details.

BA = Address within the block being erased, set/cleared block lock bit or set block lock-down bit.

WA = Address of memory location for the Program command or the first address for the Page Buffer Program command.

OA = Address of OTP block to be read or programmed (See Figure 3).

PCRC = Partition configuration register code presented on the address A0 − A15.

3. ID = Data read from identifier codes. (See Table 3 and Table 4).

QD = Data read from query database. Refer to Appendix for details.

SRD = Data read from status register. See Table 10 and Table 11 for a description of the status register bits.

WD = Data to be programmed at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first)

during command write cycles.

OD = Data within OTP block. Data is latched on the rising edge of #WE or #CE (whichever goes high first) during command

write cycles.

N-1 = N is the number of the words to be loaded into a page buffer.

4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock

configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4). The Read

Query command is available for reading CFI (Common Flash Interface) information.

5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block

can be erased or programmed when #RESET is VIH.

6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.

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W28F641B/T

7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid

address within the target block to be programmed and the confirm command (D0H). Refer to Appendix for details.

8. If the program operation in one partition is suspended and the erase operation in other partition is also suspended, the

suspended program operation should be resumed first, and then the suspended erase operation should be resumed next.

9. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted while

the block erase operation is being suspended.

10. Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when #WP is VIL. When #WP is

VIH, lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration.

11. Commands other than those shown above are reserved by Winbond for future device implementations and should not be

used.

Table 7. Functions of Block Lock⁽⁵⁾and Block Lock-Down

CURRENT STATE

ERASE/PROGRAM

(2)

ALLOWED

State

[000]

#WP

DQ1⁽¹⁾

DQ0⁽¹⁾

State Name

Unlocked

Locked

Locked-down

Unlocked

Locked

0

1

0

1

0

1

0

1

0

1

0

1

Yes

No

Yes

No

Yes

No

[001]⁽³⁾

[011]

[100]

[101]⁽³⁾

[110]⁽⁴⁾

[111]

Lock-down Disable

Notes:

1. DQ0 = 1: a block is locked; DQ0 = 0: a block is unlocked.

DQ1 = 1: a block is locked-down; DQ1 = 0: a block is not locked-down.

2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program

operations.

3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [001] (#WP = 0) or [101] (#WP

= 1), regardless of the states before power-off or reset operation.

4. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.

5. OTP (One Time Program) block has the lock function, which is different from those described above.

Table 8. Block Locking State Transitions upon Command Write⁽⁴⁾

CURRENT STATE

RESULT AFTER LOCK COMMAND WRITTEN (NEXT STATE)

(1)

State

[000]

[001]

[011]

[100]

[101]

[110]

[111]

#WP

0

DQ1

0

DQ0

0

1

0

1

0

1

Set Lock

Clear Lock

No Change

[000]

No Change

[100]

No Change

[110]

Set Lock-down

[001]

[011]⁽²⁾

0

No Change⁽³⁾

No Change

[101]

[011]

0

1

No Change

1

0

[111]⁽²⁾

1

0

No Change

[111]

1

[111]⁽²⁾

1

No Change

Publication Release Date: March 27, 2003

Revision A3

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W28F641B/T

Notes:

1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down"

means Set Block Lock-Down Bit command.

2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0 = 0), the corresponding block is locked-

down and automatically locked at the same time.

3. "No Change" means that the state remains unchanged after the command written.

4. In this state transitions table, assumes that #WP is not changed and fixed VIL or VIH.

Table 9. Block Locking State Transitions upon #WP Transition⁽⁴⁾

RESULT AFTER #WP TRANSITION

CURRENT STATE

(NEXT STATE)

PREVIOUS STATE

#WP = 0→1⁽¹⁾

#WP = 1→0⁽¹⁾

State

[000]

[001]

#WP

0

DQ1

0

DQ0

0

1

-

[100]

[101]

-

0

[110]⁽²⁾

[110]

-

Other than [110]⁽²⁾

[111]

-

[011]

0

1

-

[100]

[101]

[110]

[111]

1

0

1

0

1

0

1

-

[000]

[001]

[011]⁽³⁾

[011]

Notes:

1. "#WP = 0→1" means that #WP is driven to VIH and "#WP = 1→0" means that #WP is driven to VIL.

2. State transition from the current state [011] to the next state depends on the previous state.

3. When #WP is driven to VIL in [110] state, the state changes to [011] and the blocks are automatically locked.

4. In this state transitions table, assumes that lock configuration commands are not written in previous, current and next state.

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W28F641B/T

Table 10. Status Register Definition

R

11

R

10

R

9

R

8

15

14

13

BEFCES

5

12

PBPOPS

4

WSMS

7

BESS

6

VPPS

3

PBPSS

2

DPS

1

R

0

NOTES:

SR.15 − SR.8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

Status Register indicates the status of the partition, not WSM

(Write State Machine). Even if the SR.7 is "1", the WSM may

be occupied by the other partition when the device is set to

2, 3 or 4 partitions configuration.

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)

1 = Block Erase Suspended

Check SR.7 to determine block erase, full chip erase, (page

buffer) program or OTP program completion. SR.6 − SR.1

are invalid while SR.7 = "0".

0 = Block Erase in Progress/Completed

If both SR.5 and SR.4 are "1"s after a block erase, full chip

erase, page buffer program, set/clear block lock bit, set block

lock-down bit, set partition configuration register attempt, an

improper command sequence was entered.

SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS

(BEFCES)

1 = Error in Block Erase or Full Chip Erase

0 = Successful Block Erase or Full Chip Erase

SR.3 does not provide a continuous indication of VPP level.

The WSM interrogates and indicates the VPP level only after

Block Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. SR.3 is not guaranteed to

report accurate feedback when VPP ≠ VPPH1, VPPH2 or VPPLK.

SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM

STATUS (PBPOPS)

1 = Error in (Page Buffer) Program or OTP Program

0 = Successful (Page Buffer) Program or OTP Program

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates the block lock bit only after Block

Erase, Full Chip Erase, (Page Buffer) Program or OTP

Program command sequences. It informs the system,

depending on the attempted operation, if the block lock bit is

set. Reading the block lock configuration codes after writing

the Read Identifier Codes/OTP command indicates block

lock bit status.

SR.3 = VPP STATUS (VPPS)

1 = VPP LOW Detect, Operation Abort

0 = VPP OK

SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS

(PBPSS)

1 = (Page Buffer) Program Suspended

0 = (Page Buffer) Program in Progress/Completed

SR.15 − SR.8 and SR.0 are reserved for future use and

should be masked out when polling the status register.

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a Locked Block,

Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

Publication Release Date: March 27, 2003

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Revision A3

W28F641B/T

Table 11. Extended Status Register Definition

R

14

R

13

R

12

R

11

R

10

R

9

R

8

15

SMS

7

R

1

R

0

6

5

4

3

2

NOTES:

XSR.15 − 8 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

After issue a Page Buffer Program command (E8H), XSR.7

= "1" indicates that the entered command is accepted. If

XSR.7 is "0", the command is not accepted and a next

Page Buffer Program command (E8H) should be issued

again to check if page buffer is available or not.

XSR.7 = STATE MACHINE STATUS (SMS)

1 = Page Buffer Program available

0 = Page Buffer Program not available

XSR.15 − 8 and XSR.6 − 0 are reserved for future use and

should be masked out when polling the extended status

register.

XSR.6-0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

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W28F641B/T

Table 12. Partition Configuration Register Definition

R

15

R

14

R

13

R

12

R

11

R

PC2

10

R

PC1

9

PC0

8

R

7

6

5

4

3

2

1

0

111 = There are four partitions in this configuration.

Each plane corresponds to each partition respectively.

Dual work operation is available between any two

partitions.

PCR.15 − 11 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

PCR.10 − 8 = PARTITION CONFIGURATION (PC2-0)

000 = No partitioning. Dual Work is not allowed.

001 = Plane1-3 are merged into one partition.

(default in a bottom parameter device)

010 = Plane 0 − 1 and Plane2 − 3 are merged into one

partition respectively.

PCR.7 − 0 = RESERVED FOR FUTURE

ENHANCEMENTS (R)

100 = Plane 0 − 2 are merged into one partition.

(default in a top parameter device)

NOTES:

011 = Plane 2 − 3 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

After power-up or device reset, PCR10 − 8 (PC2 − 0) is set

to "001" in a bottom parameter device and "100" in a top

parameter device.

110 = Plane 0 − 1 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

See Figure 4 for the detail on partition configuration.

PCR.15 − 11 and PCR.7 − 0 are reserved for future use

and should be masked out when checking the partition

configuration register.

101 = Plane 1 − 2 are merged into one partition.

There are three partitions in this configuration.

Dual work operation is available between any

two partitions.

PC2 PC1 PC0

PARTITIONING FOR DUAL WORK

PARTITION0

PC2 PC1 PC0

PARTITIONING FOR DUAL WORK

PARTITION2 PARTITION1 PARTITION0

0

1

0

1

0

PARTITION1

PARTITION0

PARTITION2PARTITION1

PARTITION0

PARTITION1

PARTITION0

PARTITION2

PARTITION1

PARTITION0

0

1

0

1

0

1

PARTITION3 PARTITION2 PARTITION1 PARTITION0

PARTITION1

PARTITION0

Figure 4. Partition Configuration

Publication Release Date: March 27, 2003

Revision A3

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W28F641B/T

4. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings*

Operating Temperature

(1)

During Read, Erase and Program ..................................................................................... -40°C to +85°C

Storage Temperature

During under Bias ................................................................................................................ -40°C to +85°C

During non Bias ................................................................................................................ .. -65°C to +125°C

Voltage On Any Pin

(2)

(except V_DDand V_PP) ......... .......................................................................................... -0.5V to V_DD+0.5V

(2)

V_DDand V_DDQSupply Voltage................................................................................................. -0.2V to +3.9V

V_PPSupply Voltage..................................................................................................... .... -0.2V to +12.6V

Output Short Circuit Current........................................................................................... ...................100 mA

(2,3,4)

(5)

*WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress

ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond

the "Operating Conditions" may affect device reliability.

Notes:

1. Operating temperature is for extended temperature product defined by this specification.

2. All specified voltages are with respect to V_SS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on V_DDand V_PP

pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins is

V_DD+0.5V, which, during transitions, may overshoot to V_DD+2.0V for periods <20 nS.

3. Maximum DC voltage on V_PPmay overshoot to +13.0V for periods <20 nS.

4. V_PPerase/program voltage is normally 2.7V to 3.6V. Applying 11.7V to 12.3V to V_PPduring erase/program can be done for a

maximum of 1,000 cycles on the main blocks and 1,000 cycles on the parameter blocks. V_PPmay be connected to 11.7V to

12.3V for a total of 80 hours maximum.

5. Output shorted for no more than one second. No more than one output shorted at a time.

Operating Conditions

PARAMETER

Operating Temperature

VDD Supply Voltage

I/O Supply Voltage

VPP Voltage when Used as a Logic Control

VPP Supply Voltage

SYM.

TA

VDD

VDDQ

VPPH1

VPPH2

MIN.

-40

2.7

1.65

TYP.

+25

3.0

MAX.

+85

3.6

UNIT

°C

V

NOTE

1

11.7

12

12.3

V

1, 2

Main Block Erase Cycling: VPP = VPPH1

Parameter Block Erase Cycling: VPP = VPPH1

Main Block Erase Cycling: VPP = VPPH2, 80 hrs.

Parameter Block Erase Cycling: VPP = VPPH2, 80 hrs.

Maximum VPP hours at VPPH2

Notes:

100,000

Cycles

Hours

1,000

80

1. See DC Characteristics tables for voltage range-specific specification.

2. Applying VPP = 11.7V to 12.3V during a erase or program can be done for a maximum of 1,000 cycles on the main blocks and

1,000 cycles on the parameter blocks. A permanent connection to VPP = 11.7V to 12.3V is not allowed and can cause

damage to the device.

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W28F641B/T

Capacitance⁽¹⁾

TA = +25° C, f = 1 MHz

PARAMETER

Input Capacitance

SYM.

CIN

TYP.

6

MAX.

8

UNIT

pF

CONDITION

VIN = 0.0V

Output Capacitance

COUT

10

12

pF

VOUT = 0.0V

Note: Sampled, not 100% tested.

AC Input/Output Test Conditions

VDDQ

TEST POINTS

VDDQ/2

INPUT

OUTPUT

VDDQ/2

0.0

AC test inputs are driven at VDDQ(min) for a Logic "1" and 0.0V for a Logic "0".

Input timing begins, and output timing ends at VDDQ/2. Input rise and fall times (10% to 90%) < 5 nS.

Worst case speed conditions are when VDD = VDD(min).

Figure 5. Transient Input/Output Reference Waveform for VDD = 2.7V to 3.6V

VDDQ(min)/2

1N914

R

_L=3.3K ohm

DEVICE

UNDER

TEST

OUT

C

L

Includes Jig Capacitance

L

Figure 6. Transient Equivalent Testing Load Circuit

Table 13. Configuration Capacitance Loading Value

TEST CONFIGURATION

CL(PF)

V_DD= 2.7V to 3.6V

50

Publication Release Date: March 27, 2003

Revision A3

- 17 -

W28F641B/T

DC Characteristics

V_DD= 2.7V to 3.6V

PARAMETER

SYM.

TEST CONDITIONS

UNIT

Min.

Typ.

Max.

Input Load Current

(note 1)

I_LI

-1.0

+1.0

µA

V_DD= V_DDMax.,

V

_DDQ= V_DDQMax.,

Output Leakage Current

(note1)

V_IN/V_OUT= V_DDQor V_SS

I_LO

-1.0

+1.0

20

V

_DD= V_DDMax. #CE =

V_DDStandby Current

(note 1)

I_CCS

4

#RESET = V_DDQ±0.2V,

µA

#WP = V_DDQor V_SS

V_DD= V_DDMax. #CE = V_SS

V_DDAutomatic Power Saving Current

(note 1, 4)

I_CCAS

I_CCD

4

20

25

10

µA

±0.2V, #WP = V_DDQor V_SS

V_DDReset Power-Down Current

(note 1)

#RESET = V_SS±0.2V

Average V_DDRead Current

Normal Mode (note1, 7)

15

5

mA

V_DD= V_DDMax.,

#CE = V_IL, #OE = V_IH,

f = 5 MHz

I_CCR

Average V_DDRead Current

Page Mode (note1, 7)

8 Word

Read

V_PP= V_PPH1

V_PP= V_PPH2

V_PP= V_PPH1

V_PP= V_PPH2

20

10

60

20

30

mA

V_DD(Page Buffer) Program Current

(note 1, 5, 7)

I_CCW

I_CCE

V_DDBlock Erase, Full Chip Erase

Current (note 1, 5, 7)

V_DD(Page Buffer) Program or Block

Erase Suspend Current (note 1, 2, 7)

I_CCWS

I_CCES

#CE = V_IH

10

2

200

5

µA

V_PPStandby or Read Current

(note 1, 6, 7)

I_PPS

I_PPR

V_PP≤ V_DD

V_PP= V_PPH1

V_PP= V_PPH2

V_PP= V_PPH1

2

10

2

5

30

5

µA

mA

µA

mA

µA

V_PP(Page Buffer) Program Current

(note 1, 5, 6, 7)

I_PPW

V_PPBlock Erase, Full Chip Erase

Current (note 1, 5, 6, 7)

I_PPE

V

_PP= V_PPH2

V_PP= V_PPH1

_PP= V_PPH2

5

15

5

2

V_PP(Page Buffer) Program Suspend

Current (note 1, 6, 7)

I_PPWS

V

10

2

200

5

V_PP= V_PPH1

V_PP= V_PPH2

V_PPBlock Erase Suspend Current (note

1, 6, 7)

I_PPES

10

200

- 18 -

W28F641B/T

DC Characteristics, continued

V_DD= 2.7V − 3.6V

TEST

PARAMETER

SYM.

UNIT

CONDITIONS

Min.

Typ.

Max.

Input Low Voltage (note 5)

Input High Voltage (note 5)

V_IL

V_IH

-0.4

0.4

V

V_DDQ

+0.4

2.4

V_DD= V_DDMin., V_DDQ

=

Output Low Voltage (note 5)

Output High Voltage (note 5)

V_OL

V_OH

0.2

V

V_DDQMin., IOL = 100 µA

V_DD= V_DDMin., V_DDQ

=

V_DDQ

-0.2

V_DDQMin., IOH = -100 µA

V_PPLockout during Normal Operations

(note 3, 5, 6)

V_PPLK

0.4

3.6

V_PPduring Block Erase, Full Chip

Erase, (Page Buffer) Program or OTP

Program Operations (note 6)

V_PPH1

1.65

3.0

12

V

V_PPduring Block Erase, (Page Buffer)

Program or OTP Program Operations

(note 6)

V_PPH2

V_LKO

11.7

1.5

12.3

V

V_DDLockout Voltage

Notes:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V_DD= 3.0V and TA = +25° C unless

V_DDis specified.

2. I_CCWSand I_CCESare specified with the device de-selected. If read or (page buffer) program is executed while in block erase

suspend mode, the device's current draw is the sum of I_CCESand I_CCRor I_CCW. If read is executed while in (page buffer)

program suspend mode, the device’s current draw is the sum of I_CCWSand I_CCR

.

3. Block erases, full chip erase, (page buffer) program and OTP program are inhibited when V_PP≤ V_PPLK, and not guaranteed in

the range between V_PPLK(max.) and V_PPH1(min.), between V_PPH1(max.) and V_PPH2(min.) and above V_PPH2(max.).

4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion.

Standard address access timings (tAVQV) provide new data when address are changed.

5. Sampled, not 100% tested.

6. V_PPis not used for power supply pin. With V_PP≤ V_PPLK, block erase, full chip erase, (page buffer) program and OTP program

cannot be executed and should not be attempted.

Applying 12V ±0.3V to V V_PPprovides fast erasing or fast programming mode. In this mode, V_PPis power supply pin and

supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths and

layout considerations given to the V_DDpower bus.

Applying 12V ±0.3V to V_PPduring erase/program can only be done for a maximum of 1,000 cycles on each block. V_PPmay be

connected to 12V ±0.3V for a total of 80 hours maximum.

7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.

Publication Release Date: March 27, 2003

- 19 -

Revision A3

W28F641B/T

AC Characteristics - Read-only Operations(1)

V_DD= 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER

Read Cycle Time

SYM.

t_AVAV

MIN.

80

MAX.

UNIT

nS

Address to Output Delay

t_AVQV

80

#CE to Output Delay (note 3)

t_ELQV

Page Address Access Time

t_APA

35

#OE to Output Delay (note 3)

t_GLQV

20

#RESET High to Output Delay

#CE or #OE to Output in High Z, whichever Occurs First (note 2)

#CE to Output in Low Z (note 2)

#OE to Output in Low Z (note 2)

t_PHQV

150

20

t_EHQZ,t_GHQZ,

t_ELQX

0

t_GLQX

Output Hold from first Occurring Address, #CE or #OE Change

(note 2)

t_OH

0

nS

Address Setup to #CE, #OE, Going Low for Reading Status

Register (note 4,6)

t

_AVEL,t_AVGL

_ELAX,t_GLAX

10

Address Hold from #CE, #OE, Going Low for Reading Status

Register (note 5,6)

t

30

nS

#CE, #OE Pulse Width High for Reading Status Register (note 6)

t_EHEL,t_GHGL

Notes:

1. See AC Input/Output Reference Waveform for timing measurements and maximum allowable input slew rate.

2. Sampled, not 100% tested.

3. #OE may be delayed up to t_ELQVto t_GLQVafter the falling edge of #CE without impact to t_ELQV

.

4. Address setup time (t_AVELto t_AVGL) is defined from the falling edge of #CE or #OE (whichever goes low last).

5. Address hold time (t_ELAXto t_GLAX) is defined from the falling edge of #CE or #OE (whichever goes low last).

6. Specifications t_AVEL, t_AVGL, t_ELAX, t_GLAX, and t_EHEL,, t_GHGLfor read operations apply to only status register read operations.

- 20 -

W28F641B/T

V

IH

Vaild Address

A21-0(A)

#CE(E)

V

IL

t

AVAV

t

AVQV

t

EHQZ

GHQZ

t

EHEL

V

IH

V

IL

t

AVEL

t

ELAX

t

AVGL

t

GLAX

GHGL

V

IH

#OE(G)

#WE(W)

V

IL

t

ELQV

V

IH

t

GLQV

V

IL

t

GLQX

t

OH

t

ELQX

V

OH

DQ15-0 (D/Q)

HIGH Z

Valid Output

V

OL

t

PHQV

V

IH

#RESET(P)

V

IL

Figure 7. AC Waveform for Single Asynchronous Read Operations from Status Register,

Identifier codes, OTP Block or Query Code

Publication Release Date: March 27, 2003

Revision A3

- 21 -

W28F641B/T

V

IH

Valid Address

A21-3(A)

A2-0(A)

V

IL

t

AVQV

V

IH

Valid

Address

Valid

Address

Valid

Address

Valid Address

V

IL

V

IH

#CE(E)

#OE(G)

#WE(W)

V

IL

t

EHQZ

GHQZ

t

ELQV

V

IH

V

IL

V

IH

t

GLQV

t

V

OH

IL

t

APA

t

GLQX

t

ELQX

V

OH

HIGH Z

Valid

Address

Valid

Address

Valid

Address

Valid

Address

DQ15-0 (D/Q)

#RESET(P)

V

OL

t

PHQV

V

IH

V

IL

Figure 8. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks

- 22 -

W28F641B/T

AC Characteristics - Write Operations^{(1, 2)}

V_DD= 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER

Write Cycle Time

SYMBOL

t_AVAV

MIN.

80

150

0

MAX.

UNIT

nS

#RESET High Recovery to #WE(#CE) Going Low (note 3)

#CE(#WE) Setup to #WE(#CE) Going Low

#WE(#CE) Pulse Width (note 4)

t_PHWL(t_PHEL

t_ELWL(t_WLEL

)

t_WLWH(t_ELEH

t_DVWH(t_DVEH

t_AVWH(t_AVEH

t_WHEH(t_EHWH

t_WHDX(t_EHDX

)

50

40

50

0

Data Setup to #WE(#CE) Going High (note 8)

Address Setup to #WE(#CE) Going High (note 8)

#CE(#WE) Hold from #WE(#CE) High

Data Hold from #WE(#CE) High

)

0

Address Hold from #WE(#CE) High

t_WHAX(t_EHAX

t_WHWL(t_EHEL

t_SHWH(t_SHEH

)

0

#WE(#CE) Pulse Width High (note 5)

#WP High Setup to #WE(#CE) Going High (note 3)

V_PPSetup to #WE(#CE) Going High (note 3)

Write Recovery before Read

)

30

0

)

t_VVWH(t_VVEH

t_WHGL(t_EHGL

t_QVSL

)

200

30

0

)

#WP High Hold from Valid SRD (note 3,6)

V_PPHold from Valid SRD (note 3,6)

t_QVVL

0

#WE(#CE) High to SR.7 Going "0" (note 3,7)

t_WHR0(t_EHR0

)

t_AVQV+50

Notes:

1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP

program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.

2. A write operation can be initiated and terminated with either #CE or #WE.

3. Sampled, not 100% tested.

4. Write pulse width (tWP) is defined from the falling edge of #CE or #WE (whichever goes low last) to the rising edge of #CE or

#WE (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.

5. Write pulse width high (tWPH) is defined from the rising edge of #CE or #WE (whichever goes high first) to the falling edge of

#CE or #WE (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.

6. VPP should be held at VPP = VPPH1/2 until determination of block erase, (page buffer) program or OTP program success

(SR.1/3/4/5 = 0) and held at VPP = VPPH1 until determination of full chip erase success (SR.1/3/5 = 0).

7. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command = tAVQV+100 nS.

8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit

configuration.

Publication Release Date: March 27, 2003

- 23 -

Revision A3

W28F641B/T

Note 4

Note 5

Note 1

Note 2

Note 3

V

IH

IL

A21-0(A)

Valid Address

t

(t

)

AVEH

t

AVWH

AVAV

t

(t

)

EHAX

WHAX

V

IH

Note 5,6

#CE(E)

V

IL

t

(t

)

WLEL

ELWL

t

(t EHWH)

WHEH

t

(t

)

EHGL

WHGL

Note 5,6

V

IH

IL

#OE(G)

#WE(W)

V

t

(t

)

PHEL

PHWL

t

(t

)

EHEL

WHWL

V

IH

V

IL

t

(t

)

DVEH

DVWH

t

(t

)

t

WHQV1,2,3

ELEH

WLWH

(t EHQV1,2,3)

t

(t

WHDX

)

EHDX

V

IH

Valid

SRD

DQ15-0(D/Q)

D

IN

V

IL

t

(t

)

EHR0

WHR0

("1")

("0")

SR.7(R)

V

IH

#RESET(P)

t

(t

)

SHEH

V

SHWH

t

IL

QVSL

QVVL

V

IH

IL

#WP(S)

t

(t

)

VVEH

VVWH

V

PPH1,2

PPLK

(V)

V

PP

V

IL

Figure 9. AC Waveform for Write Operations

Notes:

1. VDD power-up and standby.

2. Write each first cycle command.

3. Write each second cycle command or valid address and data.

4. Automated erase or program delay.

5. Read status register data.

6. For read operation, #OE and #CE must be driven active, and #WE de-asserted.

- 24 -

W28F641B/T

Reset Operations

t

PHQV

V

IH

#RESET(P)

V

IL

t

PLPH

V

OH

High Z

(A)Reset During Read Array Mode

DQ15-0(D/Q)

Valid Output

V

OL

SR.7="1"

Abort

Complete

t

PHQV

PLRH

V

IH

#RESET(P)

V

IL

t

PLPH

V

OH

High Z

(B)Reset During Erase or Program Mode

Valid Output

DQ15-0(D/Q)

V

OL

(min)

V

DD

V

DD

t

VHQV

Vss

t

PHQV

t

2VPH

V

IH

#RESET(P)

V

IL

V

OH

High Z

Valid Output

DQ15-0(D/Q)

V

OL

(C)#RESET Rising Timing

Figure 10. AC Waveform for Reset Operation

Reset AC Specifications

V_DD= 2.7V to 3.6V, TA = -40°C to +85°C

PARAMETER

SYM.

MIN.

MAX.

UNIT

#RESET Low to Reset during Read

(#RESET should be low during power-up.) (note 1, 2, 3)

#RESET Low to Reset during Erase or Program (note 1, 3, 4)

100

nS

t_PLPH

22

1

t_PLRH

t_2VPH

t_VHQV

µS

nS

V_DD2.7V to #RESET High (note 1, 3, 5)

V_DD2.7V to Output Delay (note 3)

100

mS

Publication Release Date: March 27, 2003

Revision A3

- 25 -

W28F641B/T

Notes:

1. A reset time, tPHQV, is required from the later of SR.7 going "1" or #RESET going high until outputs are valid. Refer to AC

Characteristics - Read-Only Operations for tPHQV.

2. tPLPH is <100 nS the device may still reset but this is not guaranteed.

3. Sampled, not 100% tested.

4. If #RESET asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing,

the reset will complete within 100 nS.

5. When the device power-up, holding #RESET low minimum 100ns is required after VDD has been in predefined range and also

has been in stable there.

Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program

Performance⁽³⁾

V_DD= 2.7V to 3.6V, TA = -40°C to +85°C

PAGE BUFFER

COMMAND IS

USED OR NOT

USED

V

_PP= V_PPH1

V

_PP= V_PPH2

(IN SYSTEM)

(IN MANUFACTURING)

PARAMETER

SYM.

UNIT

MIN. TYP.⁽¹⁾MAX.⁽²⁾MIN. TYP.⁽¹⁾MAX.⁽²⁾

Not Used

Used

0.05

0.03

0.38

0.24

11

0.3

0.12

2.4

0.04

0.02

0.31

0.17

9

0.12

0.06

1.0

S

4K-Word Parameter Block

Program Time (note 2)

t_WPB

t_WMB

t_WHQV1/

Not Used

Used

S

32K-Word Main Block

Program Time (note 2)

1.0

0.5

S

Not Used

Used

200

100

185

90

µS

Word Program Time (note 2)

OTP Program Time (note 2)

t_EHQV1

7

5

t_WHOV1/

Not Used

36

400

4

27

0.2

0.5

185

4

µS

t_EHOV1

t_WHQV2/

t_EHQV2

4K-Word Parameter Block

Erase Time (note 2)

-

0.3

S

t_WHQV3/

t_EHQV3

32K-Word Main Block Erase

Time (note 2)

0.6

80

5

S

Full Chip Erase Time (note 2)

700

(Page Buffer) Program

Suspend Latency Time to

Read (note 4)

t_WHRH1/

t_EHRH1

-

5

10

20

5

10

20

µS

t_WHRH2/

Block Erase Suspend Latency

Time to Read (note 4)

t_EHRH2

Latency Time from Block

Erase Resume Command to

Block Erase Suspend

Command (note 5)

-

500

T_ERES

µS

Notes:

1. Typical values measured at V_DD= 3.0V, V_PP= 3.0V or 12V, and TA = +25°C. Assumes corresponding lock bits are not set.

Subject to change based on device characterization.

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

- 26 -

W28F641B/T

4. A latency time is required from writing suspend command (#WE or #CE going high) until SR.7 going "1".

5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than

tERES and its sequence is repeated, the block erase operation may not be finished.

5. ADDITIONAL INFORMATION

Recommended Operating Conditions

At Device Power-Up

AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at

device power-up. If the timing in the figure is ignored, the device may not operate correctly.

(min)

V

DD

V

#RESET

Vpp

DD

t_2VPH

t_VR

t_PHQV

Vss

V

IH

(p)

V

IL

^*1(V)

V

PPH1/2

Vss

t_AVQV

t_R

_ort_F

V

IH

Valid Address

t_ELQV

(A)

(E)

ADDRESS

#CE

V

IL

t_F

t_R

V

IH

V

IL

V

IH

(W)

(G)

#WE

#OE

V

IL

t_R

t_F

t_GLQV

V

IH

V

IL

V

IH

(S)

#WP

V

IL

V

OH

DATA (D/Q)

HIGH Z

V

OL

Valid Output

*1 To prevent the unwanted writes, system designers should consider the design, which applies VPP to 0V during read

operations and VPPH1/2 during write or erase operations.

Figure A-1. AC Timing at Device Power-up

For the AC specifications t_VR, t_R, t_Fin the figure, refer to the next page. See the “ELECTRICAL SPECIFICATIONS“ described in

specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.

Publication Release Date: March 27, 2003

- 27 -

Revision A3

W28F641B/T

Rise and Fall Time

PARAMETER

V_DDRise Time (note 1)

SYMBOL

MIN.

0.5

MAX.

30000

UNIT

µS/ V

t_VR

t_R

Input Signal Rise Time (note1, 2)

Input Signal Fall Time (note1, 2)

1

t_F

Notes:

1. Sampled, not 100% tested.

2. This specification is applied for not only the device power-up but also the normal operations.

Glitch Noises

Do not input the glitch noises which are below V_IH(Min.) or above V_IL(Max.) on address, data, reset,

and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure

A-2 (a).

Input Singal

V

Input Singal

V

IH(Min.)

(Max.)

V

IL

V

IL

Input Singal

(b) NOT Acceptable Glitch Noises

(a) Acceptable Glitch Noises

Figure A-2. Waveform for Glitch Noises

See the "DC CHARACTERISTICS" described in specifications for V_IH(Min.) and V_IL(Max.).

- 28 -

W28F641B/T

6. ORDERING INFORMATION

OPERATING

ACCESS

TEMPERATURE

TIME

(nS)

80

PART NO.

BOOT BLOCK

PACKAGE

(°C)

W28F641BT80L

W28F641BB80L

W28F641TT80L

W28F641TB80L

Bottom Boot

Top Boot

48-Pin TSOP

48-Ball TFBGA

48-Pin TSOP

48-Ball TFBGA

-40º C to 85° C

-40º C to 85º C

-40º C to 85° C

-40º C to 85º C

80

Top Boot

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications

where personal injury might occur as a consequence of product failure.

Publication Release Date: March 27, 2003

- 29 -

Revision A3

W28F641B/T

7. PACKAGE DIMENSIONS

48-pin Standard Thin Small Outline Package (measured in millimeters)

1

48

MILLIMETER

INCH

NOM.

Sym.

MIN.

NOM.

MAX.

0.047

MAX. MIN.

1.20

e

A

A1

0.05

0.002

A2 0.95 1.00 1.05 0.037 0.039 0.041

E

18.4 18.5

0.724 0.728

18.3

19.8

11.9

0.720

0.780

0.468

D

b

0.795

0.476

20.0 20.2

0.787

0.472

0.009

H_D

E

12.1

12.0

0.011

0.008

0.17 0.22 0.27 0.007

b

c

0.10

0.004

0.21

c

0.020

0.50

D

e

0.024

0.031

0.50

L

0.60 0.70 0.020

0.80

0.028

H^D

A2

A1

L1

Y

0.004

5

0.10

A

θ

L

θ

0

5

L1

Y

48-ball TFBGA (8 mm x 11 mm) (measurements in millimeters)

CONTROL DIMENSIONS ARE IN MILLIMETERS

b

1

2

3

4

5

6

MILLIMETER

INCH

SYMBOL

MIN. NOM. MAX. MIN. NOM. MAX.

H

G

F

E

D

C

B

A

-

A

1.05

0.042

e

0.20 0.25 0.30 0.008 0.010 0.012

7.80 8.00 8.20 0.312 0.320 0.328

A1

D2

D

3.75 BASIC

0.150 BASIC

D2

E

10.80 11.00 11.20 0.400 0.440 0.480

e

E2

E

5.25 BASIC

0.10 BASIC

0.210

E2

y

0.004 BASIC

0.37 0.40 0.43 0.015 0.016 0.017

0.75 BASIC 0.030 BASIC

b

e

A

SEATING PLANE

A1

- 30 -

W28F641B/T

8. VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

A2

A3

Jan. 7, 2003

Feb. 17, 2003

March 27, 2003

-

29

All

Initial Issued

Modify TFBGA Package Dimension drawing

Typo Correction

Headquarters

Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.

27F, 2299 Yan An W. Rd. Shanghai,

200336 China

2727 North First Street, San Jose,

CA 95134, U.S.A.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 1-408-9436666

TEL: 86-21-62365999

FAX: 86-21-62365998

TEL: 886-3-5770066

FAX: 1-408-5441798

FAX: 886-3-5665577

http://www.winbond.com.tw/

Taipei Office

Winbond Electronics Corporation Japan

7F Daini-ueno BLDG, 3-7-18

Shinyokohama Kohoku-ku,

Yokohama, 222-0033

Winbond Electronics (H.K.) Ltd.

Unit 9-15, 22F, Millennium City,

No. 378 Kwun Tong Rd.,

Kowloon, Hong Kong

9F, No.480, Rueiguang Rd.,

Neihu District, Taipei, 114,

Taiwan, R.O.C.

TEL: 886-2-8177-7168

FAX: 886-2-8751-3579

TEL: 81-45-4781881

TEL: 852-27513100

FAX: 81-45-4781800

FAX: 852-27552064

Please note that all data and specifications are subject to change without notice.

All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.

Publication Release Date: March 27, 2003

Revision A3

- 31 -


型号：	W28F641B
厂家：	WINBOND
描述：	64MBIT (4MBIT × 16) PAGE MODE DUAL WORK FLASH MEMORY 64Mbit的（的4Mbit × 16 ）页模式的双功FLASH MEMORY
文件：	总31页 (文件大小：1618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W28F641B [WINBOND]

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