W29C020CT90B_技术文档

W29C020C

256K ´ 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

´

The W29C020C is a 2-megabit, 5-volt only CMOS flash memory organized as 256K 8 bits. The

device can be written (erased and programmed) in-system with a standard 5V power supply. A 12-volt

PP

V

is not required. The unique cell architecture of the W29C020C results in fast write

(erase/program) operations with extremely low current consumption compared to other comparable 5-

volt flash memory products. The device can also be written (erased and programmed) by using

standard EPROM programmers.

FEATURES

·

· Single 5-volt write (erase and program)

operations

Software and hardware data protection

Low power consumption

· Fast page-write operations

- Active current: 25 mA (typ.)

-

128 bytes per page

-

m

Standby current: 20 A (typ.)

Page write (erase/program) cycle: 10 mS

(max.)

· Automatic write (erase/program) timing with

internal V generation

PP

-

Effective byte-write (erase/program) cycle

· End of write (erase/program) detection

m

time: 39 S

-

Toggle bit

-

Optional software-protected data write

Data polling

· Fast chip-erase operation: 50 mS

· Two 8 KB boot blocks with lockout

· Whole chip cycling: 10K (typ.)

· Read access time: 70/90/120 nS

· Twenty-year data retention

· Latched address and data

· All inputs and outputs directly TTL compatible

· JEDEC standard byte-wide pinouts

· Available packages: 32-pin 600 mil DIP, 32-pin

TSOP, and 32-pin PLCC

Publication Release Date: April 2000

- 1 -

Revision A2

W29C020C

PIN CONFIGURATIONS

BLOCK DIAGRAM

V

DD

32

31

30

29

28

27

1

2

3

V_DD

WE

NC

A16

A15

A12

A7

VSS

A17

A14

4

5

CE

OE

WE

DQ0

.

A13

6

OUTPUT

BUFFER

A6

A8

CONTROL

7

26

25

24

23

22

21

20

19

A9

A5

32-pin

DIP

8

A11

A4

A3

A2

A1

DQ7

9

OE

10

A10

11

12

13

CE

DQ7

A0

DQ0

DQ1

DQ2

GND

8K Byte Boot Block (Optional)

DQ6

DQ5

DQ4

DQ3

A0

.

14

15

16

18

17

CORE

ARRAY

.

DECODER

A

1

2

A

1

6

V

D

/

W

E

A

1

7

A

1

5

8K Byte Boot Block (Optional)

N

C

A17

3

4

2

1

32 31 30

5

6

7

8

9

29

28

27

26

25

24

23

22

21

A14

A7

A6

A5

A4

A3

A2

A1

A0

A13

A8

32-pin

PLCC

A9

A11

10

11

12

13

OE

A10

CE

DQ7

DQ0

PIN DESCRIPTION

14 15 16 17 18

19 20

D

Q

1

D

Q

2

G

N

D

Q

4

D

Q

3

D

Q

5

D

Q

6

SYMBOL

PIN NAME

Address Inputs

Data Inputs/Outputs

-

A0 A17

1

2

3

4

5

32

OE

A10

A11

A9

A8

A13

A14

A17

-

DQ0 DQ7

31

30

29

28

27

26

25

CE

DQ7

DQ6

DQ5

Chip Enable

Output Enable

Write Enable

Power Supply

Ground

CE

OE

WE

6

7

8

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A0

A1

A2

A3

WE

VDD

NC

A16

32-pin

TSOP

9

10

24

23

22

21

20

19

18

17

11

12

13

14

15

16

A15

A12

A7

A6

A5

DD

V

A4

GND

NC

No Connection

- 2 -

W29C020C

FUNCTIONAL DESCRIPTION

Read Mode

CE

OE

, both of which have to be low for

The read operation of the W29C020C is controlled by

and

CE

the host to obtain data from the outputs.

is used for device selection. When

is high, the chip

is the output control and is used to gate

OE

is de-selected and only standby power will be consumed.

CE

OE

is high.

data from the output pins. The data bus is in high impedance state when either

Refer to the read cycle timing waveforms for further details.

or

Page Write Mode

The W29C020C is written (erased/programmed) on a page basis. Every page contains 128 bytes of

data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the

device. Any byte that is not loaded will be erased to "FF hex" during the write operation of the page.

CE

WE

OE

low and high. The write procedure

The write operation is initiated by forcing

and

consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the

device.

Step 2 is an internal write (erase/program) cycle, during which the data in the page buffers are

simultaneously written into the memory array for non-volatile storage.

CE

WE

,

During the byte-load cycle, the addresses are latched by the falling edge of either

or

CE WE

whichever occurs last. The data are latched by the rising edge of either

or

, whichever

BLC

occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (T

) of

200 mS after the initial byte-load cycle, the W29C020C will stay in the page load cycle. Additional

bytes can then be loaded consecutively. The page load cycle will be terminated and the internal write

(erase/program) cycle will start if no additional byte is loaded into the page buffer A7 to A17 specify

the page address. All bytes that are loaded into the page buffer must have the same page address.

A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential

loading is not required.

In the internal write cycle, all data in the page buffers, i.e., 128 bytes of data, are written

simultaneously into the memory array. Before the completion of the internal write cycle, the host is

free to perform other tasks such as fetching data from other locations in the system to prepare to

write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is

enabled, any write operation requires a three-byte command sequence (with specific data to a

specific address) to be performed before the data load operation. The three-byte load command

sequence begins the page load cycle, without which the write operation will not be activated. This

write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by

noise during system power-up and power-down.

The W29C020C is shipped with the software data protection enabled. To enable the software data

protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The

device will then enter the software data protection mode, and any subsequent write operation must be

preceded by the three-byte command sequence cycle. Once enabled, the software data protection

will remain enabled unless the disable commands are issued. A power transition will not reset the

software data protection feature. To reset the device to unprotected mode, a six-byte command

Publication Release Date: April 2000

- 3 -

Revision A2

W29C020C

sequence is required. For information about specific codes, see the Command Codes for Software

Data Protection in the Table of Operating Modes. For information about timing waveforms, see the

timing diagrams below.

Hardware Data Protection

The integrity of the data stored in the W29C020C is also hardware protected in the following ways:

WE

(1) Noise/Glitch Protection: A

pulse of less than 15 nS in duration will not initiate a write cycle.

DD

(2) V Power Up/Down Detection: The write operation is inhibited when V is less than 2.5V.

OE

CE

WE

high will inhibit the write operation. This

(3) Write Inhibit Mode: Forcing

low,

high, or

prevents inadvertent writes during power-up or power-down periods.

DD

(4) V power-on delay: When V reaches its sense level, the device will automatically timeout for

5 mS before any write (erase/program) operation.

Chip Erase Modes

The entire device can be erased by using a six-byte software command code. See the Software Chip

Erase Timing Diagram.

Boot Block Operation

There are two boot blocks (8K bytes each) in this device, which can be used to store boot code. One

of them is located in the first 8K bytes and the other is located in the last 8K bytes of the memory.

The first 8K or last 8K of the memory can be set as a boot block by using a seven-byte command

sequence.

See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set

the data for the designated block cannot be erased or programmed (programming lockout); other

memory locations can be changed by the regular programming method. Once the boot block

programming lockout feature is activated, the chip erase function will be disabled. In order to detect

whether the boot block feature is set on the two 8K blocks, users can perform a six-byte command

sequence: enter the product identification mode (see Command Codes for Identification/Boot Block

Lockout Detection for specific code), and then read from address "00002 hex" (for the first 8K bytes)

or "3FFF2 hex" (for the last 8K bytes). If the output data is "FF hex," the boot block programming

lockout feature is activated; if the output data is "FE hex," the lockout feature is deactivated and the

block can be programmed.

To return to normal operation, perform a three-byte command sequence to exit the identification

mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.

Data Polling (DQ7)- Write Status Detection

The W29C020C includes a data polling feature to indicate the end of a write cycle. When the

W29C020C is in the internal write cycle, any attempt to read DQ7 from the last byte loaded during the

page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.

DQ7 will show the true data. See the OE Polling Timing Diagram.

- 4 -

W29C020C

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W29C020C provides another method for determining the end of a write

cycle. During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating

0's and 1's. When the write cycle is completed, this toggling between 0's and 1's will stop. The device

is then ready for the next operation. See Toggle Bit Timing Diagram.

Product Identification

The product ID operation outputs the manufacturer code and device code. The programming

equipment automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed through software or by hardware operation. In

the software access mode, a six-byte command sequence can be used to access the product ID. A

read from address "00000 hex" outputs the manufacturer code "DA hex." A read from address "00001

hex" outputs the device code "45 hex." The product ID operation can be terminated by a three-byte

command sequence.

CE

OE

WE

low,

In the hardware access mode, access to the product ID is activated by forcing

high, and raising A9 to 12 volts.

and

TABLE OF OPERATING MODES

Operating Mode Selection

Operating Range: 0 to 70 C (Ambient Temperature), VDD = 5V 10%, VSS = 0V, VHH = 12V

°

±

MODE

PINS

ADDRESS

DQ.

CE OE WE

IL

IH

IN

Read

V

A

X

A

Dout

IL

IH

IL

V

Write

V

Din

IH

Standby

V

X

High Z

IL

V

OUT

Write Inhibit

X

High Z/D

High Z

IH

V

OUT

X

IH

Output Disable

V

X

IL

IH

IL

V

IN

D

5-Volt Software Chip

Erase

V

IL

V

IH

Product ID

V

Manufacturer Code DA

(Hex)

IL

-

A0 = V ; A1 A17 = V ;

A9 = V

HH

IL

V

IH

Device Code

45 (Hex)

IH

IL

-

A0 = V ; A1 A17 = V ;

A9 = V

HH

Publication Release Date: April 2000

Revision A2

- 5 -

W29C020C

Command Codes for Software Data Protection

BYTE SEQUENCE

TO ENABLE PROTECTION

TO DISABLE PROTECTION

ADDRESS

5555H

DATA

ADDRESS

5555H

DATA

AAH

55H

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

AAH

55H

A0H

2AAAH

5555H

2AAAH

5555H

2AAAH

5555H

80H

-

AAH

55H

20H

Software Data Protection Acquisition Flow

Software Data Protection

Enable Flow

Software Data Protection

Disable Flow

Load data AA

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Load data 80

to

address 5555

Load data AA

to

address 5555

Sequentially load

up to 128 bytes

of page data

(Optional page-load

operation)

Load data 55

to

Pause 10 mS

Exit

address 2AAA

Load data 20

to

address 5555

Pause 10 mS

Exit

Notes for software program code:

Data Format: DQ7 DQ0 (Hex)

-

Address Format: A14 A0 (Hex)

-

- 6 -

W29C020C

Command Codes for Software Chip Erase

BYTE SEQUENCE

0 Write

ADDRESS

DATA

AAH

55H

5555H

2AAAH

5555H

2AAAH

5555H

1 Write

2 Write

80H

3 Write

AAH

55H

4 Write

5 Write

10H

Software Chip Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 50 mS

Exit

Notes for software chip erase:

Data Format: DQ7 DQ0 (Hex)

-

Address Format: A14 A0 (Hex)

-

Publication Release Date: April 2000

Revision A2

- 7 -

W29C020C

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (7)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION EXIT

ADDRESS

DATA

ADDRESS

5555H

DATA

AAH

55H

ADDRESS

DATA

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

5555

AA

55

90

-

5555H

AAH

2AAA

2AAAH

5555H

2AAAH

55H

5555

80H

5555H

F0H

-

5555H

AAH

55H

-

2AAAH

5555H

-

60H

m

S

m

S

m

S

Pause 10

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Product

Identification

Exit (1)

Identification

and Boot Block

Lockout Detection

Mode (3)

Load data AA

to

address 5555

(2)

(4)

(5)

Load data 55

to

Load data AA

Read address = 00000

data = DA

to

address 5555

address 2AAA

Load data 80

to

address 5555

Load data 55

to

address 2AAA

Read address = 00001

data = 45

Load data AA

to

address 5555

Load data F0

to

address 5555

Read address = 00002

data = FF/FE

Load data 55

to

address 2AAA

Read address = 3FFF2

data = FF/FE

m

S

Pause 10

(6)

Load data 60

to

address 5555

Normal Mode

Pause 10

m

Notes for software product identification/boot block lockout detection:

-

(1) Data Format: DQ7 DQ0 (Hex); Address Format: A14 A0 (Hex)

-

(2) A1 A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.

(3) The device does not remain in identification and boot block (address 0002 Hex/3FFF2 Hex respond to first 8K/last 8K) lockout detection mode if

power down.

(4), (5) If the output data is "FF Hex," the boot block programming lockout feature is activated; if the output data "FE Hex," the lockout feature is

inactivated and the block can be programmed.

(6) The device returns to standard operation mode.

(7) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new

designs, Winbond recommends that the 3 byte command code sequence be used.

- 8 -

W29C020C

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

BOOT BLOCK LOCKOUT FEATURE SET ON

FIRST 8K ADDRESS BOOT BLOCK

BOOT BLOCK LOCKOUT FEATURE SET

ON LAST 8K ADDRESS BOOT BLOCK

ADDRESS

5555H

DATA

AAH

55H

80H

AAH

55H

40H

00H

ADDRESS

5555H

DATA

AAH

55H

0 Write

1 Write

2 Write

3 Write

4 Write

5 Write

6 Write

2AAAH

5555H

2AAAH

5555H

80H

5555H

AAH

55H

2AAAH

5555H

2AAAH

5555H

40H

00000H

3FFFFH

FFH

Pause 10

S

m

Pause 10 S

m

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set on First 8K

Address Boot Block

Boot Block Lockout

Feature Set on Last 8K

Address Boot Block

Load data AA

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Load data 40

to

address 5555

Load data 00

to

address 00000

Load data FF

to

address 3FFFF

Pause 10 mS

Notes for boot block lockout enable:

1. Data Format: DQ7 DQ0 (Hex)

-

2. Address Format: A14 A0 (Hex)

-

3. If you have any questions about this commend sequence, please contact the local distributor or Winbond Electronics Corp.

Publication Release Date: April 2000

- 9 -

Revision A2

W29C020C

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

UNIT

SS

Power Supply Voltage to V Potential

-0.5 to +7.0

0 to +70

V

Operating Temperature

°

C

Storage Temperature

-65 to +150

°

C

DD

D.C. Voltage on Any Pin to Ground Potential Except A9

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

-0.5 to V +1.0

V

DD

-1.0 to V +1.0

V

-0.5 to 12.5

OE

Voltage on A9 and

Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

Operating Characteristics

DD

SS

A

(V = 5.0V 10 , V = 0V, T = 0 to 70 C)

±

%

°

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

UNIT

MIN.

TYP.

MAX.

CC

I

-

50

mA

CE OE

WE

= V ,

Power Supply Current

IL

= V ,

IH

=

all DQs open

IL IH

Address inputs = V /V ,

at f = 5 MHz

SB

I

1

-

2

3

mA

DD

CE

Standby V Current

IH

= V , all DQs open

(TTL input)

IL IH

Other inputs = V /V

SB

2

20

100

m

A

DD

CE

Standby V Current

DD

= V -0.3V, all DQs

open

(CMOS input)

LI

IN

DD

I

V

= GND to V

-

10

0.8

-

m

A

Input Leakage Current

Output Leakage Current

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

LO

IL

IN

= GND to V

m

A

V

-

V

-

IH

2.0

-

V

-

OL

OH

I

= 2.0 mA

0.45

-

OH1

OH2

2.4

4.2

m

= -400 A

-

CC

= -100 mA; V = 4.5V

Output High Voltage

CMOS

- 10 -

W29C020C

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

PU

Power-up to Read Operation

Power-up to Write Operation

T

. READ

100

5

m

S

PU

T

. WRITE

mS

CAPACITANCE

(VDD = 5.0V, TA = 25 C, f = 1 MHz)

°

PARAMETER

DQ Pin Capacitance

Input Pin Capacitance

SYMBOL

CONDITIONS

MAX.

12

UNIT

pF

DQ

C

DQ

V

= 0V

IN

C

IN

V

= 0V

6

pF

AC CHARACTERISTICS

AC Test Conditions

(VDD = 5.0V 10 for 90 nS and 120 nS; VDD = 5.0V 5% for 70 nS)

±

%

±

PARAMETER

CONDITIONS

Input Pulse Levels

Input Rise/Fall Time

Input/Output Timing Level

Output Load

0V to 3V

<5 nS

1.5V/1.5V

L

1 TTL Gate and C = 100 pF for 90/120 nS

L

C = 30 pF for 70 nS

AC Test Load and Waveform

+5V

1.8K

W

D_OUT

100 pF for 90/120 nS

30 pF for 70 nS

(Including Jig and Scope)

1.3K

W

Input

Output

3V

1.5V

0V

Test Point

Publication Release Date: April 2000

Revision A2

- 11 -

W29C020C

AC Characteristics, continued

Read Cycle Timing Parameters

(VDD = 5.0V 10 for 90 nS and 120 nS; VDD = 5.0V 5% for 70 nS, VSS = 0V, TA = 0 to 70 C)

±

%

±

°

W29C020C-70 W29C020C-90 W29C020C-12

MIN. MAX. MIN. MAX. MIN. MAX.

PARAMETER

SYM.

UNIT

RC

Read Cycle Time

T

70

-

90

-

120

-

nS

CE

Chip Enable Access Time

Address Access Time

Output Enable Access Time

T

70

35

25

90

40

25

-

120

50

AA

-

OE

CHZ

-

30

CE

OE

High to High-Z Output

OHZ

OH

T

-

25

-

25

-

30

-

nS

Output Hold from Address change

0

Byte/Page-write Cycle Timing Parameters

PARAMETER

Write Cycle (erase and program)

Address Setup Time

SYMBOL

MIN.

TYP.

MAX.

UNIT

WC

T

-

0

-

10

-

mS

nS

AS

T

AH

T

Address Hold Time

50

0

-

CS

T

-

WE

OE

CE

and

Setup Time

Hold Time

CH

T

0

-

nS

OES

T

High Setup Time

High Hold Time

Pulse Width

OEH

T

0

CP

T

70

100

WP

T

WE

Pulse Width

WPH

T

High Width

DS

Data Setup Time

Data Hold Time

T

50

0

-

nS

DH

T

BLC

T

Byte Load Cycle Time

-

200

m

S

Note: All AC timing signals observe the following guideline for determining setup and hold times:

Reference level is VIH for high-level signal and VIL for low-level signal.

- 12 -

W29C020C

AC Characteristics, continued

(1)

DATA

Polling Characteristics

PARAMETER

SYMBOL

MIN.

10

TYP.

MAX.

UNIT

nS

DH

T

Data Hold Time

-

OEH

T

10

nS

OE

Hold Time

(2)

OE

T

-

nS

to Output Delay

WR

T

Write Recovery Time

0

Notes:

(1) These parameters are characterized and not 100% tested.

OE

.

(2) See T spec in A.C. Read Cycle Timing Parameters

(1)

Toggle Bit Characteristics

PARAMETER

Data Hold Time

SYMBOL

MIN.

10

TYP.

MAX.

UNIT

nS

DH

T

-

OEH

T

10

nS

OE

Hold Time

(2)

OE

T

-

150

0

-

nS

to Output Delay

High Pulse

OEHP

WR

Write Recovery Time

Notes:

(1) These parameters are characterized and not 100% tested.

(2) See TOE spec in A.C. Read Cycle Timing Parameters.

TIMING WAVEFORMS

Read Cycle Timing Diagram

T

RC

Address A17-0

T

CE

T

OE

T

OHZ

V

IH

WE

T

OH

T

CHZ

High-Z

DQ7-0

Data Valid

AA

T

Publication Release Date: April 2000

Revision A2

- 13 -

W29C020C

Timing Waveforms, continued

WE

Controlled Write Cycle Timing Diagram

T_WC

T_AS

T_AH

Address A17-0

CE

T_CS

T_CH

T_OEH

T_OES

OE

T_WP

T_WPH

WE

T_DS

DQ7-0

Data Valid

T_DH

Internal write starts

CE Controlled Write Cycle Timing Diagram

AS

T

T_WC

TAH

Address A17-0

T_WPH

T_CP

CE

T_OES

T_OEH

OE

T_CS

CH

T

WE

T_DS

High Z

DQ7-0

Data Valid

T_DH

Internal Write Starts

- 14 -

W29C020C

Timing Waveforms, continued

Page Write Cycle Timing Diagram

TWC

Address A17-0

DQ7-0

CE

OE

TBLC

T_WPH

WP

T

WE

Byte 0

Byte 1

Byte 2

Byte N-1

Internal Write Start

Byte N

DATA

Polling Timing Diagram

Address A15-0

WE

CE

T_OEH

OE

T_DH

T_WR

HIGH-Z

DQ7

T_OE

Publication Release Date: April 2000

Revision A2

- 15 -

W29C020C

Timing Waveforms, continued

Toggle Bit Timing Diagram

WE

CE

T_OEH

OE

T_DH

T_OE

T_WR

HIGH-Z

DQ6

Page Write Timing Diagram Software Data Protection Mode

T_WC

Byte/page load

Three-byte sequence for

cycle starts

software data protection mode

Address A15-0

2AAA

5555

DQ7-0

CE

AA

55

A0

OE

T_BLC

T_WP

WE

T_WPH

Word N

(last word)

Word 0

Word N-1

SW1

SW2

SW0

Internal write starts

- 16 -

W29C020C

Timing Waveforms, continued

Reset Software Data Protection Timing Diagram

Six-byte sequence for resetting

software data protection mode

T_WC

Address A15-0

5555

80

5555

2AAA

55

5555

AA

2AAA

DQ7-0

CE

AA

55

20

OE

T_WP

T_BLC

WE

T_WPH

SW0

SW2

SW3

SW5

SW4

SW1

Internal programming starts

Software Chip Erase Timing Diagram

Six-byte code for 5V-only software

chip erase

T_WC

Address A15-0

5555

80

5555

2AAA

55

5555

AA

2AAA

55

DQ7-0

CE

AA

10

OE

T_WP

T_BLC

WE

T_WPH

SW0

SW2

SW3

SW5

SW4

SW1

Internal erasing starts

Publication Release Date: April 2000

Revision A2

- 17 -

W29C020C

ORDERING INFORMATION

PART NO.

ACCESS

TIME

POWER

STANDBY

PACKAGE

CYCLING

SUPPLY CURRENT VDD CURRENT

(nS)

MAX. (mA)

MAX. ( A)

m

W29C020C-70B

W29C020C-90B

W29C020C-12B

W29C020CT70B

W29C020CT90B

W29C020CT12B

W29C020CP70B

W29C020CP90B

W29C020CP12B

70

90

50

100

600 mil DIP

10K

600 mil DIP

120

70

600 mil DIP

Type one TSOP

32-pin PLCC

90

120

70

90

120

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in

applications where personal injury might occur as a consequence of product failure.

- 18 -

W29C020C

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in mm

Dimension in inches

Symbol

A

Nom.

Min.

Max. Min.

0.210

Max.

5.33

0.010

0.150

0.25

A

B

c

1

0.155 0.160

3.81

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

2

0.016 0.018 0.022 0.41

0.050

1.22

0.20

0.048

0.008

0.054

1

0.010 0.014

1.650 1.660

D

17

32

41.91 42.16

D

E

e

15.49

14.10

2.79

0.610

0.555

0.110

15.24

0.590 0.600

14.99

13.84 13.97

0.545

0.090 0.100

0.550

1

2.29

3.05

0

2.54

3.30

E1

0.120

0

0.140

15

0.130

3.56

15

L

a

17.02

2.16

0.630 0.650 0.670 16.00 16.51

0.085

A

e

S

16

1

Notes:

E

S

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

c

2.Dimension E1 does not include interlead flash.

2

A

L

A1

Base Plane

3.Dimensions D & E1 include mold mismatch and

.

are determined at the mold parting line.

4.Dimension B1 does not include dambar

protrusion/intrusion.

Seating Plane

5.Controlling dimension: Inches.

6.General appearance spec. should be based on

final visual inspection spec.

B

1

e

e_A

a

1

32-pin TSOP

H D

Dimension in Inches

Min. Nom. Max.

Dimension in mm

Max.

Symbol

Min. Nom.

D

__

A

1.20

0.15

1.05

0.23

c

0.047

0.006

__

0.002

0.037

0.05

0.95

A ₁

A 2

b

0.041

0.009

1.00

0.20

0.15

0.039

M

e

0.007 0.008

0.17

0.12

E

c

D

E

0.005 0.006

0.720 0.724

0.17

0.007

0.728

0.10(0.004)

18.30 18.40 18.50

b

0.311 0.315

0.780 0.787

7.90

8.00

8.10

0.319

19.80

__

20.00 20.20

0.795

__

H_D

e

__

0.020

0.50

0.016 0.020

0.40

__

0.50

0.60

__

0.024

__

L

__

0.031

0.80

__

L

1

A

__

0.10

5

0.000

0.004

5

0.00

1

Y

A2

1

3

q

L

1

A

Y

L₁

Note:

Controlling dimension: Millimeters

Publication Release Date: April 2000

Revision A2

- 19 -

W29C020C

Package Dimensions, continued

32-pin PLCC

HE

E

4

1

32

30

Dimension in Inches

Min. Nom. Max.

0.140

Dimension in mm

Symbol

A

Min. Nom. Max.

5

29

3.56

0.020

0.50

1

A

0.105

0.026

0.110

0.028

0.018

0.010

0.115

0.032

2.67

0.66

2.80

0.71

0.46

0.25

2.93

0.81

A₂

b

c

1

0.016

0.008

0.022

0.014

0.41

0.20

0.56

0.35

G

D

H

0.547

0.447

0.044

0.553

0.453

0.056

13.89

11.35

1.12

14.05

11.51

1.42

0.550

0.450

0.050

0.510

0.410

0.590

0.490

0.090

13.97

11.43

1.27

D

E

e

12.95

0.490

0.390

0.530

0.430

12.45

9.91

13.46

10.92

D

G

H

H _E

L

y

10.41

14.99

12.45

2.29

E

D

21

13

0.585

0.485

0.595

0.495

14.86

12.32

15.11

12.57

0.075

0.095

0.004

1.91

2.41

0.10

14

c

20

°

0

10

q

Notes:

L

A

2

1

A

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches.

4. General appearance spec. should be based on final

visual inspection sepc.

q

e

b

1

Seating Plane

y

E

G

- 20 -

W29C020C

VERSION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

A2

May 1999

Apr. 2000

-

Initial Issued

Change Byte Load Cycle Time from 150 mS to 200 mS

12

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-7197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-7190505

FAX: 886-2-7197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: April 2000

Revision A2

- 21 -


型号：	W29C020CT90B
厂家：	WINBOND
描述：	256K X 8 CMOS FLASH MEMORY 256K ×8 CMOS FLASH MEMORY 闪存存储内存集成电路光电二极管
文件：	总21页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W29C020CT90B [WINBOND]

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