W29C102-12B [WINBOND]

64K 16 CMOS FLASH MEMORY; 64K 16 CMOS FLASH MEMORY
W29C102-12B
型号: W29C102-12B
厂家: WINBOND    WINBOND
描述:

64K 16 CMOS FLASH MEMORY
64K 16 CMOS FLASH MEMORY

文件: 总21页 (文件大小:253K)
中文:  中文翻译
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W29C102  
64K ´ 16 CMOS FLASH MEMORY  
GENERAL DESCRIPTION  
The W29C102 is a 1-megabit, 5-volt only CMOS flash memory organized as 64K ´ 16 bits. The  
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is  
not required. The unique cell architecture of the W29C102 results in fast program/erase operations  
with extremely low current consumption (compared to other comparable 5-volt flash memory  
products). The device can also be programmed and erased using standard EPROM programmers.  
FEATURES  
· Single 5-volt program and erase operations  
· Fast page-write operations  
· Low power consumption  
- Active current: 25 mA (typ.)  
- Standby current: 20 mA (typ.)  
- 128 words per page  
· Automatic program timing with internal VPP  
generation  
- Page program cycle: 10 mS (max.)  
- Effective word-program cycle time: 39 mS  
- Optional software-protected data write  
· Fast chip-erase operation: 50 mS  
· Read access time: 70/90/120 nS  
· Typical page program/erase cycles: 1K/10K  
· Ten-year data retention  
· End of program detection  
- Toggle bit  
- Data polling  
· Latched address and data  
· TTL compatible I/O  
· JEDEC standard word-wide pinouts  
· Software and hardware data protection  
· Available packages: 40-pin 600 mil DIP, TSOP  
and 44-pin PLCC  
Publication Release Date: March 1998  
- 1 -  
Revision A3  
W29C102  
PIN CONFIGURATIONS  
BLOCK DIAGRAM  
1
VDD  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
NC  
2
CE  
DQ15  
DQ14  
DQ13  
WE  
NC  
3
4
A15  
A14  
A13  
A12  
A11  
A10  
A9  
V
V
DD  
5
6
DQ12  
DQ11  
SS  
7
8
DQ10  
DQ9  
9
DQ0  
.
40-pin  
DIP  
CE  
OE  
WE  
10  
DQ8  
GND  
11  
OUTPUT  
BUFFER  
GND  
A8  
.
CONTROL  
12  
DQ7  
DQ6  
13  
A7  
A6  
DQ15  
14  
DQ5  
DQ4  
DQ3  
15  
A5  
A4  
A3  
16  
17  
DQ2  
DQ1  
18  
A2  
A1  
19  
DQ0  
20  
A0  
OE  
A0  
CORE  
.
.
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A9  
1
GND  
A8  
DECODER  
A10  
A11  
A12  
A13  
2
ARRAY  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
3
4
5
A14  
A15  
6
A15  
7
NC  
8
9
WE  
VDD  
NC  
40-pin  
TSOP  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
OE  
DQ0  
DQ1  
CE  
DQ15  
DQ14  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ13  
DQ12  
DQ11  
DQ10  
DQ9  
24  
23  
22  
21  
DQ7  
GND  
DQ8  
PIN DESCRIPTION  
A
1
5
A
1
4
/
C
E
V
D
D
D
Q
D
Q
D
Q
/
W
E
N
C
N
C
N
C
13 14 15  
SYMBOL  
PIN NAME  
2
1
44 43 42 41 40  
6
5
3
4
Address Inputs  
A0- A15  
7
39  
A13  
DQ12  
8
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A12  
A11  
A10  
A9  
DQ11  
DQ10  
DQ9  
9
Data Inputs/Outputs  
Chip Enable  
DQ0- DQ15  
10  
DQ8  
11  
12  
13  
14  
15  
16  
17  
44-pin  
PLCC  
CE  
OE  
GND  
GND  
NC  
NC  
A8  
A7  
Output Enable  
Write Enable  
Power Supply  
Ground  
DQ7  
DQ6  
DQ5  
DQ4  
A6  
A5  
WE  
VDD  
GND  
NC  
18  
20  
22 23  
25 26 27  
24 28  
19  
21  
D
Q
3
D
Q
2
D
Q
1
/
O
E
N
C
A
0
A
1
A
2
A
3
A
4
D
Q
0
No Connection  
- 2 -  
W29C102  
FUNCTIONAL DESCRIPTION  
Read Mode  
The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for  
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip  
is de-selected and only standby power will be consumed. OE is the output control and is used to gate  
data from the output pins. The data bus is in high impedance state when either CE or OE is high.  
Refer to the timing waveforms for further details.  
Page Write Mode  
The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of  
data within a page is to be changed, data for the entire page must be loaded into the device. Any  
word that is not loaded will be erased to "FFh" during programming of the page.  
The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists  
of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device.  
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously  
written into the memory array for non-volatile storage.  
During the word-load cycle, the addresses are latched by the falling edge of either CE or WE,  
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs  
first. If the host loads a second word into the page buffer within a word-load cycle time (TBLC) of 200  
mS, after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words  
can then be loaded consecutively. The page load cycle will be terminated and the internal  
programming cycle will start if no additional word is loaded into the page buffer. A7 to A15 specify the  
page address. All words that are loaded into the page buffer must have the same page address. A0 to  
A6 specify the word address within the page. The words may be loaded in any order; sequential  
loading is not required.  
In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written  
simultaneously into the memory array. The typical programming time is 5 mS. The entire memory  
array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host  
is free to perform other tasks such as fetching data from other locations in the system to prepare to  
write the next page.  
Software-protected Data Write  
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is  
enabled, any write operation requires a series of three-word program commands (with specific data to  
a specific address) to be performed before the data load operation. The three-word load command  
sequence begins the page load cycle, without which the write operation will not be activated. This  
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by  
noise during system power-up and power-down.  
The W29C102 is shipped with the software data protection enabled. To enable the software data  
protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The  
device will then enter the software data protection mode, and any subsequent write operation must be  
preceded by the three-word program command cycle. Once enabled, the software data protection will  
remain enabled unless the disable commands are issued. A power transition will not reset the  
Publication Release Date: March 1998  
- 3 -  
Revision A3  
W29C102  
software data protection feature. To reset the device to unprotected mode, a six-word command  
sequence is required. See Table 3 for specific codes and Figure 10 for the timing diagram.  
Hardware Data Protection  
The integrity of the data stored in the W29C102 is also hardware protected in the following ways:  
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.  
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than  
2.5V.  
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This  
prevents inadvertent writes during power-up or power-down periods.  
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out  
5 mS before any write (erase/program) operation.  
Data Polling (DQ7 & DQ15)- Write Status Detection  
The W29C102 includes a data polling feature to indicate the end of a programming cycle. When the  
W29C102 is in the internal programming cycle, any attempt to read DQ7 and/or DQ15 of the last word  
loaded during the page/word-load cycle will receive the complement of the true data. Once the  
programming cycle is completed. DQ7 will show the true data.  
Toggle Bit (DQ6 & DQ14)- Write Status Detection  
In addition to data polling, the W29C102 provides another method for determining the end of a  
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 and/or  
DQ14 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling  
between 0's and 1's will stop. The device is then ready for the next operation.  
5-Volt-only Software Chip Erase  
The chip-erase mode can be initiated by a six-word command sequence. After the command loading  
cycles, the device enters the internal chip erase mode, which is automatically timed and will be  
completed in 50 mS. The host system is not required to provide any control or timing during this  
operation.  
Product Identification  
The product ID operation outputs the manufacturer code and device code. Programming equipment  
automatically matches the device with its proper erase and programming algorithms.  
The manufacturer and device codes can be accessed by software or hardware operation. In the  
software access mode, a six-word command sequence can be used to access the product ID. A read  
from address 0000H outputs the manufacturer code (00DAh). A read from address 0001H outputs the  
device code (004Fh). The product ID operation can be terminated by a three-word command  
sequence.  
In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE  
high, and raising A9 to 12 volts.  
- 4 -  
W29C102  
TABLE OF OPERATING MODES  
Operating Mode Selection  
(VHH = 12V)  
MODE  
PINS  
CE OE WE  
ADDRESS  
DQ.  
Read  
VIL VIL VIH AIN  
VIL VIH VIL AIN  
Dout  
Din  
Write  
Standby  
Write Inhibit  
VIH  
X
X
VIL  
X
X
X
X
X
X
X
High Z  
High Z/DOUT  
High Z/DOUT  
High Z  
X
VIH  
X
Output Disable  
X
VIH  
5-Volt Software Chip Erase VIL VIH VIL AIN  
DIN  
Product ID  
VIL VIL VIH  
Manufacturer Code  
00DA (Hex)  
A0 = VIL; A1- A15 = VIL;  
A9 = VHH  
VIL VIL VIH  
Device Code  
004F (Hex)  
A0 = VIH; A1- A15 = VIL;  
A9 = VHH  
Publication Release Date: March 1998  
Revision A3  
- 5 -  
W29C102  
Command Codes for Software Data Protection  
BYTE SEQUENCE  
TO ENABLE PROTECTION  
TO DISABLE PROTECTION  
ADDRESS  
DATA  
ADDRESS  
5555H  
DATA  
AAAAH  
5555H  
8080H  
AAAAH  
5555H  
2020H  
0 Write  
1 Write  
2 Write  
3 Write  
4 Write  
5 Write  
5555H  
AAAAH  
2AAAH  
5555H  
2AAAH  
5555H  
5555H  
A0A0H  
-
-
-
-
-
-
5555H  
2AAAH  
5555H  
Software Data Protection Acquisition Flow  
Software Data Protection  
Enable Flow  
Software Data Protection  
Disable Flow  
Load data AAAA  
to  
address 5555  
Load data AAAA  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Load data 5555  
to  
address 2AAA  
Load data A0A0  
to  
address 5555  
Load data 8080  
to  
address 5555  
Load data AAAA  
to  
address 5555  
Sequentially load  
up to 128 words  
of page data  
(Optional page-load  
operation)  
Load data 5555  
to  
Pause 10 mS  
Exit  
address 2AAA  
Load data 2020  
to  
address 5555  
Pause 10 mS  
Exit  
Notes for software program code:  
Data Format: DQ15- DQ0 (Hex)  
Address Format: A14- A0 (Hex)  
- 6 -  
W29C102  
Command Codes for Software Chip Erase  
BYTE SEQUENCE  
0 Write  
ADDRESS  
DATA  
5555H  
2AAAH  
5555H  
5555H  
2AAAH  
5555H  
AAAAH  
5555H  
8080H  
AAAAH  
5555H  
1010H  
1 Write  
2 Write  
3 Write  
4 Write  
5 Write  
Software Chip Erase Acquisition Flow  
Load data AAAA  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Load data 8080  
to  
address 5555  
Load data AAAA  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Load data 1010  
to  
address 5555  
Pause 50 mS  
Exit  
Notes for software chip erase:  
Data Format: DQ15- DQ0 (Hex)  
Address Format: A14- A0 (Hex)  
Publication Release Date: March 1998  
Revision A3  
- 7 -  
W29C102  
Command Codes for Product Identification  
BYTE  
SEQUENCE  
ALTERNATE SOFTWARE (5)  
SOFTWARE PRODUCT  
IDENTIFICATION ENTRY  
SOFTWARE PRODUCT  
IDENTIFICATION EXIT  
PRODUCT IDENTIFICATION  
ENTRY  
ADDRESS  
DATA  
ADDRESS  
DATA  
ADDRESS  
DATA  
0 Write  
1 Write  
2 Write  
3 Write  
4 Write  
5 Write  
5555H  
AAH  
5555H  
2AAAH  
5555H  
5555H  
2AAAH  
5555H  
AAH  
55H  
80H  
AAH  
55H  
60H  
5555H  
AAH  
2AAAH  
55H  
2AAAH  
55H  
5555H  
90H  
5555H  
F0H  
-
-
-
-
-
-
-
-
-
-
-
-
Pause 10 mS  
Pause 10 mS  
Pause 10 mS  
Software Product Identification Acquisition Flow  
Product Identification Entry (1)  
Product Identification Exit (1)  
Product Identification Mode (2, 3)  
Load data AAAA  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Load data AAAA  
to  
address 5555  
Load data 8080  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Read address = 0  
data = 00DA  
Load data AAAA  
to  
address 5555  
Load data F0F0  
to  
address 5555  
Load data 5555  
to  
address 2AAA  
Read address = 1  
data = 004F  
Pause 10 mS  
(4)  
Load data 6060  
to  
address 5555  
Normal Mode  
Pause 10  
S
m
Notes for software product identification:  
(1) Data format: DQ15- DQ0 (Hex); address format: A14- A0 (Hex).  
(2) A1- A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.  
(3) The device does not remain in identification mode if power down.  
(4) The device returns to standard operation mode.  
(5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte  
command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used.  
- 8 -  
W29C102  
DC CHARACTERISTICS  
Absolute Maximum Ratings  
PARAMETER  
RATING  
-0.5 to +7.0  
0 to +70  
UNIT  
V
Power Supply Voltage to Vss Potential  
Operating Temperature  
°C  
Storage Temperature  
-65 to +150  
°C  
-0.5 to VDD +1.0  
V
D.C. Voltage on Any Pin to Ground Potential except OE  
Transient Voltage (<20 nS ) on Any Pin to Ground Potential  
-1.0 to VDD +1.0  
-0.5 to 12.5  
V
V
Voltage on A9 and OE Pin to Ground Potential  
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the  
device.  
DC Operating Characteristics  
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)  
PARAMETER  
SYM.  
TEST CONDITIONS  
LIMITS  
UNIT  
MIN. TYP. MAX.  
Power Supply Current ICC  
-
-
-
25  
2
60  
mA  
CE OE  
WE  
= VIH, all I/Os open  
=
= VIL,  
Address inputs = VIL/VIH, at f = 5 MHz  
CE  
Standby VDD Current  
(TTL input)  
ISB1  
ISB2  
ILI  
3
mA  
= VIH, all I/Os open  
Other inputs = VIL/VIH  
CE  
Standby VDD Current  
(CMOS input)  
20  
200  
mA  
= VDD -0.3V, all I/Os open  
Other inputs = VDD -0.3V/GND  
VIN = GND to VDD  
Input Leakage  
Current  
-
-
-
-
10  
10  
mA  
mA  
Output Leakage  
Current  
ILO VOUT = GND to VDD  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
VIL  
-
-
-
-
-
-
-
-
0.8  
V
V
V
V
V
VIH  
2.0  
-
-
VOL IOL = 2.1 mA  
VOH IOH = -0.4 mA  
0.45  
2.4  
4.2  
-
-
Output High Voltage  
CMOS  
VOH2  
IOH = -100 mA; VCC = 4.5V  
Publication Release Date: March 1998  
Revision A3  
- 9 -  
W29C102  
Power-up Timing  
PARAMETER  
SYMBOL  
TPU. READ  
TPU. WRITE  
TYPICAL  
UNIT  
mS  
Power-up to Read Operation  
Power-up to Write Operation  
100  
5
mS  
CAPACITANCE  
(VDD = 5.0V, TA = 25° C, f = 1 MHz)  
PARAMETER  
I/O Pin Capacitance  
Input Capacitance  
SYMBOL  
CI/O  
CONDITIONS  
VI/O = 0V  
MAX.  
12  
UNIT  
pf  
CIN  
VIN = 0V  
6
pf  
AC CHARACTERISTICS  
AC Test Conditions  
PARAMETER  
Input Pulse Levels  
CONDITIONS  
0V to 3.0V  
<5 nS  
Input Rise/Fall Time  
Input/Output Timing Level  
Output Load  
1.5V/1.5V  
1 TTL Gate and CL = 100 pF for 90/120 nS  
CL = 30 pF for 70 nS  
AC Test Load and Waveform  
+5V  
1.8K  
W
DOUT  
100 pF for 90/120 nS  
30 pF for 70 nS  
(Including Jig and Scope)  
1.3K  
W
Input  
Output  
3V  
1.5V  
1.5V  
0V  
Test Point  
Test Point  
- 10 -  
W29C102  
AC Characteristics, continued  
Read Cycle Timing Parameters  
(VDD = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)  
PARAMETER  
SYM. W29C102-70 W29C102-90 W29C102-12 UNIT  
MIN. MAX. MIN. MAX. MIN. MAX.  
Read Cycle Time  
TRC  
TCE  
TAA  
70  
-
-
90  
-
-
120  
-
nS  
nS  
nS  
nS  
nS  
Chip Enable Access Time  
Address Access Time  
Output Enable Access Time  
70  
70  
35  
25  
90  
90  
45  
25  
-
-
-
-
120  
120  
60  
-
-
TOE  
TCHZ  
-
-
-
-
30  
CE  
OE  
High to High-Z Output  
High to High-Z Output  
TOHZ  
TOH  
-
25  
-
-
25  
-
-
30  
-
nS  
nS  
Output Hold from Address Change  
0
0
0
Byte/Page-write Cycle Timing Parameters  
PARAMETER  
Write Cycle (erase and program)  
Address Setup Time  
SYMBOL  
MIN.  
TYP.  
MAX.  
UNIT  
mS  
nS  
TWC  
TAS  
TAH  
TCS  
-
0
-
-
-
-
10  
-
Address Hold Time  
50  
0
-
nS  
-
nS  
WE  
WE  
OE  
OE  
CE  
CE  
CE  
and  
and  
Setup Time  
Hold Time  
TCH  
TOES  
TOEH  
TCP  
0
0
-
-
-
-
-
-
-
-
-
-
-
-
nS  
nS  
nS  
nS  
nS  
nS  
High Setup Time  
High Hold Time  
Pulse Width  
0
70  
70  
100  
TWP  
WE  
WE  
Pulse Width  
TWPH  
High Width  
Data Setup Time  
Data Hold Time  
TDS  
TDH  
50  
0
-
-
-
-
-
nS  
nS  
mS  
Byte Load Cycle Time  
TBLC  
-
150  
Notes:  
All AC timing signals observe the following guidelines for determining setup and hold times:  
(a) High level signal's reference level is VIH.  
(b) Low level signal's reference level is VIL.  
Publication Release Date: March 1998  
Revision A3  
- 11 -  
W29C102  
AC Characteristics, continued  
(1)  
DATA Polling Characteristics  
PARAMETER  
SYMBOL  
TDH  
MIN.  
10  
TYP.  
MAX.  
UNIT  
nS  
Data Hold Time  
-
-
-
-
TOEH  
10  
nS  
OE Hold Time  
OE to Output Delay (2)  
Write Recovery Time  
Notes:  
TOE  
-
-
-
-
-
nS  
nS  
TWR  
0
(1) These parameters are characterized and not 100% tested.  
(2) See TOE spec in A.C. Read Cycle Timing Parameters.  
(1)  
Toggle Bit Characteristics  
PARAMETER  
Data Hold Time  
SYMBOL  
TDH  
MIN.  
10  
TYP.  
MAX.  
UNIT  
nS  
-
-
-
-
TOEH  
10  
nS  
OE Hold Time  
OE to Output Delay (2)  
TOE  
-
150  
0
-
-
-
-
-
-
nS  
nS  
nS  
TOEHP  
TWR  
OE High Pulse  
Write Recovery Time  
Notes:  
(1) These parameters are characterized and not 100% tested.  
(2) See TOE spec in A.C. Read Cycle Timing Parameters.  
- 12 -  
W29C102  
TIMING WAVEFORMS  
Read Cycle Timing Diagram  
T
RC  
Address A15-0  
CE  
T
CE  
T
OE  
OE  
T
OHZ  
V
IH  
WE  
T
OH  
T
CHZ  
High-Z  
High-Z  
DQ15-0  
Data Valid  
Data Valid  
AA  
T
WE Controlled Write Cycle Timing Diagram  
T
WC  
T
AS  
T
AH  
Address A15-0  
CE  
T
CS  
T
CH  
T
OES  
T
OEH  
WPH  
OE  
T
T
WP  
WE  
T
DS  
DQ15-0  
Data Valid  
T
DH  
Internal write starts  
Publication Release Date: March 1998  
Revision A3  
- 13 -  
W29C102  
Timing Waveforms, continued  
CE Controlled Write Cycle Timing Diagram  
AS  
T
TWC  
AH  
T
Address A15-0  
CE  
TCPH  
TCP  
TOES  
TOEH  
OE  
WE  
TDS  
High Z  
DQ15-0  
Data Valid  
TDH  
Internal Write Starts  
Page Write Cycle Timing Diagram  
TWC  
Address A15-0  
DQ15-0  
CE  
OE  
BLC  
T
TWPH  
TWP  
WE  
Word 1  
Word 0  
Word 2  
Word N-1  
Word N  
Internal Write Start  
- 14 -  
W29C102  
Timing Waveforms, continued  
DATA Polling Timing Diagram  
Address A15-0  
An  
An  
An  
An  
An  
WE  
CE  
T
OEH  
OE  
T
DH  
T
WR  
HIGH-Z  
T
OE  
DQ7 or  
DQ15  
Toggle Bit Timing Diagram  
WE  
CE  
T
OEH  
OE  
T
DH  
TOE  
T
WR  
HIGH-Z  
DQ6 or  
DQ14  
Notes:  
1. Toggling either  
or  
or both  
and  
will operate toggle bit.  
CE  
OE  
CE  
OE  
2. Beginning and ending state of DQ6 and DQ14 may vary.  
3. Any address location may be used but the address should not vary.  
Publication Release Date: March 1998  
Revision A3  
- 15 -  
W29C102  
Timing Waveforms, continued  
Page Write Timing Diagram Software Data Protection Mode  
TWC  
Byte/page load  
Three-byte sequence for  
cycle starts  
software data protection mode  
Address A15-0  
2AAA  
5555  
5555  
DQ15-0  
CE  
AAAA  
5555  
A0A0  
OE  
T
BLC  
TWP  
WE  
TWPH  
Word N  
(last word)  
Word 0  
Word N-1  
SW2  
SW1  
SW0  
Internal write starts  
Reset Software Data Protection Timing Diagram  
Six-word sequence for resetting  
software data protection mode  
T
WC  
Address A15-0  
5555  
5555  
2AAA  
5555  
5555  
5555  
2AAA  
DQ15-0  
CE  
AAAA  
2020  
5555  
8080  
AAAA  
OE  
T
WP  
T
BLC  
WE  
T
WPH  
SW0  
SW2  
SW3  
SW5  
SW4  
SW1  
Internal programming starts  
- 16 -  
W29C102  
Timing Waveforms, continued  
5-Volt-only Software Chip Erase Timing Diagram  
Six-word code for 5V-only software  
T
WC  
chip erase  
Address A15-0  
5555  
5555  
2AAA  
5555  
5555  
2AAA  
DQ15-0  
CE  
AAAA  
5555  
8080  
AAAA  
1010  
5555  
OE  
T
WP  
T
BLC  
WE  
T
WPH  
SW0  
SW2  
SW3  
SW5  
SW1  
SW4  
Internal programming starts  
Publication Release Date: March 1998  
Revision A3  
- 17 -  
W29C102  
ORDERING INFORMATION  
PART NO.  
ACCESS POWER SUPPLY  
STANDBY VDD  
CURRENT MAX.  
(mA)  
PACKAGE  
CYCLE  
TIME  
(nS)  
CURRENT MAX.  
(mA)  
W29C102-70  
70  
90  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
60  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
200  
600 mil DIP  
600 mil DIP  
600 mil DIP  
1K  
1K  
1K  
W29C102-90  
W29C102-12  
120  
70  
W29C102Q-70  
W29C102Q-90  
W29C102Q-12  
W29C102T-70  
W29C102T-90  
W29C102T-12  
W29C102P-70  
W29C102P-90  
W29C102P-12  
W29C102-70B  
W29C102-90B  
W29C102-12B  
W29C102Q-70B  
W29C102Q-90B  
W29C102Q-12B  
W29C102T-70B  
W29C102T-90B  
W29C102T-12B  
W29C102P-70B  
W29C102P-90B  
W29C102P-12B  
1K  
1K  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
44-pin PLCC  
90  
120  
70  
1K  
1K  
90  
1K  
120  
70  
1K  
1K  
90  
44-pin PLCC  
1K  
120  
70  
44-pin PLCC  
1K  
600 mil DIP  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
10K  
90  
600 mil DIP  
120  
70  
600 mil DIP  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 14 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
40-pin TSOP (10 mm ´ 20 mm)  
44-pin PLCC  
90  
120  
70  
90  
120  
70  
90  
44-pin PLCC  
120  
44-pin PLCC  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in  
applications where personal injury might occur as a consequence of product failure.  
- 18 -  
W29C102  
PACKAGE DIMENSIONS  
40-pin PDIP  
Dimension in mm  
Dimension in inches  
Min. Nom. Max.  
0.210  
Symbol  
A
Min. Nom.  
Max.  
5.33  
0.010  
0.25  
1
A
A
0.150  
0.016  
0.048  
0.008  
0.155  
0.018  
0.050  
0.010  
2.055  
0.600  
0.545  
0.100  
0.130  
0.160  
0.022  
0.054  
0.014  
2.070  
0.610  
3.81  
0.41  
1.22  
0.20  
3.94  
0.46  
4.06  
0.56  
1.37  
0.36  
52.58  
15.49  
13.97  
2.79  
3.56  
15  
2
B
B
1.27  
1
0.25  
c
D
E
52.20  
15.24  
13.84  
2.54  
D
0.590  
0.540  
0.090  
14.99  
13.72  
40  
21  
0.550  
0.110  
E
e
L
a
1
1
2.29  
3.05  
0
0.140  
15  
3.30  
0.120  
0
1
E
0.630  
0.670  
0.090  
16.00  
17.02  
2.29  
0.650  
16.51  
A
e
S
20  
1
Notes:  
1. Dimensions D Max & S include mold flash or  
tie bar burrs.  
E
S
2. Dimension E1 does not include interlead flash.  
c
3. Dimensions D & E1 include mold mismatch and  
Base Plane  
2
A
A
L
.
A1  
are determined at the mold parting line.  
4. Dimension B1 does not include dambar  
protrusion/intrusion.  
Seating Plane  
5. Controlling dimension: Inches.  
6. General appearance spec. should be based on  
final visual inspection spec.  
B
B
e1  
eA  
a
1
44-pin PLCC  
D
H
D
1
6
44  
40  
Dimension in inches  
Dimension in mm  
Symbol  
Max. Min. Nom.  
Min. Nom.  
Max.  
4.70  
0.185  
0.155  
7
39  
A
0.020  
0.51  
A
1
0.145 0.150  
0.026 0.028  
0.016 0.018  
3.68 3.81  
3.94  
0.81  
0.56  
0.36  
A 2  
b1  
b
0.032 0.66  
0.71  
0.022  
0.41 0.46  
E
H
E
E
0.008 0.010 0.014 0.20 0.25  
G
c
16.46 16.59 16.71  
16.46 16.59 16.71  
0.648 0.653 0.658  
0.648 0.653 0.658  
D
E
e
BSC  
1.27 BSC  
0.050  
0.590  
0.590  
0.680  
0.680  
14.99 15.49 16.00  
0.610 0.630  
0.610 0.630  
D
G
G
17  
29  
16.00  
17.53 17.78  
17.53 17.78  
14.99 15.49  
E
17.27  
17.27  
0.700  
0.700  
0.690  
0.690  
HD  
HE  
L
18  
28  
c
0.090 0.100  
2.54  
2.79  
0.10  
0.110 2.29  
0.004  
y
Notes:  
L
2
A
A
1. Dimension D & E do not include interlead flash.  
2. Dimension b1 does not include dambar  
protrusion/intrusion.  
3. Controlling dimension: Inches  
4. General appearance spec. should be based  
on final visual inspection spec.  
q
e
b
b1  
A 1  
Seating Plane  
y
GD  
Publication Release Date: March 1998  
Revision A3  
- 19 -  
W29C102  
Package Dimensions, continued  
40-pin TSOP (10 mm ´ 14 mm)  
D
H
Dimension in mm  
Dimension in Inches  
Min. Nom. Max.  
Symbol  
D
Min. Nom. Max.  
c
A
0.047  
1.20  
0.15  
0.05  
1
A 1 0.002  
0.006  
0.037 0.039 0.041  
0.007 0.009 0.011  
0.004 0.006 0.008  
2
A
0.95  
0.17 0.22  
0.10 0.15  
1.00  
1.05  
0.27  
0.20  
e
M
b
c
E
0.10(0.004)  
0.484 0.488 0.492 12.30 12.40 12.50  
0.390 0.394 0.398 9.90 10 10.10  
0.543 0.551 0.559 13.80 14.00 14.20  
D
E
b
D
H
0.020  
0.50  
0.60  
e
L
0.024 0.028  
0.020  
0.70  
0.50  
A
L
1
0.031  
0.004  
0.8  
A
A1  
2
0.000  
0
0.00  
0
0.10  
5
Y
q
q
L
3
5
3
Y
L1  
Controlling dimension: Millimeters  
40-pin TSOP (10 mm ´ 20 mm)  
D
H
Dimension in mm  
Dimension in Inches  
Min. Nom. Max.  
Symbol  
D
Min. Nom. Max.  
c
A
0.047  
0.006 0.05  
1.20  
1
1
0.002  
0.15  
A
0.95  
2
0.037 0.039 0.041  
1.00 1.05  
e
A
M
0.007 0.009 0.011 0.17 0.22 0.27  
0.004 0.006 0.008 0.10 0.15 0.20  
0.72 0.724 0.728 18.3 18.4 18.5  
b
c
E
0.10(0.004)  
D
b
0.390 0.394 0.398 9.90 10  
10.10  
E
20.0 20.2  
0.50  
D
0.780 0.787 0.795  
0.020  
19.8  
H
e
L
0.024  
0.031  
0.020  
0.028 0.50 0.60 0.70  
0.8  
1
A
L
2
A
A
0.00  
0
0.10  
5
0.000  
0
0.004  
5
Y
q
q
1
L
3
3
Y
L
1
Controlling dimension: Millimeters  
- 20 -  
W29C102  
VERSION HISTORY  
VERSION  
DATE  
Mar. 1998  
PAGE  
DESCRIPTION  
A3  
6
7
Add. pause 10 mS  
Add. pause 50 mS  
8
Correct the time from 10 mS to 10 mS  
Change VDD from 5% to 10% for 70 nS  
11  
Winbond Electronics (H.K.) Ltd.  
Winbond Electronics North America Corp.  
Headquarters  
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5796096  
123 Hoi Bun Rd., Kwun Tong,  
Winbond Microelectronics Corp.  
Winbond Systems Lab.  
2727 N. First Street, San Jose,  
CA 95134, U.S.A.  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
http://www.winbond.com.tw/  
Voice & Fax-on-demand: 886-2-27197006  
TEL: 408-9436666  
FAX: 408-5441798  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.,  
Taipei, Taiwan  
TEL: 886-2-27190505  
FAX: 886-2-27197502  
Note: All data and specifications are subject to change without notice.  
Publication Release Date: March 1998  
Revision A3  
- 21 -  

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