W29EE011Q90Z [WINBOND]
Flash, 128KX8, 90ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP-32;
| 型号： | W29EE011Q90Z |
| 厂家： | 
WINBOND |
| 描述： | Flash, 128KX8, 90ns, PDSO32, 8 X 14 MM, LEAD FREE, STSOP-32 光电二极管 内存集成电路 |
| 文件： | 总26页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W29EE011
128K × 8 CMOS FLASH MEMORY
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATIONS............................................................................................................. 4
BLOCK DIAGRAM ...................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION.................................................................................................... 6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Read Mode ..................................................................................................................... 6
Page Write Mode............................................................................................................ 6
Software-protected Data Write ....................................................................................... 6
Hardware Data Protection .............................................................................................. 7
Data Polling (DQ7)-Write Status Detection .................................................................... 7
Toggle Bit (DQ6)-Write Status Detection........................................................................ 7
5-Volt-only Software Chip Erase..................................................................................... 7
Product Identification ...................................................................................................... 7
7.
8.
TABLE OF OPERATING MODES .............................................................................................. 8
7.1
7.2
Operating Mode Selection .............................................................................................. 8
Command Codes for Software Data Protection ............................................................. 8
7.2.1
Software Data Protection Acquisition Flow...............................................................9
7.3
7.4
Command Codes for Software Chip Erase .................................................................. 10
7.3.1
Software Chip Erase Acquisition Flow....................................................................10
Command Codes for Product Identification.................................................................. 11
7.4.1
Software Product Identification Acquisition Flow ....................................................11
ELECTRICAL CHARACTERISTICS......................................................................................... 12
8.1
Absolute Maximum Ratings.......................................................................................... 12
8.2
DC Characteristics........................................................................................................ 12
8.2.1
8.2.2
8.2.3
Operating Characteristics.......................................................................................12
Power-up Timing ....................................................................................................12
Capacitance............................................................................................................13
8.3
AC Characteristics........................................................................................................ 13
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
AC Test Conditions.................................................................................................13
AC Test Load and Waveforms................................................................................13
Read Cycle Timing Parameters..............................................................................14
Byte/Page-write Cycle Timing Parameters .............................................................14
Data Polling and Toggle Bit Timing Parameters.....................................................15
9.
TIMING WAVEFORMS............................................................................................................. 16
9.1
9.2
9.3
Read Cycle Timing Diagram......................................................................................... 16
#WE Controlled Write Cycle Timing Diagram............................................................... 16
#CE Controlled Write Cycle Timing Diagram ............................................................... 17
Publication Release Date: April 11, 2006
- 1 -
Revision A18
W29EE011
9.4
9.5
9.6
9.7
9.8
9.9
Page Write Cycle Timing Diagram................................................................................ 17
#DATA Polling Timing Diagram.................................................................................... 18
Toggle Bit Timing Diagram ........................................................................................... 18
Page Write Timing Diagram Software Data Protection Mode ...................................... 19
Reset Software Data Protection Timing Diagram......................................................... 19
5 Volt-only Software Chip Erase Timing Diagram ........................................................ 20
10.
11.
12.
ORDERING INFORMATION..................................................................................................... 21
HOW TO READ THE TOP MARKING...................................................................................... 22
PACKAGE DIMENSIONS......................................................................................................... 23
12.1 32-pin P-DIP ................................................................................................................. 23
12.2 32-pin PLCC ................................................................................................................. 23
12.3 32-pin TSOP (8 x 20 mm)............................................................................................. 24
12.4 32-pin STSOP (8 x 14 mm) .......................................................................................... 24
VERSION HISTORY................................................................................................................. 25
13.
- 2 -
W29EE011
1. GENERAL DESCRIPTION
The W29EE011 is a 1-megabit, 5-volt only CMOS flash memory organized as 128K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W29EE011 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
y
y
Single 5-volt program and erase operations
Fast page-write operations
− 128 bytes per page
− Page program cycle: 10 mS (max.)
− Effective byte-program cycle time: 39 µS
− Optional software-protected data write
y
y
y
y
y
y
Fast chip-erase operation: 50 mS
Read access time: 90/150 nS
Page program/erase cycles: 1K/10K
Ten-year data retention
Software and hardware data protection
Low power consumption
− Active current: 25 mA (typ.)
− Standby current: 20 µA (typ.)
Automatic program timing with internal VPP generation
End of program detection
y
y
− Toggle bit
− Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin 600 mil DIP, 32-pin TSOP (8 x 20 mm), 32-pin STSOP
(8 x 14 mm), 32-pin PLCC, and Lead-free 32-pin PLCC
y
y
y
y
Publication Release Date: April 11, 2006
Revision A18
- 3 -
W29EE011
3. PIN CONFIGURATIONS
32
31
30
29
28
27
NC
1
2
VDD
A16
#WE
3
A15
A12
NC
A14
4
5
A13
A7
A6
6
A8
7
26
25
24
23
22
21
20
A9
A5
32-pin
DIP
8
A11
A4
9
A3
#OE
A10
10
A2
A1
11
12
13
#CE
DQ7
DQ6
A0
DQ0
14
15
16
19
DQ5
DQ4
DQ3
DQ1
DQ2
GND
18
17
A
1
2
A
V
D
D
#
W
E
A
1
5
1
6
N
C
N
C
3
4
2
1
32 31 30
29
28
27
26
25
24
23
22
21
A14
5
6
A7
A6
A13
A8
7
A5
32-pin
PLCC
8
A9
A4
9
A11
#OE
A3
10
11
12
13
A2
A10
A1
A0
#CE
DQ7
DQ0
14 15 16 17 18 19 20
D
Q
1
D
Q
2
G
N
D
D
Q
4
D
Q
5
D
Q
3
D
Q
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
#OE
A10
A11
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A9
A8
#CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A13
A14
NC
#WE
V DD
NC
32-pin
TSOP
A16
A15
A12
A7
A6
A5
A1
A2
A3
A4
- 4 -
W29EE011
4. BLOCK DIAGRAM
VDD
GND
#CE
#OE
#WE
DQ0
.
OUTPUT
BUFFER
.
CONTROL
DECODER
DQ7
A0
.
CORE
ARRAY
.
A16
5. PIN DESCRIPTION
SYMBOL
A0 − A16
DQ0 − DQ7
#CE
PIN NAME
Address Inputs
Data Inputs/Outputs
Chip Enable
#OE
#WE
Output Enable
Write Enable
Power Supply
Ground
VDD
GND
NC
No Connection
Publication Release Date: April 11, 2006
Revision A18
- 5 -
W29EE011
6. FUNCTIONAL DESCRIPTION
6.1 Read Mode
The read operation of the W29EE011 is controlled by #CE and #OE, both of which have to be low for
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is
de-selected and only standby power will be consumed. #OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.
Refer to the timing waveforms for further details.
6.2 Page Write Mode
The W29EE011 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing #CE and #WE low and #OE high. The write procedure
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device. Step 2 is an internal programming cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either #CE or #WE,
whichever occurs last. The data are latched by the rising edge of either #CE or #WE, whichever occurs
first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
µS, after the initial byte-load cycle, the W29EE011 will stay in the page load cycle. Additional bytes can
then be loaded consecutively. The page load cycle will be terminated and the internal programming
cycle will start if no additional byte is loaded into the page buffer within 300 µS (TBLCO) from the last
byte-load cycle, i.e., there is no subsequent #WE high-to-low transition after the last rising edge of
#WE. A7 to A16 specify the page address. All bytes that are loaded into the page buffer must have the
same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any
order; sequential loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
6.3 Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up and power-down.
The W29EE011 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required. See Table 3 for specific codes and Figure 10 for the timing diagram.
- 6 -
W29EE011
6.4 Hardware Data Protection
The integrity of the data stored in the W29EE011 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is
less than 3.8V.
(3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
6.5 Data Polling (DQ7)-Write Status Detection
The W29EE011 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE011 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during
the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is
completed. DQ7 will show the true data.
6.6 Toggle Bit (DQ6)-Write Status Detection
In addition to data polling, the W29EE011 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.
6.7 5-Volt-only Software Chip Erase
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.
6.8 Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C1h). The product ID operation can be terminated by a three-byte command sequence.
In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE
high, and raising A9 to 12 volts.
Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details.
Publication Release Date: April 11, 2006
- 7 -
Revision A18
W29EE011
7. TABLE OF OPERATING MODES
7.1 Operating Mode Selection
Operating Range = 0 to 70°C (Ambient Temperature), VDD = 5V ±10%, VSS = 0V, VHH = 12V
PINS
ADDRESS
MODE
#CE
VIL
VIL
VIH
X
#OE #WE
DQ.
Read
VIL
VIH
X
VIH
VIL
X
AIN
AIN
X
Dout
Din
High Z
Write
Standby
Write Inhibit
VIL
X
X
X
X
X
High Z/DOUT
High Z/DOUT
High Z
X
X
VIH
X
Output Disable
VIH
5-Volt Software Chip
Erase
VIL
VIL
VIL
VIH
VIL
VIL
VIL
VIH
VIH
AIN
DIN
Manufacturer Code DA
(Hex)
A0 = VIL; A1 − A16 = VIL;
Product ID
A9 = VHH
Device Code
C1 (Hex)
A0 = VIH; A1 − A16 = VIL;
A9 = VHH
7.2 Command Codes for Software Data Protection
TO ENABLE PROTECTION
TO DISABLE PROTECTION
BYTE SEQUENCE
ADDRESS
DATA
ADDRESS
5555H
DATA
AAH
55H
80H
AAH
55H
20H
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
5555H
AAH
2AAAH
55H
2AAAH
5555H
5555H
A0H
-
-
-
-
-
-
5555H
2AAAH
5555H
- 8 -
W29EE011
7.2.1 Software Data Protection Acquisition Flow
Software Data Protection
Disable Flow
Software Data Protection
Enable Flow
Load data AA
to
Load data AA
to
address 5555
address 5555
Load data 55
to
Load data 55
to
address 2AAA
address 2AAA
Load data 80
to
Load data A0
to
address 5555
address 5555
(Optional page
load operation)
Sequentially load
up to 128 bytes
of page data
Load data AA
to
address 5555
Pause 10 mS
Exit
Load data 55
to
address 2AAA
Load data 20
to
address 5555
Pause 10 mS
Exit
Notes for software program code:
Data Format: DQ7 − DQ0 (Hex)
Address Format: A14 − A0 (Hex)
Publication Release Date: April 11, 2006
Revision A18
- 9 -
W29EE011
7.3 Command Codes for Software Chip Erase
BYTE SEQUENCE
0 Write
ADDRESS
5555H
2AAAH
5555H
5555H
2AAAH
5555H
DATA
AAH
55H
80H
AAH
55H
10H
1 Write
2 Write
3 Write
4 Write
5 Write
7.3.1 Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Exit
Notes for software chip erase:
Data Format: DQ7 − DQ0 (Hex)
Address Format: A14 − A0 (Hex)
- 10 -
W29EE011
7.4 Command Codes for Product Identification
SOFTWARE PRODUCT
SOFTWARE PRODUCT
IDENTIFICATION EXIT
IDENTIFICATION ENTRY
BYTE SEQUENCE
ADDRESS
5555H
2AAAH
5555H
5555H
2AAAH
DATA
AAH
55H
80H
AAH
55H
60H
ADDRESS
5555H
2AAAH
5555H
DATA
AAH
55H
F0H
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
-
-
-
-
-
-
5555H
Pause 10 µS
Pause 10 µS
7.4.1 Software Product Identification Acquisition Flow
Product Identification Entry(1) Product Identification Mode(2, 3)
Product Identification Exit(1)
Load data AA
to
address 5555
Load data 55
to
Load data AA
to
address 2AAA
address 5555
Load data 80
Load data 55
to
Read address = 0
to
data = DA
address 5555
address 2AAA
Load data AA
to
Load data FO
to
address 5555
address 5555
Load data 55
Read address = 1
to
Sm
Pause 10
µ
data = C1
address 2AAA
(4)
Load data 60
to
Normal Mode
address 5555
Pause 10
S
µ
Notes for software product identification:
(1) Data format: DQ7 − DQ0 (Hex); address format: A14 − A0 (Hex).
(2) A1 − A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.
Publication Release Date: April 11, 2006
Revision A18
- 11 -
W29EE011
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER
Power Supply Voltage to GND Potential
Operating Temperature
RATING
-0.5 to +7.0
0 to +70
UNIT
V
°C
°C
V
V
V
Storage Temperature
-65 to +150
D.C. Voltage on Any Pin to Ground Potential Except #OE
Transient Voltage (< 20 nS) on Any Pin to Ground Potential
Voltage on #OE Pin to Ground Potential
-0.5 to VDD +1.0
-1.0 to VDD +1.0
-0.5 to 12.5
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8.2 DC Characteristics
8.2.1 Operating Characteristics
(VDD = 5.0V ±10%, GND = 0V, TA = 0 to 70° C)
LIMITS
TYP.
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MIN.
MAX.
#CE = #OE = VIL, #WE = VIH,
all I/Os open
Power Supply Current
ICC
-
-
50
mA
Address inputs = VIL/VIH,
at f = 5 MHz
ISB1 #CE = VIH, all I/Os open
Other inputs = VIL/VIH
Standby VDD Current
(TTL input)
-
-
2
3
mA
#CE = VDD -0.3V, all I/Os open
Standby VDD Current
(CMOS input)
ISB2
20
100
µA
Other inputs = VDD -0.3V/GND
Input Leakage Current
Output Leakage Current ILO
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ILI
VIN = GND to VDD
-
-
-
-
-
-
-
-
1
10
0.8
µA
µA
V
V
V
VIN = GND to VDD
VIL
VIH
-
-
-0.3
2.0
-
VDD +0.5
0.45
-
VOL IOL = 2.1 mA
VOH IOH = -0.4 mA
2.4
V
8.2.2 Power-up Timing
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
SYMBOL
TPU.READ
TPU.WRITE
TYPICAL
UNIT
100
5
µS
mS
- 12 -
W29EE011
8.2.3 Capacitance
(VDD = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CONDITIONS
VI/O = 0V
MAX.
12
6
UNIT
pF
pF
CI/O
CIN
VIN = 0V
8.3 AC Characteristics
8.3.1 AC Test Conditions
(VDD = 5V ±10%)
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise/Fall Time
Input/Output Timing Level
Output Load
< 5 nS
1.5V/1.5V
1 TTL Gate and CL = 30 pF for 70 nS and 100 pF for others.
8.3.2 AC Test Load and Waveforms
+5V
1.8K ohm
D
OUT
100 pF for 90/120/150 nS
30 pF for 70 nS
1.3K ohm
(Including Jig and Scope)
Input
Output
3V
1.5V
1.5V
0V
Test Point
Test Point
Publication Release Date: April 11, 2006
Revision A18
- 13 -
W29EE011
8.3.3 Read Cycle Timing Parameters
(VDD = 5.0V ±10 %, VDD = 5.0 ±5 % for 70 nS, GND = 0V, TA = 0 to 70° C)
W29EE011-90
W29EE011-15
PARAMETER
Read Cycle Time
Chip Enable Access Time
Address Access Time
Output Enable Access Time
#CE Low to Active Output
#OE Low to Active Output
#CE High to High-Z Output
#OE High to High-Z Output
Output Hold from Address Change
SYMBOL
UNIT
MIN.
MAX.
MIN.
MAX.
TRC
TCE
TAA
TOE
TCLZ
TOLZ
TCHZ
TOHZ
TOH
90
-
-
-
150
-
-
-
150
150
70
-
nS
nS
nS
nS
nS
nS
nS
nS
nS
90
90
45
-
-
-
0
0
-
-
0
0
0
-
-
0
-
-
45
45
-
45
45
-
8.3.4 Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (Erase and Program)
Address Setup Time
Address Hold Time
#WE and #CE Setup Time
#WE and #CE Hold Time
#OE High Setup Time
#OE High Hold Time
#CE Pulse Width
#WE Pulse Width
#WE High Width
Data Setup Time
Data Hold Time
SYMBOL
TWC
TAS
TAH
TCS
MIN.
-
0
50
0
0
10
10
70
70
150
50
10
0.22
300
TYP.
MAX.
10
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
µS
µS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TCH
TOES
TOEH
TCP
TWP
TWPH
TDS
-
-
TDH
-
200
-
Byte Load Cycle Time
Byte Load Cycle Time-out
TBLC
TBLCO
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
- 14 -
W29EE011
8.3.5 Data Polling and Toggle Bit Timing Parameters
W29EE011-90
W29EE011-15
PARAMETER
SYM.
UNIT
MIN.
MAX.
45
MIN.
MAX.
70
#OE to Data Polling Output Delay
#CE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
#CE to Toggle Bit Output Delay
TOEP
TCEP
TOET
TCET
-
-
-
-
-
-
-
-
nS
nS
nS
nS
90
150
70
45
90
150
Publication Release Date: April 11, 2006
Revision A18
- 15 -
W29EE011
9. TIMING WAVEFORMS
9.1 Read Cycle Timing Diagram
TRC
Address A16-0
#CE
TCE
TOE
#OE
TOHZ
TOLZ
V
IH
#WE
TCLZ
TOH
Data Valid
TCHZ
High-Z
High-Z
DQ7-0
Data Valid
AA
T
9.2 #WE Controlled Write Cycle Timing Diagram
T
BLCO
T
WC
T
AS
T
AH
Address A16-0
#CE
T
CS
T
CH
T
OES
T
OEH
WPH
#OE
#WE
T
WP
T
T
DS
DQ7-0
Data Valid
T
DH
Internal write starts
- 16 -
W29EE011
9.3 #CE Controlled Write Cycle Timing Diagram
T
BLCO
AS
T
T
WC
TAH
Address A16-0
#CE
T
CPH
T
CP
T
OES
T
OEH
#OE
#WE
T
DS
High Z
DQ7-0
Data Valid
T
DH
Internal Write Starts
9.4 Page Write Cycle Timing Diagram
TWC
Address A16-0
DQ7-0
#CE
#OE
TBLCO
BLC
T
TWPH
TWP
#WE
Byte 1
Byte 0
Byte 2
Byte N-1
Byte N
Internal Write Start
Publication Release Date: April 11, 2006
Revision A18
- 17 -
W29EE011
9.5 #DATA Polling Timing Diagram
Address A16-0
#WE
T
CEP
#CE
#OE
T
OES
T
OEH
T
OEP
DQ7-0
X
X
X
X
T
WC
9.6 Toggle Bit Timing Diagram
Address A16-0
#WE
#CE
TOES
TOEH
#OE
DQ6
TWC
- 18 -
W29EE011
9.7 Page Write Timing Diagram Software Data Protection Mode
TWC
Byte/page load
Three-byte sequence for
software data protection mode
cycle starts
Address A16-0
DQ6
2AAA
5555
5555
A0
AA
55
#CE
#OE
TBLC
TBLCO
TWP
#WE
TWPH
Byte N
(last byte)
Byte 0
Byte N-1
SW1
SW2
SW0
Internal write starts
9.8 Reset Software Data Protection Timing Diagram
Six-byte sequence for resetting
software data protection mode
TWC
Address A16-0
5555
80
5555
5555
2AAA
55
5555
AA
2AAA
55
DQ7-0
#CE
AA
20
#OE
#WE
TWP
TBLC
TBLCO
TWPH
SW0
SW2
SW3
SW5
SW4
SW1
Internal programming starts
Publication Release Date: April 11, 2006
Revision A18
- 19 -
W29EE011
9.9 5 Volt-only Software Chip Erase Timing Diagram
Six-byte code for 5V-only software
chip erase
TWC
Address A16-0
5555
80
5555
5555
2AAA
55
5555
AA
2AAA
55
DQ7-0
#CE
AA
10
#OE
#WE
TWP
TBLC
TBLCO
TWPH
SW0
SW2
SW3
SW5
SW4
SW1
Internal programming starts
- 20 -
W29EE011
10. ORDERING INFORMATION
POWER
STANDBY VDD
CURRENT
ACCESS
HARDWARE
CYCLING SID READ
FUNCTION
SUPPLY
PART NO.
TIME
(NS)
PACKAGE
600 mil DIP
CURRENT
MAX. (MA)
MAX. (µA)
W29EE011-90
W29EE011-15
90
150
50
50
100
100
1K
1K
Y
Y
600 mil DIP
TSOP
W29EE011T-90
W29EE011T-15
W29EE011Q-90
W29EE011Q-15
90
150
90
50
50
50
50
100
100
100
100
1K
1K
1K
1K
Y
Y
Y
Y
(8 x 20 mm)
TSOP
(8 x 20 mm)
STSOP
(8 x 14 mm)
STSOP
(8 x 14 mm)
150
W29EE011P-90
W29EE011P-15
W29EE011-90B
W29EE011-15B
W29EE011T90B
W29EE011T15B
W29EE011Q90B
W29EE011Q15B
W29EE011P90B
W29EE011P15B
W29EE011-90N
W29EE011-15N
W29EE011P90N
W29EE011P15N
90
150
90
150
90
150
90
150
90
150
90
150
90
50
50
50
50
50
50
50
50
50
50
50
50
50
50
100
100
100
100
100
100
100
100
100
100
100
100
100
100
32-pin PLCC
32-pin PLCC
600 mil DIP
1K
1K
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
10K
10K
10K
10K
10K
10K
10K
10K
1K
600 mil DIP
TSOP (8x20mm)
TSOP (8x20mm)
STSOP (8x14mm)
STSOP (8x14mm)
32-pin PLCC
32-pin PLCC
600 mil DIP
600 mil DIP
32-pin PLCC
32-pin PLCC
1K
1K
1K
150
Lead-free 32-pin
W29EE011P90Z
90
50
100
1K
Y
PLCC
Lead-free 32-pin
PLCC
STSOP (8x14mm)
W29EE011P15Z
150
90
50
50
100
100
1K
Y
Y
W29EE011Q90Z
10K
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
3. In Hardware SID Read column: Y = with SID read function; N = without SID read function.
Publication Release Date: April 11, 2006
Revision A18
- 21 -
W29EE011
11. HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W29EE011P15N
W29EE011P15N
2138977A-A12
149OBRA
1st line: winbond logo
2nd line: the part number: W29EE011P15N
3rd line: the lot number
4th line: the tracking code: 149 O B RA
149: Packages made in ’01, week 49
O: Assembly house ID: A means ASE, O means OSE, ...etc.
B: IC revision; A means version A, B means version B, ...etc.
RA: Process code
- 22 -
W29EE011
12. PACKAGE DIMENSIONS
12.1 32-pin P-DIP
Dimension in inches
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
5.33
0.210
0.010
0.150 0.155 0.160 3.81
0.25
A
A
B
1
3.94
0.46
4.06
0.56
2
0.016 0.018
0.41
1.22
0.022
0.054
0.050
1.27
1.37
0.048
0.008
1
B
0.010 0.014 0.20
1.650 1.660
0.25
0.36
c
D
17
32
41.91
15.24
13.97
2.54
42.16
15.49
14.10
2.79
D
E
0.610
0.555
0.110
0.590 0.600
14.99
13.84
2.29
0.545
0.550
E
1
0.090 0.100
e1
1
E
3.05
0
3.30
0.120 0.130 0.140
15
3.56
15
L
0
a
0.630 0.650 0.670 16.00 16.51 17.02
0.085
e
S
A
2.16
16
1
Notes:
E
S
1.Dimensions D Max. & S include mold flash or
tie bar burrs.
c
2.Dimension E1 does not include interlead flash.
A
2
A
L
A1
Base Plane
3.Dimensions D & E1 include mold mismatch and
.
are determined at the mold parting line.
4.Dimension B1 does not include dambar
protrusion/intrusion.
Seating Plane
5.Controlling dimension: Inches
B
B
1
e
eA
a
6.General appearance spec. should be based on
final visual inspection spec.
1
12.2 32-pin PLCC
Dimension in Inches
Min. Nom. Max. Min. Nom. Max.
Dimension in mm
Symbol
H E
E
0.140
3.56
A
0.020
0.105
0.026
0.016
0.008
0.50
2.67
0.66
0.41
0.20
A
A
b
b
c
1
2
1
4
1
32
30
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.51
0.115
0.032
0.022
0.014
2.80
0.71
0.46
0.25
13.97
11.43
1.27
12.9
2.93
0.81
0.56
0.35
5
29
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
13.89
11.35
1.12
14.05
11.51
1.42
D
E
e
12.45
9.91
13.46
10.92
15.11
12.57
2.41
G
G
H
H
D
G
D
0.410
0.590
0.49
10.41
14.99
12.45
2.29
E
D
E
D
HD
14.86
12.32
1.91
0.090
L
0.10
y
0
10
0
10
θ
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches
14
20
c
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A
θ
e
1
b
b 1
A
Seating Plane
y
E
G
Publication Release Date: April 11, 2006
Revision A18
- 23 -
W29EE011
Package Dimensions, continued
12.3 32-pin TSOP (8 x 20 mm)
H D
D
Dimension in Inches
Min. Nom. Max.
Dimension in mm
Symbol
Min. Nom.
Max.
__
__
__
__
A
1.20
0.15
1.05
0.23
0.047
0.006
c
__
__
0.002
0.037
0.05
0.95
A 1
A 2
b
0.041
0.009
1.00
0.20
0.15
0.039
M
e
0.007 0.008
0.17
0.12
E
c
0.005 0.006
0.720 0.724
0.17
0.007
0.728
0.10(0.004)
18.30 18.40 18.50
D
b
0.311 0.315
7.90
8.00
8.10
0.319
E
0.780 0.787
19.80
__
20.00 20.20
0.795
__
HD
e
__
__
0.020
0.50
0.016 0.020
0.40
__
0.50
0.60
__
L
0.024
__
__
0.031
0.80
__
L
1
A
__
0.000
0.004
5
0.10
5
0.00
1
Y
A2
A1
1
3
3
θ
θ
L
Y
L1
Note:
Controlling dimension: Millimeters
12.4 32-pin STSOP (8 x 14 mm)
HD
D
Dimension in Inches Dimension in mm
Symbol
Max.
1.20
Min. Nom. Max. Min. Nom.
c
0.047
A
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
0.15
1
A
e
0.040
1.00
0.22
2
A
1.05
0.27
0.007 0.009 0.010
b
E
0.004
0.008
-----
12.40
8.00
0.21
-----
0.488
c
b
D
E
0.315
0.551
0.020
14.00
D
H
0.50
0.60
0.80
e
L
0.50
0.70
0.020 0.024 0.028
0.031
1
L
0.000
0.00
0
0.10
5
0.004
5
Y
0
3
3
θ
θ
A
A
1 A
2
L
Y
L
1
- 24 -
W29EE011
13. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A9
Feb. 1998
6
7
Add pause 10 mS
Add pause 50 mS
8
Correct the time 10 mS to 10 µS
1, 17
Add cycing 100 item
A10
A11
A12
Jun. 1998
Aug. 1998
Jul. 1999
1, 10, 11, 12, 17 Add 70 nS bining
1, 2, 17, 19
1, 17
Add TSOP package
Change endurance cycles as 1K/10K
Delete 70, 120 nS bining
1, 11, 12, 17
1, 17, 18
4, 17
Delete SOP package
A13
A14
Dec. 2000
Mar. 2001
Add in Hardware SID Read Function note
Add in TSOP (8 x 14 mm) package
Correct Part No. in Ordering Information
1, 17, 18
17
Modify VDD Power Up/Down Detection in Hardware
Data Protection
A15
Feb. 19, 2002
4
18
1, 17, 20
1, 17
23
Add HOW TO READ THE TOP MARKING
Rename TSOP (8 x 14 mm) as STSOP (8 X 14 mm)
Add in Lead-free 32-pin PLCC package
Add important notice
A16
A17
A18
Feb. 17, 2004
April 15 ,2005
April 11, 2006
21
Add W29EE011Q90Z package
Publication Release Date: April 11, 2006
- 25 -
Revision A18
W29EE011
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further more, Winbond products are not intended for applications wherein failure of Winbond
products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 26 -
相关型号：
©2020 ICPDF网 联系我们和版权申明