W29EE512Q-70 [WINBOND]
64K X 8 CMOS FLASH MEMORY; 64K ×8 CMOS FLASH MEMORY
| 型号： | W29EE512Q-70 |
| 厂家： | 
WINBOND |
| 描述： | 64K X 8 CMOS FLASH MEMORY |
| 文件： | 总22页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W29EE512
´ 8 CMOS FLASH MEMORY
64K
GENERAL DESCRIPTION
The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K ´ 8 bits. The device
can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not
required. The unique cell architecture of the W29EE512 results in fast program/erase operations with
extremely low current consumption (compared to other comparable 5-volt flash memory products). The
device can also be programmed and erased using standard EPROM programmers.
FEATURES
· Single 5-volt program and erase operations
· Fast page-write operations
· Low power consumption
- Active current: 50 mA (max.)
- Standby current: 100 mA (max.)
- 128 bytes per page
· Automatic program timing with internal VPP
generation
- Page program cycle: 10 mS (max.)
- Effective byte-program cycle time: 39 mS
- Optional software-protected data write
· Fast chip-erase operation: 50 mS
· Read access time: 70/90/120 nS
· Typical page program/erase cycles: 1K/10K
· Ten-year data retention
· End of program detection
- Toggle bit
- Data polling
· Latched address and data
· TTL compatible I/O
· JEDEC standard byte-wide pinouts
· Software and hardware data protection
· Available packages: 32-pin PLCC, TSOP and
VSOP
Publication Release Date: February 18, 2002
- 1 -
Revision A7
W29EE512
PIN CONFIGURATIONS
BLOCK DIAGRAM
VDD
VSS
A
A
V
C
C
#
W
E
1
N
C
N
C
N
C
1
2
5
DQ0
4
3
2
1
32 31 30
#CE
.
OUTPUT
BUFFER
.
#OE
5
6
29
28
27
26
25
24
23
22
21
A14
CONTROL
A7
A6
A13
A8
DQ7
#WE
7
A5
8
32-pin
PLCC
A9
A4
9
A11
OE
A3
10
11
12
13
#
A2
A10
CE
A1
#
A0
DQ7
DQ0
A0
14 15 16 17 18 19 20
CORE
ARRAY
.
DECODER
D
Q
1
D
Q
2
G
N
D
D
Q
3
D
Q
4
D
Q
5
D
Q
6
.
A15
1
2
3
32
#
A10
OE
A11
A9
A8
A13
A14
NC
31
30
29
28
27
26
25
#
CE
4
5
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
6
7
8
WE
#
32-pin
TSOP
VCC
NC
NC
A15
A12
A7
9
24
23
22
21
20
19
18
17
10
11
12
13
14
15
16
A6
A1
PIN DESCRIPTION
A5
A2
A3
A4
SYMBOL
PIN NAME
OE
1
2
3
32
#
A11
A9
A8
A13
A14
NC
Address Inputs
Data Inputs/Outputs
A0 - A15
DQ0 - DQ7
#CE
A10
#CE
31
30
29
28
27
26
25
4
5
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
6
7
WE
#
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
32-pin
VSOP
VCC
NC
NC
A15
A12
A7
8
9
24
23
22
2
10
#OE
11
12
13
14
15
16
20
1
#WE
A6
A1
A5
1
A2
A3
VCC
A4
17
GND
NC
No Connection
- 2 -
W29EE512
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29EE512 is controlled by
and
, both of which have to be low for
#OE
#CE
the host to obtain data from the outputs.
is used for device selection. When
is high, the chip
#CE
is de-selected and only standby power will be consumed.
#CE
is the output control and is used to gate
#OE
data from the output pins. The data bus is in high impedance state when either
Refer to the timing waveforms for further details.
or
is high.
#OE
#CE
Page Write Mode
The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of
data within a page is to be changed, data for the entire page must be loaded into the device. Any byte
that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing
and
low and
high. The write procedure
#OE
#CE
#WE
consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the
device. Step 2 is an internal programming cycle, during which the data in the page buffers are
simultaneously written into the memory array for non-volatile storage.
During the byte-load cycle, the addresses are latched by the falling edge of either
or
,
#WE
#CE
, whichever occurs
whichever occurs last. The data are latched by the rising edge of either
or
#CE #WE
first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 200
mS, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can
then be loaded consecutively. The page load cycle will be terminated and the internal programming
cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the page address. All
bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte
address within the page. The bytes may be loaded in any order; sequential loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written
simultaneously into the memory array. Before the completion of the internal programming cycle, the
host is free to perform other tasks such as fetching data from other locations in the system to prepare
to write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-byte program commands (with specific data to a
specific address) to be performed before the data load operation. The three-byte load command
sequence begins the page load cycle, without which the write operation will not be activated. This write
scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise
during system power-up and power-down.
The W29EE512 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-byte program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the software
data protection feature. To reset the device to unprotected mode, a six-byte command sequence is
required.
Publication Release Date: February 18, 2002
- 3 -
Revision A7
W29EE512
Hardware Data Protection
The integrity of the data stored in the W29EE512 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A pulse of less than 15 nS in duration will not initiate a write cycle.
#WE
(2) VCC Power Up/Down Detection: The programming and read operation are inhibited when VCC is
less than 2.8V.
(3) Write Inhibit Mode: Forcing
low,
high, or
high will inhibit the write operation. This
#WE
#OE
#CE
prevents inadvertent writes during power-up or power-down periods.
Data Polling (DQ7)-Write Status Detection
The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the
W29EE512 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during
the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is
completed. DQ7 will show the true data.
Toggle Bit (DQ6)-Write Status Detection
In addition to data polling, the W29EE512 provides another method for determining the end of a
program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's
and 1's will stop. The device is then ready for the next operation.
5-Volt-only Software Chip Erase
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycles, the device enters the internal chip erase mode, which is automatically timed and will be
completed in 50 mS. The host system is not required to provide any control or timing during this
operation.
Product Identification
The product ID operation outputs the manufacturer code and device code. Programming equipment
automatically matches the device with its proper erase and programming algorithms.
The manufacturer and device codes can be accessed by software or hardware operation. In the
software access mode, a six-byte command sequence can be used to access the product ID. A read
from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the
device code (C8h). The product ID operation can be terminated by a three-byte command sequence.
In the hardware access mode, access to the product ID is activated by forcing
and
low,
#OE
#CE
high, and raising A9 to 12 volts.
#WE
- 4 -
W29EE512
TABLE OF OPERATING MODES
Operating Mode Selection
(Operating Range = 0 to 70° C (Ambient Temperature), VCC = 5V ±10%, VSS = 0V, VHH = 12V)
MODE
PINS
#CE #OE #WE
ADDRESS
DQ.
Read
VIL
VIL
VIH
X
VIL
VIH
X
VIH AIN
Dout
Write
VIL
X
AIN
X
Din
Standby
High Z
Write Inhibit
VIL
X
X
X
High Z/DOUT
High Z/DOUT
High Z
X
VIH
X
X
Output Disable
X
VIH
VIH
VIL
X
5-Volt Software Chip Erase
Product ID
VIL
VIL
VIL
VIH
AIN
DIN
Manufacturer Code
DA (Hex)
A0 = VIL; A1 - A15 = VIL;
A9 = VHH
VIL
VIL
VIH
Device Code
C8 (Hex)
A0 = VIH; A1 - A15 = VIL;
A9 = VHH
Publication Release Date: February 18, 2002
Revision A7
- 5 -
W29EE512
Command Codes for Software Data Protection
BYTE SEQUENCE
TO ENABLE PROTECTION
TO DISABLE PROTECTION
ADDRESS
DATA
ADDRESS
5555H
DATA
AAH
55H
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
5555H
AAH
2AAAH
55H
2AAAH
5555H
5555H
A0H
80H
-
-
-
-
-
-
5555H
AAH
55H
2AAAH
5555H
20H
Software Data Protection Acquisition Flow
Software Data Protection
Enable Flow
Software Data Protection
Disable Flow
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data 80
to
address 5555
Load data AA
to
address 5555
Sequentially load
up to 128 bytes
of page data
(Optional page-load
operation)
Load data 55
to
Pause 10 mS
Exit
address 2AAA
Load data 20
to
address 5555
Pause 10 mS
Exit
Notes for software program code:
Data Format: DQ7 - DQ0 (Hex)
Address Format: A14 - A0 (Hex)
- 6 -
W29EE512
Command Codes for Software Chip Erase
BYTE SEQUENCE
0 Write
ADDRESS
5555H
DATA
AAH
55H
1 Write
2AAAH
5555H
2 Write
80H
3 Write
5555H
AAH
55H
4 Write
2AAAH
5555H
5 Write
10H
Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Exit
Notes for software chip erase:
Data Format: DQ7 - DQ0 (Hex)
Address Format: A14 - A0 (Hex)
Publication Release Date: February 18, 2002
Revision A7
- 7 -
W29EE512
Command Codes for Product Identification
BYTE
SEQUENCE
ALTERNATE SOFTWARE (5)
SOFTWARE PRODUCT
IDENTIFICATION ENTRY
SOFTWARE PRODUCT
IDENTIFICATION EXIT
PRODUCT IDENTIFICATION
ENTRY
ADDRESS
DATA
ADDRESS
DATA
ADDRESS
DATA
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
5555H
AAH
5555H
2AAAH
5555H
5555H
2AAAH
5555H
AAH
55H
80H
AAH
55H
60H
5555H
AAH
2AAAH
55H
2AAAH
55H
5555H
90H
5555H
F0H
-
-
-
-
-
-
-
-
-
-
-
-
Pause 10 mS
Pause 10 mS
Pause 10 mS
Software Product Identification Acquisition Flow
Product Identification Entry (1)
Product Identification Mode (2,3)
Product Identification Exit (1)
Load data AA
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data 55
to
address 2AAA
Read address = 0
data = DA
Load data FO
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Read address = 1
data = C8
Pause 10 mS
(4)
Load data 60
to
address 5555
Normal Mode
Pause 10
S
m
Notes for software product identification:
(1) Data format: DQ7 - DQ0 (Hex); address format: A14 - A0 (Hex).
(2) A1 - A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in identification mode if power down.
(4) The device returns to standard operation mode.
(5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code
sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used.
- 8 -
W29EE512
DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage to Vss Potential
Operating Temperature
-0.5 to +7.0
0 to +70
V
°C
°C
V
Storage Temperature
-65 to +150
D.C. Voltage on Any Pin to Ground Potential except A9
Transient Voltage (¡ Õ20 nS) on Any Pin to Ground Potential
-0.5 to VCC +1.0
-1.0 to VCC +1.0
-0.5 to 12.5
V
Voltage on A9 and
Pin to Ground Potential
V
#OE
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Operating Characteristics
(VCC = 5.0V ±10%, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM.
TEST CONDITIONS
LIMITS
UNIT
MIN. TYP. MAX.
Power Supply
Current
ICC
=
= VIL,
= VIH,
#WE
-
-
50
mA
#CE #OE
all I/Os open
Address inputs = VIL/VIH, at f = 5 MHz
= VIH, all I/Os open
Standby Vcc Current
(TTL Input)
ISB1
ISB2
-
-
2
3
mA
#CE
Other inputs = VIL/VIH
Standby Vcc Current
(CMOS Input)
= VCC -0.3V, all I/Os open
#CE
20
100
mA
Other inputs = VCC -0.3V/GND
VIN = GND to VCC
Input Leakage
Current
ILI
-
-
-
-
10
10
mA
mA
Output Leakage
Current
ILO
VIN = GND to VCC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
VIL
VIH
-
-
-
-
-
-
-
-
0.8
V
V
V
V
V
2.0
-
-
VOL IOL = 2.1 mA
VOH1 IOH = -0.4 mA
0.45
2.4
4.2
-
-
Output High Voltage
CMOS
VOH2
IOH = -100 mA; VCC = 4.5V
Publication Release Date: February 18, 2002
Revision A7
- 9 -
W29EE512
Power-up Timing
PARAMETER
SYMBOL
TPU.READ
TPU.WRITE
TYPICAL
UNIT
mS
Power-up to Read Operation
Power-up to Write Operation
100
5
mS
CAPACITANCE
(VCC = 5.0V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
MAX.
12
UNIT
pF
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
CONDITIONS
0V to 3V
Input Rise/Fall Time
Input/Output Timing Level
Output Load
< 5 nS
1.5V/1.5V
1 TTL Gate and CL = 100 pF/30 pF
AC Test Load and Waveform
+5V
1.8
Kohm
DOUT
(For 90 nS/120 nS)
(For 70 nS)
100 pF
30 pF
1.3Kohm
Output
Input
3V
0V
1.5V
1.5V
Test Point
Test Point
- 10 -
W29EE512
Read Cycle Timing Parameters
(VCC = 5.0V ±10%, VCC = 5.0 ±5% for 70 nS, VSS = 0V, TA = 0 to 70° C)
PARAMETER
SYM. W29EE512-70 W29EE512-90 W29EE512-12 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
TRC
TCE
70
-
-
90
-
-
120
-
nS
nS
nS
nS
nS
nS
nS
Chip Enable Access Time
Address Access Time
70
70
35
25
25
-
90
90
40
25
25
-
-
-
120
120
50
30
30
-
TAA
-
-
Output Enable Access Time
TOE
TCHZ
TOHZ
TOH
-
-
-
High to High-Z Output
High to High-Z Output
-
-
-
#CE
#OE
-
-
-
Output Hold from Address Change
0
0
0
Byte/Page-write Cycle Timing Parameters
PARAMETER
Write Cycle (Erase and Program)
Address Setup Time
SYMBOL
TWC
TAS
MIN.
TYP.
MAX.
UNIT
mS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
mS
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
10
-
Address Hold Time
TAH
50
0
-
and
and
Setup Time
Hold Time
TCS
-
#WE
#WE
#OE
#OE
#CE
#WE
#WE
#CE
#CE
TCH
0
-
High Setup Time
High Hold Time
Pulse Width
TOES
TOEH
TCP
0
-
0
-
90
90
100
35
0
-
Pulse Width
TWP
TWPH
TDS
-
High Width
-
Data Setup Time
Data Hold Time
-
-
TDH
Byte Load Cycle Time
TBLC
-
200
Notes: All AC timing signals observe the following guidelines for determining setup and hold times:
(1) High level signal's reference level is VIH.
(2) Low level signal's reference level is VIL.
Publication Release Date: February 18, 2002
Revision A7
- 11 -
W29EE512
#DATA Polling Characteristics (1)
PARAMETER
SYMBOL
TDH
MIN.
10
10
-
TYP.
MAX.
UNIT
nS
Data Hold Time
-
-
-
-
-
-
Hold Time
TOEH
TOE
nS
#OE
#OE
(2)
nS
to Output Delay
Write Recovery Time
TWR
0
-
-
nS
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.
Toggle Bit Characteristics (1)
PARAMETER
Data Hold Time
SYMBOL
TDH
MIN.
10
10
-
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
Hold Time
TOEH
TOE
nS
#OE
#OE
#OE
(2)
nS
to Output Delay
High Pulse
TOEHP
TWR
150
0
-
-
-
-
nS
nS
Write Recovery Time
Notes:
(1) These parameters are characterized and not 100% tested.
(2) See TOE spec in A.C. Read Cycle Timing Parameters.
- 12 -
W29EE512
TIMING WAVEFORMS
Read Cycle Timing Diagram
T
RC
Address A15-0
#CE
T
CE
T
O
#OE
T
OH
V
IH
#WE
T
O
T
CH
High-Z
High-Z
DQ7-0
Data Valid
Data Valid
AA
T
Controlled Write Cycle Timing Diagram
#WE
TWC
TAS
TAH
Address A15-0
#CE
TCS
TCH
TOES
TOEH
#OE
TWPH
TWP
#WE
TDS
DQ7-0
Data Valid
TDH
Internal write starts
Publication Release Date: February 18, 2002
Revision A7
- 13 -
W29EE512
Timing Waveforms, continued
Controlled Write Cycle Timing Diagram
#CE
AS
T
TWC
TAH
Address A15-0
TCPH
TCP
#CE
TOES
TOEH
#OE
#WE
TDS
High Z
DQ7-0
Data Valid
TDH
Internal write starts
Page Write Cycle Timing Diagram
WC
T
Address A15-0
DQ7-0
#CE
#OE
TBLC
WP
T
T
WPH
#WE
Byte 0
Byte 1
Byte 2
Byte N-1
Byte N
Internal write starts
- 14 -
W29EE512
Timing Waveforms, continued
Polling Timing Diagram
#DATA
Address A15-0
#WE
#CE
T
OEH
#OE
DQ7
T
DH
T
WR
HIGH-Z
T
OE
Toggle Bit Timing Diagram
#WE
#CE
T
OEH
#OE
T
DH
T
OE
T
WR
HIGH-Z
DQ6
Publication Release Date: February 18, 2002
Revision A7
- 15 -
W29EE512
Timing Waveforms, continued
Page Write Timing Diagram Software Data Protection Mode
TWC
Byte/page load
Three-byte sequence for
cycle starts
software data protection mode
Address A15-0
2AAA
5555
A0
5555
DQ7-0
#CE
AA
55
#OE
BLC
T
TWP
#WE
WPH
T
Word N
(last word)
Word 0
Word N-1
SW1
SW2
SW0
Internal write starts
Reset Software Data Protection Timing Diagram
TWC
Six-byte sequence for resetting
software data protection mode
Address A15-0
DQ7-0
5555
5555
80
5555
2AAA
55
5555
2AAA
AA
55
20
AA
#CE
#OE
#WE
T
WP
T
BLC
TWPH
SW0
SW2
SW3
SW5
SW4
SW1
Internal programming starts
- 16 -
W29EE512
Timing Waveforms, continued
5-Volt-only Software Chip Erase Timing Diagram
Six-byte code for 5V-only
software chip erase
T
WC
Address A15-0
5555
2AAA
55
5555
2AAA
55
5555
5555
DQ7-0
#CE
80
AA
AA
10
#OE
#WE
T
WP
T
BLC
T
WPH
SW0
SW2
SW3
SW5
SW4
SW1
Internal programming starts
Publication Release Date: February 18, 2002
Revision A7
- 17 -
W29EE512
ORDERING INFORMATION
PART NO.
ACCESS POWER SUPPLY
STANDBY VCC
PACKAGE
CYCLE
TIME
(nS)
CURRENT MAX.
(mA)
CURRENT MAX.
(mA)
W29EE512P-70
W29EE512P-90
W29EE512P-12
W29EE512T-70
W29EE512T-90
W29EE512T-12
W29EE512Q-70
W29EE512Q-90
W29EE512P-70B
W29EE512P-90B
W29EE512P-12B
W29EE512T-70B
W29EE512T-90B
W29EE512T-12B
W29EE512Q-70B
W29EE512Q-90B
70
90
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
32-pin PLCC
1K
32-pin PLCC
1K
120
70
32-pin PLCC
1K
Type one TSOP
Type one TSOP
Type one TSOP
Type one VSOP
Type one VSOP
32-pin PLCC
1K
90
1K
120
70
1K
1K
90
1K
70
10K
10K
10K
10K
10K
10K
10K
10K
90
32-pin PLCC
120
70
32-pin PLCC
Type one TSOP
Type one TSOP
Type one TSOP
Type one VSOP
Type one VSOP
90
120
70
90
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
- 18 -
W29EE512
HOW TO READ THE TOP MARKING
Example: The top marking of 32L-PLCC W29EE512P-70B
W29EE512P-70B
2138977A-A12
149OBRA
1st line: winbond logo
2nd line: the part number: W29EE512P-70B
3rd line: the lot number
4th line: the tracking code: 149 O B RA
149: Packages made in ’01, week 49
O: Assembly house ID: A means ASE, O means OSE, ... etc.
B: IC revision; A means version A, B means version B, ... etc.
RA: Process code
Publication Release Date: February 18, 2002
Revision A7
- 19 -
W29EE512
PACKAGE DIMENSIONS
32-pin PLCC
H E
E
4
1
32
30
Dimension In mm
Min. Nom. Max. Min. Nom. Max.
Dimension In Inches
Symbol
A
5
0.140
3.56
29
0.020
0.105
0.026
0.016
0.008
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.50
2.67
1
A
A
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
0.115
0.032
0.022
0.014
0.553
0.453
0.056
0.530
0.430
0.595
0.495
2.80
0.71
2.93
0.81
2
0.66
1
b
b
c
D
E
e
G
G
H
H
L
y
0.41
0.56
0.46
0.20
0.35
0.25
D
G
D
D
H
13.89
11.35
1.12
14.05
11.51
1.42
13.97
11.43
1.27
12.45
9.91
12.95
10.41
14.99
12.45
2.29
13.46
10.92
15.11
12.57
D
E
D
21
14.86
12.32
13
E
0.075
0.095
0.004
1.91
2.41
0.10
14
20
c
°
°
°
°
10
0
10
0
q
Notes:
L
1. Dimensions D & E do not include interlead flash.
2. Dimension b does not include dambar protrusion/intrusion.
3. Controlling dimension: Inches.
4. General appearance spec. should be based on fina visual
inspection sepc.
2
1
A
A
A
e
b
q
b
1
Seating Plane
y
G
E
32-pin TSOP
H D
D
Dimension In Inches
Min. Nom. Max.
Dimension In mm
Symbol
Min. Nom. Max.
__
__
__
__
A
1.20
0.15
1.05
0.23
0.047
0.006
c
__
__
0.002
0.037
0.05
0.95
A 1
A 2
b
0.041
0.009
1.00
0.039
M
e
0.007 0.008
0.17 0.20
0.12 0.15
E
c
0.005 0.006
0.720 0.724
0.17
0.007
0.728
0.10(0.004)
D
18.30 18.40 18.50
b
0.311 0.315
0.780 0.787
7.90 8.00
8.10
E
0.319
19.80
__
20.00 20.20
0.795
__
HD
e
__
__
0.020
0.50
0.016 0.020
0.40
__
0.50
0.60
__
L
0.024
__
__
L 1
0.031
0.80
__
A
__
0.000
0.004
5
0.10
5
0.00
1
Y
A2
1
3
3
q
q
L
1
A
Y
L1
Note:
Controlling dimension: Millimeters
- 20 -
W29EE512
Package Dimensions, continued
32-pin VSOP
H D
D
Dimension In Inches
Min. Nom. Max.
Dimension In mm
Symbol
Min. Nom.
Max.
__
__
__
__
A
A
1.20
0.15
0.25
0.047
0.006
__
__
A1
0.002
0.05
A 1
b
0.006 0.008
0.484 0.488
0.311 0.315
0.15 0.20
0.010
0.492
0.319
M
e
D
12.30 12.40 12.50
E
7.90 8.00
8.10
E
0.10(0.004)
0.543 0.551
13.80
__
14.00 14.20
0.559
__
HD
e
__
__
b
0.020
0.50
0.020 0.024
0.50
0.60
__
0.70
L
0.028
__
0.004
0.008
5
0.20
5
0.10
0
Y
__
__
0
q
Note:
Controlling dimension: Millimeters
Y
q
L
Publication Release Date: February 18, 2002
Revision A7
- 21 -
W29EE512
VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A5
Mar. 1998
6
7
8
Add. pause 10 mS
Add. pause 50 mS
Correct the time from 10 mS to 10 mS
1, 2, 18, 19 Eliminate 600 mil DIP, 450 mil SOP packages
1, 2, 18, 20 Add 32-pin VSOP package
A6
A7
Oct. 1999
3, 11
4
Change Byte Load Cycle Time from 150 mS to 200 mS
Feb. 18, 2002
Modify VCC Power Up/Down Detection in Hardware
Data Protection
21
Add HOW TO READ THE TOP MARKING
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
2727 North First Street, San Jose,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
200336 China
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
TEL: 86-21-62365999
FAX: 86-21-62365998
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu Chiu, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
FAX: 81-45-4781800
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 22 -
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