W29N01HV_技术文档

W29N01HV

1G-BIT 3.3V

NAND FLASH MEMORY

Release Date: January 11^th, 2018

Revision C

1

W29N01HV

Table of Contents

1.

2.

3.

GENERAL DESCRIPTION...............................................................................................................6

FEATURES.......................................................................................................................................6

PACKAGE TYPES AND PIN CONFIGURATIONS ..........................................................................7

3.1

3.2

3.3

3.4

Pin assignment 48-pin TSOP1(x8).......................................................................................7

Pin assignment 48 ball VFBGA (x8).....................................................................................8

Pin assignment 63 ball VFBGA............................................................................................9

Pin Descriptions..................................................................................................................10

4.

PIN DESCRITPIONS......................................................................................................................11

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Chip Enable (#CE)..............................................................................................................11

Write Enable (#WE)............................................................................................................11

Read Enable (#RE) ............................................................................................................11

Address Latch Enable (ALE) ..............................................................................................11

Command Latch Enable (CLE) ..........................................................................................11

Write Protect (#WP)............................................................................................................11

Ready/Busy (RY/#BY)........................................................................................................11

Input and Output (I/Ox).......................................................................................................11

5.

6.

BLOCK DIAGRAM..........................................................................................................................12

MEMORY ARRAY ORGANIZATION..............................................................................................13

6.1

Array Organization (x8) ......................................................................................................13

7.

8.

9.

MODE SELECTION TABLE ...........................................................................................................14

COMMAND TABLE.........................................................................................................................15

DEVICE OPERATIONS..................................................................................................................16

9.1

READ operation..................................................................................................................16

9.1.1 PAGE READ (00h-30h).........................................................................................................16

9.1.2 RANDOM DATA OUTPUT (05h-E0h)...................................................................................17

9.1.3 READ ID (90h)......................................................................................................................17

9.1.4 READ PARAMETER PAGE (ECh) .......................................................................................18

9.1.5 READ STATUS (70h)............................................................................................................21

PROGRAM operation.........................................................................................................22

9.2.1 PAGE PROGRAM (80h-10h)................................................................................................22

9.2.2 SERIAL DATA INPUT (80h)..................................................................................................22

9.2.3 RANDOM DATA INPUT (85h) ..............................................................................................23

COPY BACK operation.......................................................................................................24

9.3.1 READ for COPY BACK (00h-35h) ........................................................................................24

9.3.2 PROGRAM for COPY BACK (85h-10h)................................................................................24

BLOCK ERASE operation ..................................................................................................26

9.4.1 BLOCK ERASE (60h-D0h)....................................................................................................26

RESET operation................................................................................................................27

9.5.1 RESET (FFh) ........................................................................................................................27

WRITE PROTECT..............................................................................................................28

9.2

9.3

9.4

9.5

9.6

10.

ELECTRICAL CHARACTERISTICS...............................................................................................30

10.1 Absolute Maximum Ratings................................................................................................30

10.2 Operating Ranges ..............................................................................................................30

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10.3 Device power-up timing......................................................................................................31

10.4 DC Electrical Characteristics..............................................................................................32

10.5 AC Measurement Conditions .............................................................................................33

10.6 AC timing characteristics for Command, Address and Data Input.....................................34

10.7 AC timing characteristics for Operation..............................................................................35

10.8 Program and Erase Characteristics ...................................................................................36

TIMING DIAGRAMS .......................................................................................................................37

INVALID BLOCK MANAGEMENT..................................................................................................46

12.1 Invalid blocks......................................................................................................................46

12.2 Initial invalid blocks.............................................................................................................46

12.3 Error in operation................................................................................................................47

12.4 Addressing in program operation .......................................................................................48

PACKAGE DIMENSIONS...............................................................................................................49

13.1 TSOP 48-pin 12x20............................................................................................................49

13.2 Fine-Pitch Ball Grid Array 48-ball.......................................................................................50

13.3 Fine-Pitch Ball Grid Array 63-ball.......................................................................................51

ORDERING INFORMATION ..........................................................................................................52

VALID PART NUMBERS................................................................................................................53

REVISION HISTORY......................................................................................................................54

11.

12.

13.

14.

15.

16.

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List of Tables

Table 3.1 Pin Descriptions ..........................................................................................................................10

Table 6.1 Addressing ..................................................................................................................................13

Table 7.1 Mode Selection ...........................................................................................................................14

Table 8.1 Command Table..........................................................................................................................15

Table 9.1 Device ID and configuration codes for Address 00h...................................................................18

Table 9.2 ONFI identifying codes for Address 20h .....................................................................................18

Table 9.3 Parameter Page Output Value....................................................................................................20

Table 9.4 Status Register Bit Definition ......................................................................................................21

Table 10.1 Absolute Maximum Ratings ......................................................................................................30

Table 10.3 Operating Ranges.....................................................................................................................30

Table 10.5 DC Electrical Characteristics ....................................................................................................32

Table 10.7 AC Measurement Conditions....................................................................................................33

Table 10.9 AC timing characteristics for Command, Address and Data Input ...........................................34

Table 10.11 AC timing characteristics for Operation ..................................................................................35

Table 10.13 Program and Erase Characteristics........................................................................................36

Table 12.1 Valid Block Number ..................................................................................................................46

Table 12.2 Block failure...............................................................................................................................47

Table 15.1 Part Numbers for Industrial Temperature .................................................................................53

Table 16.1 History Table.............................................................................................................................54

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List of Figures

Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)......................................................................7

Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D).....................................................................8

Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B)....................................................................9

Figure 5-1 NAND Flash Memory Block Diagram ........................................................................................12

Figure 6-1 Array Organization.....................................................................................................................13

Figure 9-1 Page Read Operations ..............................................................................................................16

Figure 9-2 Random Data Output.................................................................................................................17

Figure 9-3 Read ID......................................................................................................................................17

Figure 9-4 Read Parameter Page...............................................................................................................18

Figure 9-5 Read Status Operation ..............................................................................................................21

Figure 9-6 Page Program............................................................................................................................22

Figure 9-7 Random Data Input ...................................................................................................................23

Figure 9-8 Copy Back Program Operation..................................................................................................25

Figure 10-1 Power ON/OFF sequence .......................................................................................................31

Figure 11-1 Command Latch Cycle ............................................................................................................37

Figure 11-2 Address Latch Cycle................................................................................................................37

Figure 11-3 Data Latch Cycle .....................................................................................................................38

Figure 11-4 Serial Access Cycle after Read...............................................................................................38

Figure 11-5 Serial Access Cycle after Read (EDO)....................................................................................39

Figure 11-6 Read Status Operation............................................................................................................39

Figure 11-7 Page Read Operation..............................................................................................................40

Figure 11-8 #CE Don't Care Read Operation.............................................................................................40

Figure 11-9 Random Data Output Operation..............................................................................................41

Figure 11-10 Read ID..................................................................................................................................42

Figure 11-11 Page Program........................................................................................................................42

Figure 11-12 #CE Don't Care Page Program Operation ............................................................................43

Figure 11-13 Page Program with Random Data Input................................................................................43

Figure 11-14 Copy Back .............................................................................................................................44

Figure 11-15 Block Erase............................................................................................................................44

Figure 11-16 Reset .....................................................................................................................................45

Figure 12-12-1 Flow chart of create initial invalid block table .....................................................................47

Figure 12-12-2 Bad block Replacement .....................................................................................................48

Figure 13-1 TSOP 48-PIN 12X20mm .........................................................................................................49

Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball............................................................................................50

Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball (9x11mm) ..........................................................................51

Figure 14-1 Ordering Part Number Description ..........................................................................................52

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1. GENERAL DESCRIPTION

The W29N01HV (1G-bit) NAND Flash memory provides a storage solution for embedded systems with

limited space, pins and power. It is ideal for code shadowing to RAM, solid state applications and storing

media data such as, voice, video, text and photos. The device operates on a single 2.7V to 3.6V power

supply with active current consumption as low as 25mA 10uA for CMOS standby current.

The memory array totals 138,412,032 bytes, and organized into 1,024 erasable blocks of 135,168 bytes.

Each block consists of 64 programmable pages of 2,112-bytes each. Each page consists of 2,048-bytes

for the main data storage area and 64-bytes for the spare data area (The spare area is typically used for

error management functions).

The W29N01HV supports the standard NAND flash memory interface using the multiplexed 8-bit bus to

transfer data, addresses, and command instructions. The five control signals, CLE, ALE, #CE, #RE and

#WE handle the bus interface protocol. Also, the device has two other signal pins, the #WP (Write

Protect) and the RY/#BY (Ready/Busy) for monitoring the device status.

2. FEATURES

 Basic Features

– Density : 1Gbit (Single chip solution)

– Vcc : 2.7V to 3.6V

– Bus width : x8

 Command set

– Standard NAND command set

– Additional command support

. Copy Back

– Operating temperature

. Industrial: -40°C to 85°C

 Single-Level Cell (SLC) technology.

 Organization

– Density: 1G-bit/128M-byte

– Page size

. 2,112 bytes (2048 + 64 bytes)

– Block size

. 64 pages (128K + 4K bytes)

 Lowest power consumption

– Read: 25mA(typ.3V),

– Program/Erase: 25mA(typ.3V),

– CMOS standby: 10uA(typ.)

 Space Efficient Packaging

– 48-pin standard TSOP1

– 48-ball VFBGA

– 63-ball VFBGA

– Contact Winbond for stacked

packages/KGD

 Highest Performance

– Read performance (Max.)

. Random read: 25us

. Sequential read cycle: 25ns

– Write Erase performance

. Page program time: 250us(typ.)

. Block erase time: 2ms(typ.)

– Endurance 100,000 Erase/Program

Cycles⁽¹⁾

– 10-years data retention

Note:

1. Endurance specification is based on 1bit/528 byte ECC (Error Correcting Code).

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Revision C

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3. PACKAGE TYPES AND PIN CONFIGURATIONS

W29N01HV is offered in a 48-pin TSOP1 package (Code S) and 48-ball VFBGA package (Code D)

and 63-ball VFBGA package (Code B) as shown in Figure 3-1 to 3-3, respectively. Package

diagrams and dimensions are illustrated in Section: Package Dimensions.

3.1

Pin assignment 48-pin TSOP1(x8)

Figure 3-1 Pin Assignment 48-pin TSOP1 (Package code S)

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3.2

Pin assignment 48 ball VFBGA (x8)

Figure 3-2 Pin Assignment 48-ball VFBGA (Package code D)

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3.3 Pin assignment 63 ball VFBGA

Top View, ball down

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

N.C

#WP

N.C

ALE

#RE

N.C

IO0

Vss

CLE

N.C

DNU

N.C

#CE

N.C

#WE RY/#BY

N.C

Vcc

N.C

F

N.C

G

H

J

DNU

N.C

Vss

IO1

IO2

N.C

IO3

Vcc

IO4

IO5

IO6

IO7

Vss

K

L

N.C

M

Figure 3-3 Pin Assignment 63-ball VFBGA (Package Code B)

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3.4

Pin Descriptions

PIN NAME

I/O

FUNCTION

#WP

ALE

I

Write Protect

I

Address Latch Enable

Chip Enable

#CE

I

#WE

RY/#BY

#RE

I

Write Enable

O

Ready/Busy

I

Read Enable

CLE

I

Command Latch Enable

Data Input/Output

Power supply

Ground

I/O[0-7]

Vcc

I/O

Supply

Vss

Supply

DNU

N.C

-

Do Not Use: DNUs must be left unconnected.

No Connect

-

Table 3.1 Pin Descriptions

Note:

1. Connect all Vcc and Vss pins to power supply or ground. Do not leave Vcc or Vss disconnected.

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4. PIN DESCRITPIONS

4.1 Chip Enable (#CE)

#CE pin enables and disables device operation. When #CE is high the device is disabled and the

I/O pins are set to high impedance and enters into standby mode if not busy. When #CE is set low

the device will be enabled, power consumption will increase to active levels and the device is ready

for Read and Write operations.

4.2 Write Enable (#WE)

#WE pin enables the device to control write operations to input pins of the device. Such as,

command instructions, addresses and data that are latched on the rising edge of #WE.

4.3 Read Enable (#RE)

#RE pin controls serial data output from the pre-loaded Data Register. Valid data is present on the

I/O bus after the tREA period from the falling edge of #RE. Column addresses are incremented for

each #RE pulse.

4.4 Address Latch Enable (ALE)

ALE pin controls address input to the address register of the device. When ALE is active high,

addresses are latched via the I/O pins on the rising edge of #WE.

4.5 Command Latch Enable (CLE)

CLE pin controls command input to the command register of the device. When CLE is active high,

commands are latched into the command register via I/O pins on the rising edge of #WE.

4.6 Write Protect (#WP)

#WP pin can be used to prevent the inadvertent program/erase to the device. When #WP pin is

active low, all program/erase operations are disabled.

4.7 Ready/Busy (RY/#BY)

RY/#BY pin indicates the device status. When RY/#BY output is low, it indicates that the device is

processing either a program, erase or read operations. When it returns to high, those operations

have completed. RY/#BY pin is an open drain.

4.8 Input and Output (I/Ox)

I/Ox bi-directional pins are used for the following; command, address and data operations.

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5. BLOCK DIAGRAM

Status

Row decode unit

register

Figure 5-2 NAND Flash Memory Block Diagram

Address

latch

Command

latch

IO0 to IO7

IO control

unit

IO8 to IO15

(x16 only)

#CE

#RE

#WE

ALE

Memory array

Logic

Control

unit

CLE

#WP

RY/#BY

High

RY/#BY

Voltage

Generator

Figure 5-1 NAND Flash Memory Block Diagram

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6. MEMORY ARRAY ORGANIZATION

6.1 Array Organization (x8)

1 page

1 block

= 2048+64 bytes

Total

1024 blocks

= 64 pages

= (128K+4K) bytes

1 block

1 device

=1024 blocks

= (128M + 4M) bytes

IO0 ~ IO7

2048

64

Data register

2112 bytes

Figure 6-1 Array Organization

I/O7

A7

I/O6

A6

I/O5

A5

I/O4

A4

I/O3

A3

I/O2

A2

I/O1

A1

I/O0

A0

1^stcycle

2^ndcycle

3^rdcycle

4^thcycle

L

A11

A15

A23

A10

A14

A22

A9

A8

A19

A27

A18

A26

A17

A25

A16

A24

A13

A21

A12

A20

Table 6.1 Addressing

Notes:

1. “L” indicates a low condition, which must be held during the address cycle to insure correct processing.

2. A0 to A11 during the 1st and 2nd cycles are column addresses. A12 to A27 during the 3rd and 4th cycles

are row addresses.

3. The device ignores any additional address inputs that exceed the device’s requirement.

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7. MODE SELECTION TABLE

MODE

CLE

H

ALE

L

#CE

#WE

#RE

H

#WP

Read

mode

Command input

Address input

Command input

Address input

L

X

H

L

H

Program

H

L

H

Erase

mode

L

H

Data input

L

H

Sequential Read and Data output

During read (busy)

During program (busy)

During erase (busy)

Write protect

H

X

H

X

H

L

Standby

0V/Vcc

Table 7.1 Mode Selection

Notes:

1. “H” indicates a HIGH input level, “L” indicates a LOW input level, and “X” indicates a Don’t Care Level.

2. #WP should be biased to CMOS HIGH or LOW for standby.

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8. COMMAND TABLE

1^ST

CYCLE CYCLE CYCLE CYCLE

2^ND

3^rd

4^th

Acceptable

during

busy

COMMAND

PAGE READ

00h

30h

35h

READ for COPY BACK

READ ID

00h

90h

READ STATUS

70h

Yes

RESET

FFh

PAGE PROGRAM

PROGRAM for COPY BACK

BLOCK ERASE

80h

10h

D0h

85h

60h

RANDOM DATA INPUT*1

RANDOM DATA OUTPUT*1

READ PARAMETER PAGE

85h

05h

ECh

E0h

Table 8.1 Command Table

Notes:

1. RANDOM DATA INPUT and RANDOM DATA OUTPUT command is only to be used within a page.

2. Any command that are not in the above table are considered as undefined and are prohibited as inputs.

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9. DEVICE OPERATIONS

9.1 READ operation

9.1.1 PAGE READ (00h-30h)

When the device powers on, 00h command is latched to command register. Therefore, system only

issues four address cycles and 30h command for initial read from the device. This operation can

also be entered by writing 00h command to the command register, and then write four address

cycles, followed by writing 30h command. After writing 30h command, the data is transferred from

NAND array to Data Register during tR. Data transfer progress can be done by monitoring the

status of the RY/#BY signal output. RY/#BY signal will be LOW during data transfer. Also, there is

an alternate method by using the READ STATUS (70h) command. If the READ STATUS command

is issued during read operation, the Read (00h) command must be re-issued to read out the data

from Data Register. When the data transfer is complete, RY/#BY signal goes HIGH, and the data

can be read from Data Register by toggling #RE. Read is sequential from initial column address to

the end of the page. (See Figure 9-1)

CLE

#CE

#WE

ALE

RE

#

Data Output (Serial Access)

00h

Address (4cycles)

30h

l/Ox

tR

RY/#BY

Don’t care

Figure 9-1 Page Read Operations

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9.1.2 RANDOM DATA OUTPUT (05h-E0h)

The RANDOM DATA OUTPUT allows the selection of random column addresses to read out data

from a single or multiple of addresses. The use of the RANDOM DATA OUTPUT command is

available after the PAGE READ (00h-30h) sequence by writing the 05h command following by the

two cycle column address and then the E0h command. Toggling #RE will output data sequentially.

The RANDOM DATA OUTPUT command can be issued multiple times, but limited to the current

loaded page.

tR

RY/#BY

#RE

Address(2cycles)

Data out

E0h

Address(4cycles)

30h

05h

00h

Data out

I/Ox

Figure 9-2 Random Data Output

9.1.3 READ ID (90h)

READ ID command is comprised of two modes determined by the input address, device (00h) or

ONFI (20h) identification information. To enter the READ ID mode, write 90h to the Command

Register followed by a 00h address cycle, then toggle #RE for 5 single byte cycles, W29N01HV.

The pre-programmed code includes the Manufacturer ID, Device ID, and Product-Specific

Information (see Table 9.1). If the READ ID command is followed by 20h address, the output code

includes 4 single byte cycles of ONFI identifying information (See Table 9.2). The device remains in

the READ ID Mode until the next valid command is issued.

CLE

#CE

#WE

tAR

ALE

#RE

tREA

tWHR

90h

00h

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

I/Ox

(or 20h)

Address, 1 cycle

Figure 9-3 Read ID

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# of

Byte/Cycles Byte/Cycle

1^st

2^nd

3^rd

4^th

5^th

Byte/Cycle

W29N01HV

EFh

F1h

00h

95h

00h

Page Size:2KB

Spare Area Size:64B

BLK Size w/o

Spare:128KB

Organized:x8 or x16

Serial Access:25ns

Cache

Programming

Non-supported

Description

MFR ID

Device ID

Table 9.1 Device ID and configuration codes for Address 00h

1^st

2^nd

3^rd

4^th

# of Byte/Cycles

Byte/Cycle

Code

4Fh

4Eh

46h

49h

Table 9.2 ONFI identifying codes for Address 20h

9.1.4 READ PARAMETER PAGE (ECh)

READ PARAMETER PAGE can read out the device’s parameter data structure, such as,

manufacturer information, device organization, timing parameters, key features, and other pertinent

device parameters. The data structure is stored with at least three copies in the device’s parameter

page. Figure 9-4 shows the READ PARAMETER PAGE timing. The RANDOM DATA OUTPUT

(05h-E0h) command is supported during data output.

CLE

#WE

ALE

#RE

P1022

P1023

00h

P0

P1

ECh

・・・

I/Ox

tR

RY/#BY

Figure 9-4 Read Parameter Page

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Byte

0-3

Description

Parameter page signature

Revision number

Value

4Fh, 4Eh, 46h, 49h

02h, 00h

4-5

Features

supported

6-7

8-9

W29N01HV

10h, 00h

Optional commands supported

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h

10-31

Reserved

57h, 49h, 4Eh, 42h, 4Fh, 4Eh, 44h, 20h, 20h, 20h, 20h,

20h

32-43

44-63

Device manufacturer

57h, 32h, 39h, 4Eh, 30h, 31h, 48h, 56h, 20h, 20h, 20h,

20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h

Device model

W29N01HV

64

Manufacturer ID

Date code

EFh

65-66

00h, 00h

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

67-79

Reserved

80-83

84-85

86-89

90-91

92-95

96-99

100

# of data bytes per page

# of spare bytes per page

# of data bytes per partial page

# of spare bytes per partial page

# of pages per block

00h, 08h, 00h, 00h

40h, 00h

00h, 02h, 00h, 00h

10h, 00h

40h, 00h, 00h, 00h

00h, 04h, 00h, 00h

01h

# of blocks per unit

# of logical units

101

# of address cycles

22h

102

# of bits per cell

01h

103-104

105-106

Bad blocks maximum per unit

Block endurance

14h, 00h

01h, 05h

Guaranteed valid blocks at beginning of

target

107

01h

Block endurance for guaranteed valid

blocks

108-109

00h, 00h

110

111

112

113

114

# of programs per page

Partial programming attributes

# of ECC bits

04h

00h

01h

00h

# of interleaved address bits

Interleaved operation attributes

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Byte

115-127

128

Description

Value

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h, 00h

Reserved

I/O pin capacitance

Timing mode

0Ah

129-130

W29N01HV

1Fh, 00h

support

131-132

133-134

135-136

137-138

Program cache timing

Maximum page program time

Maximum block erase time

Maximum random read time

00h, 00h

BCh, 02h

10h, 27h

19h, 00h

tCCS

139-140

141-163

W29N01HV

minimum

3Ch, 00h

00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,

00h

Reserved

164-165

166-253

254-255

256-511

512-767

>767

Vendor specific revision #

Vendor specific

01h,00h

00h

Integrity CRC

Set at shipment

Value of bytes 0-255

Additional redundant parameter pages

Table 9.3 Parameter Page Output Value

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9.1.5 READ STATUS (70h)

The W29N01HV has an 8-bit Status Register which can be read during device operation. Refer to

Table 9.4 for specific Status Register definitions. After writing 70h command to the Command

Register, read cycles will only read from the Status Register. The status can be read from I/O[7:0]

outputs, as long as #CE and #RE are LOW. Note; #RE does not need to be toggled for Status

Register read. The Command Register remains in status read mode until another command is

issued. To change to normal read mode, issue the PAGE READ (00h) command. After the PAGE

READ command is issued, data output starts from the initial column address.

#CE

tCLR

CLE

tREA

#WE

#RE

Status Output

70h

I/Ox

Figure 9-5 Read Status Operation

SR bit

Page Read Page Program Block Erase

Definition

0=Successful Program/Erase

1=Error in Program/Erase

I/O 0

Not Use

Pass/Fail

Not Use

Pass/Fail

Not Use

0=Successful Program

1=Error in Program

I/O 1

I/O 2

I/O 3

I/O 4

Not Use

0

Ready = 1

Busy = 0

I/O 5

I/O 6

I/O 7

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready/Busy

Write Protect

Ready = 1

Busy = 0

Unprotected = 1

Protected = 0

Table 9.4 Status Register Bit Definition

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9.2 PROGRAM operation

9.2.1 PAGE PROGRAM (80h-10h)

The W29N01HV Page Program command will program pages sequentially within a block, from the

lower order page address to higher order page address. Programming pages out of sequence is

prohibited. The W29N01HV supports partial-page programming operations up to 4 times before an

erase is required if partitioning a page. Note; programming a single bit more than once without first

erasing it is not supported.

9.2.2 SERIAL DATA INPUT (80h)

Page Program operation starts with the execution of the Serial Data Input command (80h) to the

Command Register, following next by inputting four address cycles and then the data is loaded.

Serial data is loaded to Data register with each #WE cycle. The Program command (10h) is written

to the Command Register after the serial data input is finished. At this time the internal write state

controller automatically executes the algorithms for program and verifies operations. Once the

programming starts, determining the completion of the program process can be done by monitoring

the RY/#BY output or the Status Register Bit 6, which will follow the RY/#BY signal. RY/#BY will

stay LOW during the internal array programming operation during the period of (tPROG). During

page program operation, only two commands are available, READ STATUS (70h) and RESET

(FFh). When the device status goes to the ready state, Status Register Bit 0 (I/O0) indicates

whether the program operation passed (Bit0=0) or failed (Bit0=1), (see Figure 9-6). The Command

Register remains in read status mode until the next command is issued.

tPROG

RY/#BY

70h

I/Ox

80h

Din

10h

Status

Address (4cycles)

I/O0=0pass

I/O0=1fail

Figure 9-6 Page Program

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9.2.3 RANDOM DATA INPUT (85h)

After the Page Program (80h) execution of the initial data has been loaded into the Data register, if

the need for additional writing of data is required, using the RANDOM DATA INPUT (85h) command

can perform this function to a new column address prior to the Program (10h) command. The

RANDOM DATA INPUT command can be issued multiple times in the same page (See Figure 9-7).

CLE

#CE

#WE

ALE

#RE

tPROG

RY/#BY

Address

Address (4cycles)

Din

10h

80h

Din

85h

70h

Status

I/Ox

(2 cycles)

Don’t care

Figure 9-7 Random Data Input

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9.3 COPY BACK operation

Copy Back operations require two command sets. Issue a READ for COPY BACK (00h-35h)

command first, then the PROGRAM for COPY BACK (85h-10h) command.

9.3.1 READ for COPY BACK (00h-35h)

The READ for COPY BACK command is used together with the PROGRAM for COPY BACK (85h-

10h) command. To start execution, READ for COPY BACK (00h) command is written to the

Command Register, followed by the four cycles of the source page address. To start the transfer of

the selected page data from the memory array to the Data register, write the 35h command to the

Command Register.

After execution of the READ for COPY BACK command sequence and RY/#BY returns to HIGH

marking the completion of the operation, the transferred data from the source page into the Data

register may be read out by toggling #RE. Data is output sequentially from the column address that

was originally specified with the READ for COPY BACK command. RANDOM DATA OUTPUT (05h-

E0h) commands can be issued multiple times without any limitation after READ for COPY BACK

command has been executed (see Figures 9-8 and 9-9).

At this point the device is in ready state to accept the PROGRAM for COPY BACK command.

9.3.2 PROGRAM for COPY BACK (85h-10h)

After the READ for COPY BACK command operation has been completed and RY/#BY goes HIGH,

the PROGRAM for COPY BACK command can be written to the Command Register. The command

results in the transfer of data to the Data Register, then internal operations start programming of the

new destination page. The sequence would be, write 85h to the Command Register, followed by the

four cycle destination page address to the NAND array. Next write the 10h command to the

Command Register; this will signal the internal controller to automatically start to program the data

to new destination page. During this programming time, RY/#BY will LOW. The READ STATUS

command can be used instead of the RY/#BY signal to determine when the program is complete.

When Status Register Bit 6 (I/O6) equals to “1”, Status Register Bit 0 (I/O0) will indicate if the

operation was successful or not.

The RANDOM DATA INPUT (85h) command can be used during the PROGRAM for COPY BACK

command for modifying the original data. Once the data is copied into the Data register using the

READ for COPY BACK (00h-35h) command, follow by writing the RANDOM DATA INPUT (85h)

command, along with the address of the data to be changed. The data to be changed is placed on

the external data pins. This operation copies the data into the Data register. Once the 10h

command is written to the Command Register, the original data and the modified data are

transferred to the Data Register, and programming of the new page commences. The RANDOM

DATA INPUT command can be issued numerous times without limitation, as necessary before

starting the programming sequence with 10h command.

Since COPY BACK operations do not use external memory and the data of source page might

include a bit errors, a competent ECC scheme should be developed to check the data before

programming data to a new destination page.

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CLE

#CE

#WE

ALE

RE

#

Status

Address

(2cycles)

00h

Address (4cycles)

35h

Data output

05h

E0h

Address(4cycles)

10h

Data Output

85h

70h

I/ Ox

Output

No limitation

Optional

tPROG

tR

RY/# BY

Don’t care

Figure 9-8 Copy Back Program Operation

CLE

#CE

#WE

ALE

#RE

Address

Status

Output

DataOutput

Optional

Data Input

Address(5cycles)

85h

10h

00h Address(5Cycles)

35h

70h

(2cycles)

I/Ox

No limitation

tPROG

tR

RY/#BY

Don’t care

Figure 9-9 Copy Back Operation with Random Data Input

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9.4 BLOCK ERASE operation

9.4.1 BLOCK ERASE (60h-D0h)

Erase operations happen at the architectural block unit. This W29N01HV has 1024 erase blocks.

Each block is organized into 64 pages (2112 bytes/page), 132K bytes (128K + 4K bytes)/block. The

BLOCK ERASE command operates on a block by block basis.

Erase Setup command (60h) is written to the Command Register. Next, the two cycle block address

is written to the device. The page address bits are loaded during row address cycle, but are ignored.

The Erase Confirm command (D0h) is written to the Command Register at the rising edge of #WE,

RY/#BY goes LOW and the internal controller automatically handles the block erase sequence of

operation. RY/#BY goes LOW during Block Erase internal operations for a period of tBERS,

The READ STATUS (70h) command can be used for confirm block erase status. When Status

Register Bit6 (I/O6) becomes to “1”, block erase operation is finished. Status Register Bit0 (I/O0)

will indicate a pass/fail condition (see Figure 9-10).

CLE

#CE

#WE

ALE

#RE

Address Input (2cycles)

D0h

Status Output

60h

70h

I/Ox

I/ O 0 = 0 pass

I/ O 0 = 1 fail

tBERS

RY/#BY

Don’t care

Figure 9-10 Block Erase Operation

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9.5 RESET operation

9.5.1 RESET (FFh)

READ, PROGRAM, and ERASE commands can be aborted by the RESET (FFh) command during

the time the W29N01HV is in the busy state. The Reset operation puts the device into known status.

The data that is processed in either the programming or erasing operations are no longer valid. This

means the data can be partially programmed or erased and therefore data is invalid. The Command

Register is cleared and is ready to accept next command. The Data Register contents are marked

invalid.

The Status Register indicates a value of E0h when #WP is HIGH; otherwise a value of 60h is

written when #WP is LOW. After RESET command is written to the command register, RY/#BY

goes LOW for a period of tRST (see Figure 9-11).

CLE

#CE

tWB

#WE

tRST

RY/#BY

FFh

I/Ox

RESET

command

Figure 9-11 Reset Operation

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9.6 WRITE PROTECT

#WP pin can enable or disable program and erase commands preventing or allowing program and

erase operations. Figure 9-12 to 9-17 shows the enabling or disabling timing with #WP setup time

(tWW) that is from rising or falling edge of #WP to latch the first commands. After first command is

latched, #WP pin must not toggle until the command operation is complete and the device is in the

ready state. (Status Register Bit5 (I/O5) equal 1)

#WE

tWW

60h

D0h

I/Ox

#WP

RY/#BY

Figure 9-12 Erase Enable

#WE

tWW

I/Ox

60h

D0h

#WP

RY/#BY

Figure 9-13 Erase Disable

#WE

I/Ox

tWW

80h

h

1100h

#WP

RY/#BY

Figure 9-14 Program Enable

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#WE

I/Ox

tWW

80 h

10h

#WP

RY/#BY

Figure 9-15 Program Disable

#WE

tWW

/

85h

10h

I Ox

#

WP

RY/#BY

Figure 9-16 Program for Copy Back Enable

#WE

tWW

85h

10h

I/Ox

#WP

RY/#BY

Figure 9-17 Program for Copy Back Disable

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10. ELECTRICAL CHARACTERISTICS

10.1 Absolute Maximum Ratings

PARAMETERS

SYMBOL

VCC

CONDITIONS

RANGE

–0.6 to +4.6

–65 to +150

5

UNIT

Supply Voltage

V

Voltage Applied to Any Pin

Storage Temperature

Short circuit output current, I/Os

VIN

Relative to Ground

TSTG

°C

mA

Table 10.1 Absolute Maximum Ratings

Notes:

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V

for periods <30ns.

2. Maximum DC voltage on input/output pins is Vcc+0.3V which, during transitions, may overshoot to

Vcc+2.0V for periods <20ns

3. This device has been designed and tested for the specified operation ranges. Proper operation outside of

these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.

Exposure beyond absolute maximum ratings may cause permanent damage.

10.2 Operating Ranges

SPEC

PARAMETER

SYMBOL

VCC

CONDITIONS

UNIT

V

MIN

MAX

Supply Voltage

2.7

3.6

Ambient Temperature,

Operating

TA

Industrial

-40

+85

°C

Table 10.2 Operating Ranges

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10.3 Device power-up timing

The device is designed to avoid unexpected program/erase operations during power transitions.

When the device is powered on, an internal voltage detector disables all functions whenever Vcc is

below about 2V at 3V device. Write Protect (#WP) pin provides hardware protection and is

recommended to be kept at VIL during power up and power down. A recovery time of minimum 1ms

is required before internal circuit gets ready for any command sequences (See Figure 10-1).

Vcc

#WP

#WE

1ms

(Min)

RY/#BY

5 ms (Max)

Undefined

Figure 10-1 Power ON/OFF sequence

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10.4 DC Electrical Characteristics

SPEC

PARAMETER

SYMBOL

CONDITIONS

UNIT

MIN

TYP

MAX

tRC= tRC MIN

#CE=VIL

Sequential Read current

Icc1

-

25

35

mA

IOUT=0mA

Program current

Erase current

Icc2

Icc3

-

25

35

mA

#CE=VIH

Standby current (TTL)

ISB1

ISB2

-

1

mA

µA

#WP=0V/Vcc

#CE=Vcc – 0.2V

Standby current (CMOS)

10

50

#WP=0V/Vcc

Input leakage current

Output leakage current

ILI

VIN= 0 V to Vcc

VOUT=0V to Vcc

-

±10

µA

ILO

I/O7~0, #CE,#WE,#RE,

#WP,CLE,ALE

Input high voltage

VIH

0.8 x Vcc

-

Vcc + 0.3

V

Input low voltage

VIL

VOH

-

-0.3

2.4

-

0.2 x Vcc

V

Output high voltage⁽¹⁾

Output low voltage⁽¹⁾

Output low current⁽²⁾

IOH=-400µA

IOL=2.1mA

VOL=0.4V

-

VOL

-

0.4

V

IOL(RY/#BY)

8

10

mA

Table 10.3 DC Electrical Characteristics

Note:

1. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.

2. IOL (RY/#BY) may need to be relaxed if RY/#BY pull-down strength is not set to full

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10.5 AC Measurement Conditions

SPEC

PARAMETER

SYMBOL

UNIT

MIN

MAX

10

Input Capacitance^{(1), (2)}

Input/Output Capacitance^{(1), (2)}

Input Rise and Fall Times

Input Pulse Voltages

CIN

CIO

TR/TF

-

pF

ns

V

10

5

0 to VCC

Vcc/2

Input/Output timing Voltage

Output load ⁽¹⁾

-

V

CL

1TTL GATE and CL=30pF

-

Table 10.4 AC Measurement Conditions

Notes:

1. Verified on device characterization , not 100% tested

2. Test conditions TA=25’C, f=1MHz, VIN=0V

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10.6 AC timing characteristics for Command, Address and Data Input

SPEC

PARAMETER

SYMBOL

UNIT

MIN

70

5

MAX

ALE to Data Loading Time⁽¹⁾

ALE Hold Time

tADL

tALH

tALS

tCH

-

ns

ALE setup Time

#CE Hold Time

10

5

CLE Hold Time

tCLH

tCLS

tCS

5

CLE setup Time

#CE setup Time

Data Hold Time

10

15

5

tDH

Data setup Time

Write Cycle Time

#WE High Hold Time

#WE Pulse Width

#WP setup Time

tDS

10

25

10

12

100

tWC

tWH

tWP

tWW

Table 10.5 AC timing characteristics for Command, Address and Data Input

Note:

1. tADL is the time from the #WE rising edge of final address cycle to the #WE rising edge of first data cycle.

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10.7 AC timing characteristics for Operation

SPEC

PARAMETER

SYMBOL

UNIT

MIN

10

-

MAX

ALE to #RE Delay

tAR

tCEA

tCHZ

tCLR

tCOH

tIR

-

ns

µs

ns

µs

ns

#CE Access Time

25

#CE HIGH to Output High-Z⁽¹⁾

CLE to #RE Delay

-

30

10

15

0

-

#CE HIGH to Output Hold

Output High-Z to #RE LOW

Data Transfer from Cell to Data Register

READ Cycle Time

-

tR

-

25

tRC

25

-

#RE Access Time

tREA

tREH

tRHOH

tRHW

tRHZ

tRLOH

tRP

20

#RE HIGH Hold Time

10

15

100

-

#RE HIGH to Output Hold

#RE HIGH to #WE LOW

#RE HIGH to Output High-Z⁽¹⁾

#RE LOW to output hold

#RE Pulse Width

-

100

5

-

12

20

-

Ready to #RE LOW

tRR

-

5/10/500

100

Reset Time (READ/PROGRAM/ERASE)⁽²⁾

#WE HIGH to Busy⁽³⁾

tRST

tWB

-

#WE HIGH to #RE LOW

tWHR

60

-

Table 10.6 AC timing characteristics for Operation

Notes:

1. Transition is measured ±200mV from steady-state voltage with load. This parameter is sampled and not

100 % tested.

2. The RESET (FFh) command is issued while the device is idle, the device goes busy for a maximum of 5us.

3. Do not issue new command during tWB, even if RY/#BY is ready.

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10.8

Program and Erase Characteristics

SPEC

PARAMETER

SYMBOL

UNIT

TYP

-

MAX

4

Number of partial page programs

NoP

cycles

µs

Page Program time

Block Erase Time

tPROG

tBERS

250

2

700

10

ms

Table 10.7 Program and Erase Characteristics

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11. TIMING DIAGRAMS

CLE

tCLS tCLH

tCS tCH

#CE

#WE

ALE

tWP

tALS

tDS

tALH

tDH

Command

I/Ox

Don’t care

Figure 11-1 Command Latch Cycle

CLE

#CE

#WE

ALE

tCLS

tCS

tWC

tWH

tWP

tALS

tALH

tDH

tDS

Address

I/Ox

Undefined

Don’t care

Figure 11-2 Address Latch Cycle

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CLE

#CE

ALE

tCLH

tCH

tALS

tWP

tWC

tWP

tDS

tWP

#WE

I/Ox

tWH

tDH

tDS tDH

tDH

tDS

Din 0

Din 1

Din Final¹

Don’t care

Note: 1. Din Final = 2,111(x8)

Figure 11-3 Data Latch Cycle

tCEA

#CE

#RE

tREA

tCHZ

tCOH

tRP

tREH

tRHZ

tRHOH

tRHZ

Dout

I/Ox

tRR

tRC

RY/#BY

Don’t care

Figure 11-4 Serial Access Cycle after Read

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#CE

#RE

tCHZ

tCOH

tRC

tREH

tRP

tRHZ

tREA

tRLOH

tREA

tCEA

tRHOH

Dout

I/Ox

tRR

RY/#BY

Don’t care

Figure 11-5 Serial Access Cycle after Read (EDO)

tCLR

CLE

#CE

#WE

#RE

I/Ox

tCLS tCLH

tCS

tCH

tWP

tCEA

tRP

tCHZ

tCOH

tWHR

tRHZ

tRHOH

tDS tDH

70h

tIR

tREA

Status

output

Don’t care

Figure 11-6 Read Status Operation

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CLE

tCLR

tAR

#CE

tWC

#WE

ALE

tWB

tRHZ

tR

tRC

tRP

#RE

tRR

Dout

n

Dout

n+1

Dout

m

00h

Address(4Cycles)

30h

I/Ox

RY/#BY

Busy

Don’t care

Figure 11-7 Page Read Operation

CLE

#CE

#RE

ALE

#WE

00h

Address (4 cycles)

30h

Data output

I/Ox

tR

RY/#BY

tCEA

tREA

Don’t care

#CE

tCHZ

tCOH

Out

#RE

I/Ox

Figure 11-8 #CE Don't Care Read Operation

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CLE

#CE

#WE

ALE

tCLR

tWC

tWB

tAR

tWHR

tREA

tRC

#RE

tRR

Dout

m

Dout

m+1

Row

Dout

Row

Col

00h

30h

05h

E0h

I/Ox

n

n+1

add 1

add 2

add 1

add 2

add 1

add 2

Column address n

Column address m

tR

Busy

RY/#BY

Don’t care

Figure 11-9 Random Data Output Operation

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CLE

#CE

#WE

ALE

#RE

I/Ox

tAR

tWHR

tREA

90h

00h

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

(or 20h)

Address, 1 cycle

Note: 1. See Table 9.1 for actual value.

Figure 11-10 Read ID

CLE

#CE

tWC

tADL

#WE

ALE

tWHR

tWB tPROG

#RE

Col

add 1

Col

add 2

Row

add 1

Row

add 2

Din

80h

10h

70h

Status

I/Ox

n

m

SERIAL DATA

INPUT command

PROGRAM

command

READ STATUS

command

1 up to m Byte

serial input

RY/#BY

x8 device:m = 2112 bytes

Don’t care

Figure 11-11 Page Program

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CLE

#CE

#WE

ALE

Address(4 cycles)

Data input

10h

80h

I/Ox

tCS

tCH

#CE

tWP

#WE

Don’t care

Figure 11-12 #CE Don't Care Page Program Operation

CLE

#CE

tADL

ｔWC

#WE

tWB

ALE

#RE

Col

Row

Col

Din

N+1

Din

N+1

Din

10h

80h

85h

Status

70h

I/Ox

add 2

add1

add2

ｎ

add 1

add1

add2

ｎ

Serial Data

Input Command

tPROG

Column address

Serial INPUT

Random Data Input

Command

Program

Command

Serial INPUT

Command

RY/#BY

Don’t care

Figure 11-13 Page Program with Random Data Input

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CLE

#CE

#WE

ALE

#RE

tADL

ｔWC

tWB

Col

Row

Col

Row

Din

n

35h

70h

00h

85h

10h

Status

I/Ox

add 1 add 2 add1 add2

1

Program

Command

Serial data INPUT

Command

tPROG

tR

RY/#BY

Busy

Don’t care

Figure 11-14 Copy Back

CLE

#CE

tWC

#WE

ALE

tWB

tBERS

#RE

Status

70h

60h

Address(2cycles)

D0h

I/Ox

RY/#BY

ERASE

command

READ STATUS

command

Busy

BLOCK ERASE SETUP

command

Don’t care

Figure 11-15 Block Erase

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CLE

#CE

#WE

tWB

tRST

RY/#BY

I/Ox

FFh

RESET

command

Figure 11-16 Reset

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12. INVALID BLOCK MANAGEMENT

12.1 Invalid blocks

The W29N01HV may have initial invalid blocks when it ships from factory. Also, additional invalid

blocks may develop during the use of the device. Nvb represents the minimum number of valid

blocks in the total number of available blocks (See Table 12.1). An invalid block is defined as blocks

that contain one or more bad bits. Block 0, block address 00h is guaranteed to be a valid block at

the time of shipment.

Parameter

Symbol

Min

Max

Unit

Valid block number

Nvb

1004

1024

blocks

Table 12.1 Valid Block Number

12.2

Initial invalid blocks

Initial invalid blocks are defined as blocks that contain one or more invalid bits when shipped from

factory.

Although the device contains initial invalid blocks, a valid block of the device is of the same quality

and reliability as all valid blocks in the device with reference to AC and DC specifications. The

W29N01HV has internal circuits to isolate each block from other blocks and therefore, the invalid

blocks will not affect the performance of the entire device.

Before the device is shipped from the factory, it will be erased and invalid blocks are marked. All

initial invalid blocks are marked with non-FFh at the first byte of spare area on the 1^stor 2^ndpage.

The initial invalid block information cannot be recovered if inadvertently erased. Therefore, software

should be created to initially check for invalid blocks by reading the marked locations before

performing any program or erase operation, and create a table of initial invalid blocks as following

flow chart

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Figure 12-12-1 Flow chart of create initial invalid block table

12.3

Error in operation

Additional invalid blocks may develop in the device during its life cycle. Following the procedures

herein is required to guarantee reliable data in the device.

After each program and erase operation, check the status read to determine if the operation failed.

In case of failure, a block replacement should be done with a bad-block management algorithm.

The system has to use a minimum 1bit ECC per 528 bytes of data to ensure data recovery.

Operation

Detection and recommended procedure

Erase

Program

Read

Status read after erase  Block Replacement

Status read after program  Block Replacement

Verify ECC  ECC correction

Table 12.2 Block failure

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Figure 12-12-2 Bad block Replacement

Note:

1. An error happens in the nth page of block A during program or erase operation.

2. Copy the data in block A to the same location of block B which is valid block.

3. Copy the nth page data of block A in the buffer memory to the nth page of block B

4. Creating or updating bad block table for preventing further program or erase to block A

.

12.4

Addressing in program operation

The pages within the block have to be programmed sequentially from LSB (least significant bit)

page to the MSB (most significant bit) within the block. The LSB is defined as the start page to

program, does not need to be page 0 in the block. Random page programming is prohibited.

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13. PACKAGE DIMENSIONS

13.1

TSOP 48-pin 12x20

1

48

e

E

b

c

D

H ^D

A2

A1

A



L

L1

Y

MILLIMETER

INCH

NOM.

Symbol

MIN.

NOM.

MAX.

0.047

MAX.

1.20

MIN.

0.002

A

A1

0.05

0.95

18.3

19.8

11.9

A2

D

1.00

18.4

20.0

12.0

1.05

18.5

20.2

12.1

0.037 0.039 0.041

0.724 0.728

0.720

0.780

0.468

0.795

0.476

0.787

0.472

0.009

H_D

E

0.011

0.008

0.17

0.10

0.22

0.27 0.007

b

c

0.21

0.004

0.020

0.50

e

0.024

0.031

0.50

0

L

0.60

0.80

0.70

0.020

0.028

L1

Y

0.004

5

0.10

5



0

Figure 13-1 TSOP 48-PIN 12X20mm

Release Date: January 11^th, 2018

Revision C

49

W29N01HV

13.2 Fine-Pitch Ball Grid Array 48-ball

Figure 13-2 Fine-Pitch Ball Grid Array 48-Ball

Release Date: January 11^th, 2018

Revision C

50

W29N01HV

13.3 Fine-Pitch Ball Grid Array 63-ball

Figure 13-3 Fine-Pitch Ball Grid Array 63-Ball (9x11mm)

Release Date: January 11^th, 2018

Revision C

51

W29N01HV

14. ORDERING INFORMATION

W 29N 01 H V S I N A

Winbond Standard Product

W: Winbond

Product Family

ONFI compatible NAND Flash memory

Density

01: 1 Gbit

Product Version

H

Supply Voltage and Bus Width

V: 2.7~3.6V and X8 device

Packages

S: TSOP-48

D: VFBGA-48

B: VFBGA-63 (9*11)

Temparature Ranges

I: -40 to 85'C

Option Information

N: General product

Reserved

A: General Product

Figure 14-1 Ordering Part Number Description

Release Date: January 11^th, 2018

Revision C

52

W29N01HV

15. VALID PART NUMBERS

The following table provides the valid part numbers for the W29N01HV NAND Flash Memory.

Please contact Winbond for specific availability by density and package type. Winbond NAND Flash

memories use a 12-digit Product Number for ordering.

Part Numbers for Industrial Temperature:

PACKAGE

TYPE

DENSITY VCC

BUS

X8

PRODUCT NUMBER

W29N01HVSINA

W29N01HVDINA

W29N01HVBINA

TOP SIDE MARKING

W29N01HVSINA

W29N01HVDINA

W29N01HVBINA

S

1G-bit

3V

TSOP-48

D

X8

VFBGA-48

B

X8

VFBGA-63

Table 15.1 Part Numbers for Industrial Temperature

Release Date: January 11^th, 2018

Revision C

53

W29N01HV

16. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

0.1

06/02/15

New Create for 3.3V product spec

Adding 63-ball BGA package

Update ordering information

0.2

06/05/15

0.3

A

07/29/15

10/15/15

Update ordering information

Remove Preliminary

10

19

Change description of DNU

B

C

12/01/17

01/11/18

Update Parameter Page Output Value

50

Update Package Dimension of VFBGA-48

Table 16.1 History Table

Trademarks

Winbond is trademark of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments,

airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion

control instruments, or for other applications intended to support or sustain life. Furthermore,

Winbond products are not intended for applications wherein failure of Winbond products could result

or lead to a situation where in personal injury, death or severe property or environmental damage

could occur.

Winbond customers using or selling these products for use in such applications do so at their own

risk and agree to fully indemnify Winbond for any damages resulting from such improper use or

sales.

Release Date: January 11^th, 2018

54

Revision C


型号：	W29N01HV
厂家：	WINBOND
描述：	1G-BIT 3.3V NAND FLASH MEMORY
文件：	总54页 (文件大小：1403K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W29N01HV [WINBOND]

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