W39L512Q-70B [WINBOND]

Flash, 64KX8, 70ns, PDSO32, 8 X 14 MM, STSOP-32;
W39L512Q-70B
型号: W39L512Q-70B
厂家: WINBOND    WINBOND
描述:

Flash, 64KX8, 70ns, PDSO32, 8 X 14 MM, STSOP-32

光电二极管
文件: 总28页 (文件大小:161K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
W39L512  
64K × 8 CMOS FLASH MEMORY  
Table of Contents-  
1.  
2.  
3.  
4.  
5.  
6.  
GENERAL DESCRIPTION ......................................................................................................... 3  
FEATURES................................................................................................................................. 3  
PIN CONFIGURATIONS ............................................................................................................ 4  
BLOCK DIAGRAM ...................................................................................................................... 5  
PIN DESCRIPTION..................................................................................................................... 5  
FUNCTIONAL DESCRIPTION ................................................................................................... 6  
6.1  
6.2  
6.3  
6.4  
Device Bus Operation..................................................................................................... 6  
6.1.1  
6.1.2  
6.1.3  
6.1.4  
6.1.5  
Read Mode...................................................................................................................6  
Write Mode ...................................................................................................................6  
Standby Mode ..............................................................................................................6  
Output Disable Mode....................................................................................................6  
Auto-select Mode..........................................................................................................6  
Data Protection............................................................................................................... 7  
6.2.1  
6.2.2  
6.2.3  
6.2.4  
6.2.5  
Boot Block Operation....................................................................................................7  
Low VDD Inhibit............................................................................................................7  
Write Pulse "Glitch" Protection .....................................................................................7  
Logical Inhibit................................................................................................................8  
Power-up Write Inhibit ..................................................................................................8  
Command Definitions ..................................................................................................... 8  
6.3.1  
6.3.2  
6.3.3  
6.3.4  
6.3.5  
Read Command ...........................................................................................................8  
Auto-select Command ..................................................................................................8  
Byte Program Command ..............................................................................................8  
Chip Erase Command ..................................................................................................9  
Page Erase Command .................................................................................................9  
Write Operation Status ................................................................................................. 10  
6.4.1  
6.4.2  
DQ7: Data Polling.......................................................................................................10  
DQ6: Toggle Bit..........................................................................................................10  
7.  
8.  
TABLE OF OPERATING MODES ............................................................................................ 11  
7.1  
7.2  
7.3  
Device Bus Operations................................................................................................. 11  
Auto-select Codes (High Voltage Method)................................................................... 11  
Software Product Identification and Boot Block Lockout Detection Flow Chart........... 17  
DC CHARACTERISTICS.......................................................................................................... 18  
8.1  
Pin Capacitance............................................................................................................ 18  
Publication Release Date: September 27, 2006  
- 1 -  
Revision A4  
W39L512  
9.  
AC CHARACTERISTICS.......................................................................................................... 19  
TIMING WAVEFORMS............................................................................................................. 22  
10.1 #CE Controlled Command Write Cycle Timing Diagram.............................................. 23  
10.2 Chip Erase Timing Diagram ......................................................................................... 23  
10.3 Page Erase Timing Diagram ........................................................................................ 24  
10.4 #DATA Polling Timing Diagram.................................................................................... 24  
10.5 Toggle Bit Timing Diagram ........................................................................................... 25  
ORDERING INFORMATION .................................................................................................... 26  
HOW TO READ THE TOP MARKING...................................................................................... 26  
PACKAGE DIMENSIONS......................................................................................................... 27  
13.1 32-pin STSOP (8 x 14 mm) .......................................................................................... 27  
VERSION HISTORY................................................................................................................. 28  
10.  
11.  
12.  
13.  
14.  
- 2 -  
W39L512  
1. GENERAL DESCRIPTION  
The W39L512 is a 512Kbit, 3.3-volt only CMOS flash memory organized as 64K × 8 bits. For flexible  
erase capability, the 512Kbits of data are divided into 16 small even pages with 4 Kbytes. The byte-  
wide (× 8) data appears on DQ7 DQ0. The device can be programmed and erased in-system with a  
standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the  
W39L512 results in fast program/erase operations with extremely low current consumption (compared  
to other comparable 3.3-volt flash memory products). The device can also be programmed and  
erased by using standard EPROM programmers.  
2. FEATURES  
Single 3.3-volt operations  
3.3-volt Read  
3.3-volt Erase  
3.3-volt Program  
Fast Program operation:  
Byte-by-Byte programming: 50 μS (max.)  
Fast Erase operation: 100 mS (max.)  
Read access time: 70/90 nS  
16 even pages with 4K bytes  
Any individual page can be erased  
Hardware protection:  
Optional 8K byte Top/Bottom Boot Block with lockout protection  
Flexible 4K-page size can be used as Parameter Blocks  
Typical program/erase cycles:  
1K/10K  
Twenty-year data retention  
Low power consumption  
Active current: 10 mA (typ.)  
Standby current: 15 μA (typ.)  
End of program detection  
Software method: Toggle bit/Data polling  
TTL compatible I/O  
JEDEC standard byte-wide pinouts  
Available packages: 32-pin PLCC and 32-pin STSOP (8 x 14 mm)  
Publication Release Date: September 27, 2006  
Revision A4  
- 3 -  
W39L512  
3. PIN CONFIGURATIONS  
A
1
2
V
D
D
#
W
E
A
1
5
N
C
N
C
N
C
3
4
2
1
32 31 30  
A14  
A13  
A8  
29  
28  
27  
26  
25  
24  
23  
22  
21  
5
6
A7  
A6  
7
A5  
32-pin  
PLCC  
8
A9  
A4  
9
A11  
A3  
#OE  
10  
11  
12  
13  
A2  
A10  
#CE  
DQ7  
A1  
A0  
DQ0  
14 15 16 17 18 19 20  
D
Q
1
D
Q
2
D
Q
4
D
Q
3
D
Q
5
D
Q
6
V
S
S
1
32  
#OE  
A10  
A11  
A9  
A8  
A13  
A14  
NC  
2
31  
30  
29  
28  
27  
26  
25  
3
#CE  
DQ7  
DQ6  
DQ5  
4
5
6
7
DQ4  
DQ3  
#WE  
VDD  
NC  
32-pin  
STSOP  
8
V
9
24  
23  
22  
21  
20  
19  
18  
17  
SS  
10  
NC  
DQ2  
DQ1  
DQ0  
A0  
11  
12  
13  
14  
15  
16  
A15  
A12  
A7  
A6  
A5  
A1  
A2  
A3  
A4  
- 4 -  
W39L512  
4. BLOCK DIAGRAM  
V
DD  
V
SS  
#CE  
DQ0  
.
.
OUTPUT  
BUFFER  
CONTROL  
#OE  
#WE  
DQ7  
A0  
CORE  
ARRAY  
.
.
DECODER  
A15  
5. PIN DESCRIPTION  
SYMBOL  
A0 A15  
DQ0 DQ7  
#CE  
PIN NAME  
Address Inputs  
Data Inputs/Outputs  
Chip Enable  
#OE  
Output Enable  
Write Enable  
Power Supply  
Ground  
#WE  
VDD  
VSS  
NC  
No Connections  
Publication Release Date: September 27, 2006  
Revision A4  
- 5 -  
W39L512  
6. FUNCTIONAL DESCRIPTION  
6.1 Device Bus Operation  
6.1.1 Read Mode  
The read operation of the W39L512 is controlled by #CE and #OE, both of which have to be low for  
the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip  
is de-selected and only standby power will be consumed. #OE is the output control and is used to gate  
data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.  
Refer to the timing waveforms for further details.  
6.1.2 Write Mode  
Device erasure and programming are accomplished via the command register. The contents of the  
register serve as inputs to the internal state machine. The state machine outputs dictate the function  
of the device.  
The command register itself does not occupy any addressable memory location. The register is a latch  
used to store the commands, along with the address and data information needed to execute the  
command. The command register is written to bring #WE to logic low state, while #CE is at logic low  
state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,  
whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens  
first. Standard microprocessor write timings are used.  
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing  
parameters.  
6.1.3 Standby Mode  
There are two ways to implement the standby mode on the W39L512 device, both using the #CE pin.  
A CMOS standby mode is achieved with the #CE input held at VDD ±0.3V. Under this condition the current  
is typically reduced to less than 20 μA. A TTL standby mode is achieved with the #CE pin held at VIH.  
Under this condition the current is typically reduced to 2 mA.  
In the standby mode the outputs are in the high impedance state, independent of the #OE input.  
6.1.4 Output Disable Mode  
With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the  
output pins to be in a high impedance state.  
6.1.5 Auto-select Mode  
The auto-select mode allows the reading of a binary code from the device and will identify its  
manufacturer and type. This mode is intended for use by programming equipment for the purpose of  
automatically matching the device to be programmed with its corresponding programming algorithm.  
This mode is functional over the entire temperature range of the device.  
To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin  
A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from  
VIL to VIH. All addresses are dont cares except A0 and A1 (see "Auto-select Codes").  
Publication Release Date: August 14, 2006  
- 6 -  
Revision A4  
W39L512  
The manufacturer and device codes may also be read via the command register, for instance, when  
the W39L512 is erased or programmed in a system without access to high voltage on the A9 pin. The  
command sequence is illustrated in "Auto-select Codes".  
Byte 0 (A0 = VIL) represents the manufacturers code (Winbond = DAH) and byte 1 (A0 = VIH) the  
device identifier code (W39L512 = 38H). All identifiers for manufacturer and device will exhibit odd  
parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the  
Auto-select, A1 must be low state.  
6.2 Data Protection  
The W39L512 is designed to offer protection against accidental erasure or programming caused by  
spurious system level signals that may exist during power transitions. During power up the device  
automatically resets the internal state machine in the Read mode. Also, with its control register  
architecture, alteration of the memory contents only occurs after successful completion of specific  
multi-bus cycle command sequences. The device also incorporates several features to prevent  
inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise.  
6.2.1 Boot Block Operation  
There are two alternatives to set the boot block. The 8K-byte in the top/bottom location of this device  
can be locked as boot block, which can be used to store boot codes. It is located in the last 8K bytes  
or first 8K bytes of the memory with the address range from E000(hex) to FFFF(hex) for top location  
or 0000(hex) to 1FFF(hex) for bottom location.  
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the  
data for the designated block cannot be erased or programmed (programming lockout), other memory  
locations can be changed by the regular programming method.  
In order to detect whether the boot block feature is set on the first/last 8K-byte block or not, users can  
perform software command sequence: enter the product identification mode (see Command Codes  
for Identification/Boot Block Lockout Detection for specific code), and then read from address  
0002(hex) for first(bottom) location or FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data  
is "1," the 8Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output  
data is "0," the lockout feature will be inactivated and the block can be erased/programmed.  
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte  
command) to exit the identification mode. For the specific code, see Command Codes for  
Identification/Boot Block Lockout Detection.  
6.2.2 Low VDD Inhibit  
To avoid initiation of a write cycle during VDD power-up and power-down, the W39L512 locks out  
when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are  
inhibited when VDD is less than 2.0V typical. The W39L512 ignores all write and read operations until  
VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V  
to prevent unintentional writes.  
6.2.3 Write Pulse "Glitch" Protection  
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.  
Publication Release Date: September 27, 2006  
- 7 -  
Revision A4  
W39L512  
6.2.4 Logical Inhibit  
Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle  
#CE and #WE must be a logical zero while #OE is a logical one.  
6.2.5 Power-up Write Inhibit  
Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising  
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state  
machine is automatically reset to the read mode on power-up.  
6.3 Command Definitions  
Device operations are selected by writing specific address and data sequences into the command  
register. Writing incorrect address and data values or writing them in the improper sequence will reset  
the device to the read mode. "Command Definitions" defines the valid register command sequences.  
6.3.1 Read Command  
The device will automatically power-up in the read state. In this case, a command sequence is not  
required to read data. Standard microprocessor read cycles will retrieve array data. This default value  
ensures that no spurious alteration of the memory content occurs during the power transition.  
The device will automatically returns to read state after completing an Embedded Program or  
Embedded Erase algorithm.  
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.  
6.3.2 Auto-select Command  
Flash memories are intended for use in applications where the local CPU can alter memory contents.  
As such, manufacture and device codes must be accessible while the device resides in the target  
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.  
However, multiplexing high voltage onto the address lines is not generally a desirable system design  
practice.  
The device contains an auto-select command operation to supplement traditional PROM programming  
methodology. The operation is initiated by writing the auto-select command sequence into the  
command register. Following the command write, a read cycle from address XX00H retrieves the  
manufacture code of DAH. A read cycle from address XX01H returns the device code (W39L512 =  
38H).  
To terminate the operation, it is necessary to write the auto-select exit command sequence into the  
register.  
6.3.3 Byte Program Command  
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The  
program command sequence is initiated by writing two "unlock" write cycles, followed by the program  
set-up command. The program address and data are written next, which in turn initiate the Embedded  
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens  
later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising  
edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program  
Algorithm. Upon executing the algorithm, the system is not required to provide further controls or  
- 8 -  
W39L512  
timings. The device will automatically provide adequate internally generated program pulses and verify  
the programmed cell margin.  
The automatic programming operation is completed when the data on DQ7 (also used as Data  
Polling) is equivalent to the data written to this bit at which time the device returns to the read mode  
and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device  
requires that a valid address to the device be supplied by the system at this particular instance of time  
for Data Polling operations. Data Polling must be performed at the memory location which is being  
programmed.  
Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a  
hardware reset occurs during the programming operation, the data at that particular location will be  
corrupted.  
Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot  
be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only  
erase operations can convert "0"s to "1"s.  
Refer to the Programming Command Flow Chart using typical command strings and bus operations.  
6.3.4 Chip Erase Command  
Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the  
"set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase  
command.  
Chip erase does not require the user to program the device prior to erase. Upon executing the  
Embedded Erase Algorithm command sequence the device will automatically erase and verify the  
entire memory for an all one data pattern. The erase is performed sequentially on each pages at the  
same time (see "Feature"). The system is not required to provide any controls or timings during these  
operations.  
The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and  
terminates when the data on DQ7 is "1" at which time the device returns to read the mode.  
Refer to the Erase Command Flow Chart using typical command strings and bus operations.  
6.3.5 Page Erase Command  
Page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the  
"set-up" command. Two more "unlock" write cycles then follows by the page erase command. The  
page address (any address location within the desired page) is latched on the falling edge of #WE,  
while the command (50H) is latched on the rising edge of #WE.  
Page erase does not require the user to program the device prior to erase. When erasing a page, the  
remaining unselected pages are not affected. The system is not required to provide any controls or  
timings during these operations.  
The automatic page erase begins after the erase command is completed, right from the rising edge of  
the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data  
Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an  
address within any of the pages being erased.  
Refer to the Erase Command flow Chart using typical command strings and bus operations.  
Publication Release Date: September 27, 2006  
- 9 -  
Revision A4  
W39L512  
6.4 Write Operation Status  
6.4.1 DQ7: Data Polling  
The W39L512 device features Data Polling as a method to indicate to the host that the embedded  
algorithms are in progress or completed.  
During the Embedded Program Algorithm, an attempt to read the device will produce the complement  
of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to  
read the device will produce the true data last written to DQ7.  
During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7  
output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce  
a "1" at the DQ7 output.  
For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write  
pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase  
#WE pulse. Data Polling must be performed at addresses within any of the pages being erased.  
Otherwise, the status may not be valid.  
Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously  
while the output enable (#OE) is asserted low. This means that the device is driving status information  
on DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on  
when the system samples the DQ7 output, it may read the status or valid data. Even if the device has  
completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 –  
DQ6 may be still invalid. The valid data on DQ0 DQ7 will be read on the successive read attempts.  
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded  
Erase Algorithm, or page erase time-out (see "Command Definitions").  
6.4.2 DQ6: Toggle Bit  
The W39L512 also features the "Toggle Bit" as a method to indicate to the host system that the  
embedded algorithms are in progress or completed.  
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling)  
data from the device at any address will result in DQ6 toggling between one and zero. Once the  
Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will  
be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising  
edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid  
after the rising edge of the sixth #WE pulse in the six write pulse sequence. For page erase, the  
Toggle Bit is valid after the last rising edge of the page erase #WE pulse. The Toggle Bit is active  
during the page erase time-out.  
Either #CE or #OE toggling will cause DQ6 to toggle.  
- 10 -  
W39L512  
7. TABLE OF OPERATING MODES  
7.1 Device Bus Operations  
(VID = 12 ±0.5V)  
PIN  
A9  
MODE  
#CE #OE #WE A0  
A1  
A1  
A1  
X
DQ0 DQ7  
Read  
VIL  
VIL  
VIH  
X
VIL  
VIH  
X
VIH  
VIL  
X
A0  
A0  
X
A9  
A9  
X
Dout  
Din  
Write  
Standby  
Write Inhibit  
High Z  
X
VIL  
X
X
X
X
High Z/Dout  
High Z/Dout  
High Z  
X
VIH  
VIH  
VIH  
VIH  
X
X
X
Output Disable  
VIL  
VIL  
VIL  
VIH  
VIL  
VIL  
X
X
X
Auto select Manufacturers ID  
Auto select Device ID  
VIL  
VIH  
VIL  
VIL  
VID  
VID  
DA(hex)  
38h  
7.2 Auto-select Codes (High Voltage Method)  
(VID = 12 ±0.5V)  
DESCRIPTION  
Manufacturer ID: Winbond  
Device ID: W39L512  
#CE #OE  
#WE  
VIH  
A9  
VID  
VID  
THE OTHER ADDRESS  
All Add = VIL  
DQ[7:0]  
DA(hex)  
38h  
VIL  
VIL  
VIL  
VIL  
VIH  
A1= VIH, All other = VIL  
Publication Release Date: September 27, 2006  
Revision A4  
- 11 -  
W39L512  
Command Definitions  
6TH  
CYCLE  
COMMAND  
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE  
7TH CYCLE  
DESCRIPTION  
Cycles Addr. (1)Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data  
Read  
1
6
6
4
AIN DOUT  
Chip Erase  
Page Erase  
Byte Program  
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10  
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 PA(3) 50  
5555 AA 2AAA 55 5555 A0 AIN DIN  
Top Boot Block  
Lockout –8KByte  
6
6
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 FFFF XX(4)  
5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 00000 XX(4)  
Bottom Boot Block  
Lockout - 8KByte  
Product ID Entry  
Product ID Exit (2)  
Product ID Exit (2)  
Notes:  
3
3
1
5555 AA 2AAA 55 5555 90  
5555 AA 2AAA 55 5555 F0  
XXXX F0  
1. Address Format: A15 A0 (Hex); Data Format: DQ7 DQ0 (Hex)  
2. Either one of the two Product ID Exit commands can be used.  
3. PA: Page Address  
PA = FXXXh for Page 15  
PA = EXXXh for Page 14  
PA = DXXXh for Page 13  
PA = CXXXh for Page 12  
PA = BXXXh for Page 11  
PA = AXXXh for Page 10  
PA = 9XXXh for Page 9  
PA = 8XXXh for Page 8  
PA = 7XXXh for Page 7  
PA = 6XXXh for Page 6  
PA = 5XXXh for Page 5  
PA = 4XXXh for Page 4  
PA = 3XXXh for Page 3  
PA = 2XXXh for Page 2  
PA = 1XXXh for Page 1  
PA = 0XXXh for Page 0  
4. XX: Don't care  
- 12 -  
W39L512  
Embedded Programming Algorithm  
Start  
Write Program Command Sequence  
(see below)  
#Data Polling/ Toggle bit  
Pause  
T
BP  
No  
Last Address  
?
Increment Address  
Yes  
Programming Completed  
Program Command Sequence (Address/Command):  
5555H/AAH  
2AAAH/55H  
5555H/A0H  
Program Address/Program Data  
Publication Release Date: September 27, 2006  
Revision A4  
- 13 -  
W39L512  
Embedded Erase Algorithm  
Start  
Write Erase Command Sequence  
(see below)  
#Data Polling or Toggle Bit  
Successfully Completed  
Pause TEC/TPEC  
Erasure Completed  
Chip Erase Command Sequence  
(Address/Command):  
Individual Page Erase  
Command Sequence  
(Address/Command):  
5555H/AAH  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
5555H/80H  
5555H/AAH  
2AAAH/55H  
5555H/10H  
5555H/AAH  
2AAAH/55H  
Page Address/50H  
- 14 -  
W39L512  
Embedded #Data Polling Algorithm  
Start  
VA = Byte address for programming  
= Any of the page addresses within  
the page being erased during page  
erase operation  
Read Byte  
(DQ0 - DQ7)  
Address = VA  
=Any of the device addresses being erased  
during chip operation  
No  
DQ7 = Data  
?
Yes  
Pass  
Embedded Toggle Bit Algorithm  
Start  
Read Byte  
(DQ0 - DQ7)  
Address = Don't Care  
Yes  
DQ6 = Toggle  
?
No  
Pass  
Publication Release Date: September 27, 2006  
Revision A4  
- 15 -  
W39L512  
Boot Block Lockout Enable Flow Chart  
Boot Block Lockout  
Feature Set Flow  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Pause 2 mS  
Load data 80  
to  
address 5555  
Exit  
Load data AA  
to  
address 5555  
Load data 55  
to  
address 2AAA  
Load data 70  
70 to lcok 8K Boot Block  
to  
address 5555  
Load data XX  
FFFF(XX) to lock Top Boot Block  
to  
0000(XX) to lock Bottom Boot Block  
address FFFF/0 h  
- 16 -  
W39L512  
7.3 Software Product Identification and Boot Block Lockout Detection Flow Chart  
Product  
Product  
Identification  
Entry (1)  
Product  
Identification  
and Boot Block  
Lockout  
Identification Exit(6)  
M
D
o
t
det
(i3)  
Load data AA  
to  
address 5555  
Load data AA  
to  
address 5555  
(2)  
Load data 55  
to  
address 2AAA  
Load data 55  
to  
address 2AAA  
Read address = 0000  
data = DA  
(2)  
(4)  
Load data 90  
to  
Load data F0  
to  
Read address = 0001  
data = 38  
address 5555  
address 5555  
Read address= 02/FFF2  
for Bottom/Top  
data: in DQ1 = "1" or "0"  
for 8K Boot Block  
Pause 10  
S
μ
Pause 10  
S
μ
(5)  
Normal Mode  
Notes for software product identification/boot block lockout detection:  
(1) Data Format: DQ7 DQ0 (Hex); Address Format: A15 A0 (Hex)  
(2) A1 A15 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.  
(3) The device does not remain in identification and boot block lockout detection mode if power down.  
(4) If the output data in DQ0 or DQ1= " 1 " the boot block programming lockout feature is activated; if the output data  
in DQ0 or DQ1= " 0," the lockout feature is inactivated and the matched boot block can be programmed.  
(5) The device returns to standard operation mode.  
(6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout  
detection.  
Publication Release Date: September 27, 2006  
- 17 -  
Revision A4  
W39L512  
8. DC CHARACTERISTICS  
Absolute maximum Ratings  
PARAMETER  
Power Supply Voltage to VSS Potential  
Operating Temperature  
RATING  
-2.0 to +4.6  
0 to +70  
UNIT  
V
°C  
°C  
V
Storage Temperature  
-65 to +125  
-2.0 to +4.6  
-2.0 to +13.0  
Voltage on Any Pin to Ground Potential Except A9  
Voltage on A9 Pin to Ground Potential  
V
Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability  
of the device.  
DC Operating Characteristics  
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)  
LIMITS  
PARAMETER  
SYM.  
TEST CONDITIONS  
UNIT  
MIN. TYP.  
MAX.  
#CE = #OE = VIL, #WE = VIH,  
IDD all DQs open, Address inputs = VIL/  
VIH, at f = 5 MHz  
mA  
Power Supply Current  
-
10  
20  
ISB1  
Standby VDD Current  
(TTL input)  
#CE = VIH, all DQs open  
Other inputs = VIL/VIH  
-
-
1
2
mA  
μA  
Standby VDD Current  
(CMOS input)  
#CE = VDD -0.3V, all DQs open  
Other inputs = VDD -0.3V/ VSS  
ISB2  
15  
50  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
ILI  
VIN = VSS to VDD  
-
-
-
-
-
-
-
-
1
μA  
μA  
V
ILO  
VIL  
VIH  
VOUT = VSS to VDD  
1
0.8  
-
-
-0.3  
2.0  
-
Input High Voltage  
VDD +0.5  
0.45  
-
V
Output Low Voltage  
Output High Voltage  
VOL IOL = 2.1 mA  
VOH IOH = -0.4 mA  
V
2.4  
V
8.1 Pin Capacitance  
(VDD = 3.3V, TA = 25° C, f = 1 MHz)  
PARAMETER  
Input Capacitance  
SYMBOL  
CIN  
CONDITIONS  
VIN = 0V  
TYP.  
6
MAX.  
UNIT  
8
pF  
pF  
Output Capacitance  
COUT  
VOUT = 0V  
10  
12  
- 18 -  
W39L512  
9. AC CHARACTERISTICS  
AC Test Conditions  
PARAMETER  
Input Pulse Levels  
CONDITIONS  
0V to 3V  
<5 nS  
Input Rise/Fall Time  
Input/Output Timing Level  
Output Load  
1.5V/1.5V  
1 TTL Gate and CL = 30 pF  
AC Test Load and Waveform  
+3.3V  
1.2K  
Ω
D
OUT  
30 pF  
(Including Jig and Scope)  
2.1K  
Ω
Input  
Output  
3V  
1.5V  
1.5V  
0V  
Test Point  
Test Point  
Publication Release Date: September 27, 2006  
Revision A4  
- 19 -  
W39L512  
AC Characteristics, continued  
Read Cycle Timing Parameters  
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)  
W39L512-70  
MIN. MAX.  
70  
W39L512-90  
PARAMETER  
SYM.  
UNIT  
MIN.  
MAX.  
Read Cycle Time  
TRC  
-
90  
-
-
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
Chip Enable Access Time  
Address Access Time  
TCE  
-
-
70  
70  
35  
-
90  
90  
45  
-
TAA  
-
Output Enable Access Time  
#CE Low to Active Output  
#OE Low to Active Output  
#CE High to High-Z Output  
#OE High to High-Z Output  
Output Hold from Address Change  
TOE  
-
-
TCLZ  
TOLZ  
TCHZ  
TOHZ  
TOH  
0
0
-
0
0
-
-
-
25  
25  
-
25  
25  
-
-
-
0
0
Write Cycle Timing Parameters  
PARAMETER  
Address Setup Time  
Address Hold Time  
#WE and #CE Setup Time  
#WE and #CE Hold Time  
#OE High Setup Time  
#OE High Hold Time  
#CE Pulse Width  
SYMBOL  
TAS  
MIN.  
0
TYP.  
MAX.  
UNIT  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
nS  
μS  
mS  
mS  
-
-
TAH  
40  
0
-
-
TCS  
-
-
TCH  
0
-
-
TOES  
TOEH  
TCP  
0
-
-
0
-
-
100  
100  
100  
40  
10  
-
-
-
-
#WE Pulse Width  
TWP  
TWPH  
TDS  
-
-
#WE High Width  
-
Data Setup Time  
-
-
Data Hold Time  
TDH  
-
-
Byte Programming Time  
Chip Erase Cycle Time  
Page Erase Cycle Time  
TBP  
35  
50  
12.5  
50  
100  
25  
TEC  
-
TEP  
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:  
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.  
- 20 -  
W39L512  
AC Characteristics, continued  
Power-up Timing  
PARAMETER  
SYMBOL  
TPU. READ  
TPU. WRITE  
TYPICAL  
UNIT  
μS  
Power-up to Read Operation  
Power-up to Write Operation  
100  
5
mS  
Data Polling and Toggle Bit Timing Parameters  
W39L512-70  
MIN. MAX.  
35  
W39L512-90  
MIN. MAX.  
45  
PARAMETER  
SYM.  
UNIT  
-
-
nS  
nS  
nS  
nS  
#OE to Data Polling Output Delay  
#CE to Data Polling Output Delay  
#OE to Toggle Bit Output Delay  
#CE to Toggle Bit Output Delay  
TOEP  
TCEP  
TOET  
TCET  
-
-
-
70  
35  
70  
-
-
-
90  
45  
90  
Publication Release Date: September 27, 2006  
Revision A4  
- 21 -  
W39L512  
10. TIMING WAVEFORMS  
Read Cycle Timing Diagram  
T
RC  
Address A15-0  
#CE  
TCE  
TOE  
#OE  
TOHZ  
TOLZ  
V
IH  
#WE  
TCLZ  
T
OH  
TCHZ  
Data Valid  
High-Z  
High-Z  
DQ7-0  
Data Valid  
AA  
T
#WE Controlled Command Write Cycle Timing Diagram  
T
AS  
T
AH  
Address A15-0  
#CE  
T
CS  
T
CH  
T
OES  
T
OEH  
#OE  
#WE  
T
WP  
T
WPH  
T
DS  
DQ7-0  
Data Valid  
T
DH  
- 22 -  
W39L512  
Timing Waveforms, continued  
10.1 #CE Controlled Command Write Cycle Timing Diagram  
AS  
T
TAH  
Address A15-0  
#CE  
T
CPH  
T
CP  
T
OES  
T
OEH  
#OE  
#WE  
T
DS  
High Z  
DQ7-0  
Data Valid  
T
DH  
10.2 Chip Erase Timing Diagram  
Six-byte code for 3.3V-only software  
chip erase  
Address A15-0  
5555  
80  
5555  
2AAA  
55  
5555  
AA  
5555  
2AAA  
55  
DQ7-0  
#CE  
AA  
10  
#OE  
#WE  
TWP  
SB0  
TEC  
TWPH  
Internal Erase starts  
SB2  
SB3  
SB5  
SB4  
SB1  
Publication Release Date: September 27, 2006  
Revision A4  
- 23 -  
W39L512  
Timing Waveforms, continued  
10.3 Page Erase Timing Diagram  
Six-byte commands for 3.3V-only  
Page Erase  
PA  
5555  
5555  
2AAA  
55  
5555  
2AAA  
55  
Address A15-0  
80  
50  
DQ7-0  
#CE  
AA  
AA  
#OE  
#WE  
T
WP  
T
EP  
T
WPH  
Internal Erase starts  
SB0  
PA = Page Address  
SB2  
SB3  
SB5  
SB4  
SB1  
Please refer to page 9 for detail informatio  
10.4 #DATA Polling Timing Diagram  
Address A15-0  
#WE  
An  
An  
An  
An  
T
CEP  
#CE  
#OE  
T
OEH  
T
OES  
T
OEP  
# X  
# X  
DQ7  
X
X
T
T
BP or EC  
- 24 -  
W39L512  
Timing Waveforms, continued  
10.5 Toggle Bit Timing Diagram  
Address A15-0  
#WE  
#CE  
OES  
T
OEH  
T
#OE  
DQ6  
TBP orTEC  
Publication Release Date: September 27, 2006  
Revision A4  
- 25 -  
W39L512  
11. ORDERING INFORMATION  
ACCESS POWER SUPPLY STANDBY VDD  
TIME  
(NS)  
70  
CURRENT MAX. CURRENT MAX.  
PART NO.  
PACKAGE  
CYCLE  
(MA)  
20  
(MA)  
W39L512P-70  
W39L512P-90  
W39L512Q-70  
W39L512Q-90  
W39L512P-70B  
W39L512P-90B  
W39L512Q-70B  
W39L512Q-90B  
W39L512P-90Z  
2
2
2
2
2
2
2
2
2
32-pin PLCC  
1K  
1K  
90  
20  
32-pin PLCC  
70  
20  
32-pin STSOP  
32-pin STSOP  
32-pin PLCC  
1K  
90  
20  
1K  
70  
20  
10K  
10K  
10K  
10K  
10K  
90  
20  
32-pin PLCC  
70  
20  
32-pin STSOP  
32-pin STSOP  
32-pin PLCC Lead free  
90  
20  
90  
20  
Notes:  
1. Winbond reserves the right to make changes to its products without prior notice.  
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in  
applications where personal injury might occur as a consequence of product failure.  
12. HOW TO READ THE TOP MARKING  
Example: The top marking of 32-pin PLCC W39L512P-70  
W39L512P-70  
2138977A-A12  
149OBSA  
1st line: winbond logo  
2nd line: the part number: W39L512P-70  
3rd line: the lot number  
4th line: the tracking code: 149 O B SA  
149: Packages made in '01, week 49  
O: Assembly house ID: A means ASE, O means OSE, ...etc.  
B: IC revision; A means version A, B means version B, ...etc.  
SA: Process code  
- 26 -  
W39L512  
13. PACKAGE DIMENSIONS  
32-pin PLCC  
HE  
E
4
1
32  
30  
Dimension in Inches  
Dimension in mm  
Symbol  
A
Min. Nom. Max.  
Min. Nom. Max.  
5
29  
0.140  
3.56  
0.020  
0.50  
1
A
0.105  
0.026  
0.016  
0.008  
0.110  
0.028  
0.018  
0.010  
0.550  
0.450  
0.050  
0.510  
0.410  
0.590  
0.490  
0.090  
0.115  
0.032  
0.022  
0.014  
2.67  
0.66  
0.41  
0.20  
2.80  
0.71  
2.93  
0.81  
0.56  
0.35  
A
b
b
c
D
E
e
2
1
0.46  
0.25  
G
D
D
HD  
0.547  
0.447  
0.044  
0.490  
0.390  
0.585  
0.485  
0.075  
0.553  
0.453  
0.056  
0.530  
0.430  
0.595  
0.495  
0.095  
0.004  
13.89  
11.35  
1.12  
14.05  
11.51  
1.42  
13.97  
11.43  
1.27  
12.45  
9.91  
12.95  
13.46  
10.92  
15.11  
12.57  
2.41  
D
E
D
E
G
G
H
H
10.41  
14.99  
12.45  
2.29  
21  
13  
14.86  
12.32  
1.91  
L
y
14  
20  
c
0.10  
0
10  
0
10  
θ
Notes:  
L
A
A
2
1
A
1. Dimensions D & E do not include interlead flash.  
2. Dimension b1 does not include dambar protrusion/intrusion.  
3. Controlling dimension: Inches.  
θ
e
b
4. General appearance spec. should be based on final  
visual inspection sepc.  
b
1
Seating Plane  
y
E
G
13.1 32-pin STSOP (8 x 14 mm)  
HD  
D
Dimension in Inches Dimension in mm  
Symbol  
c
Max.  
Min. Nom. Max. Min. Nom.  
0.047  
1.20  
e
A
0.002  
0.035  
0.006  
0.041  
0.05  
0.95  
0.17  
0.10  
0.15  
1
A
0.040  
1.00  
0.22  
2
E
A
1.05  
0.27  
0.007 0.009 0.010  
b
c
D
E
b
0.004  
0.008  
-----  
12.40  
8.00  
0.21  
-----  
0.488  
0.315  
0.551  
0.020  
14.00  
D
H
e
0.50  
0.60  
0.80  
0.50  
0.70  
0.020 0.024 0.028  
0.031  
L
1
L
θ
0.000  
0
0.00  
0
0.10  
5
0.004  
5
Y
A
A
1 A  
2
L
Y
3
3
θ
L
1
Publication Release Date: September 27, 2006  
Revision A4  
- 27 -  
W39L512  
14. VERSION HISTORY  
VERSION  
DATE  
PAGE  
DESCRIPTION  
A1  
June 4, 2002  
-
Initial Issued  
Remove Block Erase from the Embedded Erase  
Algorithm  
11  
A2  
July 9, 2002  
12  
25  
26  
Correct Embedded #Data Polling Algorithm  
Add important notice  
A3  
A4  
April 14, 2005  
September 27, 2006  
Add W39L512P-90Z lead free package  
Important Notice  
Winbond products are not designed, intended, authorized or warranted for use as components  
in systems or equipment intended for surgical implantation, atomic energy control  
instruments, airplane or spaceship instruments, transportation instruments, traffic signal  
instruments, combustion control instruments, or for other applications intended to support or  
sustain life. Further more, Winbond products are not intended for applications wherein failure  
of Winbond products could result or lead to a situation wherein personal injury, death or  
severe property or environmental damage could occur.  
Winbond customers using or selling these products for use in such applications do so at their  
own risk and agree to fully indemnify Winbond for any damages resulting from such improper  
use or sales.  
Headquarters  
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.  
27F, 2299 Yan An W. Rd. Shanghai,  
2727 North First Street, San Jose,  
No. 4, Creation Rd. III,  
Science-Based Industrial Park,  
Hsinchu, Taiwan  
TEL: 886-3-5770066  
FAX: 886-3-5665577  
200336 China  
CA 95134, U.S.A.  
TEL: 86-21-62365999  
FAX: 86-21-62365998  
TEL: 1-408-9436666  
FAX: 1-408-5441798  
http://www.winbond.com.tw/  
Taipei Office  
Winbond Electronics Corporation Japan  
Winbond Electronics (H.K.) Ltd.  
9F, No.480, Rueiguang Rd.,  
Neihu District, Taipei, 114,  
Taiwan, R.O.C.  
TEL: 886-2-8177-7168  
FAX: 886-2-8751-3579  
7F Daini-ueno BLDG, 3-7-18  
Shinyokohama Kohoku-ku,  
Yokohama, 222-0033  
TEL: 81-45-4781881  
FAX: 81-45-4781800  
Unit 9-15, 22F, Millennium City,  
No. 378 Kwun Tong Rd.,  
Kowloon, Hong Kong  
TEL: 852-27513100  
FAX: 852-27552064  
Please note that all data and specifications are subject to change without notice.  
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.  
- 28 -  

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