W39V040FAQZ [WINBOND]
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| 型号： | W39V040FAQZ |
| 厂家： | 
WINBOND |
| 描述： | 暂无描述 存储 闪光灯 PC |
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W39V040A
512K × 8 CMOS FLASH MEMORY
WITH LPC INTERFACE
1. GENERAL DESCRIPTION
The W39V040A is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K × 8 bits. For
flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are
composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased
in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture
of the W39V040A results in fast program/erase operations with extremely low current consumption. This
device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in
the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs.
But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also
be programmed and erased using standard EPROM programmers.
2. FEATURES
• Single 3.3-volt Operations:
− 3.3-volt Read
− 3.3-volt Erase
− 3.3-volt Program
• Fast Program Operation:
− Byte-by-Byte programming: 35 µS (typ.)
• Hardware protection:
− Optional 16K byte or 64K byte Top Boot Block
with lockout protection
− #TBL & #WP support the whole chip hardware
protection
• Flexible 4K-page size can be used as Parameter
Blocks
• Low power consumption
• Fast Erase Operation:
− Active current: 12.5 mA (typ. for LPC mode)
− Chip erase 100 mS (max.)
− Sector erase 25 mS (max.)
− Page erase 25 mS (max.)
• Automatic program and erase timing with
internal VPP generation
• End of program or erase detection
− Toggle bit
− Data polling
• Fast Read access time: Tkq 11 nS
• Endurance: 10K cycles (typ.)
• Twenty-year data retention
• Latched address and data
• TTL compatible I/O
• Available packages: 32L PLCC, 32L STSOP
• 8 Even sectors with 64K bytes each, which is
composed of 16 flexible pages with 4K bytes
• Any individual sector or page can be erased
Publication Release Date: December 19, 2002
- 1 -
Revision A2
W39V040A
3. PIN CONFIGURATIONS
4. BLOCK DIAGRAM
#WP
7FFFF
BOOT BLOCK,
16K BYTES
7C000
#TBL
LPC
CLK
7BFFF
PARAMETER BLOCK1,
Interface
MAIN MEMORY
SECTOR7,
8K BYTES
LAD[3:0]
#LFRAM
7A000
79FFF
64K BYTES
PARAMETER BLOCK2,
8K BYTES
78000
MODE
77FFF
MEMORY BLOCK,
32K BYTES
70000
6FFFF
#RESET
MAIN MEMORY SECTOR6, 64K BYTES
MAIN MEMORY SECTOR5, 64K BYTES
MAIN MEMORY SECTOR4, 64K BYTES
MAIN MEMORY SECTOR3, 64K BYTES
A
1
0
^
R
/
A
8
^
A
9
^
60000
#
C
^
5FFFF
#
R
E
S
E
T
G
P
I
G
P
I
G
P
I
50000
4FFFF
R/#C
C
L
K
v
V
D
D
40000
2
v
3
v
N
C
4
v
A[10:0]
Program-
mer
3FFFF
30000
2FFFF
DQ[7:0]
Interface
4
3
2
1
32 31 30
MAIN MEMORY SECTOR2, 64K BYTES
MAIN MEMORY SECTOR1, 64K BYTES
MAIN MEMORY SECTOR0, 64K BYTES
20000
#OE
#WE
1FFFF
A7(GPI1)
A6(GPI0)
5
6
29
28
27
26
25
24
23
22
21
MODE
Vss
10000
0FFFF
00000
7
NC
A5(#WP)
A4(#TBL)
A3(RSV)
A2(RSV)
A1(RSV)
A0(RSV)
DQ0(LAD0)
8
NC
32L PLCC
9
VDD
#OE(#INIT)
10
11
12
13
#WE(#LFRAM)
NC
5. PIN DESCRIPTION
DQ7(RSV)
14 15 16 17 18 19 20
INTERFACE
D
Q
1
D
Q
2
D
Q
5
V
S
S
D
Q
4
D
Q
6
D
Q
3
SYM.
PIN NAME
PGM
LPC
^
^
^
^
^
^
L
L
R
S
V
v
R
S
V
v
R
S
V
v
L
A
D
1
A
D
2
A
D
3
MODE
#RESET
#INIT
#TBL
#WP
*
*
*
*
*
*
*
*
*
*
*
*
Interface Mode Selection
Reset
Initialize
Top Boot Block Lock
Write Protect
CLK Input
General Purpose Inputs
Identification Inputs
Address/Data Inputs
LPC Cycle Initial
Row/Column Select
Address Inputs
Data Inputs/Outputs
Output Enable
Write Enable
v
v
v
NC
NC
#OE(#INIT)
#WE(#LFRAM
1
2
3
4
5
32
CLK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
NC
SS
DD
GPI[4:0]
ID[3:0]
LAD[3:0]
#LFRAM
R/#C
A[10:0]
DQ[7:0]
#OE
#WE
VDD
VSS
RSV
DQ7(RSV)
DQ6(RSV)
DQ5(RSV)
DQ4(RSV)
DQ3(LAD3)
V
MODE
A10(GPI4)
R/#C(CLK)
VDD
6
7
8
32L STSOP
NC
#RESET
A9(GPI3)
A8(GPI2)
A7(GPI1)
A6(GPI0)
VSS
9
10
DQ2(LAD2)
DQ1(LAD1)
DQ0(LAD0)
A0(RSV)
A1(RSV)
A2(RSV)
A3(RSV)
11
12
13
14
15
16
*
*
*
*
*
*
*
*
*
A5(#WP)
A4(#TBL)
*
*
*
*
Power Supply
Ground
Reserve Pins
No Connection
NC
- 2 -
W39V040A
6. FUNCTIONAL DESCRIPTION
Interface Mode Selection And Description
This device can be operated in two interface modes, one is Programmer interface mode, and the other is
LPC interface mode. The MODE pin of the device provides the control between these two interface
modes. These interface modes need to be configured before power up or return from #RESET. When
MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to
low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash
parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is
mapped to the higher internal address A[18:11]. And the column address is mapped to the lower internal
address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.0. Through
the LAD[3:0] and #LFRAM to communicate with the system chipset .
Read(Write) Mode
In Programmer interface mode, the read(write) operation of the W39V040A is controlled by #OE (#WE).
The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the
output control and is used to gate data from the output pins. The data bus is in high impedance state
when #OE is high. As in the LPC interface the "bit 1 of CYCLE TYPE+DIR" determines mode, the read
or write. Refer to the timing waveforms for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is
in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be
at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read
or standby mode, it depends on the control signals.
Boot Block Operation and Hardware Protection at Initial - #TBL and #WP
There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this
device can be locked as boot block, which can be used to store boot codes. It is located in the last
16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex).
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
Besides the software method, there is a hardware method to protect the top boot block and other
sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not
be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be
programmed/erased.
In order to detect whether the boot block feature is set on or not, users can perform software command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output
data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the
DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be
erased/programmed. But the hardware protection will override the software lock setting, i.e., while the
#TBL pin is trapped at low state, the top boot block cannot be programmed/erased whether the output
data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL will lock the whole 64Kbytes top boot
Publication Release Date: December 19, 2002
- 3 -
Revision A2
W39V040A
block, it will not partially lock the 16Kbytes boot block. You can check the DQ2/DQ3 at the address
7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin
is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend
on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then
boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP
state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block
can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot
block are programmed/erased inhibited.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading
cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed
within fast 100 mS (max). The host system is not required to provide any control or timing during this
operation. If the boot block programming lockout is activated, only the data in the other memory sectors
will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state
before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase
operation if the “boot block programming lockout feature” is not activated. The device will automatically
return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be
used to detect end of erase cycle.
Sector/Page Erase Operation
Sector/page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing
the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command.
The sector/page address (any address location within the desired sector/page) is latched on the rising
edge of R/C, while the command (30H/50H) is latched on the rising edge of #WE in programmer mode.
Sector/page erase does not require the user to program the device prior to erase. When erasing a
sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is
not required to provide any controls or timings during these operations.
The automatic sector/page erase begins after the erase command is completed, right from the rising
edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on
DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be
performed at an address within any of the sectors/pages being erased.
Refer to the Erase Command flow Chart using typical command strings and bus operations.
Program Operation
The W39V040A is programmed on a byte-by-byte basis. Program operation can only change logical
data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot
block from "0" to "1", is needed before programming.
The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte
Programming). The device will internally enter the program operation immediately after the
byte-program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be
used to detect end of program cycle.
- 4 -
W39V040A
Hardware Data Protection
The integrity of the data stored in the W39V040A is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming and read operation is inhibited when VDD is less
than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the devices will automatically time-out 5
mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W39V040A includes a data polling feature to indicate the end of a program or erase cycle. When
the W39V040A is in the internal program or erase cycle, any attempts to read DQ7 of the last byte
loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7
will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become logical
"1" or true data when the erase cycle has been completed.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W39V040A provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Multi-Chip Operation
Multiple devices can be wired on the single LPC bus. There are four ID pins can be used to support up to
16 devices. But in order not to violate the BIOS ROM memory space defined by Intel, Winbond
W39V040A will only used 3 ID pins to allow up to 8 devices, 4Mbytes for BIOS code and 4Mbytes for
registers memory space.
Register
There are two kinds of registers on this device, the General Purpose Input Registers and Product
Identification Registers. Users can access these registers through respective address in the 4Gbytes
memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the states of GPI[4:0] pins on the W39V040A. This is a pass-through register, which
can be read via memory address FFBxE100(hex). The "x" in the addresses represents the ID [3:0] pin
straps. Since it is pass-through register, there is no default value.
Publication Release Date: December 19, 2002
- 5 -
Revision A2
W39V040A
GPI Register
BIT
7 − 5
FUNCTION
Reserved
4
3
2
1
0
Read GPI4 pin status
Read GPI3 pin status
Read GPI2 pin status
Read GPI1 pin status
Read GPI0 pin status
Product Identification Registers
There is an alternative software method (six commands bytes) to read out the Product Identification in
both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment
can automatically matches the device with its proper erase and programming algorithms.
In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access
the product ID for programmer interface mode. A read from address 0000(hex) outputs the
manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 3D(hex).” The
product ID operation can be terminated by a three-byte command sequence or an alternate one-byte
command sequence (see Command Definition table for detail).
Identification Input Pins ID[3:0]
These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot
device should be 0000b. And all the subsequent parts should use the up-count strapping. Note that a 1M
byte ROM will occupy two Ids. For example: a 1MByte ROM's ID is 0000b, the next ROM's ID is 0010b.
These pins all are pulled down with internal resistor.
Memory Address Map
There are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M
system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS storage
space, the ID[2:0] pins are inverted in the ROM and are compared to address lines [21:19]. ID[3] can be
used as like active low chip-select pin.
The 32Mbit address space is as below:
BLOCK
LOCK
ADDRESS RANGE
4M Byte BIOS ROM
None
FFFF, FFFFh: FFC0, 0000h
The ROM responds to 640K (top 512K + bottom 128K) byte pages based on the ID pins strapping
according to the following table:
ID[2:0] PINS
ROM BASED ADDRESS RANGE
FFFF, FFFFh: FFF8, 0000h & 000F, FFFFh: 000E, 00000h
FFF7, FFFFh: FFF0, 0000h
FFEF, FFFFh: FFE8, 0000h
FFE7, FFFFh: FFE0, 0000h
000
001
010
011
- 6 -
W39V040A
Continued
100
FFDF, FFFFh: FFD8, 0000h
FFD7, FFFFh: FFD0, 0000h
FFCF, FFFFh: FFC8, 0000h
FFC7, FFFFh: FFC0, 0000h
101
110
111
Table of Operating Modes
Operating Mode Selection - Programmer Mode
PINS
ADDRESS
MODE
#OE
VIL
VIH
X
VIL
X
#WE #RESET
DQ.
Read
Write
VIH
VIL
X
VIH
VIH
VIL
VIH
VIH
VIH
AIN
AIN
X
X
X
Dout
Din
Standby
High Z
X
High Z/DOUT
High Z/DOUT
High Z
Write Inhibit
Output Disable
VIH
VIH
X
X
Operating Mode Selection - LPC Mode
Operation modes in LPC interface mode are determined by "cycle type" when it is selected. When it is
not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory
Cycle Definition".
Standard LPC Memory Cycle Definition
NO. OF
FIELD
DESCRIPTION
CLOCKS
"0000b" appears on LPC bus to indicate the initial
Start
1
"010Xb" indicates memory read cycle; while "011xb" indicates memory write
cycle. "X" mean don't have to care.
Cycle Type & Dir
TAR
1
2
Turned Around Time
Address Phase for Memory Cycle. LPC supports the 32 bits address protocol.
The addresses transfer most significant nibble first and least significant nibble
last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.)
Synchronous to add wait state. "0000b" means Ready, "0101b" means Short
Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error,
other values are reserved.
Addr.
Sync.
Data
8
N
2
Data Phase for Memory Cycle. The data transfer least significant nibble first
and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first , then DQ[7:4] on
LAD[3:0] last.)
Publication Release Date: December 19, 2002
- 7 -
Revision A2
W39V040A
Table of Command Definition
COMMAND
NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE
DESCRIPTION
Read
Cycles
Addr. Data
AIN DOUT
5555 AA
5555 AA
5555 AA
5555 AA
Addr. Data
Addr. Data
Addr. Data
Addr. Data
Addr. Data
1
6
6
6
4
Chip Erase
2AAA 55
2AAA 55
2AAA 55
2AAA 55
5555 80
5555 80
5555 80
5555 A0
5555 AA
5555 AA
5555 AA
2AAA 55
2AAA 55
2AAA 55
5555 10
SA(3) 30
PA(4) 50
Sector Erase
Page Erase
Byte Program
AIN
DIN
Top Boot Block Lockout
– 64K/16KByte
6
5555 AA
2AAA 55
5555 80
5555 AA
2AAA 55
5555 40/70
Product ID Entry
Product ID Exit (1)
Product ID Exit (1)
3
3
1
5555 AA
5555 AA
XXXX F0
2AAA 55
2AAA 55
5555 90
5555 F0
Notes:
1. The cycle means the write command cycle not the LPC clock cycle.
2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address
A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]
3. Address Format: A14 − A0 (Hex); Data Format: DQ7 − DQ0 (Hex)
4. Either one of the two Product ID Exit commands can be used.
5. SA: Sector Address
SA = 7XXXXh for Unique Sector7 (Boot Sector)
SA = 6XXXXh for Unique Sector6
SA = 3XXXXh for Unique Sector3
SA = 2XXXXh for Unique Sector2
SA = 1XXXXh for Unique Sector1
SA = 0XXXXh for Unique Sector0
SA = 5XXXXh for Unique Sector5
SA = 4XXXXh for Unique Sector4
6. PA: Page Address
PA = 7FXXXh for Page 15 in Sector 7
PA = 7EXXXh for Page 14 in Sector 7
PA = 7DXXXh for Page 13 in Sector 7
PA = 7CXXXh for Page 12 in Sector 7
PA = 7BXXXh for Page 11 in Sector 7
PA = 7AXXXh for Page 10 in Sector 7
PA = 79XXXh for Page 9 in Sector 7
PA = 78XXXh for Page 8 in Sector 7
PA = 77XXXh for Page 7 in Sector 7
PA = 76XXXh for Page 6 in Sector 7
PA = 75XXXh for Page 5 in Sector 7
PA = 74XXXh for Page 4 in Sector 7
PA = 73XXXh for Page 3 in Sector 7
PA = 72XXXh for Page 2 in Sector 7
PA = 71XXXh for Page 1 in Sector 7
PA = 70XXXh for Page 0 in Sector 7
PA =
6FXXXh
to
60XXXh
for
PA =
5FXXXh
to
50XXXh
for
PA =
4FXXXh
to
40XXXh
for
PA =
3FXXXh
to
30XXXh
for
PA =
2FXXXh
to
20XXXh
for
PA =
1FXXXh
to
10XXXh
for
PA =
0FXXXh
to
00XXXh
for
Page 15
Page 15
Page 15
Page 15
Page 15
Page 15
Page 15
to
to
to
to
to
to
to
Page 0
In
Sector 6
Page 0
In
Sector 5
Page 0
In
Sector 4
Page 0
In
Sector 3
Page 0
In
Sector 2
Page 0
In
Sector 1
Page 0
In
Sector 0
(Reference (Reference (Reference (Reference (Reference (Reference (Reference
to the
first
to the
first
to the
first
to the
first
to the
firs
to the
first
to the
first
column)
column)
column)
column)
column)
column)
column)
- 8 -
W39V040A
Embedded Programming Algorithm
Start
Write Program Command Sequence
(see below)
Pause
BP
T
#Data Polling/ Toggle bit
No
Last Address
?
Increment Address
Yes
Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
Publication Release Date: December 19, 2002
Revision A2
- 9 -
W39V040A
Embedded Erase Algorithm
Start
Write Erase Command Sequence
(see below)
#Data Polling or Toggle Bit
Successfully Completed
EC SEC PEC
Pause T /T
/T
Erasure Completed
Chip Erase Command Sequence
Individual Page Erase
Command Sequence
(Address/Command):
Individual Sector Erase
Command Sequence
(Address/Command):
(Address/Command):
5555H/AAH
5555H/AAH
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/80H
2AAAH/55H
5555H/80H
5555H/AAH
2AAAH/55H
5555H/10H
5555H/AAH
2AAAH/55H
5555H/AAH
2AAAH/55H
PageAddress/50H
Sector Address/30H
- 10 -
W39V040A
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
Read Byte
(DQ0 - DQ7)
Address = VA
= Any of the page addresses within
the sector being erased during page
erase operation
= Any of the device addresses within
the chip being erased during chip
erase operation
No
DQ7 = Data
?
Yes
Pass
Embedded Toggle Bit Algorithm
Start
Read Byte
(DQ0 - DQ7)
Address = Don't Care
No
DQ6 = Toggle
?
Yes
Fail
Publication Release Date: December 19, 2002
Revision A2
- 11 -
W39V040A
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product
Product
Identification
Entry (1)
Product
Identification
and Boot Block
Lockout Detection
Mode (3)
Identification Exit (6)
Load data AA
to
Load data AA
to
address 5555
address 5555
(2)
Load data 55
to
Load data 55
to
Read address = 00000
data = DA
address 2AAA
address 2AAA
(2)
(4)
Load data 90
to
Load data F0
to
Read address = 00001
data = 3D
address 5555
address 5555
Read address = 00002
DQ0/DQ1 of data outputs
Pause 10 S
Pause 10 S
µ
µ
= 1/0
(5)
Normal Mode
Notes for software product identification/boot block lockout detection:
(1) Data Format: DQ7 − DQ0 (Hex); Address Format: A14 − A0 (Hex)
(2) A1 − A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH.
(3) The device does not remain in “identification and boot block lockout detection” mode if power down.
(4) The DQ[3:0] to indicate the sectors protect status as below:
DQ0
DQ1
DQ2
DQ3
64Kbytes Boot Block
Unlocked by Software
16Kbytes Boot Block
Unlocked by Software
64Kbytes Boot Block Unlocked
by #TBL hardware trapping
Whole Chip Unlocked by #WP hardware
trapping Except Boot Block
0
1
64Kbytes Boot Block
Locked by Software
16Kbytes Boot Block
Locked by Software
64Kbytes Boot Block Locked by
#TBL hardware trapping
Whole Chip Locked by #WP hardware
trapping Except Boot Block
(5) The device returns to standard operation mode.
(6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the “product identification/boot block lockout
detection.”
- 12 -
W39V040A
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout
Feature Set Flow
Load data AA
to
address 5555
Load data 55
to
Pause T BP
Exit
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 40/70
to
40 to lock 64K Boot Block
70 to lcok 16K Boot Block
address 5555
Publication Release Date: December 19, 2002
Revision A2
- 13 -
W39V040A
7. DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
RATING
UNIT
Power Supply Voltage to VSS Potential
Operating Temperature
-0.5 to +4.6
0 to +70
V
°C
°C
V
Storage Temperature
D.C. Voltage on Any Pin to Ground Potential
Transient Voltage (<20 nS) on Any Pin to Ground Potential
-65 to +150
-0.5 to VDD +0.5
-1.0 to VDD +0.5
V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
Programmer Interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
LIMITS
MIN. TYP.
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MAX.
In Read or Write mode, all DQs open
Address inputs = 3.0V/0V, at f = 3 MHz
mA
Power Supply
Current
ICC
ILI
-
10
20
Input Leakage
Current
Output Leakage
Current
VIN = VSS to VDD
-
-
-
-
90
90
µA
µA
ILO VOUT = VSS to VDD
Input Low Voltage
Input High Voltage
Output Low Voltage
VIL
VIH
-
-
-0.3
2.0
-
-
-
-
-
0.8
VDD +0.5
0.45
V
V
V
V
VOL IOL = 2.1 mA
Output High Voltage VOH IOH = -0.1mA
2.4
-
- 14 -
W39V040A
LPC Interface Mode DC Operating Characteristics
(VDD = 3.3V ± 0.3V, VSS= 0V, TA = 0 to 70° C)
LIMITS
MIN. TYP.
PARAMETER
SYM.
ICC
TEST CONDITIONS
UNIT
MAX.
All Iout = 0A, CLK = 33 MHz,
in LPC mode operation.
mA
Power Supply Current
-
-
-
12.5
5
20
#LFRAM = 0.9 VDD, CLK = 33 MHz,
all inputs = 0.9 VDD / 0.1 VDD
#LFRAM = 0.1 VDD, CLK = 33 MHz,
all inputs = 0.9 VDD / 0.1 VDD
-
µA
CMOS Standby
Current
Isb1
Isb2
25
10
mA
TTL Standby Current
Input Low Voltage
Input Low Voltage of
#INIT Pin
3
VIL
-0.5
-0.5
-
-
0.3 VDD
0.2 VDD
V
V
VILI
-
-
-
0.5
VDD
+0.5
VDD
+0.5
Input High Voltage
VIH
-
-
-
-
V
V
V
V
VDD
Input High Voltage of
#INIT Pin
VIHI
1.35V
-
0.1
Output Low Voltage
Output High Voltage
VOL1 IOL = 1.5 mA
VOH1 IOH = -0.5 mA
VDD
0.9
VDD
VDD
Power-up Timing
PARAMETER
Power-up to Read Operation
Power-up to Write Operation
SYMBOL
TPU. READ
TPU. WRITE
TYPICAL
UNIT
µS
mS
100
5
Capacitance
(VDD = 3.3V, TA = 25° C, f = 1 MHz)
PARAMETER
I/O Pin Capacitance
Input Capacitance
SYMBOL
CI/O
CONDITIONS
VI/O = 0V
VIN = 0V
MAX.
12
6
UNIT
pF
pF
CIN
Publication Release Date: December 19, 2002
Revision A2
- 15 -
W39V040A
8. PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise/Fall Time
Input/Output Timing Level
Output Load
CONDITIONS
0V to 0.9 VDD
< 5 nS
1.5V/1.5V
1 TTL Gate and CL = 30 pF
AC Test Load and Waveform
+3.3V
1.8K
Ω
D
OUT
Input
Output
30 pF
(Including Jig and
Scope)
0.9VDD
1.5V
0V
1.3K
Ω
1.5V
Test Point
Test Point
- 16 -
W39V040A
AC Characteristics
Read Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
W39V040A
MAX.
PARAMETER
SYMBOL
UNIT
MIN.
Read Cycle Time
TRC
TAS
300
50
50
-
-
0
-
-
-
nS
nS
nS
nS
nS
nS
nS
nS
Row/Column Address Set Up Time
Row/Column Address Hold Time
Address Access Time
Output Enable Access Time
#OE Low to Act Output
TAH
TAA
TOE
TOLZ
TOHZ
TOH
175
75
-
35
-
#OE High to High-Z Output
Output Hold from Address Change
-
0
Write Cycle Timing Parameters
PARAMETER
Reset Time
SYMBOL
TRST
TAS
MIN.
TYP.
-
-
-
-
-
-
-
-
MAX.
-
UNIT
µS
nS
nS
nS
nS
nS
nS
nS
1
50
50
50
100
100
50
50
0
Address Setup Time
Address Hold Time
R/#C to Write Enable High Time
#WE Pulse Width
#WE High Width
Data Setup Time
-
-
-
-
-
-
-
-
TAH
TCWH
TWP
TWPH
TDS
Data Hold Time
#OE Hold Time
TDH
TOEH
TBP
-
nS
Byte Programming Time
Sector/Page Erase Cycle Time
Chip Erase Cycle Time
-
35
20
75
50
25
100
µS
mS
mS
TPEC
TEC
-
-
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
W39V040A
PARAMETER
SYMBOL
UNIT
MIN.
-
-
MAX.
40
#OE to Data Polling Output Delay
#OE to Toggle Bit Output Delay
TOEP
TOET
nS
nS
40
Publication Release Date: December 19, 2002
Revision A2
- 17 -
W39V040A
9. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET
TRST
TRC
Row Address
Column Address
Column Address
TAH
Row Address
A[10:0]
R/#C
TAH
TAS
TAS
V
IH
#WE
#OE
TAA
TOH
TOE
TOHZ
TOLZ
High-Z
High-Z
DQ[7:0]
Data Valid
Write Cycle Timing Diagram
T
RST
#RESET
A[10:0]
Column Address
Row Address
T
AS
T
AS
T
AH
T
AH
R/#C
#OE
T
CWH
T
OEH
T
WP
T
WPH
#WE
T
DH
T
DS
DQ[7:0]
Data Valid
- 18 -
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle
A[10:0]
Programmed Address
2AAA
55
5555
(Internal A[18:0])
DQ[7:0]
5555
A0
Data-In
AA
R/#C
#OE
TWPH
BP
T
WP
T
#WE
Internal Write Start
Byte 1
Byte 0
Byte 2
Byte 3
Note: The internal address A[18:0] are converted from external Column/Row address
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
#DATA Polling Timing Diagram
A[10:0]
(Internal A[18:0])
An
An
An
An
R/#C
#WE
#OE
DQ7
TOEP
X
X
X
X
T
BP or TEC
Publication Release Date: December 19, 2002
Revision A2
- 19 -
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0]
R/#C
#WE
#OE
TOET
DQ6
TBP or
TEC
Boot Block Lockout Enable Timing Diagram
SIX-byte code for Boot Block Lockout command
A[10:0]
2AAA
55
5555
AA
5555
AA
5555
80
2AAA
55
5555
(Internal A[18:0])
DQ[7:0]
40/70
R/#C
#OE
WP
T
WC
T
#WE
WPH
T
SB0
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
When 40(hex) is loaded, the 64KByte are locked; while 70(hex) is loaded, the 16KByte is locked.
- 20 -
W39V040A
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Diagram
Six-byte code for 3.3V-only software chip erase
A[10:0]
2AAA
5555
5555
5555
2AAA
5555
(Internal A[18:0])
AA
55
80
55
AA
10
DQ[7:0]
R/#C
#OE
TWP
SB0
TEC
#WE
TWPH
Internal Erasure Starts
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
Sector/Page Erase Timing Diagram
Six-byte code for 3.3V-only
Sector/Page Erase
A[10:0]
5555
AA
2AAA
55
(Internal A[18:0])
DQ[7:0]
5555
80
5555
AA
2AAA
55
SA/PA
30/50
R/#C
#OE
TWP
SB0
TEC
#WE
TWPH
Internal Erase starts
SB2
SB3
SB5
SB4
SB1
Note: The internal address A[18:0] are converted from external Column/Row address.
Column/Row Address are mapped to the Low/High order internal address.
i.e. Column Address A[10:0] are mapped to the internal A[10:0],
Row Address A[7:0] are mapped to the internal A[18:11].
SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"
Publication Release Date: December 19, 2002
Revision A2
- 21 -
W39V040A
10. LPC INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input Pulse Levels
Input Rise/Fall Slew Rate
Input/Output Timing Level
Output Load
CONDITIONS
0.6 VDD to 0.2 VDD
1 V/nS
0.4 VDD / 0.4 VDD
1 TTL Gate and CL = 10 pF
Read/Write Cycle Timing Parameters
(VDD = 3.3V ±0.3V, VSS = 0V, TA = 0 to 70° C)
W39V040A
MAX.
PARAMETER
Clock Cycle Time
Input Set Up Time
Input Hold Time
SYMBOL
UNIT
MIN.
30
7
0
2
TCYC
TSU
THD
TKQ
-
-
-
nS
nS
nS
nS
Clock to Data Valid
11
Note: Minimum and Maximum time has different loads. Please refer to PCI specification.
Reset Timing Parameters
PARAMETER
VDD Stable to Reset Active
Clock Stable to Reset Active
Reset Pulse Width
Reset Active to Output Float
Reset Inactive to Input Active
SYMBOL
TPRST
TKRST
TRSTP
TRSTF
TRST
MIN.
1
TYP.
MAX.
UNIT
mS
µS
nS
nS
-
-
-
-
-
-
-
100
100
-
-
50
-
1
µS
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is input high and (b) low level signal's reference level is input low.
Ref. to the AC testing condition.
- 22 -
W39V040A
11. TIMING WAVEFORMS FOR LPC INTERFACE MODE
Read Cycle Timing Diagram
T
CYC
CLK
#RESET
#LFRAM
LAD[3:0]
T
T
T
KQ
SU HD
Memory
Read
Address
A[31:28] A[27:24] A[23:20] A[19:16]
TAR
1111b Tri-State 0000b
2 Clocks
Next Start
0000b
Start
Data
D[3:0]
Sync
Cycle
0000b
TAR
010Xb
A[15:12] A[11:8] A[7:4]
Load Address in 8 Clocks
A[3:0]
D[7:4]
1 Clock Data out 2 Clocks
1 Clock 1 Clock
1 Clock
Write Cycle Timing Diagram
T
CYC
CLK
#RESET
T
T
#LFRAM
SU HD
Memory
Write
TAR
Sync
0000b
Address
Next Start
0000b
Start
Data
D[7:4]
Cycle
0000b
011Xb A[31:28] A[27:24] A[23:20] A[19:16]
A[7:4]
1111b
TAR
A[15:12] A[11:8]
Load Address in 8 Clocks
A[3:0]
Tri-State
LAD[3:0]
D[3:0]
Load Data in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Publication Release Date: December 19, 2002
Revision A2
- 23 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Program Cycle Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
TAR
Sync
Address
XXXXb
Load Address "5555" in 8 Clocks
Cycle
command
1st Start
0000b
TAR
XXXXb
1111b
0000b
Tri-State
LAD[3:0]
011Xb
XXXXb
0101b
0101b
0101b
1010b
1010b
XXXXb
X101b
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Address
XXXXb
Sync
0000b
Cycle
2nd Start
0000b
TAR
XXXXb
1111b
2 Clocks
011Xb
XXXXb
1010b
1010b
1010b
0101b
0101b
Tri-State
XXXXb
X010b
Load Data "55"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Sync
0000b
Address
Cycle
3rd Start
0000b
TAR
XXXXb
0000b
1010b
1111b
Tri-State
011Xb
XXXXb
0101b
0101b
0101b
XXXXb
XXXXb
X101b
Load Data "A0"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
program start
Memory
Write
Address
A[19:16]
Data
TAR
Sync
0000b
4th Start Cycle
0000b
011Xb
A[31:28]
A[27:24]
A[23:20]
TAR
Internal
D[3:0]
D[7:4]
1111b
2 Clocks
A[15:12]
A[11:8]
A[7:4]
A[3:0]
Tri-State
program start
Load Din in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Ain in 8 Clocks
Write the 4th command(target location to be programmed) to the device in LPC mode.
- 24 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
TAR
Sync
Address
Cycle
command
1st Start
0000b
0000b
Dn[3:0] Dn[7:4]
TAR
TAR
TAR
An[15:12]
An[7:4]
An[3:0]
1111b
2 Clocks
0000b
LAD[3:0]
011Xb
A[31:28]
XXXXb
An[31:28]
A[27:24]
XXXXb
An[27:24]
A[23:20]
A[19:16]
An[11:8]
Tri-State
Load Data "Dn"
in 2 Clocks
1 Clock
1 Clock
1 Clock 1 Clock
Load Address "An" in 8 Clocks
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Address
TAR
Tri-State
Next Start
0000b
Start
Data
Sync
Cycle
0000b
010Xb
XXAn[17:16]
An[3:0]
An[15:12]
An[11:8]
An[7:4]
XXXXb
1111b
0000b
XXXXb Dn7,xxx
2 Clocks
Read the DQ7 to see if the internal write complete or not.
1 Clock
Data out 2 Clocks
1 Clock 1 Clock
Load Address in 8 Clocks
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Start
Address
An[19:16]
TAR
1111b
Tri-State 0000b
Next Start
0000b
Sync
Data
Cycle
0000b
010Xb
XXXXb
1 Clock
Data out 2 Clocks
Dn7,xxx
An[23:20]
An[15:12]
An[11:8]
An[7:4]
An[3:0]
1 Clock
1 Clock
2 Clocks
When internal write complete, the DQ7 will equal to Dn7.
Load Address in 8 Clocks
1 Clock
Publication Release Date: December 19, 2002
Revision A2
- 25 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
Dn[3:0] Dn[7:4]
TAR
Sync
Address
Cycle
command
1st Start
0000b
XXAn[17:16]
An[7:4]
An[3:0]
An[15:12]
TAR
TAR
TAR
LAD[3:0]
011Xb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
An[11:8]
1111b
Tri-State
0000b
XXXXb
Load Data "Dn"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "An" in 8 Clocks
1 Clock
Write the last command(program or erase) to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Address
XXXXb
TAR
Tri-State
Next Start
0000b
Start
Data
X,D6,XXb
XXXXb
Sync
Cycle
0000b
010Xb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
1111b
0000b
2 Clocks
Read the DQ6 to see if the internal write complete or not.
1 Clock Data out 2 Clocks
1 Clock 1 Clock
Load Address in 8 Clocks
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Read
Start
Address
XXXXb
TAR
Tri-State
Next Start
0000b
Sync
Data
X,D6,XXb
XXXXb
Cycle
0000b
010Xb
XXXXb
XXXXb
XXXXb
XXXXb
XXXXb
1111b
0000b
1 Clock
1 Clock
2 Clocks
1 Clock Data out 2 Clocks
Load Address in 8 Clocks
1 Clock
When internal write complete, the DQ6 will stop toggle.
- 26 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
Data
1010b 1010b
TAR
Sync
Cycle
Address
XXXXb
command
1st Start
1111b
2 Clocks
0000b
TAR
TAR
TAR
0000b
LAD[3:0
XXXXb
XXXXb
XXXXb
Tri-State
011Xb
XXXXb
XXXXb
XXXXb
0101b
0101b
0101b
XXXXb
X101b
Load Data "AA"
in 2 Clocks
Write the 1st command to the device in LPC mode.
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0
Memory
Write
Start next
command
Address
XXXXb
Data
0101b 0101b
TAR
Sync
0000b
Cycle
2nd Start
0000b
1111b
2 Clocks
Tri-State
011Xb
1010b
1010b
1010b
XXXXb
X010b
Load Data "55"
in 2 Clocks
Write the 2nd command to the device in LPC mode.
1 Clocks
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
CLK
#RESET
#LFRAM
LAD[3:0
Memory
Write
Start next
command
Data
TAR
Cycle
Sync
0000b
Address
3rd Start
0000b
011Xb
1111b
0000b
1000b
Tri-State
0101b
Load Address "5555" in 8 Clocks
0101b
0101b
XXXXb
XXXXb
X101b
Load Data "80"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0
Memory
Write
Start next
command
Data
1010b 1010b
TAR
Address
XXXXb
Sync
0000b
Cycle
4th Start
0000b
TAR
XXXXb
1111b
2 Clocks
Tri-State
011Xb
XXXXb
0101b
0101b
0101b
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0
Memory
Write
Start next
command
Data
TAR
Sync
Cycle
Address
5th Start
TAR
0000b
011Xb
1111b
0000b
XXXXb
Tri-State
XXXX
1010b
Load Address "2AAA" in 8 Clocks
1010b
1010b
0101b
0101b
XXXXb
XXXXb
X010b
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
Memory
Write
Data
Start next
command
Address
TAR
Cycle
Sync
0000b
6th Start
0000b
0100b
0111b
0000b
TAR
XXXXb
1111b
Tri-State
011Xb
XXXXb
X101
b
0101
b
0101b
0101b
XXXXb XXXXb
LAD[3:0
Load Data "40"
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" 8 Clocks
1 Clock
or "70" in 2 Clocks
Write the 6th command to the device in LPC mode.
Publication Release Date: December 19, 2002
Revision A2
- 27 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
command
Data
1010b 1010b
TAR
Tri-State
2 Clocks
Sync
Cycle
Address
XXXXb
1st Start
0000b
1111b
0000b
TAR
LAD[3:0]
XXXXb
011Xb
XXXXb
0101b
0101b
0101b
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
0101b
TAR
Cycle
Sync
0000b
2nd Start
0000b
011Xb
TAR
XXXXb
1111b
2 Clocks
XXXXb
1010b
1010b
1010b
0101b
Tri-State
XXXXb
X010b
Load Data "55"
in 2 Clocks
1 Clock
1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
Sync
0000b
Cycle
Address
3rd Start
0000b
TAR
1000b
1111b
XXXXb
0000b
Tri-State
011Xb
XXXXb
0101b
Load Address "5555" in 8 Clocks
0101b
0101b
XXXXb
XXXXb
X101b
Load Data "80"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
1010b
TAR
Cycle
Sync
0000b
4th Start
0000b
011Xb
TAR
XXXXb
1111b
2 Clocks
XXXXb
0101b
0101b
0101b
1010b
Tri-State
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
0101b 0101b
TAR
Sync
Cycle
Address
XXXXb
5th Start
0000b
011Xb
1111b
0000b
TAR
XXXXb
Tri-State
XXXXb
1010b
1010b
1010b
XXXXb
X010b
Load Data "55"
in 2 Clocks
1 Clock
Load Address "2AAA" in 8 Clocks
2 Clocks
1 Clock
1 Clock
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
erase start
Memory
Write
Address
Data
TAR
Sync
6th Start Cycle
Internal
0000b
011Xb
0001b
1111b
2 Clocks
0000b
TAR
XXXXb
Tri-State
X101b
0000b
XXXXb
0101b
0101b
0101b
XXXXb XXXXb
erase start
Load Data "10"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
Write the 6th command to the device in LPC mode.
- 28 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
command
Data
1010b 1010b
TAR
Tri-State
2 Clocks
Sync
Cycle
Address
XXXXb
1st Start
0000b
1111b
0000b
TAR
LAD[3:0]
XXXXb
011Xb
XXXXb
0101b
0101b
0101b
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
0101b
TAR
Sync
Cycle
2nd Start
0000b
TAR
XXXXb
1111b
0000b
011Xb
XXXXb
1010b
1010b
1010b
0101b
Tri-State
XXXXb
X010b
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
1111b
2 Clocks
Sync
Cycle
Address
3rd Start
0000b
011Xb
0000b
TAR
XXXXb
Tri-State
XXXXb
0101b
0101b
0101b 0000b
1000b
XXXXb
XXXXb
X101b
Load Data "80"
in 2 Clocks
1 Clocks
1 Clocks1 Clocks
Load Address "5555" in 8 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
1010b 1010b
TAR
Sync
4th Start Cycle
0000b
011Xb
TAR
XXXXb
1111b
2 Clocks
0000b
Tri-State
XXXXb
0101b
0101b
0101b
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock
1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
1111b
2 Clocks
Sync
Address
5th Start Cycle
0000b
TAR
0000b
XXXXb
Tri-State
XXXXb XXXXb
011Xb
XXXXb
X010b
1010b
1010b
0101b
0101b
1010b
Load Data "55"
in 2 Clocks
Write the 5th command to the device in LPC mode.
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
CLK
#RESET
Internal
#LFRAM
LAD[3:0]
erase start
Memory
Write
Address
SA[18:16]
Data
0011b
TAR
Sync
Cycle
6th Start
0000b
Internal
TAR
XXXXb
0000b
1111b
Tri-State
0000b
XXXXb
XXXXb XXXXb
011Xb
XXXXb
XXXXb
XXXXb
erase start
Load Data "30"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Sector Address in 8 Clocks
Write the 6th command(target sector to be erased) to the device in LPC mode.
Publication Release Date: December 19, 2002
Revision A2
- 29 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
Page Erase Timing Diagram
CLK
#RESET
#LFRAM
Memory
Write
Start next
command
Data
1010b 1010b
TAR
Tri-State
2 Clocks
Sync
Cycle
Address
1st Start
0000b
1111b
0000b
TAR
XXXXb
LAD[3:0]
011Xb
XXXXb
0101b
Load Address "5555" in 8 Clocks
0101b
0101b
XXXXb
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
1 Clock 1 Clock
1 Clock
Write the 1st command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
0101b 0101b
TAR
Sync
0000b
Cycle
2nd Start
0000b
TAR
XXXXb
1111b
Tri-State
011Xb
XXXXb
1010b
1010b
1010b
XXXXb
X010b
Load Data "55"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 2nd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
1111b
2 Clocks
Sync
Cycle
Address
3rd Start
TAR
0000b
011Xb
0000b
XXXXb
Tri-State
XXXXb
0101b
Load Address "5555" in 8 Clocks
0101b
0101b 0000b
1000b
XXXXb
XXXXb
X101b
Load Data "80"
in 2 Clocks
1 Clocks
1 Clocks1 Clocks
1 Clocks
Write the 3rd command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Address
XXXXb
Data
1010b
TAR
Sync
0000b
4th Start Cycle
TAR
0000b
011Xb
XXXXb
1111b
XXXXb
0101b
0101b
0101b
1010b
Tri-State
XXXXb
X101b
Load Data "AA"
in 2 Clocks
1 Clock
2 Clocks
1 Clock
1 Clock
Load Address "5555" in 8 Clocks
1 Clock
Write the 4th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Memory
Write
Start next
command
Data
TAR
1111b
2 Clocks
Sync
Address
5th Start Cycle
0000b
TAR
0000b
XXXXb
XXXXb
Tri-State
XXXXb
011Xb
XXXXb
X010b
1010b
1010b
0101b
0101b
1010b
Load Data "55"
in 2 Clocks
1 Clock
1 Clock 1 Clock
Load Address "2AAA" in 8 Clocks
1 Clock
Write the 5th command to the device in LPC mode.
CLK
#RESET
#LFRAM
LAD[3:0]
Internal
erase start
Memory
Write
Address
Data
TAR
Sync
Cycle
6th Start
0000b
Internal
PA[18:16] PA[15:12]
0101b
TAR
XXXXb
0000b
1111b
Tri-State
0000b
XXXXb
XXXXb XXXXb
011Xb
XXXXb
XXXXb
erase start
Load Data "50"
in 2 Clocks
2 Clocks
1 Clock
1 Clock 1 Clock
Load Page Address in 8 Clocks
Write the 6th command(target page to be erased) to the device in LPC mode.
- 30 -
W39V040A
Timing Waveforms for LPC Interface Mode, continued
GPI Register Readout Timing Diagram
CLK
#RESET
#LFRAM
Memory
Read
Address
XXXXb
TAR
Tri-State
Next Start
0000b
Start
Data
Sync
Cycle
0000b
0001b
D[3:0]
D[7:4]
TAR
1111b
1110b
0000b
0000b
LAD[3:0]
010Xb
1111b
1011b
1111b
0000b
Load Address "FFBXE100(hex)" in 8 Clocks
2 Clocks
1 Clock Data out 2 Clocks
1 Clock 1 Clock
1 Clock
Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved bits.
Reset Timing Diagram
VDD
CLK
TPRST
TKRST
TRSTP
#RESET
TRST
TRST
LAD[3:0]
#LFRAM
Publication Release Date: December 19, 2002
Revision A2
- 31 -
W39V040A
12. ORDERING INFORMATION
ACCESS
POWER SUPPLY
CURRENT MAX.
STANDBY VDD
TIME
(nS)
11
CURRENT MAX.
PART NO.
PACKAGE
(mA)
20
(mA)
10
W39V040AP
W39V040AQ
32L PLCC
11
20
10
32L STSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
13. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin STSOP W39V040AQ
W39V040AQ
2138977A-A12
149OBSA
1st line: Winbond logo
2nd line: the part number: W39V040AQ
3rd line: the lot number
4th line: the tracking code: 149 O B SA
149: Packages made in '01, week 49
O: Assembly house ID: A means ASE, O means OSE, ... etc.
B: IC revision; A means version A, B means version B, ... etc.
SA: Process code
- 32 -
W39V040A
14. PACKAGE DIMENSIONS
32L PLCC
Dimension in Inches
Min. Nom. Max. Min. Nom. Max.
Dimension in mm
Symbol
H E
E
0.140
3.56
A
0.020
0.105
0.026
0.016
0.008
0.50
2.67
0.66
0.41
0.20
A
A
b
1
2
1
4
1
32
30
0.110
0.028
0.018
0.010
0.550
0.450
0.050
0.510
0.410
0.590
0.490
0.090
0.115
0.032
0.022
0.014
2.80
0.71
2.93
0.81
0.56
0.35
0.46
b
5
29
0.25
c
0.547
0.447
0.044
0.490
0.390
0.585
0.485
0.075
0.553
0.453
0.056
0.530
0.430
0.595
0.495
0.095
0.004
13.89
11.35
1.12
14.05
11.51
1.42
13.97
11.43
1.27
D
E
e
12.45
9.91
12.95
13.46
10.92
15.11
12.57
2.41
G
G
H
H
D
GD
10.41
14.99
12.45
2.29
E
D
E
D
HD
14.86
12.32
1.91
L
0.10
y
0
10
0
10
θ
21
13
Notes:
1. Dimensions D & E do not include interlead flash.
2. Dimension b1 does not include dambar protrusion/intrusio
3. Controlling dimension: Inches
14
20
c
4. General appearance spec. should be based on final
visual inspection sepc.
L
A2
A
θ
e
1
b
b1
A
Seating Plane
y
E
G
32L STSOP
HD
D
c
Dimension in Inches Dimension in mm
Symbol
Max.
1.20
Min. Nom. Max. Min. Nom.
e
0.047
A
0.002
0.035
0.006
0.041
0.05
0.95
0.17
0.10
0.15
1
A
E
0.040
1.00
0.22
2
A
1.05
0.27
b
0.007 0.009 0.010
b
c
0.004
0.008
-----
12.40
8.00
0.21
-----
0.488
D
E
0.315
0.551
0.020
14.00
D
H
0.50
0.60
0.80
e
0.50
0.70
0.020 0.024 0.028
0.031
L
θ
1
L
A
A
1 A
2
0.000
0.004
0.00
0
0.10
5
L
Y
Y
0
3
5
3
θ
L
1
Publication Release Date: December 19, 2002
Revision A2
- 33 -
W39V040A
15. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
October 8, 2002
Dec. 19, 2002
-
14
Initial Issued
Modify PGM mode power supply current (Icc)
parameter from 20 mA (typ.) to 10 mA (typ.)
and 30 mA (max.) to 20 mA (max.)
1, 15, 32
15
Modify LPC mode power supply current (Icc)
parameter from 40 mA (typ.) to 12.5 mA (typ.)
and 60 mA (max.) to 20 mA (max.)
Modify CMOS standby current (Isb1) parameter
from 20 µA (typ.) to 5 µA (typ.) and 100 µA (max.)
to 25 µA (max.)
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 34 -
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