W49F020_技术文档

Preliminary W49F020

256K 8 CMOS FLASH MEMORY

´

GENERAL DESCRIPTION

The W49F020 is a 2-megabit, 5-volt only CMOS flash memory organized as 256K ´ 8 bits. The device

can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not

required. The unique cell architecture of the W49F020 results in fast program/erase operations with

extremely low current consumption (compared to other comparable 5-volt flash memory products). The

device can also be programmed and erased using standard EPROM programmers.

FEATURES

· Single 5-volt operations:

· Low power consumption

- Active current: 25 mA (typ.)

- Standby current: 20 mA (typ.)

- 5-volt Read

- 5-volt Erase

- 5-volt Program

·

Automatic program and erase timing with

internal VPP generation

· Fast Program operation:

- Byte-by-Byte programming: 50 mS (max.)

· Fast Erase operation: 100 mS (typ.)

· Fast Read access time: 70/90 nS

· Endurance: 1K/10K cycles (typ.)

· Twenty-year data retention

· End of program or erase detection

- Toggle bit

- Data polling

· Latched address and data

· TTL compatible I/O

·

Hardware data protection

· JEDEC standard byte-wide pinouts

· One 8K byte Boot Block with Lockout

protection

· Available packages: 32-pin DIP and 32-pin

TSOP and 32-pin-PLCC

Publication Release Date: October 1999

- 1 -

Revision A1

Preliminary W49F020

PIN CONFIGURATIONS

BLOCK DIAGRAM

32

1

2

NC

V_DD

WE

31

30

29

28

27

A16

3

4

A15

A12

A7

A17

A14

W49F020

5

A13

A8

A6

6

V

DD

SS

7

A5

A4

26

25

24

23

22

21

20

A9

32-pin

DIP

8

A11

CE

9

DQ0

A3

A2

A1

A0

OE

.

OUTPUT

BUFFER

OE

10

A10

.

CONTROL

DECODER

DQ7

11

12

13

WE

CE

DQ7

DQ6

DQ0

DQ1

DQ2

GND

14

15

16

19

18

17

DQ5

DQ4

DQ3

3FFFF

A0

.

MAIM MEMORY

248K BYTES

02000

01FFF

.

A

1

2

A

1

5

A

1

6

V

/

A

1

7

N

C

D W

BOOT BLOCK

8K BYTES

A17

D

E

00000

3

4

2

1

32 31 30

29

28

27

26

25

24

23

22

21

A14

A13

A8

5

6

A7

A6

A5

A4

A3

A2

A1

A0

7

32-pin

PLCC

8

A9

9

A11

10

11

12

13

OE

A10

CE

DQ7

DQ0

PIN DESCRIPTION

14 15 16 17 18 19 20

D

Q

1

D

Q

2

G

N

D

Q

4

D

Q

3

D

Q

5

D

Q

6

SYMBOL

PIN NAME

Address Inputs

A0- A17

1

2

3

32

OE

A10

A11

A9

A8

A13

A14

A17

Data Inputs/Outputs

Chip Enable

DQ0- DQ7

31

30

29

28

27

26

25

CE

DQ7

4

5

CE

OE

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A0

6

7

8

Output Enable

WE

V_DD

NC

32-pin

TSOP

9

10

24

23

22

21

20

19

18

17

Write Enable

Power Supply

Ground

A16

WE

VDD

GND

NC

11

12

A15

A12

A7

A6

A5

13

14

15

16

A1

A2

A3

A4

No Connection

- 2 -

Preliminary W49F020

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W49F020 is controlled by CE and OE, both of which have to be low for the

host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is

de-selected and only standby power will be consumed. OE is the output control and is used to gate data

from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the

timing waveforms for further details.

Boot Block Operation

There is an 8K-byte boot block in this device, which can be used to store boot code. The boot block

locates in the first 8K bytes of the memory with the address range from 0000(hex) to 1FFF(hex). For the

specific code, please see Command Codes for Boot Block Lockout Enable.

When the boot block is enabled, data for the designated block cannot be erased or programmed

(programming lockout); other memory locations can be changed by the regular programming method.

When the boot block programming lockout feature is activated, the chip erase function cannot erase the

boot block any longer.

In order to detect whether the boot block feature is set on the 8K-bytes block or not, users can perform

software command sequence to check it. First, enter the product identification mode (see Command

Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address

"0002 hex". If the output data is "1," the boot block programming lockout feature is activated; if the

output data is "0," the lockout feature is inactivated and the block can be erased/programmed.

To return to normal operation, perform a three-byte command sequence (or an alternate single-word

command) to exit the identification mode. For the specific code, see Command Codes for

Identification/Boot Block Lockout Detection.

Chip Erase Operation

The chip-erase mode can be initiated by a six-word command sequence. After the command loading

cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed

in a fast 100 mS (typical). The host system is not required to provide any control or timing during this

operation. If the boot block programming lockout is activated, only the data in the main memory blocks

will be erased to FF(hex), and the data in the boot block will not be erased (remains same as before the

chip erase operation). The entire memory array will be erased to FF hex by the chip erase operation if

the boot block programming lockout feature is not activated. Once the boot block lockout feature is

activated, the chip erase function erase the main memory block but not the boot block. The device will

automatically return to normal read mode after the erase operation completed. Data polling and/or

Toggle Bits can be used to detect end of erase cycle.

Program Operation

The W49F020 is programmed on a byte-by-byte basis. Program operation can only change logical data

"1" to logical data "0." The erase operation (changed entire data in main memory blocks and/or boot

block from "0" to "1") is needed before programming.

The program operation is initiated by a 4-word command cycle (see Command Codes for Byte

Programming). The device will internally enter the program operation immediately after the

byte-program command is entered. The internal program timer will automatically time-out (50 mS max. -

Publication Release Date: October 1999

- 3 -

Revision A1

Preliminary W49F020

TBP) when completing programming and return to normal read mode. Data polling and/or Toggle Bits

can be used to detect end of program cycle.

Hardware Data Protection

The integrity of the data stored in the W49F020 is also hardware protected in the following ways:

(1) Noise/Glitch Protection: A WE pulse with less than 15 nS in duration will not initiate a write cycle.

(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than

2.5V typical.

(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This

prevents inadvertent writes during power-up or power-down periods.

(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out

5 mS before any write (erase/program) operation.

Data Polling (DQ7)- Write Status Detection

The W49F020 features a data polling function which used to indicate the end of a program or erase

cycle. When the W49F020 is in the internal program or erase cycle, any attemption to read DQ7 of the

last word loaded will receive the complement of the true data. Once the program or erase cycle is

completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and

become logical "1" or true data when the erase cycle has been completed.

Toggle Bit (DQ6)- Write Status Detection

In addition to data polling, the W49F020 provides another method for determining the end of a program

cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce

alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's

will stop. The device is then ready for the next operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment

automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In software

access mode, a three-word (or JEDEC 3-word) command sequence can be used to access the product

ID. A read from address 0000H outputs the manufacturer code DA(hex); and a read from address

0001H outputs the device code 8C(hex) for W49F020. The product ID operation can be terminated by a

three-word command sequence or an alternated one-word command sequence (see Command

Definition table).

In the hardware access mode, access to the product ID will be activated by forcing CE and OE low,

WE high, and raising A9 to 12 volts.

- 4 -

Preliminary W49F020

TABLE OF OPERATING MODES

Operating Mode Selection

(V_HH= 12V ± 5%)

MODE

PINS

ADDRESS

DQ.

CE

VIL

OE

VIL

VIH

X

WE

VIH AIN

VIL AIN

Read

Dout

Write

Din

IH

Standby

Write Inhibit

V

X

High Z

X

VIL

X

High Z/DOUT

X

VIH

IH

Output Disable

Product ID

X

V

X

High Z

VIL

VIH

Manufacturer Code DA (Hex)

A0 = VIL; A1- A17 = VIL;

A9 = VHH

VIL

VIH

Device Code 8C (Hex)

A0 = VIL; A1- A17 = VIL;

A9 = VHH

TABLE OF COMMAND DEFINITION

NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

COMMAND

Cycles Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

DESCRIPTION

A_IND_OUT

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10

5555 AA 2AAA 55 5555 A0 A_IND_IN

Read

1

Chip Erase

6

4

Byte Program

5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40

5555 AA 2AAA 55 5555 90

Boot Block Lockout

Product ID Entry

Product ID Exit ⁽¹⁾

Notes:

6

3

1

5555 AA 2AAA 55 5555 F0

XXXX F0

1. Address Format: A14 A0 (Hex); Data Format: DQ7-DQ0 (Hex)

-

2. Either one of the two Product ID Exit commands can be used.

Publication Release Date: October 1999

Revision A1

- 5 -

Preliminary W49F020

Command Codes for Byte Program

WORD SEQUENCE

0 Write

ADDRESS

DATA

5555H

2AAAH

AAH

55H

1 Write

2 Write

5555H

A0H

3 Write

Programmed-Address

Programmed-Data

Byte Program Flow Chart

Byte Program

Command Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data A0

to

address 5555

Load data Din

to

programmed-

address

Pause 50

Exit

S

m

Notes for software program code:

Data Format: DQ7- DQ0 (Hex

Address Format: A14- A0 (Hex)

- 6 -

Preliminary W49F020

Command Codes for Chip Erase

BYTE SEQUENCE

1 Write

ADDRESS

5555H

DATA

AAH

55H

80H

AAH

55H

10H

2 Write

2AAAH

5555H

3 Write

4 Write

5555H

5 Write

2AAAH

5555H

6 Write

Chip Erase Acquisition Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 10

to

address 5555

Pause 1 Sec.

Exit

Notes for chip erase:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

Publication Release Date: October 1999

Revision A1

- 7 -

Preliminary W49F020

Command Codes for Product Identification and Boot Block Lockout Detection

BYTE

SEQUENCE

ALTERNATE PRODUCT (6)

IDENTIFICATION/BOOT BLOCK

LOCKOUT DETECTION ENTRY

SOFTWARE PRODUCT

IDENTIFICATION/BOOT BLOCK LOCKOUT

DETECTION EXIT (7)

ADDRESS

DATA

ADDRESS

DATA

1 Write

2 Write

3 Write

5555

2AAA

5555

AA

55

90

5555H

2AAAH

5555H

AAH

55H

F0H

Pause 10 mS

Software Product Identification and Boot Block Lockout Detection Acquisition Flow

Product

Identification

Entry (1)

Product

Identification Exit(7)

Identification

and Boot Block

Lockout Detection

Mode (3)

Load data AA

to

address 5555

Load data AA

to

address 5555

(2)

Load data 55

to

address 2AAA

Load data 55

to

address 2AAA

Read address = 00000

data = DA

(2)

(4)

Load data 90

Load data F0

to

Read address = 00001

data =8C

to

address 5555

Read address = 00002

data in DQ0 = "1"/"0"

m

Pause 10 S

m

S

Pause 10

(5)

Normal Mode

Notes for software product identification/boot block lockout detection:

(1) Data Format: DQ7- DQ0 (Hex); Address Format: A14- A0 (Hex)

(2) A1- A17 = V_IL; manufacture code is read for A0 = V_IL; device code is read for A0 = V_IH

.

(3) The device does not remain in identification and boot block lockout detection mode if power down.

(4) If the output data in DQ0= " 1," the boot block programming lockout feature is activated; if the output data in DQ0= " 0," the lockout feature is

inactivated and the block can be programmed.

(5) The device returns to standard operation mode.

(6) Optional 1-word cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection.

- 8 -

Preliminary W49F020

Command Codes for Boot Block Lockout Enable

BYTE SEQUENCE

BOOT BLOCK LOCKOUT FEATURE SET

ADDRESS

DATA

1 Write

2 Write

3 Write

4 Write

5 Write

6 Write

5555H

2AAAH

5555H

2AAAH

5555H

AAH

55H

80H

AAH

55H

40H

Pause 1 Sec.

Boot Block Lockout Enable Acquisition Flow

Boot Block Lockout

Feature Set Flow

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 80

to

address 5555

Load data AA

to

address 5555

Load data 55

to

address 2AAA

Load data 40

to

address 5555

Pause 1 Sec.

Exit

Notes for boot block lockout enable:

Data Format: DQ7- DQ0 (Hex)

Address Format: A14- A0 (Hex)

Publication Release Date: October 1999

Revision A1

- 9 -

Preliminary W49F020

DC CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

RATING

-0.5 to +7.0

0 to +70

UNIT

V

Power Supply Voltage to Vss Potential

Operating Temperature

°C

Storage Temperature

-65 to +150

C

°

DD

-0.5 to V +1.0

V

D.C. Voltage on Any Pin to Ground Potential except OE

Transient Voltage (<20 nS ) on Any Pin to Ground Potential

-1.0 to VDD +1.0

-0.5 to 12.5

V

Voltage on OE Pin to Ground Potential

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Operating Characteristics

(V_DD= 5.0V ±10%, V_SS= 0V, T_A= 0 to 70° C)

PARAMETER

SYM.

TEST CONDITIONS

LIMITS

MIN. TYP.

UNIT

MAX.

CC

I

Power Supply

Current

-

25

50

mA

CE OE

all DQs open

WE

= VIH,

=

= VIL,

Address inputs = VIL/VIH, at f = 5 MHz

CE

Standby VDD

ISB1

-

2

3

mA

IH

= V , all DQs open

Other inputs = VIL/VIH

CE

Current (TTL input)

Standby VDD Current ISB2

(CMOS input)

20

100

mA

DD

= V -0.3V, all DQs open

Other inputs = VDD -0.3V/GND

VIN = GND to VDD

Input Leakage

Current

ILI

-

10

mA

LO

I

OUT DD

V = GND to V

Output Leakage

Current

IL

Input Low Voltage

Input High Voltage

Output Low Voltage

V

-

-0.3

2.0

-

0.8

V

IH

DD

V

+0.5

0.45

VOL IOL = 2.1 mA

Output High Voltage VOH IOH = -0.4 mA

2.4

-

- 10 -

Preliminary W49F020

Power-up Timing

PARAMETER

SYMBOL

TYPICAL

UNIT

mS

PU

Power-up to Read Operation

Power-up to Write Operation

T

. READ

100

5

TPU. WRITE

mS

CAPACITANCE

(V_DD= 5.0V, T_A= 25° C, f = 1 MHz)

PARAMETER

I/O Pin Capacitance

Input Capacitance

SYMBOL

CI/O

CONDITIONS

VI/O = 0V

MAX.

12

UNIT

pf

CIN

VIN = 0V

6

pf

AC CHARACTERISTICS

AC Test Conditions

PARAMETER

Input Pulse Levels

CONDITIONS

0V to 3.0V

< 5 nS

Input Rise/Fall Time

Input/Output Timing Level

Output Load

1.5V/1.5V

1 TTL Gate and CL = 100 pF for 90nS

CL = 30 pF for 70nS

AC Test Load and Waveform

+5V

1.8K

W

D

OUT

30 pF for 70nS

100 pF for 90nS

(Including Jig and

1.3K

W

Scope)

Input

Output

3V

1.5V

0V

Test Point

Publication Release Date: October 1999

Revision A1

- 11 -

Preliminary W49F020

AC Characteristics, continued

Read Cycle Timing Parameters

(V_CC= 5.0V ±10%, V_CC= 0V, T_A= 0 to 70° C)

PARAMETER

SYM.

W49F020-70

W49F020-90

UNIT

MIN.

MAX.

MIN.

MAX.

Read Cycle Time

TRC

TCE

TAA

70

-

90

-

nS

Chip Enable Access Time

Address Access Time

70

35

-

90

40

-

OE

Output Enable Access Time

T

-

TCLZ

TOLZ

TCHZ

TOHZ

TOH

0

CE Low to Active Output

OE Low to Active Output

CE High to High-Z Output

0

-

0

-

nS

25

-

25

-

OE High to High-Z Output

Output Hold from Address Change

0

Write Cycle Timing Parameters

PARAMETER

Address Setup Time

SYMBOL

MIN.

0

TYP.

MAX.

UNIT

nS

AS

T

-

Address Hold Time

TAH

TCS

50

0

nS

WE and

Setup Time

Hold Time

CE

TCH

0

-

nS

TOES

TOEH

TCP

High Setup Time

High Hold Time

OE

0

100

CE Pulse Width

WE Pulse Width

TWP

TWPH

WE High Width

Data Setup Time

Data Hold Time

TDS

TDH

50

0

-

nS

mS

S

BP

Byte programming Time

Erase Cycle Time

T

10

0.1

50

1

TEC

-

Note: All AC timing signals observe the following guidelines for determining setup and hold times:

(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.

- 12 -

Preliminary W49F020

AC Characteristics, continued

Data Polling and Toggle Bit Timing Parameters

PARAMETER

SYM.

W49F020-70

W49F020-90

MIN. MAX.

40

UNIT

MIN.

MAX.

35

70

35

70

-

TOEP

TCEP

TOET

TCET

-

nS

OE

CE

OE

CE

to Data Polling Output Delay

to Toggle Bit Output Delay

-

90

40

90

-

TIMING WAVEFORMS

Read Cycle Timing Diagram

T_RC

Address A17-0

CE

T_CE

T_OE

OE

T_OHZ

T_OLZ

V

IH

WE

T_CLZ

T

OH

T_CHZ

Data Valid

High-Z

DQ7-0

Data Valid

AA

T

Publication Release Date: October 1999

Revision A1

- 13 -

Preliminary W49F020

Timing Waveforms, continued

WE Controlled Command Write Cycle Timing Diagram

T

AS

T

AH

Address A17-0

CE

T

CS

T

CH

T

OES

OEH

OE

T

WP

T

WPH

WE

T

DS

DQ7-0

Data Valid

T

DH

CE Controlled Command Write Cycle Timing Diagram

AS

T

AH

T

Address A17-0

CE

TCPH

TCP

T

OES

TOEH

OE

WE

TDS

High Z

DQ7-0

Data Valid

TDH

- 14 -

Preliminary W49F020

Timing Waveforms, continued

Program Cycle Timing Diagram

Byte Program Cycle

5555 Address

2AAA

Address A17-0

5555

55

A0

Data-In

AA

DQ7-0

CE

OE

T _WPH

TBP

WP

T

WE

Internal Write Start

Byte 1

Byte 0

Byte 2

Byte 3

DATA

Polling Timing Diagram

Address A17-0

WE

T_CEP

CE

OE

T_OEH

T_OES

T_OEP

DQ7

X

TBP or TEC

Publication Release Date: October 1999

Revision A1

- 15 -

Preliminary W49F020

Timing Waveforms, continued

Toggle Bit Timing Diagram

Address A17-0

WE

CE

OE

T_OES

T_OEH

DQ6

T_{BP or}T_EC

Boot Block Lockout Enable Timing Diagram

Six byte code for Boot Block

Lockout Feature Enable

Address A17-0

5555

2AAA

XX55

5555

2AAA

XX55

DQ7-0

CE

XX80

XXAA

XX40

OE

TWP

SB0

T_EC

WE

T_WPH

SB2

SB3

SB5

SB4

SB1

- 16 -

Preliminary W49F020

Timing Waveforms, continued

Chip Erase Timing Diagram

Six-byte code for 5V-only software

chip erase

Address A17-0

5555

2AAA

XX55

5555

2AAA

XX55

5555

DQ7-0

XX80

XXAA

XX10

CE

OE

T_WP

T_EC

WE

T_WPH

Internal Erase starts

SB0

SB2

SB3

SB5

SB4

SB1

Publication Release Date: October 1999

Revision A1

- 17 -

Preliminary W49F020

ORDERING INFORMATION

PART NO.

ACCESS

TIME

POWER

SUPPLY

CURRENT

MAX.

STANDBY

PACKAGE

CYCLE

DD

V

CURRENT

(nS)

MAX.

(mA)

50

( A)

m

W49F020-70

70

90

70

90

70

90

70

90

70

90

70

90

100 (CMOS) 32-pin DIP

1K

W49F020-90

W29F020Q-70

W29F020Q-90

W29F020P-70

W29F020P-90

W49F020-70B

W49F020-90B

W29F020Q-70B

W29F020Q-90B

W29F020P-70B

W29F020P-90B

100 (CMOS)

1K

32-pin TSOP (8 mm ´ 20 mm)

1K

100 (CMOS) 32-pin PLCC

100 (CMOS) 32-pin DIP

1K

10K

100 (CMOS)

32-pin TSOP (8 mm ´ 20 mm)

32-pin TSOP (8 mm 20 mm)

´

100 (CMOS) 32-pin PLCC

Notes:

1. Winbond reserves the right to make changes to its products without prior notice.

2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications

where personal injury might occur as a consequence of product failure.

3. There are two kinds of boot block in this device. The part number shown in the Ordering Information table is only for Bottom Boot

Block part, which is in the lower address range. For the requirement of the higher address range boot block, the Top Boot Block,

please contact Winbond FAE for details.

- 18 -

Preliminary W49F020

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

0.210

5.33

A

0.010

0.150

0.25

3.81

0.41

1.22

A₁

0.155 0.160

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

2

A

0.016 0.018

0.022

0.054

B

0.050

0.048

0.008

B

c

1

0.010 0.014 0.20

1.650 1.660

D

17

32

41.91 42.16

D

E

E₁

e₁

15.49

14.10

2.79

0.610

15.24

0.590 0.600

14.99

13.84 13.97

0.545

0.550

0.555

0.110

0.090 0.100

2.29

2.54

3.30

E1

0.120

0

0.140 3.05

15

0.130

3.56

15

L

a

0

0.630 0.650 0.670 16.00 16.51 17.02

0.085

e_A

S

2.16

16

1

Notes:

E

S

1.Dimensions D Max. & S include mold flash or

tie bar burrs.

c

2.Dimension E1 does not include interlead flash.

2

A

A1

Base Plane

3.Dimensions D & E1 include mold mismatch and

.

are determined at the mold parting line.

4.Dimension B1 does not include dambar

protrusion/intrusion.

L

Seating Plane

5.Controlling dimension: Inches

6.General appearance spec. should be based on

final visual inspection spec.

B

1

e

e_A

a

1

B

32-pin PLCC

Dimension in Inches

Dimension in mm

Symbol

Min. Nom. Max. Min. Nom. Max.

H _E

E

0.140

3.56

A

0.020

0.105

0.026

0.016

0.008

0.50

2.67

0.66

0.41

0.20

A ₁

A ₂

b ₁

b

c

D

4

1

32

30

0.110

0.028

0.018

0.010

0.550

0.450

0.050

0.51

0.115

0.032

0.022

0.014

2.80

0.71

0.46

0.25

13.97

11.43

1.27

12.9

2.93

0.81

0.56

0.35

5

29

0.547

0.447

0.044

0.490

0.390

0.585

0.485

0.075

0.553

0.453

0.056

0.530

0.430

0.595

0.495

0.095

0.004

13.89

11.35

1.12

14.05

11.51

1.42

E

e

12.45

9.91

13.46

10.92

15.11

12.57

2.41

G_D

G_E

H _D

H

L

y

G

D

0.410

0.590

0.49

10.41

14.99

12.45

2.29

D

HD

14.86

12.32

1.91

E

0.090

0.10

°

10

0

10

0

q

21

13

Notes:

1. Dimensions D & E do not include interlead flash.

2. Dimension b1 does not include dambar protrusion/intrusion.

3. Controlling dimension: Inches

14

c

20

4. General appearance spec. should be based on final

visual inspection sepc.

L

A2

A1

A

q

e

b

b1

Seating Plane

y

E

G

Publication Release Date: October 1999

Revision A1

- 19 -

Preliminary W49F020

Package Dimensions, continued

32-pin TSOP

H D

D

Dimension in Inches

Dimension in mm

Max.

Min. Nom.

Symbol

Min. Nom.

Max.

__

A

1.20

0.15

1.05

c

0.047

0.006

__

0.002

0.05

0.95

A ₁

0.037 0.039 0.041

1.00

0.20

0.15

2

A

M

e

0.007 0.008

0.009

0.17

0.12

0.23

0.17

b

E

c

D

E

0.005 0.006

0.720 0.724

0.007

0.728

0.10(0.004)

18.30 18.40 18.50

b

0.311 0.315

0.780 0.787

7.90

8.00

8.10

0.319

19.80

__

20.00 20.20

0.795

__

H_D

e

__

0.020

0.50

0.016 0.020

0.40

__

0.50

0.60

__

L

0.024

__

0.031

0.80

__

L

1

A

__

0.000

0.004

5

0.10

5

0.00

1

Y

A2

A 1

1

3

q

L

Y

L₁

Note:

Controlling dimension: Millimeters

- 20 -

Preliminary W49F020

VERSION HISTORY

VERSION

DATE

Oct. 1999

PAGE

DESCRIPTION

A1

-

Initial Issued

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Winbond Memory Lab.

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Headquarters

Rm. 803, World Trade Square, Tower II,

123 Hoi Bun Rd., Kwun Tong,

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5796096

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

Publication Release Date: October 1999

Revision A1

- 21 -


型号：	W49F020
厂家：	WINBOND
描述：	256K X 8 CMOS FLASH MEMORY 256K ×8 CMOS FLASH MEMORY
文件：	总21页 (文件大小：189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W49F020 [WINBOND]

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