W6810_1 [WINBOND]
Codec Evaluation System User’s Guide; 编解码器评价系统用户指南
| 型号： | W6810_1 |
| 厂家： | 
WINBOND |
| 描述： | Codec Evaluation System User’s Guide |
| 文件： | 总16页 (文件大小：598K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Winbond W6810 Codec
Evaluation System
User’s Guide
W6810DK Evaluation Board
Rev 1.06
1
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Chapter - 1...................................................................................................................................................... 3
General Description........................................................................................................................................ 3
Introduction:................................................................................................................................................... 3
W6810DK Features:....................................................................................................................................... 3
Figure 1: W6810DK Evaluation System Component Placement ............................................................................. 4
Chapter - 2...................................................................................................................................................... 5
Hardware Description..................................................................................................................................... 5
Clock Generator: ............................................................................................................................................ 5
Frame Sync:.................................................................................................................................................... 5
BIT CLOCK:.................................................................................................................................................. 6
256 KHZ:........................................................................................................................................................ 6
Figure 2: W6810DK Evaluation System Schematics diagram....................................................................... 7
Chapter - 3...................................................................................................................................................... 9
Jumper Descriptions....................................................................................................................................... 9
J2A: Frame Sync: .................................................................................................................................. 10
J3: Power Supply 5VDC.......................................................................................................................... 10
J4: GND TST points................................................................................................................................ 10
J5: Side Tone ........................................................................................................................................... 10
J6: VAG CAP ENABLE: ........................................................................................................................ 10
J7: Transmitter......................................................................................................................................... 10
J8: RJ11 Handset connector.................................................................................................................... 10
J9A: 2.5V Reference Voltage................................................................................................................. 10
J9B: SPKR+ = PAO ................................................................................................................................ 10
J10: A-Law and µ-Law Selection:........................................................................................................... 10
J11: 2x20 pin Header:.............................................................................................................................. 11
J12A: SPKR- = R0- ................................................................................................................................. 11
J12B: SPKR-=PA0+................................................................................................................................ 11
J13: PCMT:.............................................................................................................................................. 11
J14: BCLKT=BCLK................................................................................................................................ 11
J15A: MCLK = 256KHz ......................................................................................................................... 11
J15B: MCLK=BCLK............................................................................................................................... 11
J16A: POWER-UP .................................................................................................................................. 11
J16B: POWER-Down.............................................................................................................................. 11
J17A: BCLKR = BCLK........................................................................................................................... 11
J17B: BCLKR = BCLK........................................................................................................................... 12
J17C: BCLKR = BCLK........................................................................................................................... 12
J18: PCMT = PCMR ............................................................................................................................... 12
J19A: FSR = FSYNC .............................................................................................................................. 12
J19B: FSR = VCC ................................................................................................................................... 12
J19C: FSR = GND................................................................................................................................... 12
J20: FSX= FSYNC.................................................................................................................................. 12
J21: Receiver Path ................................................................................................................................... 12
Chapter - 4.................................................................................................................................................... 13
Operation Modes .......................................................................................................................................... 13
Standalone Operation: .................................................................................................................................. 13
Back-To-Back Operation: ............................................................................................................................ 14
2
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Chapter - 1
General Description
Winbond’s W6810DK Evaluation/Development System is a Stand-Alone unit that serves
as a simple, easy-to-use demonstration board as well as a powerful evaluation system. All
the functions of the W6810 PCM Codec may be selected in real time to allow complete
evaluation of this IC for an end application. The hardware includes many useful
connectors that will allow easy connection to external hardware for use as an evaluation
tool.
Introduction:
The W6810 is a member of the W68XX family of PCM Codecs. This CMOS product
includes a single voice band CODEC. The CODEC complies with the specifications of
the ITU-T G.712 recommendation. The W6810 also includes a complete µ-Law and A-
Law compander. The µ-Law and A-Law companders are designed to comply with the
specifications of the ITU-T G.711 recommendation. The system can work at 256 kHz,
512 kHz, 1536 kHz, 1544 kHz, 2048 kHz, 2560 kHz & 4096 kHz clock rates. The system
clock is supplied through the master clock input and can be derived from the bit-clock if
desired.
User I/O to the W6810DK Evaluation board is provided via a number of connectors.
These connectors are:
• A 40-pin header provides access to W6810 analog and digital signals (J11)
• RJ11 handset jack (J8)
• Analog transmit(J8) and receive path headers.(J7,J21)
W6810DK Features:
• Easy to use (a stand-alone evaluation system)
• Single 5 V power supply
• Single 3v Power Supply for W6811 or W68310
• Prototype area for application development
• Useful connectors that can be used to connect to standard test equipment
• RJ11 jack for standard handset
3
WECA
W6810DK
2727 N First Street, San Jose CA 95134
J11 Connector for Back-To-
Back Operation Mode
Dip Switches Select JX
W6810 Socket
J17
J1 BIT CLOCK
Select
J2
J5
SW3
J9A
J6J9B
J10A
J10B
J12A
J12B
SW4
SW5
J13
Prototype
Area
J15A
J15B
J14
J16A
J16B
SW2
J18
J19A
J19B
01
Power Jack
J3
Frame Sync Width
Selector
RJ11 Handset connector
J8
Figure 1: W6810DK Evaluation System Component Placement
4
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Chapter - 2
Hardware Description
Clock Generator:
All the necessary clock rates such as Frame Sync, Bit Clock and the 256KHz for the
W6810DK evaluation system are driven from a single 4.096MHz crystal oscillator.
Frame Sync:
The Frame Sync is generated on the W6810DK evaluation board. J19 and J20(SW5)
control the FSR (Frame Sync Receive) and FSX (Frame Sync Transmit) routing.
Populating these jumpers also routes the signal to the 40-pin header (J11).
Setting Dip Switches:
Switch SW2 selects the width of the Frame Sync. The pulse width is set as a number of
BCLKs. The following number of BCLKs for Frame Sync can be set with SW2.
• 1-2-3-4-5-6-7-8
The Dip-Switch SW2 configurations are:
Frame Sync = 8 BCLK
Frame Sync = 7 BCLK
Frame Sync = 5 BCLK
ON
ON
OFF
OFF
1
8
ON
ON
OFF
OFF
5
WECA
2727 N First Street, San Jose CA 95134
W6810DK
Frame Sync = 4 BCLK
Frame Sync = 3 BCLK
ON
ON
OFF
OFF
Long Frame Sync
Short Frame Sync
Frame Sync = 1
Frame Sync = 2
ON
ON
OFF
OFF
1
8
1
8
BIT CLOCK:
Bit clock is routed to the 2x20 (J11) header connector pins 5 (BCLKT) and 36 (BCLKR)
through J17A and J14. J1 is used to select the frequency at which Bit Clock operates. The
selected frequencies are 4.096 MHz, 2.048 MHz, 1.024 MHz, 512KHz, 128KHz and
64KHz.
256 KHZ:
The 256 KHz is a possible frequency setting for the master clock (MCLK) J15A(SW4)
input on the chosen PCM Codec-filter. J15B will configure the MCLK input to have a
frequency equal to Bit Clock.
6
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Ext
Analog
VCC
R6
R4
1K
C10
R5
20K
R7
100
1uJF5
C12
3.9K
R8
C11
1uF
C13
1uF
J5
C14
R9
256KHz
68uF
.1uF
20K
619
FSYNC
BCLK
R10
R11
20K
J6
200K
C15
R12
20K
.01uF
J8
TX
BCLKR
J9
MIC+
A
B
1
2
3
4
J7
U7
1
2
20
VCC
Handset
Vref
VAG
AI+
SW DIP
19
18
17
16
15
14
13
12
11
RO
3
VCC
PAI
AI-
J11
4
J10
PAO-
PAO+
VDD
FSR
PCMI
AO
MIC-
A
B
5
U/A
VSS
FSX
FSX
6
1
3
2
7
J13
SW DIP
4
BCLKT
PCMO
MCLK
8
SW DIP
5
6
PCMO
A
9
7
8
BCLKR BCLKT
10
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PUI
MCLK
J12
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
W6810
B
J14
J15
A
B
J16
VCC
A
B
SW DIP
VCC
R13
20K
SW DIP
A
B
C
SW DIP
R14
3K
SW DIP
J17
VCC
VCC
R15
J19
VCC
HEADER 20X2
A
B
C
SW DIP J18
47k
C16
68uF
SW DIP
J20
SW DIP
FSR
R16
20K
VCC
PCMO
C17
1uF
C18
.1uF
Receive
Audio
RX
J21
Figure 2: W6810DK Evaluation System Schematic Diagram
7
WECA
W6810DK
2727 N First Street, San Jose CA 95134
74HCU04/SO
VCC
74HCU04/SO
3
74HCU04/SO
1
2
BCLK
4
5
6
U1A
RP1
10K
U1B
U1C
BCLK
74HCU04/SO U1D
74HCU04/SO U1E
VCC
1
PL
J1
U4A
2
4
5
15
2
D
Q
6
CKE
4096KHz
2048KHz
1
3
2
PRE
CLK
CLR
Q
9
8
11
10
1
2
3
4
5
6
4
CLK
CLR
QA
QB
QC
QD
CLK
1024KHz
512KHz
256KHz
128KHz
64KHz
5
6
3
1
R1
7
8
6
D7
D6
D5
D4
D3
D2
D1
D0
100
9
10
12
14
5
R2
11
13
4
3
74HC393/SO
74HC74
U3A
14
13
12
11
10M
HEADER
Y1
U4B
7
9
Q7
Q7
10
SDI
13
11
10
9
U5A
CLK
QA
QB
QC
QD
74HC393/SO
74HC165
32KHz
4.096MHz
12
1
3
4
5
6
1
3
4
U2
CLR
CLK
QA
QB
QC
QD
8KHz
C1
8
2
22pF
2
CLR
C2
22pF
74HC393/SO
HEADER 2X2
J2
U1F
74HCU04/SO
VCC
13
12
256KHz
U6A
1
PWR OFF/ON
CLR
VCC
3
4
2
CLK
PRE
D
SW1
6
Q
5
Q
EG1903-ND
C3
D2
LED
68uF
1N5341
D1
FSYNC
74HC74
U5B
On
R3
330
13
12
11
10
9
CLK
CLR
QA
QB
QC
QD
PJ_202A
1
8
+5VDC
2
Off
74HC393/SO
VCC
J4
SW2
U1
U2
U3
U4
U5
1
2
3
4
5
6
C9
C4
C5
C6
C7
C8
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
Figure 3: W6810DK Evaluation System Schematic Diagram:
8
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Chapter - 3
Jumper Descriptions
Dips switches on the left hand corner of the evaluation system are used to select a
particular jumper. When a Jumper is populated (switch is closed), it enables the function;
an unpopulated Jumper(Open Switches) disables the function. A Jumper, when
referenced as a letter for example J7A, J7B. Only one Jumper is populated for a selected
function not both.
Please see page 4.Figure 1: W6810DK Evaluation System Component Placement
9
WECA
W6810DK
2727 N First Street, San Jose CA 95134
J1: Bit Clock Select:
J1 selects the Bit Clock frequencies from 4.096MHz to 64KHz.
J2A: Frame Sync:
J2A sets the Frame Sync (FSR) to 8KHz (SW3-2)
J3: Power Supply 5VDC
J4: GND TST points
J5: Side Tone (SW3-6)
J5 enables the side tone path on the PCM Codec filter
J6: VAG CAP ENABLE: (SW4-1)
J6 enables VAG filter cap
J7: Transmitter
Transmit output level at 1000Hz: -46dBV ± 4dB
Output Impedance at 100 Hz: 1000 ± 300 Ω
J8: RJ11 Handset connector.
J9A: 2.5V Reference Voltage (SW3-7)
J9A is not used.
J9B: SPKR+ = PAO
(SW3-8)
J9B connects pin 4 W6810 to the RJ11 handset
J10: A-Law and µ-Law Selection: (SW4-2)
J10A Selects µ _Law and J10B Selects A-Law.
10
WECA
W6810DK
2727 N First Street, San Jose CA 95134
J11: 2x20 pin Header:
This 40-pin header provides access to W6810 analog and digital signals for a user
defined system, or a second W6810DK evaluation system for back-to-back operation.
J12A: SPKR- = R0- (SW4-4)
J12A connects RO- (Pin2) to the RJ11 and the RX output connector.
J12B: SPKR-=PA0+ (SW4-5)
J12B connects PA0+ (Pin 5) to the RJ11 and the RX output connector.
J13: PCMT: (SW4-6)
J13 Connects the PCMT (PCM output W6810) to J11 (Pin 9).
J14: BCLKT=BCLK (SW5-1)
J14 connects BCLK to BCLKT (Pin 12) of the W6810 Codec-Filter.
J15A: MCLK = 256KHz (SW4-7)
J15A sets the MCLK Pin 11 to 256KHz.
J15B: MCLK=BCLK (SW4-8)
J15B sets the MCLK Pin 11 to be equal to BCLK.
J16A: POWER-UP (SW5-2)
J16A connects the PUI Pin10 of the W6810 Codec to VCC to power up the device.
J16B: POWER-Down (SW5-3)
J16B connects the PUI Pin10 of the W6810 Codec to GND to power down the device.
J17A: BCLKR = BCLK
J17A connects BCLKR (Pin 9) of the PCM W6810 Codec to BCLK.
11
WECA
W6810DK
2727 N First Street, San Jose CA 95134
J17B: BCLKR = BCLK
J17B connects BCLKR (Pin 9) of the PCM W6810 Codec to VCC.
J17C: BCLKR = BCLK
J17Cconnects BCLKR (Pin 9) of the PCM W6810 Codec to Ground
J18: PCMT = PCMR (SW5-4)
J18 Connects PCM output data transmit Pin (13) to PCM input data receive Pin (8) of the
W6810 Codec.
J19A: FSR = FSYNC (SW5-5)
J19 A connects FSR (Pin 7) of the W6810 Codec to Frame Sync.
J19B: FSR = VCC (SW5-6)
J19 B connects FSR (Pin 7) of the W6810 Codec to VCC.
J19C: FSR = GND (SW5-7)
J19 C connects FSR (Pin 7) of the W6810 Codec to Ground.
J20: FSX= FSYNC (SW5-8)
J20 connects the on board generated Frame Sync to W6810 FSX (Pin 14) as well as to
Pin 1 of the J11.
J21: Receiver Path
J21 can be connected to test equipment for measurements.
Receive output level at 1000Hz: 79dBSPL ± 4dB
Receive input Impedance at 100 Hz: 150Ω ± 20%
12
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Chapter - 4
Operation Modes
The W6810DK operates in two modes, Standalone and Back- To- Back mode.
Standalone Operation:
In this mode of operation the W6810DK the signal input at Transmit input (J7), is
presented to the encoder of the W6810, where it is digitized and output on the PCM input
data transmit pin (J6). This provides a local loop back. Of the PCM, data to the PCM data
input receive pin (PCMR) of the W6810, where it is reconstructed and output at J12
(RX). The following Jumpers are populated in this mode J1 (2.048MHz), J17A and J20
the Dipswitches are set as follows.
J17 = A
0
1
0
0
0
1
0
1
1
1
0
0
1
0
0
1
1
1
0
1
1
0
0
1
13
WECA
W6810DK
2727 N First Street, San Jose CA 95134
Back-To-Back Operation:
The W6810DK evaluation system can be connected back to back using the 20x2 header
(J11) .The cable should be maximum 2-3 inches in length. It makes all necessary
electrical connections, allowing a full “analog-to-analog, “handset-to-handset” path to be
established.
For Back to Back operation the jumper setting are set to ON position as follows for
(W6810DK #1 Master board) unit. J1 (2.048MHz), J2B, J5 (side tone), J9B, J6, J10, J7A
J12B, J13, J15B, J14, J16, J19Aand J20B W6810DK #1 acts as the system master,
providing BCLK and FSYNC to W6810DK #2. The jumper setting for board #2 is as
follows. J1 (2.048MHz), J2, J5, J9B, J6, J10A J12B, J13, J15B and J16.
The following Dip-switches are set as for back-to-back -mode
Note: Do not connect the power supply to the second board. It will be bussed to the
second board through the 2x20 cable. Make sure the cable is connected as shown
below.
J17 = Open
J17 = A
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
1
14
WECA
2727 N First Street, San Jose CA 95134
W6810DK
W6810 Conversion to W6811.
The W6811 is a general-purpose single channel PCM CODEC with pin-selectable µ-Law or A-
Law companding. The device is compliant with the ITU G.712 specification. It operates off a
separated analog (5V) and digital (3V) power supplies. Functions performed include digitization
and reconstruction of voice signals, and band limiting and smoothing filters required for PCM
systems. The filters are compliant with ITU G.712 specification. W6811 performance is specified
over the industrial temperature range of –40°C to+85°C.
The W6811 includes an on-chip precision voltage reference and an additional power amplifier,
Capable of driving 300 ohm loads differentially up to a level of 6.3V peak-to-peak. The analog
section is fully differential, reducing noise and improving the power supply rejection ratio.
For evaluation of the W6811, use W6810DK prototype area to connect the W6811 to
W6810 socket as shown below (only if it is desired to connect a separate 3V power
supply for digital I/O otherwise use the direct connection below)
U1
1
2
20
19
18
17
16
15
14
13
12
11
Vref
VAG
AI+
RO
U2
3
PAI
AI-
4
1
2
24
23
22
21
20
19
18
17
16
15
14
13
PAO-
PAO+
VDD
FSR
PCMI
AO
Vref
VAG
AI+
VDDD
5
U/A
RO-
47UF Tant
6
3
VSS
FSX
PCMO
PAI
AI-
7
4
PAO-
PAO+
VDDA
NC
AO
8
5
+
U/A
C2
9
6
BCLKR BCLKT
VSS
NC
10
7
PUI
MCLK
8
+5V
VDDD
FSR
VSSD
FST
PCMT
9
W6810
10
11
12
PCMR
L1
INDUCTOR
C1
VDDD
U1
BCLKR BCLKT
PUI
MCLK
W6811
8
5
1
2
IN
SHDN
3.0V
+
SENSE
.1UF
U3A
3
6
7
C3
GND
GND
GND
47UF Tant
2
4
6
8
18
16
14
12
A0
A1
A2
A3
Y0
Y1
Y2
Y3
VDDD
C4
100uF
LT1521-3
1
U3B
OE
VCCD
11
13
15
17
9
A0
A1
A2
A3
Y0
MC74HC244ADW
7
5
3
Y1
Y2
Y3
R1
33K
19
OE
JP1
2
1
MC74HC244ADW
15
WECA
2727 N First Street, San Jose CA 95134
W6810DK
For performance evaluation of the W6811 with 5v Digital I/O (the device works
similar to W6810) you can connect the W6810 Socket on the W6810DK to a
prototype board which has the W6811 foot print as below.
U2
1
24
23
22
21
20
19
18
17
16
15
14
13
Vref
VAG
AI+
2
RO-
3
PAI
AI-
4
PAO-
PAO+
VDDA
NC
AO
5
U/A
6
VSS
NC
7
8
VDDD
FSR
VSSD
FST
PCMT
9
10
11
12
PCMR
BCLKR BCLKT
PUI
MCLK
W6811
U1
1
2
20
19
18
17
16
15
14
13
12
11
Vref
VAG
RO
AI+
AI-
3
PAI
4
PAO-
PAO+
VDD
FSR
PCMI
AO
5
U/A
6
VSS
FSX
PCMO
7
8
9
BCLKR BCLKT
10
PUI
MCLK
W6810
16
WECA
2727 N First Street, San Jose CA 95134
W6810DK
相关型号：
©2020 ICPDF网 联系我们和版权申明