W682310 [WINBOND]
DUAL-CHANNEL VOICEBAND CODECS; 双通道语音频带编解码器
| 型号： | W682310 |
| 厂家： | 
WINBOND |
| 描述： | DUAL-CHANNEL VOICEBAND CODECS |
| 文件： | 总35页 (文件大小：1177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED
W682510/W682310
DUAL-CHANNEL VOICEBAND CODECS
Publication Release Date: May 2003
Revision 0.35
- 1 -
W682510/W682310
1. GENERAL DESCRIPTION
The W682510 and W682310 are general-purpose dual channel PCM CODECs with pin-selectable µ-
Law or A-Law companding. The device is compliant with the ITU G.712 specification. It operates from
a single power supply (+5V for the W682510, +3V for the W682310) and is available in 20-pin PDIP
(W682510 only), SSOP, and 24-pin SOP package options. Functions performed include digitization
and reconstruction of voice signals, and band limiting and smoothing filters required for PCM systems.
The filters are compliant with ITU G.712 specification. The W682510 and W682310 performance is
specified over the industrial temperature range of –40°C to +85°C.
The W682510 includes an on-chip precision voltage reference and receive output buffer amplifiers,
capable of driving 600Ω loads (line transformers.) The analog section is fully differential, reducing
noise and improving the power supply rejection ratio. The data transfer protocol supports either
parallel or serial synchronous communications for PCM applications. The W682510 and W682310
have a build in PLL that eliminates the need for a master clock and automatically determines the
division ratio for the required internal clock.
For fast evaluation and prototyping purposes, the W682510DK & W682310DK development kits are
available.
APPLICATIONS
2. FEATURES
•
•
Digital Telephone Systems
Central Office Equipment (Gateways,
Switches, Routers)
PBX Systems (Gateways, Switches)
PABX/SOHO Systems
Hands free system
Speakerphone devices
VoIP Terminals
•
Single power supply
o
4.5V to 5.5V (W682510)
2.7V to 3.8V (W682310)
o
•
•
•
•
•
•
•
•
•
Typical power dissipation of 35 mW,
power-down mode of 5 µW
•
•
Fully-differential analog circuit design
On-chip precision reference-
o
W682510: 1.73V for a 0.8 dBm
0TLP at 600 Ω
Enterprise Phones
ISDN Terminals
Analog line cards
o
W682310: 1.41V reference for a
0TLP of –3.8 dBm into 1200 Ω
•
•
•
•
Pin-selectable
µ-Law
and
A-Law
companding (compliant with ITU G.711)
CODEC A/D and D/A filtering compliant
with ITU G.712
Industrial temperature range (–40°C to
+85°C)
Three packages: 20-pin SSOP, 20-pin
PDIP, and 24-pin SOP
- 2 -
W682510/W682310
3. BLOCK DIAGRAM
DATA T1
DATA R1
/A-Law
CODEC
Filter 1
RO1
AO1-
AI1
µ
PCMT1
PCMT2
FST
BCLK
FSR
/A-Law
µ
PCMMS
PCMR1
PCMR2
DATA T2
DATA R2
RO2
AO2-
AI2
/A-Law
µ
CODEC
Filter 2
VREF
PLL
Voltage reference
Power Conditioning
Publication Release Date: May 2003
Revision 0.35
- 3 -
W682510/W682310
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION..................................................................................................................2
1. GENERAL DESCRIPTION..................................................................................................................2
2. FEATURES..........................................................................................................................................2
3. BLOCK DIAGRAM..............................................................................................................................3
4. TABLE OF CONTENTS......................................................................................................................4
5. PIN CONFIGURATION .......................................................................................................................6
6. PIN DESCRIPTION .............................................................................................................................7
7. FUNCTIONAL DESCRIPTION............................................................................................................8
7.1. Transmit Path.............................................................................................................................8
7.1.1. AI1, AI2, AO1-, AO2-..............................................................................................................9
7.1.2. PCMT1 ...................................................................................................................................9
7.1.3. PCMT2 .................................................................................................................................10
7.2. Receive Path............................................................................................................................10
7.2.1. RO1, RO2.............................................................................................................................10
7.2.2. PCMR1.................................................................................................................................11
7.2.3. PCMR2.................................................................................................................................11
7.3. Power Signals ..........................................................................................................................11
7.3.1. VDD ........................................................................................................................................11
7.3.2. VSSA.......................................................................................................................................11
7.3.3. VSSD.......................................................................................................................................11
7.3.4. VREF.......................................................................................................................................12
7.3.5. PUI........................................................................................................................................12
7.4. PCM Interface ..........................................................................................................................12
7.4.1. µ/A-Law ................................................................................................................................12
7.4.2. BCLK ....................................................................................................................................13
7.4.3. FSR.......................................................................................................................................13
7.4.4. FST.......................................................................................................................................13
7.4.5. PCMMS ................................................................................................................................13
7.5. Power State Modes.................................................................................................................13
7.5.1. Power Save Mode ................................................................................................................13
7.5.2. Power Down Mode...............................................................................................................14
7.5.3. Power Save/Down Output pin state .....................................................................................14
8. TIMING DIAGRAMS..........................................................................................................................15
9. ABSOLUTE MAXIMUM RATINGS...................................................................................................19
- 4 -
W682510/W682310
10. ELECTRICAL CHARACTERISTICS ..............................................................................................20
10.1. General Parameters W682510 4.5V – 5.5V................................................................20
10.2. General Parameters W682310 2.7V – 3.8V................................................................20
10.3. Analog Signal Level and Gain Parameters .......................................................................22
10.4. Analog Distortion and Noise Parameters ..........................................................................24
10.5. Analog Input and Output Amplifier Parameters................................................................25
10.6. Digital I/O................................................................................................................................26
11. TYPICAL APPLICATION CIRCUIT ................................................................................................29
12. PACKAGE DRAWING AND DIMENSIONS ...................................................................................31
12.1. 20L (PDIP) Plastic Dual Inline Package Dimensions (W682510 only) .........................31
12.2. 20L SSOP – 209 mil Shrink Small Outline Package Dimensions..................................32
12.3. 24 SOP – 300 mil ..................................................................................................................33
13. ORDERING INFORMATION...........................................................................................................34
14. VERSION HISTORY........................................................................................................................35
Publication Release Date: May 2003
- 5 -
Revision 0.35
W682510/W682310
5. PIN CONFIGURATION
AI2
VREF
RO2
NC
RO1
PUI
PCMMS
NC
VDD
VSSD
FSR
1
2
24
23
22
21
20
19
18
17
16
15
AO2-
AO1-
AI1
3
4
W682510/
NC
5
W682310
DUAL
CHANNEL
CODEC
A-Law
µ/
6
VSSA
NC
7
8
BCLK
FST
9
10
PCMT2
PCMT1
PCMR2
PCMR1
11
12
14
13
SOP
AI2
VREF
RO2
RO1
PUI
PCMMS
VDD
VSSD
FSR
PCMR2
PCMR1
1
2
20
19
18
17
16
15
14
13
12
11
AO2-
AO1-
AI1
3
4
W682510/
W682310
DUAL
CHANNEL
CODEC
A-Law
VSSA
µ/
5
6
BCLK
FST
PCMT2
PCMT1
7
8
9
10
PDIP (W682510 only), SSOP
- 6 -
W682510/W682310
6. PIN DESCRIPTION
Pin #
Pin #
Pin
Functionality
Name
SSOP
PDIP
SOP
(CH1 = Channel 1, CH2 = Channel 2)
VREF
1
1
This pin is used to bypass the signal ground. It needs to be decoupled to VSS
through a 0.1 µF ceramic decoupling capacitor. No external loads should be
tied to this pin.
RO2
RO1
PUI
2
3
4
5
6
2
4
5
6
8
CH2 Non-Inverting output of the receive smoothing filter. This pin can typically
drive a 600 Ω load (W682510) or 1200 Ω load (W682310).
CH1 Non-Inverting output of the receive smoothing filter. This pin can typically
drive a 600 Ω load (W682510) or 1200 Ω load (W682310)..
Power up input signal. When this pin is HIGH (tied to VDD) the part is powered
up. When LOW (tied to VSS) the part is powered down.
PCM mode select input (serial or parallel data interface) HIGH = Parallel, LOW
= Serial
PCMMS
VDD
Power supply. This pin should be decoupled to VSS with a 0.1µF ceramic
capacitor.
VSSD
FSR
7
8
9
This is the digital supply ground. This pin should be connected to 0V.
8 kHz Frame Sync input for the PCM receive section. It can also be connected
to the FST pin when transmit and receive are synchronous operations.
10
PCMR2
PCMR1
PCMT1
PCMT2
9
11
12
13
14
CH2 PCM input data receive pin. The data needs to be synchronous with the
FSR and BCLK pins.
CH1 PCM input data receive pin. The data needs to be synchronous with the
FSR and BCLK pins.
CH1 PCM output data transmit pin. The output data is synchronous with the
FST and BCLK pins.
CH2 PCM output data transmit pin. The output data is synchronous with the
FST and BCLK pins.
10
11
12
FST
13
14
15
16
15
16
18
19
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
PCM transmit and receive bit clock input pin for CH1 and CH2 transmit.
This is the analog supply ground. This pin should be connected to 0V.
BCLK
VSSA
μ/A-Law
Compander mode select pin. µ-Law companding is selected when this pin is
LOW (tied to VSS.) A-Law companding is selected when pin is HIGH (tied to
VDD.)
AI1
17
18
19
20
21
22
23
24
CH1 Non-Inverting input of the first gain stage in the transmit path.
CH1 Inverting analog output of the first gain stage in the transmit path.
CH2 Inverting analog output of the first gain stage in the transmit path
CH2 Non-Inverting input of the first gain stage in the transmit path.
AO1-
AO2-
AI2
Publication Release Date: May 2003
- 7 -
Revision 0.35
W682510/W682310
7. FUNCTIONAL DESCRIPTION
W682510/W682310 is a single-rail, dual channel PCM CODEC for voiceband applications. The
CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC includes
two complete µ-Law and A-Law companders. The µ-Law and A-Law companders are designed to
comply with the specifications of the ITU-T G.711 recommendation.
The block diagram in section 3 shows the main components of the W682510/W682310. The chip
consists of a PCM interface, which can process the data in parallel or serial formats. The PLL of the
chip provides the internal clock signals and synchronizes the CODEC sample rate with the external
frame sync frequency. The power-conditioning block provides the internal power supply for the digital
and the analog section, while the voltage reference block provides a precision analog ground voltage
for the analog signal processing.
8
-
8 bit /A-Law
DATA
R1
µ
RO1
RO2
DAC
+
fC = 3400 Hz
Buffer1
Av=1
Smoothing
Filter 1a
Smoothing
Filter 1b
/A-
Control
µ
8
-
8 bit /A-Law
DATA
R2
µ
DAC
+
fC = 3400 Hz
Buffer2
Av=1
Smoothing
Filter 2a
Smoothing
Filter 2b
/A-
µ
Control
AO1-
AI1
8
-
8 bit /A-Law
DATA
T1
µ
ADC
fC = 200 Hz
fC = 3400 Hz
+
Aliasing
Aliasing
Anti-
Filter 1b
High Pass
Filter
Anti-
Filter 1a
/A-
Control
µ
AO2-
AI2
8
-
DATA
T2
8 bit /A-Law
µ
ADC
fC = 200 Hz
fC = 3400 Hz
+
High Pass
Filter
Anti-Aliasing
Filter 2a
Anti-
Aliasing
Filter 2b
/A-
Control
µ
FIGURE 7.1: THE W682510 AND W682310 SIGNAL PATH
7.1. TRANSMIT PATH
The A-to-D path of the CODEC contains an analog input amplifier with externally configurable gain
setting (see application examples in section 11). The transmit amplifier output is the input to the
encoder section.
The output of the input amplifier is fed through a low-pass filter to prevent aliasing at the switched
capacitor 3.4 kHz low pass filter. The 3.4 kHz switched capacitor low pass filter prevents aliasing of
input signals above 4 kHz, due to the sampling at 8 kHz. The output of the 3.4 kHz low pass filter is
filtered by a high pass filter with a 200 Hz cut-off frequency. The filters are designed according to the
recommendations in the G.712 ITU-T specification. From the output of the high pass filter the signal is
digitized. The signal is converted into a compressed 8-bit digital representation with either µ-Law or A-
- 8 -
W682510/W682310
Law format. The µ-Law or A-Law format is pin-selectable through the µ/A-Law pin. The compression
format can be selected according to Table 7.1.
TABLE 7.1: PIN-SELECTABLE COMPRESSION FORMAT
Format
/A-Law Pin
µ
VDD (HIGH)
VSSA (LOW)
A-Law
µ-Law
The digital 8-bit µ-Law or A-Law samples are fed to the PCM interface for serial or parallel
transmission at the sample rate supplied by the external frame sync FST.
7.1.1. AI1, AI2, AO1-, AO2-
AI1 and AI2 are the transmit analog inputs for channels 1 and 2. AO1- and AO2- are the transmit level
feedback for channels 1 and 2. AI1 and AI2 are inverting inputs for the Op-Amps. AO1- and AO2- are
connected to the outputs of the Op-Amps and are used to set the level, as illustrated below. When AI1
and AI2 are not used, connect AI1 to AO1- and AI2 to AO2-. During power saving mode and power
down mode, the AO1- and AO2- outputs are tied weakly to VSSA on the W682510 or are high
impedance on the W682310 (See table on page 14).
R2
AO1-
Gain=R2/R1 10
≤
C1 R1
R2 > 20 k Ohm
AI1
CH1 Analog Input
CH2 Analog Input
-
+
R4
AO2-
AI2
Gain=R4/R3 10
≤
C2 R3
R4 > 20 k Ohm
-
+
7.1.2. PCMT1
The PCM signal output of channel 1 when the parallel mode is selected. The PCM output signal is
sent from PCMT1 in a sequential order, synchronizing with the rising edge of the BCLK signal. The
MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST.
This output pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power-saving state or power-down. When serial operation is selected, this pin
is configured to be the output of the serial multiplexed two channel PCM signal. A pull-up resistor must
Publication Release Date: May 2003
- 9 -
Revision 0.35
W682510/W682310
be connected to this pin , as it is an open drain output. This device is compatible with the ITU-T coding
law and output coding format recommendation.
TABLE 7.15: PCM CODES FOR ZERO AND FULL SCALE
A-Law
Chord Bits
010
-Law
µ
Level
Sign bit
Chord bits
000
Step bits
0000
Sign Bit
Step Bits
1010
+ Full Scale
+ Zero
1
1
0
0
1
1
0
0
111
1111
101
0101
- Zero
111
1111
101
0101
- Full Scale
000
0000
010
1010
7.1.3. PCMT2
The PCM signal output for channel 2 when the parallel mode is selected. The PCM output signal is
sent from PCMT2 in a sequential order, synchronized with the rising edge of the BCLK signal. The
MSB may be output at the rising edge of the FST signal, based on the timing between BCLK and FST.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high impedance
state during power-saving state or power-down. When the serial operation is selected, this pin is left
open. A pull-up resistor must be connected to this pin , as it is an open drain output. This device is
compatible with the ITU-T coding law and output coding format recommendation.
7.2. RECEIVE PATH
The 8-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and
converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed
through the pin-selectable µ-Law or A-Law expander and converted to analog samples. The mode of
expansion is selected by the µ/A-Law pin as shown in Table 7.2. The analog samples are filtered by a
low-pass smoothing filter with a 3.4 kHz cut-off frequency, according to the ITU-T G.712 specification.
A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is
buffered to provide the receive output signal RO.
7.2.1. RO1, RO2
RO1 and RO2 are the receive analog outputs for channel 1 and channel 2. The output signal of the
W682510 has an amplitude of 3.46 Vpp (2.03 Vpp for W682310) around the signal ground voltage
(VREF). When the digital PCM signal of +3 dBm0 is presented to PCMR1 or PCMR2, it can drive a load
of 600 Ohms or more at 5 V supply voltage for the W682510 and 1200 Ohms at 3V supply for the
W682310. During power saving mode, these outputs are at the voltage level of VREF with a high
impedance. These outputs have a feature that reduces audio “pop” noises when switching between
active and inactive states and back.
- 10 -
W682510/W682310
7.2.2. PCMR1
The PCM signal input for channel 1 when in the parallel mode. D/A conversion is performed on the
serial PCM signal input to this pin. The FSR signal, synchronous with the serial PCM signal, and the
BCLK signal, processes the code. Then the analog output is output from the RO1 pin. The data rate of
the PCM signal is equal to the frequency of the BCLK signal.
The PCM signal is shifted in on the falling edge of the BCLK signal. It is latched into the internal 8-bit
register. The start of the PCM data (MSB) is synchronized with the rising edge of FSR. In the serial
mode, this pin is not used and should be connected to GND (0V).
7.2.3. PCMR2
PCM signal input for channel 2 when the parallel mode is selected. D/A conversion is performed with
the serial PCM signal input to this pin, the FSR signal, synchronous with the serial PCM signal, and
the BCLK signal, and then the analog output is output from the RO2 pin. The data rate of the PCM
signal is equal to the frequency of the BCLK signal. The PCM signal is shifted at the falling edge of the
BCLK signal and latched into the internal register when shifted by eight bits. The start of the PCM data
(MSB) is identified at the rising edge of FSR. In the serial mode this pin is used for the two channel
multiplexed PCM signal input.
7.3. POWER SIGNALS
7.3.1. VDD
The power supply for the analog and digital parts of the W682510 must be 5V +/- 10% and 2.7V to
3.8V for the W682310. This supply voltage is connected to the VDD pin. The VDD pin needs to be
decoupled to ground through a 0.1 µF ceramic capacitor. A power supply for an analog circuit in the
system to which the device is applied should be used. A bypass capacitor of 0.1 µF to 1 µF with good
high-frequency characteristics (Low ESR) and a capacitor of 10 µF to 20 µF should be connected
between this pin and the VSSA pin if needed.
7.3.2. VSSA
Ground for the analog signal circuits. This ground is separate from the digital signal ground. The VSSA
pin must be connected to the VSSD pin on the printed circuit board to make a common ground.
However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB
and run the VSSA and VSSD traces separately to the device.
7.3.3. VSSD
Ground for the digital signal circuits. This ground is separate from the analog signal ground. The VSSD
pin must be connected to the VSSA pin on the printed circuit board to make a common ground.
However, it’s advised to connect the PCB traces of these pins at the main supply hookup of the PCB
and run the VSSA and VSSD traces separately to the device
Publication Release Date: May 2003
- 11 -
Revision 0.35
W682510/W682310
7.3.4. VREF
This pin carries the signal ground voltage level and requires a bypass capacitor. A 0.1µF ceramic
(with low ESR for good high frequency response) capacitor needs to be connected between the VSSA
pin and the VREF pin.
7.3.5. PUI
Power up input signal. When the PUI pin is set to logic “0” level, the CODEC will go into power down
mode.
7.4. PCM INTERFACE
The PCM interface is controlled by pins PCMMS, BCLK, FSR & FST. The input data is received
through the PCMR pin and the output data is transmitted through the PCMT pin. The modes of
operation of the interface are shown in Table 7.2.
TABLE 7.2: PCM INTERFACE MODE SELECTIONS
PCMMS
PCM Mode
Data Available
VDD
[HIGH]
VSS
Parallel
Mode
CH1 data on PCMT1 & PCMR1
CH2 data on PCMT2 and PCMR2 (same timing as CH1)
CH1 data followed by CH2 receive data on PCMR2 (total 16 bits)
CH1 data followed by CH2 transmit data on PCMT1 (total 16 bits)
Serial Mode
[LOW]
7.4.1. /A-Law
µ
This pin selects the desired companding law. The CODEC will operate in the µ-law when this pin is at
a logic “0” level and in the A-law when at a logic “1” level. The CODEC operates µ-law if the pin is left
open, since this pin is internally pulled down.
TABLE 7.25: PIN-SELECTABLE COMPRESSION FORMAT
Format
A-Law
µ-Law
/A-Law pin
µ
HIGH (VDD
)
LOW (VSS), Floating
- 12 -
W682510/W682310
7.4.2. BCLK
This is the shift clock signal input for the PCMR1, PCMR2, PCMT1, and PCMT2 signals. The
frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, 2048 or
200 kHz. Setting this signal to a steady logic “1” or “0” sets both transmit and receive circuits to the
power saving state.
7.4.3. FSR
This is the receive synchronizing signal input. The required eight-bits of PCM data are selected from
the PCM data signal to the PCMR1 and PCMR2 pins by the receive synchronizing signal. All timing
signals in the receive section are synchronized by this synchronizing signal. This signal must be in
phase with the BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics.
This device can operate in the range of 6 kHz to 9 kHz, but the electrical characteristics specified in
the data sheet are not guaranteed.
7.4.4. FST
The transmit synchronizing signal input. The PCM output signal from PCMT1 and PCMT2 is sent in
synchronization with this transmit synchronizing signal. This FST signal triggers the PLL and
synchronizes all timing signals of the transmit section. The synchronizing signal must be in phase with
BCLK. The frequency should be 8 kHz ± 50 ppm to guarantee the AC characteristics. This device can
operate in the range of 6 kHz to 9 kHz sample rates, but the electrical characteristics are not
guaranteed. Setting this signal to logic HIGH or LOW drives both transmit and receive circuits to
power saving state.
7.4.5. PCMMS
The control signal for mode selection of the PCM input and output. When this signal is HIGH, the PCM
input and output are in the parallel mode. The PCM data of CH1 and CH2 is input to PCMR1 and
PCMR2, and output from PCMT1 and PCMT2, with the same timing. When this signal is at a LOW
level, the PCM input and output are in the serial mode. The PCM data of CH1 and CH2 is input to
PCMR2 and output from PCMT1 as two serial 8-bit bytes.
7.5. POWER STATE MODES
7.5.1. Power Save Mode
In the power save mode, all internal analog circuits except the internal reference are powered down.
The CODEC automatically enters the power save mode when the FST or BCLK signal is set to digital
“1” or digital “0”;
Upon power up with FST and BCLK signals present, it will take 2 to 10 milliseconds for the internal
PLL to lock. In addition to the PLL lock-in time, the analog outputs will be set to the internal signal
ground for 1 millisecond. This will avoid power up glitches at the outputs. The digital open drain
outputs will remain at high impedance during this power up delay.
Publication Release Date: May 2003
- 13 -
Revision 0.35
W682510/W682310
7.5.2. Power Down Mode
When the power up indicator pin, PUI, is set LOW all internal circuits will go into the power down state.
It will take 2 to 10 milliseconds for the PLL to lock when operation is resumed with the FST and BCLK
signals applied and PUI set HIGH. An additional 1-millisecond delay is used to set the analog outputs
to the signal ground reference in order to avoid power up glitches. The digital open drain outputs will
remain at high impedance during this power up delay.
7.5.3. Power Save/Down Output pin state
The following table shows the states of the output pins in the power save or power down mode.
TABLE 7.5: OUTPUT PIN STATES
Output Pin
Product Name
AO1-, A02-
VSSA
High Z
RO1, RO2
W682510
W682310
Signal Ground
Signal Ground
- 14 -
W682510/W682310
8. TIMING DIAGRAMS
BCLK
FST
PCMT1
MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 D3 D2 D1 D0
Channel 1 Transmit PCM Data Channel 2 Transmit PCM Data
Figure 8-1a. Transmit Side Serial Mode Timing (PCMMS=0)
BCLK
FSR
PCMR2
MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 D3 D2 D1 D0
Channel 1 Receive PCM Data
Channel 2 Receive PCM Data
Figure 8-1b. Receive Side Serial Mode Timing (PCMMS=0)
FIGURE 8.1: SERIAL MODE PCM TIMING
BCLK
FST
PCMT1
PCMT2
MSB D6 D5 D4 D3 D2 D1 D0
Figure 8-2a. Transmit Side Parallel Mode Timing (PCMMS=1)
BCLK
FSR
PCMR1
PCMR2
MSB D6 D5 D4 D3 D2 D1 D0
Figure 8-2b. Receive Side Parallel Mode Timing (PCMMS=1)
FIGURE 8.2: PARALLEL MODE PCM TIMING
Publication Release Date: May 2003
Revision 0.35
- 15 -
W682510/W682310
BCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
FST
FSR
PCMT1
PCMR2
MSB D6 D5 D4 D3 D2 D1 D0 MSB D6 D5 D4 D3 D2 D1 D0
Channel 1 PCM Data Channel 2 PCM Data
Figure 8-3a. Burst Mode with Serial Timing (PCMMS=0)
BCLK
1
2
3
4
5
6
7
8
9
FST
FSR
PCMTx
PCMRx
MSB D6 D5 D4 D3 D2 D1 D0
Figure 8-3b. Burst Mode with Parallel Timing (PCMMS=1)
FIGURE 8.3: BURST MODE PCM TIMING
- 16 -
W682510/W682310
TABLE 8.1: PCM SYNCHRONIZATION PARAMETERS
DESCRIPTION MIN TYP
---
SYMBOL
MAX UNIT
fFS
tWS
tj
FST, FSR frequency
FST, FSR Pulse Width
FST, FSR allowable jitter
BCLK frequency
8
---
7
500
KHz
TBCLK
nsec
1
0
---
---
fBCLK
64, 128, 256, 512, kHz
1024, 2048, 96, 192,
384,
768,
1536,
1544, 200
DC
tIr
BCLK Duty Cycle
FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS ---
input rise time
40
50
---
60
50
%
nsec
tIf
FSR, FST, BCLK, PCMR1, PCMR2, PUI, PCMMS ---
input fall time
---
50
nsec
TBCLK=1/fBCLK
DC
tIr
tIf
BCLK
1
2
3
4
5
6
7
8
TFS=1/fFS
FSR
FST
tWS
tj
FIGURE 8.4: PCM SYNCHRONIZATION PARAMETERS
Publication Release Date: May 2003
Revision 0.35
- 17 -
W682510/W682310
TABLE 8.2: PCM TIMING PARAMETERS
DESCRIPTION
MIN
TBCLK ---
SYMBOL
TYP
MAX UNIT
tWS
FST, FSR Pulse Width
100
µ
sec
tXS
tSX
tSD
tXD1
tXD2
tXD3
tRS
tSR
tDS
BCLK low to FST high setup time
FST high to BCLK low hold time
100
100
20
20
20
---
---
---
---
---
---
---
---
---
---
---
---
---
---
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
Ohm
pF
PCMT1, PCMT2 output delay; Cl = 100 pF
PCMT1, PCMT2 output delay; Cl = 100 pF
PCMT1, PCMT2 output delay; Cl = 100 pF
PCMT1, PCMT2 output delay; Cl = 100 pF
BCLK low to FSR high setup time
FSR high to BCLK low hold time
PCMR1, PCMR2 Data in setup time
PCMR1, PCMR2 Data in hold time
PCMT1, PCMT2 Pull-up resistor
200
200
200
200
---
---
---
---
---
20
100
100
100
100
500
---
tDH
RTL
CTL
PCMT1, PCMT2 Load capacitance
100
tXS
BCLK
FST
1
2
3
4
5
6
7
8
9
10
11
tSX
tXD2
tXD3
tWS
tSD
PCMT1
PCMT2
MSB D6
D5
D4
D3
D2
D1
D0
tXD1
Figure 8-5a. Transmit Timing
tRS
BCLK
FSR
1
2
3
4
5
6
7
8
9
10
11
tSR
tWS
tDS tDH
PCMR1
PCMR2
MSB D6
D5
D4
D3
D2
D1
D0
Figure 8-5b. Receive Timing
FIGURE 8.5 PCM TIMING PARAMETERS
- 18 -
W682510/W682310
9. ABSOLUTE MAXIMUM RATINGS
TABLE 9.1: ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)
Condition
Junction temperature
Value
1500C
Storage temperature range
Voltage Applied to any pin
-650C to +1500C
(VSS - 0.3V) to (VDD + 0.3V)
(VSS – 1.0V) to (VDD + 1.0V)
3000C
Voltage applied to any pin (Input current limited to +/-20 mA)
Lead temperature (soldering – 10 seconds)
VDD - VSS
-0.5V to +6V
Note
: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely
affect the life and reliability of the device. Functional operation is not implied at these
conditions.
TABLE 9.2: OPERATING CONDITIONS (PACKAGED PARTS)
Condition
Industrial operating temperature
Value
-400C to +850C
Supply voltage (VDD) W682510 5V
Supply voltage (VDD) W682310 3V
Ground voltage (VSS)
+4.5V to +5.5V
+2.7V to +3.8V
0V
Publication Release Date: May 2003
Revision 0.35
- 19 -
W682510/W682310
10. ELECTRICAL CHARACTERISTICS
10.1. GENERAL PARAMETERS W682510 4.5V – 5.5V
Symbol Parameters
Conditions
Min (2)
0.0
Typ (1)
Max (2)
0.8
Units
VIL
Input Low Voltage
V
V
V
VIH
VOL
Input High Voltage
2.2
VDD
PCMT1, PCMT2 Output
Low Voltage
0.0
0.2
7
0.4
R
pullup>500 Ω
VDD Current (Operating) -
ADC + DAC
14
mA
IDD
No Load, No Signal
ISB
IPD
IIL
VDD Current (Standby)
FST or BCLK =OFF; PUI=VDD
PUI= Vss
800
1
1300
10
µA
µA
µA
µA
µA
VDD Current (Power Down)
Input Low Leakage Current VSS<VIN<VDD
Input High Leakage Current VSS<VIN<VDD
0.5
2
IIH
VSS<PCMT<VDD
High Z State
IOL
PCMT1, PCMT2 Output
Leakage Current
+/-10
CIN
Digital Input Capacitance
5
10
15
pF
pF
COUT
PCMT1, PCMT2 Output PCMT1, PCMT2 = High Z
Capacitance
1. Typical values: TA = 25°C, VDD = 5.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
10.2. GENERAL PARAMETERS W682310 2.7V – 3.8V
Symbol Parameters
Conditions
Min (2)
0.0
Typ (1)
Max (2)
0.16xVDD
VDD
Units
VIL
Input Low Voltage
V
V
V
VIH
VOL
Input High Voltage
0.45xVDD
0.0
PCMT1, PCMT2 Output
Low Voltage
0.2
7.4
0.4
R
pullup>500 Ω
VDD Current (Operating) -
ADC + DAC
14
mA
IDD
No Load, No Signal
ISB
IPD
IIL
VDD Current (Standby)
FST or BCLK =OFF; PUI=VDD
PUI= Vss
700
1
2000
10
µA
µA
µA
VDD Current (Power Down)
Input Low Leakage Current VSS<VIN<VDD
0.5
- 20 -
W682510/W682310
Symbol Parameters
Conditions
Min (4)
Typ (3)
Max (4)
2
Units
µA
IIH
Input High Leakage Current VSS<VIN<VDD
VSS<PCMT<VDD
High Z State
IOL
PCMT1, PCMT2 Output
Leakage Current
+/-10
µA
CIN
Digital Input Capacitance
5
10
15
pF
pF
COUT
PCMT1, PCMT2 Output PCMT1, PCMT2 = High Z
Capacitance
1. Typical values: TA = 25°C, VDD = 3.0 V
2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all
specifications are 100 percent tested.
Publication Release Date: May 2003
- 21 -
Revision 0.35
W682510/W682310
10.3. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS
W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
;
;
PARAMETER
SYM.
CONDITION
TYP.
TRANSMIT (A/D) RECEIVE (D/A)
MIN. MAX. MIN. MAX.
--- --- --- ---
UNIT
Reference Level LABS
Out
0 dBm0 = +0.8 dBm @
0.850
VRMS
600Ω load 1020 Hz
W682510 5V
Reference Level T0TLP
In
W682510 5V
1020 Hz
0.850
0.500
0.350
---
---
---
---
---
---
---
---
---
---
---
---
VRMS
VRMS
VRMS
Reference Level LABS
Out
W682310 3V
0 dBm0 = -3.8 dBm @
1200Ω load 1020 Hz
Reference Level T0TLP
Out
1020 Hz
W682310 3V
Max. Transmit
Level In
TXMAX
TXMAX
GABS
1.732
1.726
---
---
---
---
---
---
---
---
VPK
VPK
3.17 dBm0 for µ-Law
3.14 dBm0 for A-Law
W682510 5V
Max. Transmit
Level In
0.712
0.708
---
---
---
---
---
---
---
---
VPK
VPK
3.17 dBm0 for µ-Law
3.14 dBm0 for A-Law
W682310 3V
Absolute Gain
(0 dBm0 @
1020 Hz;
0 dBm0 @ 1020 Hz;
0
-0.2
+0.2
-0.2
+0.2
dB
TA=+25°C
TA=+25°C)
Absolute Gain
variation with
Temperature
GABST
0
-0.08
-0.1
+0.08
+0.1
-0.08
-0.1
+0.08
+0.1
dB
dB
TA=0°C to TA=+70°C
TA=-40°C to TA=+85°C
Frequency
Response,
Relative to
0dBm0 @ 1020
Hz
GRTV
15 Hz
50 Hz
60 Hz
200 Hz
300 to 3000 Hz
3300 Hz
3400 Hz
3600 Hz
4000 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
-1.5
-0.20
-0.50
-0.8
---
-40
-30
-20
-0.4
+0.20
+0.20
0
0
-14
-32
-0.5
-0.5
-0.5
-0.5
-0.20
-0.50
-0.8
---
0
0
0
0
+0.20
+0.20
0
0
-14
-30
---
---
---
---
4600 Hz to 100 kHz
- 22 -
W682510/W682310
Gain Variation
vs. Level Tone
(1020 Hz
relative to –10
dBm0)
GLT
+3 to –40 dBm0
-40 to –50 dBm0
-50 to –55 dBm0
---
---
---
-0.3
-0.5
-1.2
+0.3
+0.5
+1.2
-0.3
-0.5
-1.2
+0.3
+0.5
+1.2
DB
Publication Release Date: May 2003
Revision 0.35
- 23 -
W682510/W682310
10.4. ANALOG DISTORTION AND NOISE PARAMETERS
W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
;
;
PARAMETER
SYM.
CONDITION
TRANSMIT (A/D)
RECEIVE (D/A)
MIN. TYP. MAX.
34
UNIT
MIN. TYP. MAX.
Total Distortion vs.
Level Tone (1020 Hz,
µ-Law, C-Message
Weighted)
+3 dBm0
0 dBm0 to -30 dBm0
-40 dBm0
-45 dBm0
+3 dBm0
0 dBm0 to -30 dBm0
-40 dBm0
-45 dBm0
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8400 Hz to 100000 Hz
300 to 3000 Hz
36
36
29
25
36
36
29
25
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
-47
---
---
---
---
---
---
---
---
---
---
---
---
---
dBC
DLTµ
36
30
25
34
36
30
25
---
---
---
---
---
---
---
---
---
---
---
-30
-40
-30
-47
Total Distortion vs.
Level Tone (1020 Hz,
A-Law, Psophometric
Weighted)
DLTA
dBp
dB
Spurious Out-Of-Band DSPO
at RO- (300 Hz to
3400 Hz @ 0dBm0)
Spurious In-Band (700 DSPI
Hz to 1100 Hz @
0dBm0)
Intermodulation
Distortion (300 Hz to
3400 Hz –4 to –21
dBm0
dB
dB
DIM
Two tones
---
---
-41
---
---
-41
Crosstalk (1020 Hz @ DXT
0dBm0)
---
---
---
---
-75
-75
---
---
---
---
-75
-75
dBm0
dBm0
Channel to Channel
Crosstalk (1020 Hz @
0dBm0)
DXTCH
Absolute Group Delay
1600 Hz
---
---
360
---
---
240
µsec
µsec
τABS
τD
Group Delay
500 Hz
600 Hz
1000 Hz
2600 Hz
2800 Hz
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
380
130
130
750
5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
750
370
120
120
750
13
Distortion (relative to
group delay @ 1200
Hz)
Idle Channel Noise
NIDL
dBrnc
dBm0p
µ-Law; C-message
A-Law; Psophometric
-69
-79
- 24 -
W682510/W682310
10.5. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS
W682510: VDD=5V ±10%; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
W682310: VDD=2.7V to 3.8V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VREF
;
;
PARAMETER
AI1, AI2 Input Offset Voltage
AI1, AI2 Input Resistance
AO1-, AO2- Output Amplitude
SYM.
CONDITION
MIN.
TYP.
MAX.
UNIT.
mV
VOFF,AI
Unity Gain
---
10
0
---
±20
RIN,AI
VAD
AI1, AI2 to VREF
---
---
---
MΩ
W682510
W682310
3.4
1.4
---
Vpp
AO1-, AO2- Load Resistance
AO1-, AO2- Load Capacitance
RO1, RO2 Load Resistance
RLOAD
CLOAD
RLOAD
20
---
---
---
kΩ
pF
kΩ
AO1-, AO2-
W682510
W682310
RO1, RO2
W682510
W682310
RO to VREF
---
30
---
0.6
1.2
---
RO1, RO2 Load Capacitance
RO1, RO2 Output Amplitude
CLOAD
VORO
---
---
50
pF
---
3.4
2.0
Vpp
RO1, RO2 Output Offset Voltage
Signal Ground Voltage to VSSA
VOFF,RO
VREF
---
---
mV
V
±100
V
--
--
DD/2 – 0.1
VDD/2
VDD/2+ 0.1
Power Supply Rejection Ratio (0 to PSRR
100 kHz to VDD, C-message)
Transmit; 50 mVpp
Receive; 50 mVpp
40
40
---
---
dBC
Publication Release Date: May 2003
Revision 0.35
- 25 -
W682510/W682310
10.6. DIGITAL I/O
TABLE 10.61: -LAW ENCODE DECODE CHARACTERISTICS
µ
Normalized
Normalized
Encode
Decision
Levels
Digital Code
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
0
Step
Step
Step
8159
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
8031
:
7903
:
4319
0
0
1
1
0
0
1
1
1
1
1
1
1
1
4191
:
4063
:
2143
2079
:
2015
:
1055
1023
:
991
:
511
495
:
479
:
239
231
:
223
:
103
99
:
95
:
35
33
:
31
:
3
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
2
0
Notes:
Sign bit = 0 for negative values, sign bit = 1 for positive values
- 26 -
W682510/W682310
TABLE 10.62: A-LAW ENCODE DECODE CHARACTERISTICS
Normalized
Digital Code
Normalized
Encode
Decision
Levels
Decode
Levels
D7
D6
D5
D4
D3
D2
D1
D0
Sign
Chord
Chord
Chord
Step
Step
Step
Step
4096
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
4032
:
3968
:
2048
0
0
0
0
0
0
0
2112
:
2048
:
1088
1056
:
1024
:
544
528
:
512
:
272
264
:
256
:
136
132
:
128
:
68
66
:
64
:
2
0
1
Notes:
1. Sign bit = 0 for negative values, sign bit = 1 for positive values
2. Digital code includes inversion of all even number bits
Publication Release Date: May 2003
Revision 0.35
- 27 -
W682510/W682310
TABLE 10.63: PCM CODES FOR ZERO AND FULL SCALE
A-Law
Chord bits
(D6,D5,D4)
010
-Law
µ
Level
Sign bit
Chord bits
Step bits
Sign bit
Step bits
(D3,D2,D1,D0)
1010
(D7)
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
+ Full Scale
+ Zero
- Zero
1
1
0
0
000
111
111
000
0000
1111
1111
0000
1
1
0
0
101
101
010
0101
0101
1010
- Full Scale
TABLE 10.64: PCM CODES FOR 0DBM0 OUTPUT
A-Law
Chord bits
(D6,D5,D4)
011
-Law
µ
Sample
Sign bit Chord bits
Step bits
Sign bit
Step bits
(D3,D2,D1,D0)
0100
(D7)
(D6,D5,D4) (D3,D2,D1,D0)
(D7)
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
001
000
000
001
001
000
000
001
1110
1011
1011
1110
1110
1011
1011
1110
0
0
0
0
1
1
1
1
010
010
011
011
010
010
011
0001
0001
0100
0100
0001
0001
0100
- 28 -
W682510/W682310
11. TYPICAL APPLICATION CIRCUIT
VDD
Power Up
Input
Channel
Analog
Input
W682510/W2310
0.1 F
µ
1 VREF
AI2 24
AO2- 23
AO1- 22
AI1 21
NC 20
2 RO2
3 NC
Channel 2
Analog
Output
Channel
Analog
Input
4 RO1
5 PUI
6 PCMMS
7 NC
A/µ 19
VSSA 18
NC 17
Channel 1
Analog
Output
8 VDD
Bit Clock Input
1 F
µ
9 VSSD
BCLK 16
FST 15
10 FSR
PCM 2 Ch Serial Input
Frame Sync Input
11 PCMR2
12 PCMR1
PCMT2 14
PCMT1 13
PCM 2 Ch. Serial Output
Ω
SOP
1k
VDD
FIGURE 11.1: APPLICATION CIRCUIT FOR SERIAL MODE OPERATION
Publication Release Date: May 2003
Revision 0.35
- 29 -
W682510/W682310
VDD
Power Up
Input
W682510/W682310
0.1
F
µ
1 VREF
2 RO2
3 NC
AI2 24
AO2 - 23
AO1 - 22
AI1 21
Analog Output
Channel 1
Analog
Input
Channel 2
4 RO1
5 PUI
Channel 1 Analog Output
NC 20
6 PCMMS
7 NC
A/ µ 19
VSSA 18
NC 17
8 VDD
Bit Clock Input
1 F
µ
9 VSSD
BCLK 16
FST 15
PCM Ch2
Serial Output
10 FSR
PCM Ch2 Serial Input
PCM Ch1 Serial Input
11 PCMR2
12 PCMR1
PCMT2 14
PCMT1 13
PCM Ch1
Serial Output
SOP
Frame Sync Input
Ω
Ω
1k
1k
VDD
FIGURE 11.2: APPLICATION CIRCUIT FOR PARALLEL MODE OPERATION
- 30 -
W682510/W682310
12. PACKAGE DRAWING AND DIMENSIONS
12.1. 20L (PDIP) PLASTIC DUAL INLINE PACKAGE DIMENSIONS (W682510 ONLY)
D
2
1
1
E
1
1
E
S
c
1
2
A
A
A
L
Base
Seating
B
e1
eA
á
B 1
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
-
NOM.
-
MAX.
4.45
-
MIN.
NOM.
-
MAX.
0.175
-
A
A1
A2
B
-
0.25
3918
0.41
1.47
0.20
-
-
0.010
0.125
0.016
0.058
0.008
-
-
3.30
0.46
1.52
0.25
20.06
7.62
6.35
2.54
3.30
-
3.43
0.56
1.63
0.36
26.42
7.87
6.48
2.79
3.56
15º
0.130
0.018
0.060
0.010
1.026
0.300
0.250
0.100
0.130
-
0.135
0.022
0.064
0.014
1.046
0.310
0.255
0.110
0.140
15º
B1
c
D
E
7.37
6.22
2.29
3.05
0º
0.290
0.245
0.090
0.120
0º
E1
e1
L
á
eA
S
8.51
-
9.02
-
9.53
1.91
0.335
-
0.355
-
0.375
0.075
Publication Release Date: May 2003
Revision 0.35
- 31 -
W682510/W682310
12.2. 20L SSOP – 209 MIL SHRINK SMALL OUTLINE PACKAGE DIMENSIONS
SEATING
Y
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
-
NOM.
MAX.
2.00
-
MIN.
-
NOM.
MAX.
A
A1
A2
b
-
-
0.079
-
0.05
1.65
0.22
0.09
6.90
5.00
7.40
-
-
0.002
0.065
0.009
0.004
0.272
0.197
0.291
-
-
0.069
-
1.75
-
1.85
0.38
0.25
7.50
5.60
8.20
-
-
0.015
0.010
0.295
0.220
0.323
-
c
-
-
D
7.20
5.30
7.80
0.65
0.75
1.25
-
0.283
0.209
0.307
0.0256
0.030
0.050
-
E
HE
e
L
0.55
-
0.95
-
0.021
-
0.037
-
L1
Y
-
0.10
8º
-
0.004
8º
0
0º
-
0
-
- 32 -
W682510/W682310
12.3. 24 SOP – 300 MIL
c
ꢂꢃ
ꢀꢁ
E
H
ꢀ
L
ꢀ
ꢂꢀ
O
D
0.25
A
Y
SEATINGPLANE
e
GAUGEPLANE
A1
b
DIMENSION (MM)
DIMENSION (INCH)
SYMBOL
MIN.
2.35
0.10
0.33
0.23
7.40
15.20
MAX.
MIN.
0.093
0.004
0.013
0.009
0.291
0.598
MAX.
0.104
0.012
0.020
0.013
0.299
0.614
A
A1
b
2.65
0.30
0.51
0.32
7.60
15.60
c
E
D
e
1.27 BSC
0.050 BSC
HE
Y
10.00
10.65
0.10
1.27
8º
0.394
0.419
0.004
0.050
8º
L
0.10
0º
0.016
0
0
Publication Release Date: May 2003
Revision 0.35
- 33 -
W682510/W682310
13. ORDERING INFORMATION
Product Number Descriptor Key
W682510 _
Package Type:
Product Family
W682510 Product
E
=
=
=
20-Lead Plastic Dual Inline Package (PDIP)
24-Lead Plastic Small Outline Package (SOP)
20-Lead Plastic Small Outline Package (SSOP)
S
R
When ordering W682510 series devices, please refer to the following part numbers.
Part Number
W682510E
W682510S
W682510R
W682310 _
Product Family
W682310 Product
Package Type:
S
=
=
24-Lead Plastic Small Outline Package (SOP)
20-Lead Plastic Small Outline Package (SSOP)
R
When ordering W682310 series devices, please refer to the following part numbers.
Part Number
W682310S
W682310R
For the latest product information, access Winbond’s worldwide website at
HTTP://WWW.WINBOND-USA.COM
- 34 -
W682510/W682310
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
Preliminary Specifications
Updates
0.31
0.34
0.35
Mar 2003
Apr. 2003
May 2003
All
Frequency response updated
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
CA 95134, U.S.A.
27F, 299 Yan An W. Rd. Shanghai,
200336 China
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.winbond-usa.com/
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respectivePowunberlsi.cation Release Date: May 2003
This product incorporates SuperFlash® technology licensed From SST.
- 35 -
Revision 0.35
相关型号：
©2020 ICPDF网 联系我们和版权申明