W741C260_技术文档

W741C260

4-BIT MICROCONTROLLER

Table of Contents--

GENERAL DESCRIPTION.........................................................................................................................2

FEATURES.................................................................................................................................................2

PIN CONFIGURATION...............................................................................................................................3

PIN DESCRIPTION.....................................................................................................................................4

BLOCK DIAGRAM......................................................................................................................................5

FUNCTIONAL DESCRIPTION ...................................................................................................................6

ABSOLUTE MAXIMUM RATINGS .............................................................................................................34

DC CHARACTERISTICS............................................................................................................................35

AC CHARACTERISTICS............................................................................................................................36

PAD ASSIGMENT & POSITIONS ..............................................................................................................37

TYPICAL APPLICATION CIRCUIT.............................................................................................................39

INSTRUCTION SET TABLE.......................................................................................................................40

PACKAGE DIMENSION.............................................................................................................................90

Publication Release Date: March 1998

- 1 -

Revision A3

W741C260

GENERAL DESCRIPTION

The W741C260 is a high-performance 4-bit microcontroller (mC) with an LCD driver. The device

contains a 4-bit ALU, two 8-bit timers, two dividers, a 32 ´ 4 LCD driver, and five 4-bit I/O ports

(including 1 output port to drive the LEDs). There are also five interrupt sources and 8-level

subroutine nesting for interrupt applications. The W741C260 has two power reduction modes, hold

mode and stop mode, which help to minimize power dissipation.

The W741C260 has two oscillator circuits and can work in dual-clock or single-clock operation mode.

It is suitable for remote controllers, watches and clocks, speech synthesis LSI controllers, hand-held

games and other products.

FEATURES

· Operating voltage: 2.2V to 5.5V (LCD drive voltage: 3.0V, or 4.5V)

· Operating frequency up to 4 MHz

· Crystal/RC oscillation circuit selectable by code option for system clock

· 32.768 KHz crystal oscillation circuit for sub-oscillator

· High-frequency clock (400 KHz to 4 MHz) or low-frequency clock (32.768 KHz) for crystal mode;

selectable by code option

· Memory

- 2048 ´ 16 bit program ROM (including 2K ´ 4 bit look-up table)

- 128 ´ 4 bit data RAM (including 16 working registers)

- 32 ´ 4 LCD data RAM

· 21 input/output pins

- Ports for input only: 2 ports/8 pins

- Input/output ports: 2 ports/8 pins

- Port for output only: 1 port /4 pins (high sink current to drive LEDs)

- MFP output pin: 1 pin (MFP)

· Power-down mode

- Hold function: no operation (except for oscillator)

- Stop function: no operation (including main oscillator)

· Five types of interrupts

- Four internal interrupts (Divider 0, Divider 1, Timer 0, Timer 1)

- One external interrupt (Port RC)

· LCD driver output

- 32 segment ´ 4 common

- Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) driving mode can be

selected

- LCD driver output pins can be used as DC output ports; selectable by code option

- 2 -

W741C260

· MFP output pin

- Output is software selectable as modulating or nonmodulating frequency

- Works as frequency output specified by Timer 1

· Two built-in 14-bit clock frequency divider circuit (divider 0 and divider 1)

· Two built-in 8-bit programmable countdown timers

- Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected

- Timer 1: includes an auto-reload function; and one of two internal clock frequencies (FOSC or

FOSC/64) can be selected or falling edge of pin RC.0 can be selected (output through MFP pin)

· Built-in 18/14-bit watchdog timer selectable for system reset

· Powerful instruction set: 118 instructions

· 8-level subroutine (include interrupt) nesting

· Up to 1 mS instruction cycle (with 4 MHz operating frequency)

· Packaged in 80-pin QFP

PIN CONFIGURATION

X

O

U

T

1

X

O

U

T

2

S

E

G

3

S

E

G

3

S

E

G

2

S

E

G

2

X

I

X

I

V

D

1

V

D

2

V

D

3

/

R

A

1

R

A

0

M

F

V

D

H

1

D

H

2

R

E

S

N

C

N

C

N

1

N

C

N

C

N

2

N

C

N

C

P

1

0

9

8

64

62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

SEG27

SEG26

SEG25

SEG24

SEG23

SEG22

SEG21

SEG20

SEG19

SEG18

SEG17

SEG16

SEG15

SEG14

SEG13

SEG12

RA2

40

39

38

37

36

35

34

33

32

31

30

RA3

RB0

RB1

RB2

RB3

RC0

RC1

RC2

RC3

RD0

RD1

RD2

RD3

RE0

RE1

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

N

C

N

C

R

E

2

R

E

3

V

S

N

C

N

C

O

M

3

C

O

M

2

C

O

M

1

C

O

M

0

S

E

G

0

S

E

G

1

S

E

G

2

S

E

G

3

S

E

G

4

S

E

G

5

S

E

G

6

S

E

G

7

S

E

G

8

S

E

G

9

S

E

G

1

S

E

G

1

N

C

0

1

Publication Release Date: March 1998

Revision A3

- 3 -

W741C260

PIN DESCRIPTION

SYMBOL

XIN1

I/O

FUNCTION

I

Input pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

XOUT1

O

Output pin for oscillator.

Connected to crystal or resistor to generate system clock by code option.

Input pin for sub-oscillator. Connected to a 32.768 KHz crystal.

Output pin for sub-oscillator. Connected to a 32.768 KHz crystal.

XIN2

I

XOUT2

RA0- RA3

O

I/O

Input/Output port.

Input/output mode specified by port mode 1 register (PM1).

I/O

I

Input/Output port.

Input/output mode specified by port mode 2 register (PM2).

RB0- RB3

RC0- RC3

4-bit port for input only.

Each pin has an independent interrupt capability.

I

4-bit port for input only.

RD0- RD3

RE0- RE3

O

Output port only.

This port provides high sink current to drive LEDs.

Output pin only.

MFP

O

This pin can output modulating or nonmodulating frequency, or Timer 1

clock output specified by mode register 1 (MR1).

I

System reset pin with pull-high resistor.

RES

O

LCD segment output pins.

SEG0- SEG31

Can also be used as DC output ports specified by code option.

O

LCD common signal output pins.

COM0- COM3

Static

Used

1/2 Duty

Used

1/3 Duty

Used

1/4 Duty

Used

COM0

COM1 Not Used

Used

COM2 Not Used Not Used

Used

COM3 Not Used Not Used Not Used

Used

The LCD alternating frequency can be selected by code option.

Connection terminals for voltage doubler (halver) capacitor.

Positive (+) supply voltage terminal.

DH1, DH2

I

VDD1, VDD2,

VDD3

Refer to Functional Description.

VDD

VSS

I

Positive power supply (+).

Negative power supply (-).

- 4 -

W741C260

BLOCK DIAGRAM

COM0 to COM3

SEG0 to SEG31

VDD1 to 3 DH1 to 2

LCD

DRIVER

RAM

(128 x 4)

RA0 to 3

RB0 to 3

RC0 to 3

RD0 to 3

RE0 to 3

PORT RA

ACC

ALU

ROM

(2048 x 16)

(look_up table

2K x 4)

PORT RB

PORT RC

+1(+2)

PC

PORT RD

PORT RE

Central Control

Unit

IEF

HEF

EVF

PEF

STACK

(8 Levels)

HCF

SEF

MR1

.

PSR0 PR

.

SEL

MFP

MUX

Modulation

Frequency

Pulse

Timer 1

(8-bit)

Timer 0

(8-bit)

Divider 1

(13/14-bit)

VDD

VSS

Watchdog Timer

(4-bit)

Divider 0

(14-bit)

Timing Generator

RES

XIN1 XOUT1 XIN2 XOUT2

Publication Release Date: March 1998

Revision A3

- 5 -

W741C260

FUNCTIONAL DESCRIPTION

Program Counter (PC)

Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses

of the 2048 ´ 16 on-chip ROM containing the program instructions. When the jump or subroutine call

instructions or the interrupt or initial reset conditions are to be executed, the address corresponding to

the instruction will be loaded into the program counter. The format used is shown below.

ITEM

Initial Reset

ADDRESS

000H

INTERRUPT PRIORITY

-

INT 0 (Divider 0)

INT 1 (Timer 0)

INT 2 (Port RC)

INT 4 (Divider 1)

INT 7 (Timer 1)

JP Instruction

004H

1st

2nd

3rd

4th

5th

-

008H

00CH

014H

020H

XXXH

Subroutine Call

-

Stack Register (STACK)

The stack register is organized as 11 bits ´ 8 levels (first-in, last-out). When either a call subroutine or

an interrupt is executed, the program counter will be pushed onto the stack register automatically. At

the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed

to pop the contents of the stack register into the program counter. When the stack register is pushed

over the eighth level, the contents of the first level will be lost. In other words, the stack register is

always eight levels deep.

Program Memory (ROM)

The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 2048

´ 4 bits. The first three quarters of ROM (000H to 5FFH) are used to store instruction codes only, but

the last quarter (600H to 7FFH) can store both instruction codes and the look-up table. Each look-up

table element is composed of 4 bits, so the look-up table can be addressed up to 2048 elements.

There are two registers (TABL and TABH) to be used in look-up table addressing and they are

controlled by MOV TABH, R and MOV TABL, R instructions. When the instruction MOVC R is

executed, the contents of the look-up table location address specified by TABH, TABL and ACC will

be read and transfered to the data RAM. Refer to the instruction table for more details. The

organization of the program memory is shown in Figure 1.

- 6 -

W741C260

16 bits

000H

TABH

TABL

ACC

- x x x x x x x x x y y

2048

address

Offset

0 1 1 x x x x x x x x x

ROM address = 600H + Offset/4

600H

7FFH

This area can be used to store both instruction code

and look-up table

3

2

1

0

Each element (4 bits) of the look-up table

2048 x 16-bit

Figure 1. Program Memory Organization

Data Memory (RAM)

1. Architecture

The static data memory (RAM) used to store data is arranged as 128 ´ 4 bits. The data memory can

be addressed directly or indirectly. The organization of the data memory is shown in Figure 2.

4 bits

00H

:

Working Register

0FH

128

address

7FH

128 x 4-bit

Figure 2. Data Memory Organization

The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers

(WR). The other data memory is used as general memory and cannot operate directly with immediate

data. The relationship between data memory locations and the page register (PAGE) in indirect

addressing mode is described in the next section.

Publication Release Date: March 1998

- 7 -

Revision A3

W741C260

2. Page Register (PAGE)

The page register is organized as a 4-bit binary register. The bit descriptions are as follows:

3

2

1

0

PAGE R/W

R/W

Note: R/W means read/write available.

Bit 3 is reserved.

Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits:

000 = Page 0 (00H- 0FH)

001 = Page 1 (10H- 1FH)

011 = Page 3 (30H- 3FH)

101 = Page 5 (50H- 5FH)

111 = Page 7 (70H- 7FH)

010 = Page 2 (20H- 2FH)

100 = Page 4 (40H- 4FH)

110 = Page 6 (60H- 6FH)

Accumulator (ACC)

The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data

between the memory, I/O ports, and registers.

Arithmetic and Logic Unit (ALU)

This is a circuit which performs arithmetic and logic operations. The ALU provides the following

functions:

· Logic operations: ANL, XRL, ORL

· Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2,

SKB3

· Shift operations: SHRC, RRC, SHLC, RLC

· Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC

After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is

stored in the internal registers. Otherwise CF can be stored or be read out by executing MOVA R, CF

or MOV CF, R.

Clock Generator

The W741C260 provides two oscillation circuits, main-oscillator and sub-oscillator. The main-

oscillator can select the crystal or RC oscillation circuit by option codes to generate the system clock

through external connections. If a crystal oscillator is used, a crystal or a ceramic resonator must be

connected to XIN1 and XOUT1, and a capacitor must be connected if an accurate frequency is

needed. When the oscillator is used, a high-frequency clock (400 KHz to 4 MHz) or low-frequency

clock (32 KHz) can be selected for the system clock by means of option codes. If the RC oscillator is

used, a resistor must be connected to XIN1 and XOUT1, and the high/low frequency clock option

must be selected to suit the operation frequency. The sub-oscillator must be connected to a 32.768

KHz crystal through XIN2 and XOUT2 external pins when the dual-clock operation mode is selected

by option code. The connection is shown in Figure 3. One machine cycle consists of a four-state

system clock sequence and can run up to 1 mS with a 4 MHz system clock.

- 8 -

W741C260

XIN2

XIN1

Resistor

XOUT1

Crystal

32 KHz

or

32 KHz or

XOUT2

400K to 4MHz

Figure 3. Oscillator Configuration

Dual-clock operation

This operation mode is selected by code option. In the dual-clock mode, the clock source of the LCD

frequency selector should be the sub-oscillator clock (32768 Hz) only. But in the single-clock mode,

the clock source of the LCD frequency selector will be Fm or Fm/32 (Fm: main oscillator clock).

In this dual-clock mode, the normal operation is performed by generating the system clock from the

main-oscillator clock (Fm). As required, the slow operation can be performed by generating the

system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow

operation is performed by resetting or setting the bit 0 of the system clock control register (SCR). If

the SCR.0 is reset to 0, the clock source of the system clock generator is the main-oscillator clock; if

the SCR.0 is set to 1, the clock source of the system clock generator is the sub-oscillator clock. In

dual-clock mode, the main-oscillator can stop oscillating when SCR.1 is set to 1. But in the single-

clock mode, the main-oscillator can not be stop from oscillating because the SCR would be disabled

in single-clock mode. Therefore, in sigle-clock mode, the clock source of the system clock generator

is the main-oscillator clock (FOSC = Fm).

When the SCR is set or reset, we must pay attention to the following:

1. X000B ® X011B: Disable the main-oscillator (Fm) should not be done simultaneously with

changing the system clock source (FOSC) from Fm to Fs. The FOSC should be changed first from

Fm to Fs before the main-oscillator (Fm) is disabled. The correct seqence is:

X000B® X001B® X011B.

2. X011B ® X000B: Enabling the main-oscillator (Fm) should not be done simultaneously with

changing the FOSC from Fs into Fm. The main-oscillator (Fm) should be enabled first before a

delay subroutine is called to allow the main-oscillator to oscillate stably. The FOSC can now be

changed from Fs into Fm. The correct sequence is therefore X011B® X001B® delay

subroutine® X000B. The suggested delay for Fm is 20 mS for 455 KHz ceramic resonator and 10

mS for 4 MHz crystal.

We must remember that the X010B state is inhibitive, because it will induce a system shutdown.

The organization of the dual-clock operation mode is shown below.

Publication Release Date: March 1998

- 9 -

Revision A3

W741C260

Mask Option (High/Low Freq.)

HOLD

SCR.0

Fm

XIN1

T1

T2

T3

Fosc

Main Oscillator

Fs

XOUT1

System Clock

Generator

T4

SCR.1

enable/disable

Divider 0

Mask Option (High/Low Freq.)

Fosc/32

Fosc

LCD Frequency

Selector

F

LCD

XIN2

Sub-oscillator

enable/disable

XOUT2

Mask Option

(Single/Dual Clock)

Mask Option (Single/Dual Clock)

INT4

Divider 1

HCF.4

SCR.3 (14/13 bit)

Figure 4. The Dual Clock Operation Mode Control Diagram

Divider

Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts.

When the main oscillator starts action, the divider0 is incremented by each clock (FOSC). When an

overflow occurs, the divider0 event flag is set to 1 (EVF.0 = 1). The interrupt is executed if the

divider0 interrupt enable flag has been set (IEF.0 = 1), and the hold state is terminated if the hold

release enable flag has been set (HEF.0 = 1). The last 4-stage of the divider0 can be reset by

executing a CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the

EVF.0 will be set to 1 periodically at each 500 mS interval.

If the sub-oscillator is enabled, the divider1 is incremented by each clock (Fs). When an overflow

occurs, the divider1 event flag is set to 1 (EVF.4 = 1). The interrupt is executed if the divider1

interrupt enable flag has been set (IEF.4 = 1), and the hold state is terminated if the hold release

enable flag has been set (HEF.4 = 1). There are two time periods (250 mS & 500 mS) that can be

selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected;

when SCR.3 = 1, the 250 mS period time is selected.

Watchdog Timer (WDT)

The watchdog timer (WDT) is organized as a 4-bit up counter and is designed to protect the program

from unknown errors. The WDT is enabled when the corresponding option code bit of the WDT is set

to 1. If the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is

FOSC/1024. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/1024) by executing

the SET PMF, #08H (or CLR PMF, #08H) instruction. The contents of the WDT can be reset by the

instruction CLR WDT. In normal operation, the application program must reset WDT before it

overflows. A WDT overflow indicates that the operation is not under control and the chip will be reset.

The WDT minimun overflow period is 468.75 mS when the system clock (FOSC) is 32 KHz and WDT

clock input is FOSC/1024. When the corresponding option code bit of the WDT is set to 0, and the

WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 4.

- 10 -

W741C260

Divider0

HEF.0

IEF.0

Fosc

Hold mode release (HCF.0)

Divider0 interrupt (INT0)

EVF.0

S

R

Q14

R

Q1 Q2

Q9 Q10 Q11 Q12 Q13

...

Q

R

1. Reset

2. CLR EVF, #01H

3. CLR DIVR0

WDT

PMF.3

Fosc/16384

Fosc/1024

Overflow signal

Qw4

R

System Reset

Qw1 Qw2 Qw3

R

Enable

1. Reset

2. CLR WDT

/Disable

Mask Option

Figure 4. Organization of Divider 0 and Watchdog Timer

Timer/Counter

1. Timer 0 (TM0)

Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into

TM0 by executing the MOV TM0L (TM0H), R or MOV TM0, #I instructions. When the MOV TM0L

(TM0H), R instructions are executed, the TM0 will stop down-counting (if the TM0 is down-counting),

the MR0.3 will be reset to 0, and the specified value is loaded into TM0. If MR0.3 is set to 1, the

event flag 1 (EVF.1) is reset and the TM0 starts to count. When it decrements to FFH, Timer 0 stops

operating and generates an underflow (EVF.1 = 1). The interrupt is executed if the Timer 0 interrupt

enable flag has been set (IEF.1 = 1); and the hold state is terminated if the hold release enable flag 1

has been set (HEF.1 = 1). The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting

MR0.0 to 1 or by resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0

is shown in Figure 5.

If the Timer 0 clock input is FOSC/4, then:

Desired Time 0 interval = (preset value +1) ´ 4 ´ 1/FOSC

If the Timer 0 clock input is FOSC/1024, then:

Desired Time 0 interval = (preset value +1) ´ 1024 ´ 1/FOSC

Preset value: Decimal number of Timer 0 preset value

FOSC: Clock oscillation frequency

Publication Release Date: March 1998

- 11 -

Revision A3

W741C260

1. Reset

2. CLR EVF, #02H

3. Reset MR0.3 to 0

4. MOV TM0L, R or MOV TM0H, R

Disable

Enable

MR0.0

HEF.1

Fosc/1024

Fosc/4

8-bit Binary

Down Counter

(Timer 0)

Hold mode release (HCF.1)

Timer 0 interrupt (INT1)

S

R

Q

IEF.1

EVF.1

4

1. Set MR0.3 to 1

2. MOV TM0, #I

8

1. Reset

2. CLR EVF, #02H

3. Set MR0.3 to 1

4. MOV TM0, #I

MOV TM0H, R

MOV TM0L, R

MOV TM0, #I

Figure 5. Organization of Timer 0

2. Timer 1 (TM1)

Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6. Timer 1 can

be used as a counter to count external events or to output an arbitrary frequency to the MFP pin. The

input clock of Timer 1 can be one of three sources: FOSC/64, FOSC, or an external clock from the

RC.0 input pin. The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At

initial reset, the Timer 1 clock input is FOSC. If an external clock is selected as the clock source of

Timer 1, the content of Timer 1 is decreased by 1 at the falling edge of RC.0. When the MOV TM1L,

R or MOV TM1H, R instruction is executed, the specified data are loaded into the auto-reload buffer

and the TM1 down-counting will be disabled (i.e. MR1.3 is reset to 0). If the bit 3 of MR1 is set

(MR1.3 = 1), the contents of the auto-reload buffer will be loaded into the TM1 down counter, Timer 1

starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the MOV TM1, #I instruction is

executed, the event flag 7 (EVF.7) and MR1.3 are reset and the specified value is loaded into auto-

reload buffer and TM1 by the internal hardware, then the MR1.3 is set, that is the TM1 starts to count

by the hardware. When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and

be auto-reloaded with the specified data, after which it will continue to count down. An interrupt is

executed if the interrupt enable flag 7 has been set to 1 (IEF.7 = 1), and the hold state is terminated if

the hold mode release enable flag 7 is set to 1 (HEF.7 = 1). The specified frequency of Timer 1 can

be delivered to the MFP output pin by programming bit 2 of MR1. Bit 3 of MR1 can be used to make

Timer 1 stop or start counting.

If the Timer 1 clock input is FT, then:

Desired Timer 1 interval = (preset value +1) / FT

Desired frequency for MFP output pin = FT ¸ (preset value + 1) ¸ 2 (Hz)

Preset value: Decimal number of Timer 1 preset value, and

FOSC: Clock oscillation frequency

- 12 -

W741C260

MOV TM1, #I

MOV TM1L, R

MOV TM1H, R

8

Underflow

signal

1. MR1.3 = 1

2. MOV TM1, #I

S

R

Q

EVF.7

4

1. Reset

2. INT 7 accept

3. CLR EVF, #80H

4. Set MR1.3 to 1

Auto-reload buffer

8 bits

MR1.1

External clock

via RC.0

Enable

Disable

5. MOV TM1, #I

F_T

8-bit Binary

Down Counter

(Timer 1)

Fosc/64

Fosc

2

circuit

MFP

output pin

Reset

Set MR1.3 to 1

MOV TM1, #I

MR1.0

MR1.2

MFP signal

1. MR1.3 = 0

Figure 6. Organization of Timer 1

For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will

output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between

the tone frequency and the preset value of TM1 is shown in the table below.

3

4

5

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

Tone

frequency

TM1 preset value &

MFP frequency

C

130.81

138.59

146.83

155.56

164.81

174.61

185.00

196.00

207.65

220.00

233.08

246.94

7CH

75H

6FH

68H

62H

5DH

58H

53H

4EH

49H

45H

41H

131.07

138.84

146.28

156.03

165.49

174.30

184.09

195.04

207.39

221.40

234.05

248.24

261.63

277.18

293.66

311.13

329.63

349.23

369.99

392.00

415.30

440.00

466.16

493.88

3EH

3AH

37H

34H

31H

2EH

2BH

29H

26H

24H

22H

20H

260.06

277.69

292.57

309.13

327.68

372.36

390.09

420.10

443.81

442.81

468.11

496.48

523.25

554.37

587.33

622.25

659.26

698.46

739.99

783.99

830.61

880.00

932.23

987.77

1EH

1CH

1BH

19H

18H

16H

15H

14H

13H

12H

11H

10H

528.51

564.96

585.14

630.15

655.36

712.34

744.72

780.19

819.20

862.84

910.22

963.76

C#

D

T

O

N

E

D#

E

F

F#

G

G#

A

A#

B

Note: Central tone is A4 (440 Hz).

Publication Release Date: March 1998

Revision A3

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W741C260

Mode Register 0 (MR0)

Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control

the operation of Timer 0. The bit descriptions are as follows:

3

2

1

0

MR0

W

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 0 is FOSC/4.

= 1 The internal fundamental frequency of Timer 0 is FOSC/1024.

Bit 1

Bit 2

Reserved

Bit 3 = 0 Timer 0 stops down-counting.

= 1 Timer 0 starts down-counting.

Mode Register 1 (MR1)

Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control

the operation of Timer 1. The bit descriptions are as follows:

3

2

1

0

MR1

W

Note: W means write only.

Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC.

= 1 The internal fundamental frequency of Timer 1 is FOSC/64.

Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock.

= 1 The fundamental frequency source of Timer 1 is the external clock from RC.0 input pin.

Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP output pin.

= 1 The specified frequency of Timer 1 is delivered at the MFP output pin.

Bit 3 = 0 Timer 1 stops down-counting.

= 1 Timer 1 starts down-counting.

- 14 -

W741C260

Interrupts

The W741C260 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and

one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the

range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to

control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF

have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts

are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be

disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold

mode will be released momentarily and interrupt subroutine will be executed. After the RTN

instruction is executed in an interrupt subroutine, the mC will enter hold mode again. The operation

flow chart is shown in Figure 8. The control diagram is shown below.

Initial Reset

EN INT

Enable

MOV IEF, #I

Divider 0

EVF.0

EVF.1

EVF.2

EVF.4

EVF.7

overflow signal

S

Q

R

IEF.0

IEF.1

IEF.2

IEF.4

IEF.7

Timer 0

underflow signal

004H

008H

00CH

014H

020H

Port RC

signal change

Interrupt

Process

Circuit

Interrupt

Vector

Generator

Divider 1

overflow signal

Timer 1

underflow signal

Initial Reset

CLR EVF, #I instruction

Disable

DIS INT instruction

Figure 7. Interrupt Event Control Diagram

Interrupt Enable Flag (IEF)

The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used

to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these

interrupts is accepted, the corresponding to the bit of the event flag will be reset, but the other bits are

unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or

EN INT is executed again. Therefore, to enable these interrupts, the instructions MOV IEF, #I or EN

Publication Release Date: March 1998

- 15 -

Revision A3

W741C260

INT must be executed again. Otherwise, these interrupts can be disabled by executing DIS INT

instruction. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

IEF

w

Note: W means write only.

IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0.

IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0.

IEF.2 = 1 Interrupt 2 is accepted by a signal change on port RC.

IEF.3

Reserved

IEF.4 = 1 Interrupt 0 is accepted by overflow from the Divider 1.

IEF.5 & IEF.6 are reserved.

IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1.

Stop Mode Operation

In stop mode, all operations of the mC cease (excluding the operation of sub-oscillator and divider 1

when the dual-clock operation mode is selected). The mC enters stop mode when the STOP

instruction is executed and exits stop mode when an external trigger is activated (by a falling signal

on the RC port). When the designated signal is accepted, the mC awakens and executes the next

instruction (if the corresponding bits of IEF and PEF have been set, It will enter the interrupt service

routine after stop mode released). To prevent erroneous execution, the NOP instruction should follow

the STOP command.

Stop Mode Wake-up Enable Flag for Port RC (SEF)

The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3).

Before port RC may be used to make the device exit the stop mode, the content of the SEF must be

set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows:

3

2

1

0

SEF

w

Note: W means write only.

SEF 0 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.0.

SEF 1 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.1.

SEF 2 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.2.

SEF 3 = 1 Device will exit stop mode when falling edge signal is applied to pin RC.3.

- 16 -

W741C260

Hold Mode Operation

In hold mode, all operations of the mC cease, except for the operation of the oscillator, timer, divider

and LCD driver. The mC enters hold mode when the HOLD instruction is executed. The hold mode

can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1 or the RC

port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the

hold mode release conditions. For more details, refer to the instruction-set table and the following flow

chart.

Divider 0, Divider 1,Timer 0

Timer1, Signal Change on

Port RC

In

HOLD

Mode?

Yes

No

Interrupt

Enable?

Interrupt

Enable?

Yes

No

IEF

Flag Set?

IEF

Flag Set?

Yes

Reset EVF.n Flag

Execute

Interrupt Service Routine

Reset EVF.n Flag

Execute

Interrupt Service Routine

HEF

Flag Set?

No

Yes

(Note)

Disable interrupt

PC <- (PC+1)

Disable interrupt

HOLD

Note : The bit of EVF corresponding to the interrupt request signal will be reset.

Figure 8. Hold Mode and Interrupt Operation Flow Chart

Publication Release Date: March 1998

Revision A3

- 17 -

W741C260

Hold Mode Release Enable Flag (HEF)

The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The

HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I

instruction. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

HEF

w

Note: W means write only.

HEF.0 = 1 Overflow from the Divider 0 causes hold mode to be released.

HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.

HEF.2 = 1 Signal change on port RC causes hold mode to be released.

HEF.3

Reserved

HEF.4 = 1 Overflow from the Divider 1 causes hold mode to be released.

HEF.5 & HEF.6 are reserved.

HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.

Port Enable Flag (PEF)

The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be

used to release the hold mode or preform interrupt function, the content of the PEF must be set first.

The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:

3

2

1

0

PEF

w

Note: W means write only.

PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.

PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.

PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.

PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.

Hold Mode Release Condition Flag (HCF)

The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It

indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The

HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF

bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset

by the CLR EVF,#I (EVF.n = 0) or MOV HEF,#I (HEF.n = 0) instructions. When EVF or HEF have

been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

HCF

R

Note: R means read only.

- 18 -

W741C260

HCF.0 = 1 Hold mode was released by overflow from the Divider0.

HCF.1 = 1 Hold mode was released by underflow from the Timer 0.

HCF.2 = 1 Hold mode was released by a signal change on port RC

HCF.3

Reservsd

HCF.4 = 1 Hold mode was released by overflow from the Divider 1.

HCF.5 = 1 Hold mode was released by underflow from the Timer 1.

HCF.6 & HCF.7 are reserved.

Event Flag (EVF)

The event flag is organized as an 8-bit binary register (EVF0 to EVF7). It is set by hardware and reset

by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows:

7

6

5

4

3

2

1

0

EVF

R

Note: R means read only.

EVF.0 = 1 Overflow from Divider 0 occurred.

EVF.1 = 1 Underflow from Timer 0 occurred.

EVF.2 = 1 Signal change on port RC occurred.

EVF.3

Reserved

EVF.4 = 1 Overflow from Divider 1 occurred.

EVF.5 & EVF.6 are reserved.

EVF.7 = 1 Underflow from Timer 1 occurred.

Parameter Flag (PMF)

The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled

by the SET PMF, #I or CLR PMF, #I instruction. The bit descriptions are as follows:

3

2

1

0

PMF

W

Note: W means write only.

Bit 0, Bit1, Bit2

Reserved

Bit 3 = 0 The fundamental frequency of the watchdog timer is FOSC/1024.

= 1 The fundamental frequency of the watchdog timer is FOSC/16384.

Publication Release Date: March 1998

Revision A3

- 19 -

W741C260

Port Mode 0 Register (PM0)

The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used

to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction.

The bit descriptions are as follows:

3

2

1

0

PM0

w

Note: W means write only.

Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type.

Bit 1 = 0 RB port is CMOS output type. Bit 0 = 1 RB port is NMOS open drain output type.

Bit 2 = 0 RC port pull-high resistor is disabled.

= 1 RC port pull-high resistor is enabled.

Bit 3 = 0 RD port pull-high resistor is disabled.

= 1 RD port pull-high resistor is enabled.

Port Mode 1 Register (PM1)

The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used

to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit

descriptions are as follows:

3

2

1

0

PM1

w

Note: W means write only.

Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin

Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin

Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin

Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin

At initial reset, port RA is input mode (PM1 = 1111B).

Port Mode 2 Register (PM2)

The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used

to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit

descriptions are as follows:

3

2

1

0

PM2

w

Note: W means write only.

Bit 0 = 0 RB.0 works as output pin; Bit 0 = 1 RB.0 works as input pin

- 20 -

W741C260

Bit 1 = 0 RB.1 works as output pin; Bit 1 = 1 RB.1 works as input pin

Bit 2 = 0 RB.2 works as output pin; Bit 2 = 1 RB.2 works as input pin

Bit 3 = 0 RB.3 works as output pin; Bit 3 = 1 RB.3 works as input pin

At initial reset, the port RB is input mode (PM2 = 1111B).

Reset Function

The W741C260 is reset either by a power-on reset or by using the external RES pin. The initial state

of the W741C260 after the reset function is executed is described below.

Program Counter (PC)

TM0, TM1

000H

Reset

MR0, MR1, PM0, PAGE, PMF registers

PM1, PM2 registers

Reset

Set (1111B)

Reset

PSR0 register

IEF, HEF, PEF, SEF, HCF, EVF flags

Timer 0 input clock

Reset

FOSC/4

FOSC

Timer 1 input clock

MFP output

Low

Input/output ports RA, RB

Output port RE

Input mode

High

RA & RB ports output type

RC & RD ports pull-high resistors

Input clock of the watchdog timer

LCD display

CMOS type

Disable

FOSC/1024

OFF

Segment output mode

LCD drive output

Publication Release Date: March 1998

Revision A3

- 21 -

W741C260

Input/Output Ports RA, RB

Port RA consists of pins RA.0 to RA.3 and port RB consists of pins RB.0 to RB.3. At initial reset,

input/output ports RA and RB are both in input mode. When RA and RB are used as output ports,

CMOS or NMOS open drain output type can be selected by the PM0 register. Each pin of port RA or

RB can be specified as input or output mode independently by the PM1 and PM2 registers. The

MOVA R, RA or MOVA R, RB instructions operate the input functions and the MOV RA, R or MOV

RB, R operate the output functions. For more details, refer to the instruction table and Figure 9.

Input/Output Pin of the RA(RB)

V_DD

PM0.0 (or PM0.1)

Output

Buffer

I/O PIN

RA.n(RB.n)

Enable

DATA

BUS

PM1.n

(or PM2.n)

MOV RA, R

(or MOV RB, R)

Instruction

Enable

MOVA R, RA

(or MOVA R, RB)

instruction

Figure 9. Architecture of Input/Output Pins

Input Ports RC, RD

Port RC consists of pins RC.0 to RC.3, and port RD consists of pins RD.0 to RD.3. Each pin of port

RC and port RD can be connected to a pull-up resistor, which is controlled by the port mode 0 register

(PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the

specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status

register 0 (PSR0) record the signal changing status on the port RC. PSR0 can be read out and

cleared by the MOVA R, PSR0, and CLR PSR0 instructions. Refer to Figure 10 and the instruction

table for more details. The RD port is used as input port only, it has no hold mode release or interrupt

functions.

- 22 -

W741C260

DATA BUS

PEF.0

PM0.2

PSR0.0

D

ck

Q

Signal

change

detector

R

RC.0

RC.1

HEF.2

EVF.2

PEF.1

PEF.2

PEF.3

D

ck

Q

HCF.2

INT 2

PSR0.1

PSR0.2

PSR0.3

D

ck

Q

Signal

change

detector

R

IEF.2

PM0.2

D

ck

Signal

change

detector

CLR EVF, #I

Reset

RC.2

RC.3

D

ck

Signal

change

detector

Reset

MOV PEF, #I

CLR PSR0

SEF.0

SEF.1

SEF.2

SEF.3

Falling

edge

detector

Falling

edge

detector

Wake up from STOP mode

Falling

edge

detector

Falling

edge

detector

Figure 10. Architecture of Input Ports RC

Output Port RE

When the MOV RE, R instruction is executed, the data in the RAM will be output to port RE and it

provides a high sink current to drive LEDs.

Port Status Register 0 (PSR0)

Port status register 0 is organized as 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or

cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows:

3

2

1

0

PSR0

R

Note: R means read only.

Bit 0 = 1 Signal change on RC.0

Bit 1 = 1 Signal change on RC.1

Bit 2 = 1 Signal change on RC.2

Bit 3 = 1 Signal change on RC.3

Publication Release Date: March 1998

Revision A3

- 23 -

W741C260

MFP Output Pin (MFP)

The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is

determined by mode register 1 (MR1). The organization of MR1 is shown in Figure 6. When bit 2 of

MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal

from among DC, 4096 Hz, 2048 Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz,

2 Hz, or 1 Hz (when using a 32.768 KHz system clock). The MOV MFP, #I instruction is used to

specify the modulation output combination. The data specified by the 8-bit operand and the MFP

output pin are shown as below:

(Fosc = 32.768 KHz)

R7 R6

R5

0

1

0

1

0

1

0

1

R4

0

1

0

1

0

1

0

1

0

R3

0

1

0

1

0

1

0

1

0

R2

0

1

0

1

0

1

0

1

0

R1

0

1

0

1

0

1

0

1

0

R0

0

1

0

1

0

1

0

1

0

FUNCTION

Low level

128 Hz

64 Hz

0 0

8 Hz

4 Hz

2 Hz

1 Hz

High level

128 Hz

64 Hz

0 1

1 0

1 1

8 Hz

4 Hz

2 Hz

1 Hz

2048 Hz

2048 Hz * 128 Hz

2048 Hz * 64 Hz

2048 Hz * 8 Hz

2048 Hz * 4 Hz

2048 Hz * 2 Hz

2048 Hz * 1 Hz

4096 Hz

4096 Hz * 128 Hz

4096 Hz * 64 Hz

4096 Hz * 8 Hz

4096 Hz * 4 Hz

4096 Hz * 2 Hz

4096 Hz * 1 Hz

- 24 -

W741C260

LCD Controller/Driver

The W741C260 can directly drive an LCD with 32 segment output pins and 4 common output pins for

a total of 32 ´ 4 dots. Option codes can be used to select one of five options for the LCD driving

mode: static, 1/2 bias 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/3 duty, or 1/3 bias 1/4 duty (see Figure

12). The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. In

addition, option codes can also be used to set up four of the LCD driver output pins (segment 0 to

segment 31) as a DC output port. The structure of the LCD alternating frequency (FLCD) is shown in

the figure below.

Fosc or Fosc/32

Fs

Fw

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

Fw/64

Fw/128

Fw/256

Fw/512

Mask Option

(Single/Dual Clock)

F_LCD

Selector

Figure 11. LCD Alternating Frequency (FLCD) Circuit Diagram

Data Bus

Option Codes

LCD

Frequency

Selection

LCD Data RAM

(32 x 4 bits)

LCD Drive

Mode

Selection

Fw

Clock

Generator

LCD Mode

Controller

MOV LCDM, #I

Instruction

LCD Duty & Bias

Power Selection

F_LCD

LCD

DH1

DH2

Waveform

Segment

Driver/Controller

LCD Voltage

Controller

Commom

Driver

VDD

VSS

VDD1 to 3

SEG0 to 31

COM0 to 3

Figure 12. LCD Driver/Controller Circuit Diagram

Publication Release Date: March 1998

Revision A3

- 25 -

W741C260

When Fw = 32.768 KHz, the LCD frequency is as shown in the table below.

LCD FREQUENCY

Fw/512 (64 Hz)

STATIC

64

1/2 DUTY

32

1/3 DUTY

1/4 DUTY

21

43

16

32

Fw/256 (128 Hz)

Fw/128 (256 Hz)

Fw/64 (512 Hz)

128

64

256

128

85

64

512

256

171

128

Corresponding to the 32 LCD drive output pins, there are 32 LCD data RAM segments (LCDR00 to

LCDR1F). Instructions such as MOV LCDR, #I; MOV WR, LCDR; MOV LCDR, WR; and MOV LCDR,

ACC are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the

segment output pins automatically without program control. When the bit value of the LCD data RAM

is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The

contents of the LCD data RAM (LCDR) are sent out through the segment 0 to segment 31 pins by a

direct memory access. The relationship between the LCD data RAM and segment/common pins is

shown below.

COM3

bit 3

0/1

COM2

bit 2

0/1

COM1

bit 1

0/1

COM0

bit 0

0/1

LCD data RAM

LCDR00

Output pin

SEG0

LCDR01

SEG1

0/1

.

LCDR1E

LCDR1F

SEG30

SEG31

0/1

The LCDON instruction turns the LCD display on (even in HOLD mode), and the LCDOFF instruction

turns the LCD display off. At initial reset, all the LCD segments are lit. When the initial reset state

ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON

must be executed. When the drive output pins are used as DC output ports (set by option codes,

please refer the user's manual of ASM741S assembler for more detail), CMOS output type or NMOS

output type can be selected by executing the instruction MOV LCDM, #I. The relation between the

LCD data RAM and segment/common pins is shown below. The data in LCDR00 are transferred to

the corresponding segment output port (SEG3 to SEG0) by a direct memory access. The other LCD

data RAM segments can be used as normal data RAM to store data.

LCD DATA RAM

LCDR00

OUTPUT PIN

BIT 3

BIT 2

BIT 1

BIT 0

SEG3

SEG2

SEG1

SEG0

SEG3- SEG0

-

SEG7

-

SEG6

-

SEG5

-

SEG4

-

LCDR03- LCDR01

LCDR04

SEG7- SEG4

-

LCDR07- LCDR05

- 26 -

W741C260

Continued

.

LCDR1C

SEG31

-

SEG30

-

SEG29

-

SEG28

-

SEG31- SEG28

-

LCDR1F- LCDR1D

The relationship between the LCD drive mode and the maximum number of drivable LCD segments

is shown below.

LCD DRIVE MODE

MAX. NUMBER OF

DRIVABLE LCD SEGMENT

CONNECTION AT

POWER INPUT

Static

32 (COM1)

Connect VDD3, VDD2 to VDD1

1/2 Bias 1/2 Duty

1/2 Bias 1/3 Duty

1/3 Bias 1/3 Duty

1/3 Bias 1/4 Duty

Connect VDD3 to VDD2

64 (COM1- COM2)

96 (COM1- COM3)

128 (COM1- COM4)

Connect VDD3 to VDD2

-

LCD Output Mode Type Flag (LCDM)

The LCD output mode type flag is organized as an 8-bit binary register (LCDM.0 to LCDM.7). These

bits are used to control the LCD output pins architecture. When LCD output pins are set to DC output

mode by option codes, the architecture of these output pins (segment 0 to segment 31) can be

selected as CMOS or NMOS type. It is controlled by the MOV LCDM, #I instruction. The bit

descriptions are as follows:

7

6

5

4

3

2

1

0

LCDM

w

Note: W means write only.

LCDM.0 = 0 SEG0 to SEG3 work as CMOS output type.

= 1 SEG0 to SEG3 work as NMOS output type.

LCDM.1 = 0 SEG4 to SEG7 work as CMOS output type.

= 1 SEG4 to SEG7 work as NMOS output type.

LCDM.2 = 0 SEG8 to SEG11 work as CMOS output type.

= 1 SEG8 to SEG11 work as NMOS output type.

LCDM.3 = 0 SEG12 to SEG15 work as CMOS output type.

= 1 SEG12 to SEG15 work as NMOS output type.

LCDM.4 = 0 SEG16 to SEG19 work as CMOS output type.

= 1 SEG16 to SEG19 work as NMOS output type.

LCDM.5 = 0 SEG20 to SEG23 work as CMOS output type.

= 1 SEG20 to SEG23 work as NMOS output type.

Publication Release Date: March 1998

Revision A3

- 27 -

W741C260

LCDM.6 = 0 SEG24 to SEG27 work as CMOS output type.

= 1 SEG24 to SEG27 work as NMOS output type.

LCDM.7 = 0 SEG28 to SEG31 work as CMOS output type.

= 1 SEG28 to SEG31 work as NMOS output type.

The output waveforms for the five LCD driving modes are shown below.

Static Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

VDD2

VDD1

VSS

Unlit LCD driver

outputs

Lit LCD driver

outputs

VDD2

VDD1

VSS

1/2 Bias 1/2 Duty Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

COM1

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0,

COM1 sides

being unlit

VDD2

VDD1

VSS

LCD driver

outputs for

only seg. on

COM0 side

being lit

VDD2

VDD1

VSS

- 28 -

W741C260

1/2 Bias 1/2 Duty Lighting System (Example)- Normal Operating Mode, continued

LCD driver

outputs for

only seg. on

COM1 side

being lit

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0,

COM1 sides

being lit

VDD2

VDD1

VSS

1/2 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

VDD2

VDD1

VSS

COM0

VDD2

VDD1

VSS

COM1

COM2

VDD2

VDD1

VSS

VDD2

VDD1

VSS

LCD driver

outputs for all

seg. on COM0,1,2

sides being unlit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0

side being lit

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM1

side being lit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0,1

sides being lit

Publication Release Date: March 1998

Revision A3

- 29 -

W741C260

1/2 Bias 1/3 Duty Lighting System (Example)- Normal Operating Mode, continued

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM2

side being lit

LCD driver

VDD2

VDD1

VSS

outputs for only

seg. on COM0,2

sides being lit

1/3 Bias 1/3 Duty Lighting System (Example)

Normal Operating Mode

VDD3

COM0

COM1

VDD2

VDD1

VSS

VDD3

VDD2

VDD1

VSS

VDD3

VDD2

VDD1

VSS

COM2

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for all

seg. on COM0,1,2

sides being unlit

LCD driver

VDD3

VDD2

VDD1

VSS

outputs for only

seg. on COM0

side being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for only

seg. on COM1

side being lit

LCD driver

outputs for seg.

on COM0,2

VDD3

VDD2

VDD1

VSS

sides being lit

LCD driver

outputs for seg.

on COM1,2

VDD3

VDD2

VDD1

VSS

sides being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for seg.

on COM0,1,2

sides being lit

- 30 -

W741C260

1/3 Bias 1/4 Duty Lighting System (Example)

Normal Operating Mode

VDD3

VDD2

VDD1

VSS

COM0

VDD3

VDD2

VDD1

VSS

COM1

COM2

VDD3

VDD2

VDD1

VSS

VDD3

VDD2

VDD1

VSS

COM3

LCD driver

outputs for

only seg. on

COM0 side

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

only seg. on

COM1 side

being lit

VDD3

VDD2

VDD1

VSS

Publication Release Date: March 1998

Revision A3

- 31 -

W741C260

1/3 Bias 1/4 Duty Lighting System (Example)- Normal Operating Mode, continued

LCD driver

outputs for

seg. on COM0,

COM1 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM1,

COM2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM1

COM2 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0

COM2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

LCD driver

outputs for

seg. on COM0

COM1,2,3 sides

being lit

VDD3

VDD2

VDD1

VSS

- 32 -

W741C260

The power connections for each LCD driving mode, which are determined by a mask option, are

shown below.

Static LCD Configuration

1/2 Bias LCD Configuration

DH1

0.1uF

DH2

DH1, DH2 floating

DH2

VSS

VDD

C

H

I

H

I

VDD

0.1uF

P

VDD1

VDD2

VDD3

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD3 = VDD

VDD1 = VDD2 = VDD3 = VDD

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

C

H

I

VDD

0.1uF

P

VDD1

VDD2

VDD3

VDD1 = 1/2 VDD, VDD2 = VDD, VDD3 = 3/2 VDD

Publication Release Date: March 1998

Revision A3

- 33 -

W741C260

LCD Configuration, continued

1/3 Bias LCD Configuration

DH1

0.1uF

DH2

VSS

VDD

C

H

I

VDD

0.1uF

P

VDD1

VDD2

VDD3

VDD1 = 1/3 VDD, VDD2 = 2/3 VDD, VDD3 = VDD

ABSOLUTE MAXIMUM RATINGS

PARAMETER

Supply Voltage to Ground Potential

Applied Input/Output Voltage

Power Dissipation

RATING

-0.3 to +7.0

120

UNIT

V

mW

°C

Ambient Operating Temperature

Storage Temperature

0 to +70

-55 to +150

°C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

- 34 -

W741C260

DC CHARACTERISTICS

(VDD- VSS = 3.0V, Fm = 4.19 MHz, Fs = 32.768 KHz, TA = 25° C, LCD on; unless otherwise specified)

PARAMETER

Op. Voltage

SYM.

VDD

CONDITIONS

MIN. TYP.

MAX. UNIT

-

2.2

-

5.5

V

Op. Current (Crystal Type)

IOP1

No load (Ext-V)

In dual-clock normal

operation

-

0.6

2.5

mA

Op. Current (RC Type)

IOP2

IOP3

No load (Ext-V)

In dual-clock normal

operation

-

1

4

mA

Op. Current (Crystal Type)

No load (Ext-V)

In dual-clock slow

operation and Fm is

stopped

8.5

20

mA

Hold Current (Crystal

Type)

IHM1 Hold mode No load (Ext-V)

In dual-clock normal

operation

-

280

450

mA

Hold Current (RC Type)

IHM2 Hold mode No load (Ext-V)

In dual-clock normal

operation

-

500

4.0

600

6

mA

Hold Current (Crystal

Type)

IHM3 Hold mode No load (Ext-V)

In dual-clock slow

operation and Fm is

stopped

Stop Current (Crystal type) ISM1 Stop mode No load (Ext-V)

In dual-clock normal

operation

-

4.0

0.1

6

2

mA

Stop Current (Crystal type) ISM2 Stop mode No load (Ext-V)

In single-clock operation

Input Low Voltage

VIL

VIH

-

VSS

-

0.3 VDD

VDD

0.4

V

Input High Voltage

0.7 VDD

MFP Output Low Voltage

MFP Output High Voltage

VML

VMH

IOL = 3.5 mA

IOH = 3.5 mA

-

2.4

-

Port RA, RB Output Low

Voltage

VABL IOL = 2.0 mA

0.4

Port RA, RB Output High

Voltage

VABH IOH = 2.0 mA

2.4

-

V

Publication Release Date: March 1998

Revision A3

- 35 -

W741C260

DC Characteristics, continue

PARAMETER

SYM.

CONDITIONS

MIN.

-

TYP.

MAX. UNIT

LCD Supply Current

ILCD All Seg. ON

-

6

-

mA

IOL1

VOL = 0.4V

0.4

SEG0- SEG31 Sink Current

VLCD = 0.0V

(Used as LCD Output)

IOH1 VOH = 2.4V

VLCD = 3.0V

0.3

-

SEG0- SEG31 Drive Current

mA

(Used as LCD Output)

Segment Output Low

Voltage

VSL

IOL = 0.6 mA

0.4

V

(Used as DC Output)

Segment Output High

Voltage

VSH

2.4

-

V

IOH = 3 mA

(Used as DC Output)

Port RE Sink Current

Port RE Source Current

Input Port Pull-up Resistor

IEL

VOL = 0.9V

VOH = 2.4V

9

13.5

1.2

-

mA

KW

IEH

0.4

100

20

RCD Port RC, RD

RRES

350

100

1000

500

-

RES Pull-up Resistor

AC CHARACTERISTICS

(VDD- VSS = 3.0V, TA = 25° C, unless otherwise specified)

PARAMETER

SYM.

CONDITIONS

MIN.

TYP.

-

MAX. UNIT

RC type

-

4000

Op. Frequency

FOSC Crystal type 1 (Option low

speed type)

32.768

-

KHz

%

Crystal type 2 (Option

high speed type)

400

-

4190

10

Frequency Deviation by

Voltage Drop for RC

Oscillator

f(3V)- f(2.4V)

Df

f(3V)

f

Instruction Cycle Time

Reset Active Width

Interrupt Active Width

TI

One machine cycle

-

4/FOSC

-

S

TRAW FOSC = 32.768 KHz

TIAW FOSC = 32.768 KHz

1

-

mS

- 36 -

W741C260

PAD ASSIGMENT & POSITIONS

2850

m

69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

53

52

51

1

2

3

4

50

49

48

47

46

45

44

43

42

41

40

39

38

37

5

Y

6

7

8

9

X

(0,0)

3330

m

10

11

12

13

14

15

16

17

18

19

36

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Note: The chip substrate must be connected to system ground (VSS).

PAD NO. PAD NAME

X

Y

PAD NO. PAD NAME

X

Y

1

2

RE2

RE3

-1227.00

1122.00

992.00

862.00

732.00

602.00

472.00

342.00

212.00

82.00

11

12

13

14

15

16

17

18

19

20

SEG3

SEG4

SEG5

SEG6

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

-1227.00

-178.00

-308.00

-438.00

-568.00

-698.00

-828.00

-958.00

3

VSS

4

COM3

COM2

COM1

COM0

SEG0

SEG1

SEG2

5

6

7

8

-1227.00 -1088.00

-1227.00 -1218.00

-975.00 -1468.00

9

10

-48.00

Publication Release Date: March 1998

Revision A3

- 37 -

W741C260

Continued

PAD NO. PAD NAME

X

Y

PAD NO. PAD NAME

X

Y

21

22

23

24

25

SEG13

SEG14

SEG15

SEG16

SEG17

-845.00

-715.00

-585.00

-455.00

-325.00

-1468.00

46

47

48

49

50

XIN2

VDD

1227.00

82.00

212.00

342.00

472.00

602.00

XOUT1

XIN1

RES

MFP

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RC0

RC1

RC2

RC3

RD0

RD1

RD2

RD3

RE0

RE1

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

VDD3

-195.00

-65.00

-1468.00

-1218.00

-1088.00

-958.00

-828.00

-698.00

-568.00

-438.00

-308.00

-178.00

-48.00

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

1227.00

862.00

992.00

65.00

1227.00 1122.00

1041.10 1453.20

911.10 1453.20

781.10 1453.20

651.10 1453.20

521.10 1453.20

391.10 1453.20

261.10 1453.20

131.10 1453.20

1.10 1453.20

195.00

325.00

455.00

585.00

715.00

845.00

975.00

1227.00

-128.90 1453.20

-258.90 1453.20

-388.90 1453.20

-518.90 1453.20

-648.90 1453.20

-778.90 1453.20

-908.90 1453.20

VDD2

VDD1

DH2

DH1

XOUT2

- 38 -

W741C260

TYPICAL APPLICATION CIRCUIT

Vcc

V_DD

RA0

RA3

COM0

LCD

Output Signal

PANEL

COM3

SEG0

RB0

RB1

RB2

RB3

(1/3 Bias

1/4 Duty)

SEG31

0.1 uF

RC0

DH1

DH2

RC1

RC2

RC3

V_DD1

V_DD2

V_DD3

RD0

RD1

RD2

RD3

Connect to capacitor and VDD

to generate LCD voltage

Vcc

RES

0.1 uF

RE0

RE1

RE2

RE3

XOUT

Vcc

XIN

OSCOUT

32.768

KHz

MFP

470

W

OSCIN

V_SS

0.1 uF

Publication Release Date: March 1998

Revision A3

- 39 -

W741C260

INSTRUCTION SET TABLE

Symbol Description

ACC:

ACC.n:

WR:

PAGE:

MR0:

MR1:

PM0:

PM1:

PM2:

PSR0:

R:

Accumulator

Accumulator bit n

Working Register

Page Register

Mode Register 0

Mode Register 1

Port Mode 0

Port Mode 1

Port Mode 2

Port Status Register 0

Memory (RAM) of address R

LCD data RAM of address LDR

Memory bit n of address R

Constant parameter

Branch or jump address

LCDR:

R.n:

I:

L:

CF:

ZF:

Carry Flag

Zero Flag

PC:

Program Counter

TM0:

Timer 0

TM1:

Timer 1

IEF.n:

HCF.n:

HEF.n:

PEF.n:

EVFn:

Interrupt Enable Flag n

HOLD mode release Condition Flag n

HOLD mode release Enable Flag n

Port Enable Flag n

Event Flag n

! =:

&:

Not equal

AND

^:

OR

- 40 -

W741C260

Symbol Description, continued

EX:

Exclusive OR

Transfer direction, result

¬ :

[PAGE*10H+()]: Contents of address PAGE(bit2, bit1, bit0)*10H+()

[P()]: Contents of port P()

Instruction Set Table 1

MNEMONIC

FLAG

CYCLE

FUNCTION

AFFECTED

Arithmetic

ADD

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R

ZF, CF

ZF

1

ACC¬ (R) + (ACC)

ADD

ACC¬ (WR) + I

ADDR

ADC

ACC, R¬ (R) + (ACC)

ACC, WR¬ (WR) + I

ACC¬ (R) + (ACC) + (CF)

ACC¬ (WR) + I + (CF)

ACC, R¬ (R) + (ACC) + (CF)

ACC, WR¬ (WR) + I + (CF)

ACC¬ (R) + (ACC)

ADC

ADCR

ADU

ZF

ACC¬ (WR) + I

ADUR

SUB

ZF

ACC, R¬ (R) + (ACC)

ACC, W R¬ (WR) + I

ACC¬ (R) - (ACC)

ZF

ZF, CF

SUB

ACC¬ (WR) - I

SUBR

SBC

ACC, R¬ (R) - (ACC)

ACC, WR¬ (WR) - I

ACC¬ (R) - (ACC) - (CF)

ACC¬ (WR) - I - (CF)

ACC, R¬ (R) - (ACC) - (CF)

ACC, WR¬ (WR) - I - (CF)

ACC, R¬ (R) + 1

SBC

SBCR

INC

DEC

R

ACC, R¬ (R) - 1

Publication Release Date: March 1998

Revision A3

- 41 -

W741C260

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

CYCLE

AFFECTED

Logic Operations

ANL

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

R, ACC

WR, #I

ZF

1

ACC¬ (R) & (ACC)

ANL

ACC¬ (WR) & I

ANLR

ORL

ORLR

XRL

ACC, R¬ (R) & (ACC)

ACC, WR¬ (WR) & I

ACC¬ (R) Ù (ACC)

ACC¬ (WR) Ù I

ACC, R¬ (R) Ù (ACC)

ACC, WR¬ (WR) Ù I

ACC¬ (R) EX (ACC)

ACC¬ (WR) EX I

XRL

XRLR

Branch

JMP

ACC, R¬ (R) EX (ACC)

ACC, WR¬ (WR) EX I

L

1

PC10- PC0¬ L10- L0

JB0

L

PC10- PC0¬ L10- L0; if ACC.0 = "1"

PC10- PC0¬ L10- L0; if ACC.1 = "1"

PC10- PC0¬ L10- L0; if ACC.2 = "1"

PC10- PC0¬ L10- L0; if ACC.3 = "1"

PC10- PC0¬ L10- L0; if ACC = 0

PC10- PC0¬ L10- L0; if ACC ! = 0

PC10- PC0¬ L10- L0; if CF = "1"

PC10- PC0¬ L10- L0; if CF ! = "1"

ACC, R¬ (R) - 1; skip if ACC = 0

ACC, R¬ (R) - 1; skip if ACC ! = 0

Skip if R.0 = "1"

JB1

L

JB2

L

JB3

L

JZ

L

JNZ

L

JC

L

JNC

L

DSKZ

DSKNZ

SKB0

SKB1

SKB2

SKB3

R

ZF, CF

Skip if R.1 = "1"

Skip if R.2 = "1"

Skip if R.3 = "1"

- 42 -

W741C260

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

CYCLE

AFFECTED

Data Move

MOV

MOVA

MOV

MOVC

WR, R

R, WR

WR, R

R, WR

R, ACC

ACC, R

R, #I

1

2

1

2

WR¬ (R)

R¬ (WR)

ZF

ACC, WR¬ (R)

ACC, R¬ (WR)

R¬ (ACC)

ACC¬ (R)

R¬ I

ZF

WR, @R

@R, WR

TABH, R

TABL, R

R

WR¬ [PR (bit2, bit1, bit0) ´ 10H + (R)]

[PR (bit2, bit1, bit0) ´ 10H +(R)]¬ WR

TAB High addresss ¬ R

TAB Low addresss ¬ R

R¬ [ TAB ´ 10H + (ACC)]

WR, #I

WR ¬ [(I6 ~ I0) ´ 10H + (ACC)]

Input & Output

MOVA

MOV

R, RA

ZF

1

ACC, R¬ [RA]

ACC, R¬ [RB]

ACC, R¬ [RC]

ACC, R¬ [RD]

[RA]¬ (R)

R, RB

R, RC

R, RD

RA, R

RB, R

RE, R

MFP, #I

MOV

[RB]¬ (R)

MOV

[RE]¬ (R)

MOV

[MFP]¬ I

Flag & Register

MOVA

MOV

R, PAGE

ZF

1

ACC, R¬ PAGE (Page Register)

PAGE, R

PAGE, #I

MR0, #I

MR1, #I

PAGE¬ (R)

PAGE¬ I

MR0¬ I

MR1¬ I

Publication Release Date: March 1998

Revision A3

- 43 -

W741C260

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

CYCLE

AFFECTED

MOVA

MOV

MOVA

CLR

R, CF

ZF

CF

ZF

1

ACC.0, R.0¬ CF

CF¬ (R.0)

CF, R

R, HCFL

R, HCFH

PMF, #I

PM0, #I

PM1, #I

PM2, #I

EVF, #I

PEF, #I

IEF, #I

ACC, R¬ HCF0- HCF3

ACC, R¬ HCF4- HCF7

Clear Parameter Flag if In = 1

Set Parameter Flag if In = 1

Port Mode 0¬ I

SET

MOV

CLR

Port Mode 1¬ I

Port Mode 2¬ I

Clear Event Flag if In = 1

Set/Reset Port Enable Flag

Set/Reset Interrupt Enable Flag

Set/Reset HOLD mode release Enable Flag

MOV

HEF, #I

SEF, #I

Set/Reset STOP mode wake-up Enable Flag

for RC port

MOV

MOVA

CLR

SET

SCR, #I

R, PSR0

PSR0

CF

Set/Reset System clock Control Resgister

ACC, R¬ Port Status Register 0

Clear Port Status Register 0

Set Carry Flag

1

ZF

CF

CLR

CF

Clear Carry Flag

DIVR0

WDT

Clear the last 4-bit of the Divider

Clear WatchDog Timer

Shift & Rotate

SHRC

R

ZF, CF

1

ACC.n, R.n¬ (R.n+1);

ACC.3, R.3¬ 0; CF¬ R.0

RRC

ACC.n, R.n¬ (R.n+1);

ACC.3, R.3¬ CF; CF¬ R.0

SHLC

RLC

ACC.n, R.n¬ (R.n-1);

ACC.0, R.0¬ 0; CF¬ R.3

ACC.n, R.n¬ (R.n-1);

ACC.0, R.0¬ CF; CF¬ R.3

- 44 -

W741C260

Instruction Set Table 1, continued

MNEMONIC

FUNCTION

FLAG

AFFECTED

CYCLE

LCD

MOV

LCDR, #I

1

LCDR¬ I

MOV

WR, LCDR

LCDR, WR

LCDR, ACC

LCDM, #I

WR¬ (LCDR)

LCDR¬ (WR)

LCDR¬ (ACC)

MOV

Select LCD output mode type

LCD ON

LCDON

LCDOFF

Timer

MOV

LCD OFF

TM0H, R

TM0L, R

TM0, #I

1

Timer 0 High register ¬ R

Timer 0 Low register ¬ R

Timer 0 set

MOV

TM1H, R

TM1L, R

TM1, #I

Timer 1 High register ¬ R

Timer 1 Low register ¬ R

Timer 1 set

MOV

Subroutine

CALL

L

1

STACK ¬ (PC)+1;

PC10- PC0 ¬ L10- L0

RTN

Other

HOLD

STOP

NOP

EN

(PC)¬ STACK

Enter Hold mode

1

Enter Stop mode

No Operation

INT

Enable Interrupt Function

Disable Interrupt Function

DIS

Publication Release Date: March 1998

Revision A3

- 45 -

W741C260

Instruction Set Table 2

ADC R, ACC

Machine Code:

Machine Cycle:

Operation:

Add R to ACC with CF

0

R6

0

1

0

R5 R4 R3 R2 R1 R0

1

ACC ¬ (R) + (ACC) + (CF)

The contents of the data memory location addressed by R6 to R0, ACC,

and CF are binary added and the result is loaded into the ACC.

Description:

Flag Affected:

CF & ZF

ADC WR, #I

Add immediate data to WR with CF

Machine Code:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

ACC ¬ (WR) + I + (CF)

Description:

The contents of the Working Register (WR), I and CF are binary added and

the result is loaded into the ACC.

Flag Affected:

CF & ZF

ADCR R, ACC

Add R to ACC with CF

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (R) + (ACC) + (CF)

Description:

The contents of the data memory location addressed by R6 to R0, ACC,

and CF are binary added and the result is placed in the ACC and the data

memory.

Flag Affected:

CF & ZF

- 46 -

W741C260

Instruction Set Table 2, continued

ADCR WR, #I

Add immediate data to WR with CF

Machine Code:

0

1

0

1

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

ACC, WR ¬ (WR) + I + (CF)

Description:

The contents of the Working Register (WR), I, CF are binary added and the

result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

ADD R, ACC

Add R to ACC

Machine Code:

Machine Cycle:

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC ¬ (R) + (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and ACC

are binary added and the result is loaded into the ACC.

Flag Affected:

CF & ZF

ADD

WR, #I

Add immediate data to WR

Machine Code:

Machine Cycle:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC ¬ (WR) + I

Description:

The contents of the Working Register (WR) and the immediate data I are

binary added and the result is loaded into the ACC.

Flag Affected:

CF & ZF

Publication Release Date: March 1998

- 47 -

Revision A3

W741C260

Instruction Set Table 2, continued

ADDR R, ACC

Add R to ACC

Machine Code:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) + (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and ACC

are binary added and the result is placed in the ACC and the data memory.

Flag Affected:

CF & ZF

ADDR WR, #I

Add immediate data to WR

Machine Code:

0

1

0

1

I3 I2 I1 I0

W2 W1 W0

W3

Machine Cycle:

Operation:

1

ACC, WR ¬ (WR) + I

Description:

The contents of the Working Register (WR) and the immediate data I are

binary added and the result is placed in the ACC and the WR.

Flag Affected:

ADU R, ACC

Machine Code:

CF & ZF

Add R to ACC with Carry Flag unchanged

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC ¬ (R) + (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and ACC

are binary added and the result is loaded into the ACC.

Flag Affected:

ZF

- 48 -

W741C260

Instruction Set Table 2, continued

ADU WR, #I

Add immediate data to WR with Carry Flag unchanged

0

1

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

Machine Code:

Machine Cycle:

1

Operation:

ACC ¬ (WR) + I

Description:

The contents of the Working Register (WR) and the immediate data I are

binary added and the result is loaded into the ACC.

Flag Affected:

ZF

ADUR R, ACC

Add R to ACC with Carry Flag unchanged

Machine Code:

Machine Cycle:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (R) + (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and ACC

are binary added and the result is placed in the ACC and the data memory.

Flag Affected:

ZF

ADUR WR, #I

Add immediate data to WR with Carry Flag unchanged

Machine Code:

Machine Cycle:

0

1

0

1

0

1

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC, WR ¬ (WR) + I

Description:

The contents of the Working Register (WR) and the immediate data I are

binary added and the result is placed in the WR and the ACC.

Flag Affected:

ZF

Publication Release Date: March 1998

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Revision A3

W741C260

Instruction Set Table 2, continued

ANL R, ACC

And R to ACC

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC ¬ (R) & (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are ANDed and the result is loaded into the ACC.

Flag Affected:

ZF

ANL

WR, #I

And immediate data to WR

Machine Code:

0

1

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

ACC ¬ (WR) & I

Description:

The contents of the Working Register (WR) and the immediate data I are

ANDed and the result is loaded into the ACC.

Flag Affected:

ZF

ANLR R, ACC

And R to ACC

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) & (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are ANDed and the result is placed in the data memory and the ACC.

Flag Affected:

ZF

- 50 -

W741C260

Instruction Set Table 2, continued

ANLR WR, #I

And immediate data to WR

Machine Code:

0

1

0

1

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

ACC, WR ¬ (WR) & I

Description:

The contents of the Working Register (WR) and the immediate data I are

ANDed and the result is placed in the WR and the ACC.

Flag Affected:

ZF

CALL

L

Call subroutine

Machine Code:

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

STACK ¬ (PC)+1;

PC10- PC0 ¬ L10- L0

Description:

The next program counter (PC10 to PC0) is saved in the STACK and then

the direct address (L10 to L0) is loaded into the program counter.

A subroutine is called.

CLR

CF

Clear CF

Machine Code:

Machine Cycle:

0

1

0

1

0

1

Clear CF

Operation:

Clear Carry Flag to 0.

CF

Description:

Flag Affected:

Publication Release Date: March 1998

Revision A3

- 51 -

W741C260

Instruction Set Table 2, continued

CLR

DIVR0

Reset the last 4 bits of the DIVideR0

Machine Code:

0

1

0

1

0

Machine Cycle:

Operation:

1

Reset the last 4 bits of the Divider0

Description:

When this instruction is executed, the last 4 bits of the Divider0 (14 bits)

are reset.

CLR EVF, #I

Clear EVent Flag

Machine Code:

0

1

0

I7 I6 I5 I4 I3 I2 I1 I0

Machine Cycle:

Operation:

1

Clear event flag

Description:

The condition corresponding to the data specified by I7 to I0 is controlled.

I0 to I8 Mode after execution of instruction

I0 = 1

I1 = 1

EVF0 caused by overflow from the Divider0 is reset.

EVF1 caused by underflow from the Timer 0 is reset.

I2 = 1 EVF2 caused by signal change on port RC is reset.

I3 = 1

I4 = 1

Reserved

EVF4 caused by overflow from the Divider1 is reset.

Reserved

I5, I6

I7 = 1 EVF7 caused by underflow from the Timer 1 is reset.

- 52 -

W741C260

Instruction Set Table 2, continued

CLR PMF, #I

Clear ParaMeter Flag

Machine Code:

0

1

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Clear Parameter Flag

Description:

Description of each flag:

I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/1024.

CLR

PSR0

Clear Port Status Register 0 (RC port signal change flag)

Machine Code:

Machine Cycle:

0

1

0

1

0

1

Operation:

Clear Port Status Register 0 (RC port signal change flag)

Description:

When this instruction is executed, the RC port signal change flag (PSR0) is

cleared.

CLR

WDT

Reset the last 4 bits of the WatchDog Timer

Machine Code:

0

1

0

1

0

Machine Cycle:

Operation:

1

Reset the last 4 bits of the watchdog timer

Description:

When this instruction is executed, the last 4 bits of the watchdog timer are

reset.

Publication Release Date: March 1998

- 53 -

Revision A3

W741C260

Instruction Set Table 2, continued

DEC

R

Decrement R contents

Machine Code:

0

1

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) - 1

Description:

Decrement the data memory contents and load result into the ACC and the

data memory.

Flag Affected:

CF & ZF

DIS INT

Disable Interrupt function

Machine Code:

0

1

0

1

0

1

0

Machine Cycle:

Operation:

1

Disable interrupt function

Description:

Interrupt function is inhibited by executing this instruction.

DSKNZ

R

Decrement R contents then skip if ACC ! = 0

Machine Code:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) - 1;

PC ¬ (PC) + 2 if ACC ! = 0

Description:

Decrement the data memory contents and load result into the ACC and the

data memory. If ACC ! = 0, the program counter is incremented by 2 and

produces a skip.

Flag Affected:

CF & ZF

- 54 -

W741C260

Instruction Set Table 2, continued

DSKZ

R

Decrement R contents then skip if ACC is zero

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (R) - 1;

PC ¬ (PC) + 2 if ACC = 0

Description:

Decrement the data memory contents and load result into the ACC and the

data memory. If ACC = 0, the program counter is incremented by 2 and

produces a skip.

Flag Affected:

CF & ZF

EN

INT

Enable Interrupt function

Machine Code:

0

1

0

1

0

1

0

Machine Cycle:

Operation:

1

Enable interrupt function

Description:

This instruction enables the interrupt function.

HOLD

Enter the HOLD mode

Machine Code:

Machine Cycle:

0

1

0

1

Operation:

Enter the HOLD mode

Description:

The following two conditions cause the HOLD mode to be released.

(1) An interrupt is accepted.

(2) The HOLD release condition specified by the HEF is met.

In HOLD mode, when an interrupt is accepted the HOLD mode will be

released and the interrupt service routine will be executed. After

completing the interrupt service routine by executing the RTN instruction,

the mC will enter HOLD mode again.

Publication Release Date: March 1998

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Revision A3

W741C260

Instruction Set Table 2, continued

INC

R

Increment R contents

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1

R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) + 1

Increment the data memory contents and load the result into the ACC and

the data memory.

Description:

Flag Affected:

CF & ZF

JB0

L

Jump when bit 0 of ACC is "1"

Machine Code:

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0; if ACC.0 = "1"

Description:

If bit 0 of the ACC is "1," PC10 to PC0 of the program counter are replaced

with the data specified by L10 to L0 and a jump occurs. If bit 0 of the ACC

is "0," the program counter (PC) is incremented.

JB1

L

Jump when bit 1 of ACC is "1"

Machine Code:

1

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0; if ACC.1 = "1"

Description:

If bit 1 of the ACC is "1," PC10 to PC0 of the program counter are replaced

with the data specified by L10 to L0 and a jump occurs. If bit 1 of the ACC

is "0," the program counter (PC) is incremented.

- 56 -

W741C260

Instruction Set Table 2, continued

JB2

L

Jump when bit 2 of ACC is "1"

Machine Code:

1

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0; if ACC.2 = "1"

Description:

If bit 2 of the ACC is "1," PC10 to PC0 of the program counter are replaced

with the data specified by L10 to L0 and a jump occurs. If bit 2 of the ACC

is "0," the program counter (PC) is incremented.

JB3

L

Jump when bit 3 of ACC is "1"

Machine Code:

1

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0; if ACC.3 = "1"

Description:

If bit 3 of the ACC is "1," PC10 to PC0 of the program counter are replaced

with the data specified by L10 to L0 and a jump occurs. If bit 3 of the ACC

is "0," the program counter (PC) is incremented.

JC

L

Jump when CF is "1"

Machine Code:

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0; if CF = "1"

Description:

If CF is "1," PC10 to PC0 of the program counter are replaced with the data

specified by L10 to L0 and a jump occurs. If the CF is "0," the program

counter (PC) is incremented.

Publication Release Date: March 1998

- 57 -

Revision A3

W741C260

Instruction Set Table 2, continued

JMP

L

Jump absolutely

Machine Code:

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

Machine Cycle:

Operation:

1

PC10- PC0 ¬ L10- L0

Description:

PC10 to PC0 of the program counter are replaced with the data specified

by L10 to L0 and an unconditional jump occurs.

JNC

L

Jump when CF is not "1"

Machine Code:

Machine Cycle:

1

0

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

1

Operation:

PC10- PC0 ¬ L10- L0; if CF = "0"

Description:

If CF is "0," PC10 to PC0 of the program counter are replaced with the data

specified by L10 to L0 and a jump occurs. If CF is "1," the program counter

(PC) is incremented.

JNZ

L

Jump when ACC is not zero

Machine Code:

Machine Cycle:

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

1

Operation:

PC10- PC0 ¬ L10- L0; if ACC ! = 0

Description:

If the ACC is not zero, PC10 to PC0 of the program counter are replaced

with the data specified by L10 to L0 and a jump occurs. If the ACC is zero,

the program counter (PC) is incremented.

- 58 -

W741C260

Instruction Set Table 2, continued

JZ

L

Jump when ACC is zero

Machine Code:

Machine Cycle:

1

0

L10 L9 L8

L7 L6 L5 L4 L3 L2 L1 L0

1

Operation:

PC10- PC0 ¬ L10- L0; if ACC = 0

Description:

If the ACC is zero, PC10 to PC0 of the program counter are replaced with

the data specified by L10 to L0 and a jump occurs. If the ACC is not zero,

the program counter (PC) is incremented.

LCDON

LCD ON

Machine Code:

0

1

0

Machine Cycle:

Operation:

1

LCD ON

Description:

Turn on LCD display.

LCDOFF

LCD OFF

Machine Code:

0

1

0

1

0

Machine Cycle:

Operation:

1

LCD OFF

Description:

Turn off LCD display.

Publication Release Date: March 1998

Revision A3

- 59 -

W741C260

Instruction Set Table 2, continued

MOV ACC, R

Move R content to ACC

Machine Code:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the ACC.

Flag Affected:

MOV CF, R

Machine Code:

ZF

Move R.0 content to CF

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

CF ¬ (R.0)

Description:

The bit 0 content of the data memory location addressed by R6 to R0 is

loaded into CF.

Flag Affected:

CF

- 60 -

W741C260

Instruction Set Table 2, continued

MOV HEF, #I

Set/Reset Hold mode release Enable Flag

Machine Code:

0

1

0

1

I7 I6 I5 I4 I3 I2 I1 I0

Machine Cycle:

1

Operation:

Hold mode release enable flag control

Description:

Operation

I0 to I7

I0 = 1

HEF0 is set so that overflow from Divider0 will caused

the HOLD mode to be released.

HEF1 is set so that underflow from Timer 0 will caused

the HOLD mode to be released.

I1 = 1

HEF2 is set so that signal change on port RC caused

the HOLD mode to be released.

I2 = 1

I3 = 1

Reserved

HEF4 is set so that overflow from Divider1 will caused

the HOLD mode to be released.

I4 = 1

I5 & I6

I7 = 1

Reserved

HEF7 is set so that underflow from Timer 1 will caused

the HOLD mode to be released.

Publication Release Date: March 1998

Revision A3

- 61 -

W741C260

Instruction Set Table 2, continued

MOV

IEF, #I

Set/Reset Interrupt Enable Flag

Machine Code:

Machine Cycle:

0

1

0

1

0

1

I7 I6 I5 I4 I3 I2 I1 I0

1

Operation:

Interrupt Enable flag Control

Description:

The interrupt enable flag corresponding to the data specified by I7- I0 is

controlled:

I0 to I5

I0 = 1

Operation

The IEF0 is set so that interrupt 0 (overflow from the

Divider0) is accepted.

The IEF1 is set so that interrupt 1 (underflow from the

Timer 0) is accepted.

I1 = 1

The IEF2 is set so that interrupt 2 (signal change on port

RC) is accepted.

I2 = 1

I3 = 1

I4 = 1

Reserved

The IEF4 is set so that interrupt 4 (overflow from the

Divider1) is accepted.

Reserved

I5 & I6

I7 = 1

The IEF7 is set so that interrupt 7 (underflow from the

Timer 1) is accepted.

MOV LCDM, #I

Select LCD output Mode type

Machine Code:

0

1

I7 I6 I5 I4 I3 I2 I1 I0

Machine Cycle:

1

Operation:

Select LCD output mode type

Description:

When LCD output pins are set to DC output mode, user can select CMOS

or NMOS as output type.

I0- I7 = 0 => CMOS type; I0- I7 = 1 => NMOS type

- 62 -

W741C260

Instruction Set Table 2, continued

MOV LCDR, ACC

Move ACC content to LCDR

Machine Code:

0

1

D4

D3 D2 D1 D0

0

Machine Cycle:

Operation:

1

LCDR ¬ (ACC)

Description:

The contents of the ACC are loaded to the LCD data RAM (LCDR) location

addressed by D4 to D0.

MOV LCDR, WR

Load WR content to LCDR

Machine Code:

0

1

0

1

0

D4

D3 D2 D1 D0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

LCDR ¬ (WR)

Description:

The contents of the WR are loaded to the LCD data RAM (LCDR) location

addressed by D4 to D0.

MOV LCDR, #I

Load immediate data to LCDR

Machine Code:

0

1

0

D4

D3 D2 D1 D0 I3 I2 I1 I0

Machine Cycle:

Operation:

1

LCDR ¬ I

Description:

The immediate data I are loaded to the LCD data RAM (LCDR) location

addressed by D4 to D0.

Publication Release Date: March 1998

- 63 -

Revision A3

W741C260

Instruction Set Table 2, continued

MOV MFP, #I

Modulation Frequency Pulse generator

Machine Code:

Machine Cycle:

0

1

0

1

I7 I6 I5 I4 I3 I2 I1 I0

0

1

Operation:

[MFP] ¬

I

Description:

If the bit 2 of MR1 is "0," the waveform specified by I7 to I0 is delivered at

the MFP output pin (MFP). The relationship between the waveform and

immediate data I is as follows:

I5~I0

I0 = 1

I1 = 1

I2 = 1

I3 = 1

Fosc

8192 16384 32768

I4 = 1 I5 = 1

Fosc Fosc

Fosc

512

Fosc

256

Fosc

4096

Signal

I7

0

1

I6

0

1

0

1

Signal

Low

High

Fosc/16

Fosc/8

- 64 -

W741C260

Instruction Set Table 2, continued

MOV MR0, #I

Load immediate data to Mode Register 0 (MR0)

Machine Code:

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

MR0 ¬

I

Description:

The immediate data I are loaded to the MR0.

MR0 bits description:

= 0 The fundamental frequency of Timer 0 is Fosc/4

= 1 The fundamental frequency of Timer 0 is Fosc/1024

bit 0

Reserved

bit 1

bit 2

= 0 Timer 0 stop down-counting

= 1 Timer 0 start down-counting

bit 3

MOV MR1, #I

Load immediate data to Mode Register 1 (MR1)

Machine Code:

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

MR1 ¬

I

Description:

The immediate data I are loaded to the MR1.

MR1 bit description:

= 0 The internal fundamental frequency of Timer 1 is Fosc

= 1 The internal fundamental frequency of Timer 1 is Fosc/64

bit0

= 0 The fundamental frequency source of Timer 1 is

internal clock

= 1 The fundamental frequency source of Timer 1 is

external clock via RC.0 input pin

bit1

= 0 The specified waveform of the MFP generator is

delivered at the MFP output pin

bit2

bit3

= 1 The specified frequency of the Timer 1 is delivered at

the MFP output pin

= 0 Timer 1 stop down-counting

= 1 Timer 1 start down-counting

Publication Release Date: March 1998

Revision A3

- 65 -

W741C260

Instruction Set Table 2, continued

MOV PAGE, #I

Load immediate data to Page Register

Machine Code:

Machine Cycle:

0

1

0

1

0

1

0

1

0

I3 I2 I1 I0

1

Operation:

Page Register ¬

I

Description:

The immediate data I are loaded to the PR.

Bit 3 is reserved.

Bit 0, bit 1, and bit 2 indirect addressing mode preselect bits:

bit2

bit1

bit0

0

= Page 0 (00H to 0FH)

= Page 1 (10H to 1FH)

= Page 2 (20H to 2FH)

= Page 3 (30H to 3FH)

= Page 4 (40H to 4FH)

= Page 5 (50H to 5FH)

= Page 6 (60H to 6FH)

= Page 7 (70H to 7FH)

0

1

0

1

0

1

0

1

0

1

0

1

MOV PEF, #I

Set/Reset Port Enable Flag

Machine Code:

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Port enable flag control

Description:

The data specified by I can cause HOLD mode to be released or an

interrupt to occur. The signal change on port RC is specified.

Signal change at port RC

I0 to I3

I0 = 1

I1 = 1

I2 = 1

I3 = 1

RC0

RC1

RC2

RC3

- 66 -

W741C260

Instruction Set Table 2, continued

MOV PM0, #I

Set/Reset Port Mode 0 register

Machine Code:

0

1

0

1

0

1

0

I2 I1 I0

I3

Machine Cycle:

1

Operation:

Set/Reset Port mode 0 register

Description:

I0 = 0: RA port is CMOS type; I0 = 1: RA port is NMOS type.

I1 = 0: RB port is CMOS type; I1 = 1: RB port is NMOS type.

I2 = 0: RC port pull-high resistor is disabled;

I2 = 1: RC port pull-high resistor is enabled.

I3 = 0: RD port pull-high resistor is disabled;

I3 = 1: RD port pull-high resistor is enabled.

MOV PM1, #I

RA port independent Input/Output control

Machine Code:

0

1

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Input/output control of 4 RA port pins is independent.

Description:

I0 = 0: RA.0 is output pin; I0 = 1: RA.0 is input pin.

I1 = 0: RA.1 is output pin; I1 = 1: RA.1 is input pin.

I2 = 0: RA.2 is output pin; I2 = 1: RA.2 is input pin.

I3 = 0: RA.3 is output pin; I3 = 1: RA.3 is input pin.

Default condition RA port is input mode (PM = 1111B).

Publication Release Date: March 1998

Revision A3

- 67 -

W741C260

Instruction set table 2, continued

MOV PM2, #I

RB port independent Input/Output control

Machine Code:

0

1

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Input/output control of 4 RB port pins is independent.

Description:

I0 = 0: RB.0 is output pin; I0 = 1: RB.0 is input pin.

I1 = 0: RB.1 is output pin; I1 = 1: RB.1 is input pin.

I2 = 0: RB.2 is output pin; I2 = 1: RB.2 is input pin.

I3 = 0: RB.3 is output pin; I3 = 1: RB.3 is input pin.

Default condition RB port is input mode (PM2 = 1111B).

MOV R, ACC

Move ACC contents to R

Machine Code:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

R ¬ (ACC)

Description:

The contents of the ACC are loaded to the data memory location

addressed by R6 to R0.

MOVA R, RA

Input RA port data to ACC & R

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

ACC , R ¬ [RA]

Description:

The data on port RA are loaded into the data memory location addressed

by R6 to R0 and the ACC.

Flag Affected:

ZF

- 68 -

W741C260

Instruction Set Table 2, continued

MOVA R, RB

Input RB port data to ACC & R

Machine Code:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC , R ¬ [RB]

The data on port RB are loaded into the data memory location addressed

by R6 to R0 and the ACC.

Description:

Flag Affected:

MOVA R, RC

Machine Code:

ZF

Input RC port data to ACC & R

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

ACC , R ¬ [RC]

Description:

The input data on the input port RC are loaded into the data memory

location addressed by R6 to R0 and the ACC.

Flag Affected:

MOVA R, RD

Machine Code:

Machine Cycle:

ZF

Input RD port data to ACC & R

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC , R ¬ [RD]

Description:

Flag Affected:

The input data on the input port RD are loaded into the data memory

location addressed by R6 to R0 and the ACC.

ZF

Publication Release Date: March 1998

- 69 -

Revision A3

W741C260

Instruction Set Table 2, continued

MOV R, WR

Move WR contents to R

Machine Code:

Machine Cycle:

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

1

Operation:

R ¬ (WR)

Description:

The contents of the WR are loaded to the data memory location addressed

by R6 to R0.

MOV

R, #I

Load immediate data to R

Machine Code:

Machine Cycle:

1

0

1

I3 I2 I1

I0 R6 R5 R4 R3 R2 R1 R0

1

Operation:

R ¬ I

The immediate data I are loaded to the data memory location addressed by

R6 to R0.

Description:

MOV RA, R

Output R contents to RA port

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

[RA] ¬ (R)

Description:

The data in the data memory location addressed by R6 to R0 are output to

the port RA.

- 70 -

W741C260

Instruction Set Table 2, continued

MOV RB, R

Output R contents to RB port

Machine Code:

0

1

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

[RB] ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

output to the port RB.

MOV RE, R

Output R contents to port RE

Machine Code:

Machine Cycle:

Operation:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

[RE] ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

output to port RE.

MOV SCR, #I

Machine Code:

Machine Cycle:

Operation:

System Clock Register control

0

1

0

1

0

1

0

I3 I2 I1 I0

1

System clock control

Description:

If the operation mode is the dual clock operation selected by the option

codes, the system clock and oscillator can be arranged by controlling the

system clock register.

SCR bits decription:

= 0, Fosc = Fm

Bit 0

= 1, Fosc = Fs

= 0, main oscillator is enabled

Bit 1

= 1, main oscillator is disabled

Bit 2

Bit 3

Reserved

= 0, divider 1 is 14-stage

= 1, divider 1 is 13-stage

Publication Release Date: March 1998

Revision A3

- 71 -

W741C260

Instruction Set Table 2, continued

MOV SEF, #I

Set/Reset STOP mode wake-up Enable Flag for port RC

Machine Code:

0

1

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Set/reset STOP mode wake-up enable flag for port RC

Description:

The data specified by I cause a wake-up from the STOP mode. The falling-

edge signal on port RC can be specified independently.

I0 to I3

I0 = 1

I1 = 1

I2 = 1

I3 = 1

Falling edge signal on port RC

RC0

RC1

RC2

RC3

MOV TM0, #I

Timer 0 set

0

1

0

I7 I6 I5 I4 I3 I2 I1 I0

Machine Code:

Machine Cycle:

Operation:

1

Timer 0 set

The data specified by I7 to I0 is loaded to the Timer 0 to start the timer.

Description:

MOV TM0L, R

Move R contents to TM0L

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Code:

Machine Cycle:

Operation:

1

TM0L ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TM0L.

- 72 -

W741C260

Instruction Set Table 2, continued

MOV TM0H, R

Move R contents to TM0H

Machine code:

Machine Cycle:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

Operation:

TM0H ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TM0H.

MOV TM1, #I

Timer 1 set

0

1

0

1

I7 I6 I5 I4 I3 I2 I1 I0

Machine Code:

Machine Cycle:

Operation:

1

Timer 1 set

The data specified by I7 to I0 is loaded to the Timer 1 to start the timer.

Description:

MOV TM1L, R

Machine Code:

Machine Cycle:

Operation:

Move R contents to TM1L

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

TM1L ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TM1L.

Publication Release Date: March 1998

- 73 -

Revision A3

W741C260

Instruction Set Table 2, continued

MOV TM1H, R

Move R contents to TM1H

Machine code:

Machine Cycle:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

Operation:

TM1H ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TM1H.

MOV TABL, R

Machine Code:

Machine Cycle:

Operation:

Move R contents to TABL

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

TABL ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TABL.

MOV TABH, R

Machine code:

Machine Cycle:

Operation:

Move R contents to TABH

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

TABH ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded into the TABH.

- 74 -

W741C260

Instruction Set Table 2, continued

MOV WR, LCDR

Load LCDR contents to WR

Machine Code:

0

1

0

1

D4

D3 D2 D1 D0 W3 W2 W1 W0

Machine Cycle:

1

Operation:

WR ¬ (LCDR)

Description:

The contents of the LCD data RAM location addressed by D4 to D0 are

loaded to the WR.

MOV

WR, R

Move R contents to WR

Machine Code:

1

0

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

WR ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded to the WR.

MOV WR, @R

Indirect load from R to WR

Machine Code:

1

0

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

2

WR ¬ [PR (bit2, bit1, bit0) ´ 10H + (R)]

Description:

The data memory contents of address [PR (bit2, bit1, bit0) ´ 10H + (R)] are

loaded to the WR.

Publication Release Date: March 1998

- 75 -

Revision A3

W741C260

Instruction Set Table 2, continued

MOV @R, WR

Indirect load from WR to R

Machine Code:

1

0

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

2

[PR (bit2, bit1, bit0) ´ 10H + (R)] ¬ WR

Description:

The contents of the WR are loaded to the data memory location addressed

by [PR (bit2, bit1, bit0) ´ 10H + (R)] .

MOV PAGE, R

Move R contents to Page Register

Machine Code:

Machine Cycle:

Operation:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

PR ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded to the Page Register.

MOVA R, CF

Move CF contents to ACC.0 & R.0

Machine Code:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC.0, R.0 ¬ (CF)

Description:

The contents of CF is loaded to bit 0 of the data memory location

addressed by R6 to R0 and the ACC. The other bits of the data memory

and ACC are reset to "0."

Flag Affected:

ZF

- 76 -

W741C260

Instruction Set Table 2, continued

MOVA R, HCFH

Move HCF4-7 to ACC & R

Machine Code:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ HCF4- 7

Description:

The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded to the data

memory location addressed by R6 to R0 and the ACC. The ACC contents

and the meaning of the bits after execution of this instruction are as

follows:

Bit 0

Bit 1

HCF4: "1" when the HOLD mode is released by overflow from Divider 1.

HCF5: "1" when the HOLD mode is released by underflow from Timer 1.

Bit 2

Bit 3

Reserved.

Flag Affected:

ZF

Move HCF0

MOVA R, HCFL

-

3 to ACC & R

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Code:

1

Machine Cycle:

Operation:

ACC, R ¬ HCF0- 3

Description:

The contents of HCF bit 0 to bit 3 (HCF0 to HCF3) are loaded to the data

memory location addressed by R6 to R0 and the ACC. The ACC contents

and the meaning of the bits after execution of this instruction are as

follows:

HCF0: "1" when the HOLD mode is released by

overflow from the Divider 0.

Bit 0

Bit 1

Bit 2

Bit 3

HCF1: "1" when the HOLD mode is released by

underflow from Timer 0.

HCF2: "1" when the HOLD mode is released by

a signal change on port RC.

Reserved

Flag Affected:

ZF

Publication Release Date: March 1998

Revision A3

- 77 -

W741C260

Instruction Set Table 2, continued

MOVA R, PAGE

Move Page Register contents to ACC & R

Machine Code:

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC , R ¬ (Page Register)

Description:

The contents of the Page Register (PR) are loaded to the data memory

location addressed by R6 to R0 and the ACC.

Flag Affected:

ZF

MOVA R, PSR0

Move Port Status Register 0 contents to ACC & R

Machine Code:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ RC port signal change flag (PSR0)

Description:

The contents of the RC port signal change flag (PSR0) are loaded to the

data memory location addressed by R6 to R0 and the ACC. When the

signal changes on any pin of the RC port, the corresponding signal change

flag should be set to 1. Otherwise, it should be 0.

Flag Affected:

ZF

MOVA R, WR

Move WR contents to ACC & R

Machine Code:

Machine Cycle:

0

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (WR)

Description:

The contents of the WR are loaded to the ACC and the data memory

location addressed by R6 to R0.

Flag Affected:

ZF

- 78 -

W741C260

Instruction Set Table 2, continued

MOVA WR, R

Move R contents to ACC & WR

0

1

0

1

W3 W2 W1

W0 R6 R5 R4 R3 R2 R1 R0

Machine Code:

Machine Cycle:

Operation:

1

ACC, WR ¬ (R)

Description:

The contents of the data memory location addressed by R6 to R0 are

loaded to the WR and the ACC.

Flag Affected:

MOVC R

ZF

Move look-up table ROM addressed by TABL and TABH to R

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine code:

2

Machine Cycle:

Operation:

WR ¬ [((TABH) ´ 100H + (TABL)) ´ 10H + ACC]

Description:

The contents of the look-up table ROM location addressed by TABH, TABL

and ACC are loaded to R.

MOVC WR, #I

Move look-up table ROM addressed by #I and ACC to WR

1

0

1

0

1

W3 W2 W1

W0 I6 I5 I4 I3 I2 I1 I0

Machine code:

Machine Cycle:

Operation:

2

WR ¬ [(I6 ~ I0) ´ 10H + (ACC)]

Description:

The contents of the look-up table ROM location addressed by I6 to I0 and

the ACC are loaded to R.

NOP

No Operation

0

Machine Code:

1

Machine Cycle:

Operation:

No Operation

Publication Release Date: March 1998

Revision A3

- 79 -

W741C260

Instruction Set Table 2, continued

ORL R, ACC

Machine Code:

Machine Cycle:

OR R to ACC

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC ¬ (R) Ù (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are ORed and the result is loaded into the ACC.

Flag Affected:

ZF

ORL WR , #I

OR immediate data to WR

Machine Code:

Machine Cycle:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC ¬ (WR) Ù I

Description:

The contents of the Working Register (WR) and the immediate data I are

ORed and the result is loaded into the ACC.

Flag Affected:

ZF

ORLR R, ACC

OR R to ACC

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (R) Ù (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are ORed and the result is placed in the data memory and the ACC.

Flag Affected:

ZF

- 80 -

W741C260

Instruction Set Table 2, continued

ORLR WR , #I

OR immediate data to WR

Machine Code:

0

1

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

1

Operation:

ACC, WR ¬ (WR) Ù I

Description:

The contents of the Working Register(WR) and the immediate data I are

ORed and the result is placed in the WR and the ACC.

Flag Affected:

ZF

RLC

R

Rotate Left R with CF

Machine Code:

Machine Cycle:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC.n, R.n ¬ R.n-1; ACC.0, R.0 ¬ CF; CF ¬ R.3

Description:

The contents of the ACC and the data memory location addressed by R6 to

R0 are rotated left one bit, bit 3 is rotated into CF, and CF rotated into bit 0

(LSB). The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

RRC

R

Rotate Right R with CF

Machine Code:

Machine Cycle:

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC.n, R.n ¬ R.n+1; ACC.3, R.3 ¬ CF; CF ¬ R.0

Description:

The contents of the ACC and the data memory location addressed by R6 to

R0 are rotated right one bit, bit 0 is rotated into CF, and CF is rotated into

bit 3 (MSB). The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

Publication Release Date: March 1998

- 81 -

Revision A3

W741C260

Instruction Set Table 2, continued

RTN

Return from subroutine

Machine Code:

Machine Cycle:

0

1

0

1

Operation:

(PC) ¬ STACK

Description:

The program counter (PC10 to PC0) is restored from the stack. A return

from a subroutine occurs.

SBC R, ACC

Machine Code:

Machine Cycle:

Subtract ACC from R with Borrow

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC ¬ (R) - (ACC) - (CF)

Description:

The contents of the ACC and CF are binary subtracted from the contents of

the data memory location addressed by R6 to R0 and the result is loaded

into the ACC.

Flag Affected:

CF & ZF

SBC WR, #I

Subtract immediate data from WR with Borrow

Machine Code:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

Operation:

1

ACC ¬ (WR) - I - (CF)

Description:

The immediate data I and CF are binary subtracted from the contents of

the WR and the result is loaded into the ACC.

Flag Affected:

CF & ZF

- 82 -

W741C260

Instruction Set Table 2, continued

SBCR R, ACC

Subtract ACC from R with Borrow

Machine Code:

0

R6

0

1

0

1

0

R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC, R ¬ (R) - (ACC) - (CF)

The contents of the ACC and CF are binary subtracted from the contents of

the data memory location addressed by R6 to R0 and the result is placed in

the ACC and the data memory.

Description:

Flag Affected:

CF & ZF

SBCR WR, #I

Subtract immediate data from WR with Borrow

Machine Code:

Machine Cycle:

0

1

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC, R ¬ (WR) - I - (CF)

Description:

The immediate data I and CF are binary subtracted from the contents of

the WR and the result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

SET

CF

Set CF

0

1

0

1

0

1

0

Machine Code:

1

Machine Cycle:

Operation:

Set CF

Set Carry Flag to 1.

CF

Description:

Flag Affected:

Publication Release Date: March 1998

Revision A3

- 83 -

W741C260

Instruction Set Table 2, continued

SET PMF, #I

Set ParaMeter Flag

Machine Code:

0

1

0

1

0

I3 I2 I1 I0

Machine Cycle:

Operation:

1

Set Parameter Flag

Description:

Description of each flag:

I0, I1, I2 : Reserved

I3 = 1 : The input clock of the watchdog timer is Fosc/16384.

SHLC

R

SHift Left R with CF and LSB = 0

Machine Code:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

ACC.n, R.n ¬ R.n-1; ACC.0, R.0 ¬ 0; CF ¬ R.3

Description:

The contents of the ACC and the data memory location addressed by R6 to

R0 are shifted left one bit, but bit 3 is shifted into CF, and bit 0 (LSB) is

replaced with "0." The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

SHRC

R

SHift Right R with CF and MSB = 0

Machine Code:

Machine Cycle:

0

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC.n, R.n ¬ R.n+1; ACC.3, R.3 ¬ 0; CF ¬ R.0

Description:

The contents of the ACC and the data memory location addressed by R6 to

R0 are shifted right one bit, but bit 0 is shifted into CF, and bit 3 (MSB) is

replaced with "0." The same contents are loaded into the ACC.

Flag Affected:

CF & ZF

- 84 -

W741C260

Instruction Set Table 2, continued

SKB0

R

If bit 0 of R is equal to 1 then skip

Machine Code:

Machine Cycle:

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

PC ¬ (PC) + 2; if R.0 = "1"

Description:

If bit 0 of R is equal to 1, the program counter is incremented by 2 and a

skip is produced. If bit 0 of R is not equal to 1, the program counter (PC) is

incremented.

SKB1

R

If bit 1 of R is equal to 1 then skip

Machine Code:

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

PC ¬ (PC) + 2; if R.1 = "1"

Description:

If bit 1 of R is equal to 1, the program counter is incremented by 2 and a

skip is produced. If bit 1 of R is not equal to 1, the program counter (PC) is

incremented.

SKB2

R

If bit 2 of R is equal to 1 then skip

Machine Code:

1

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

PC ¬ (PC) + 2; if R.2 = "1"

Description:

If bit 2 of R is equal to 1, the program counter is incremented by 2 and a

skip is produced. If bit 2 of R is not equal to 1. The program counter (PC) is

incremented.

Publication Release Date: March 1998

- 85 -

Revision A3

W741C260

Instruction Set Table 2, continued

SKB3

R

If bit 3 of R is equal to 1 then skip

Machine Code:

1

0

1

0

1

0

1

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

Operation:

1

PC ¬ (PC) + 2; if R.3 = "1"

Description:

If bit 3 of R is equal to 1, the program counter is incremented by 2 and a

skip is produced. If bit 3 of R is not equal to 1, the program counter (PC) is

incremented.

STOP

Enter the STOP mode

Machine Code:

0

1

0

Machine Cycle:

1

Operation:

STOP oscillator

Description:

Device enters STOP mode. When the falling edge signal of RC port is

accepted, the mC will wake up and execute the next instruction.

SUB R, ACC

Subtract ACC from R

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC ¬ (R) - (ACC)

Description:

The contents of the ACC are binary subtracted from the contents of the

data memory location addressed by R6 to R0 and the result is loaded into

the ACC.

Flag Affected:

CF & ZF

- 86 -

W741C260

Instruction Set Table 2, continued

SUB WR , #I

Subtract immediate data from WR

Machine Code:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

1

Operation:

ACC ¬ (WR) - I

Description:

The immediate data I are binary subtracted from the contents of the WR

and the result is loaded into the ACC.

Flag Affected:

CF & ZF

SUBR R, ACC

Subtract ACC from R

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

0

1

Operation:

ACC, R ¬ (R) - (ACC)

Description:

The contents of the ACC are binary subtracted from the contents of the

data memory location addressed by R6 to R0 and the result is placed in the

ACC and the data memory.

Flag Affected:

CF & ZF

SUBR WR , #I

Subtract immediate data from WR

Machine Code:

Machine Cycle:

0

1

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC, WR ¬ (WR) - I

Description:

The immediate data I are binary subtracted from the contents of the WR

and the result is placed in the ACC and the WR.

Flag Affected:

CF & ZF

Publication Release Date: March 1998

- 87 -

Revision A3

W741C260

Instruction Set Table 2, continued

XRL R, ACC

Exclusive OR R to ACC

Machine Code:

0

1

0

R6 R5 R4 R3 R2 R1 R0

Machine Cycle:

1

Operation:

ACC ¬ (R) EX (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are exclusive-ORed and the result is loaded into the ACC.

Flag Affected:

ZF

XRL WR, #I

Exclusive OR immediate data to WR

Machine Code:

Machine Cycle:

0

1

0

I3 I2 I1 I0 W3 W2 W1 W0

1

Operation:

ACC ¬ (WR) EX I

Description:

The contents of the Working Register (WR) and the immediate data I are

exclusive-ORed and the result is loaded into the ACC.

Flag Affected:

ZF

XRLR R, ACC

Exclusive OR R to ACC

Machine Code:

Machine Cycle:

0

1

0

1

0

R6 R5 R4 R3 R2 R1 R0

1

Operation:

ACC, R ¬ (R) EX (ACC)

Description:

The contents of the data memory location addressed by R6 to R0 and the

ACC are exclusive-ORed and the result is placed in the data memory and

the ACC.

Flag Affected:

ZF

- 88 -

W741C260

Instruction Set Table 2, continued

XRLR WR, #I

Exclusive OR immediate data to WR

Machine Code:

0

1

0

1

I3 I2 I1 I0 W3 W2 W1 W0

Machine Cycle:

1

Operation:

ACC, WR ¬ (WR) EX I

Description:

The contents of the Working Register(WR) and the immediate data I are

exclusive-ORed and the result is placed in the WR and the ACC.

Flag Affected:

ZF

Publication Release Date: March 1998

- 89 -

Revision A3

W741C260

PACKAGE DIMENSION

80-Lead QFP

D

H

D

80

65

64

1

E

H_E

24

41

25

40

e

b

c

2

A

q

1

See Detail F

L

A

y

Seating Plane

L ₁

Detail F

Dimension in Inches

Min. Max.

0.130

Dimension in mm

Symbol

Min.

Nom.

Max.

3.30

A

b

0.004

0.10

1

2

0.107 0.112 0.117 2.73

2.85

0.35

2.97

0.45

0.012

0.004

0.30

0.10

0.014 0.018

0.006

0.15

0.25

0.010

c

14.00

20.00

0.80

13.87

19.87

0.65

0.546 0.551 0.556

14.13

20.13

0.95

D

E

e

0.792

0.037

0.752

0.782 0.787

0.031

0.740

0.976

0.025

0.728

0.964

18.80 19.10

18.49

D

H

L

y

0.988 24.49 24.80 25.10

E

1.00 1.20

1.40

2.62

0.055

0.103

0.004

0.047

0.094

0.039

0.087

2.21

0

2.40

1

0.10

12

0

12

q

- 90 -

W741C260

Notes:

Publication Release Date: March 1998

Revision A3

- 91 -

W741C260

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792766

123 Hoi Bun Rd., Kwun Tong,

Winbond Microelectronics Corp.

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

http://www.winbond.com.tw/

Voice & Fax-on-demand: 886-2-27197006

TEL: 408-9436666

FAX: 408-5441798

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

- 92 -


型号：	W741C260
厂家：	WINBOND
描述：	4-BIT MICROCONTROLLER 4位微控制器微控制器和处理器外围集成电路时钟
文件：	总92页 (文件大小：478K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W741C260 [WINBOND]

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