W78C154P-24 [WINBOND]
Microcontroller, 8-Bit, MROM, 8051 CPU, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | W78C154P-24 |
| 厂家： | 
WINBOND |
| 描述： | Microcontroller, 8-Bit, MROM, 8051 CPU, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44 时钟 微控制器 外围集成电路 |
| 文件： | 总17页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78C154
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C154 is an single-chip 8-bit microcontroller that is functionally compatible with the standard
80C52 microcontroller series. Like the W78C52, the W78C154 has the following features (except that
it has 16K bytes of on-chip ROM, and P1.6 and P1.7 are open-drain output. See Page 12 Application
Note.) 256 bytes of on-chip scratchpad RAM, four 8-bit bidirectional parallel ports, three 16-bit
timer/counters, one full duplex serial port, a six-source two-level interrupt structure, an on-chip
oscillator and clock circuitry.
The W78C154 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
· 8-bit CMOS microcontroller
· Fully static design
· Low standby current at full supply voltage
· DC-40 MHz operation
· 256 bytes of on-chip scratchpad RAM
· 16K bytes of on-chip mask ROM
· 64K bytes program memory address space
· 64K bytes data memory address space
· Four 8-bit bidirectional ports
· Additional open-drain output port pins: P1.6 and P1.7
· Three 16-bit timer/counters
· One full duplex serial port
· Boolean processor
· Six-source, two-level interrupt capability
· Built-in power management
· Code protection
· Packages:
- DIP 40: W78C154-16/24/40
- PLCC 44: W78C154P-16/24/40
- QFP 44: W78C154F-16/24/40
- TQFP 44: W78C154M-16/24/40
Publication Release Date: October 1997
- 1 -
Revision A5
W78C154
PIN CONFIGURATIONS
40-Pin DIP (W78C154)
1
VCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
P1.4
P1.5
P1.6
4
5
6
7
8
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin QFP/TQFP (W78C154F/W78C154M)
44-Pin PLCC (W78C154P)
T
2
E
X
,
T
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
2
E
X
,
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
T
2
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
V
C
C
V
C
C
N
C
N
C
1
0
3
4
3
2
0
1
2
1
0
3
4
3
2
0
1
2
34
33
43 42 41 40
38 37 36
35
39
44
40
6
5
4
3
2
1 44 43 42
41
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
1
2
7
8
9
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P1.5
P1.6
39
38
37
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
P1.7
10
11
12
13
14
15
36
35
34
33
32
31
RST
RXD, P3.0
RXD, P3.0
Vss
Vcc
Vss
Vcc
TXD, P3.1
*
*
*
*
TXD, P3.1
ALE
ALE
INT0, P3.2
INT1, P3.3
T0, P3.4
INT0, P3.2
PSEN
P2.7, A15
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
10
11
12
24
23
P2.6, A14
P2.5, A13
16
17
30
29
P2.6, A14
P2.5, A13
T1, P3.5
T1, P3.5
13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
P
3
.
7
,
/
X
T
A
L
2
X
T
A
L
1
V
S
S
N
C
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
3
,
A
1
1
P
2
.
4
,
A
1
2
P
2
.
V
S
S
N
C
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
P
2
.
0
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
P
2
.
4
,
A
1
2
2
,
6
,
7
,
3
,
A
1
0
/
/
A
1
1
W R
R
W R
D
R
D
It is recommended that connect Vcc to pin 6 and Vss to pin 28 in PQFP.
It is recommended that connect Vcc to pin 12 and Vss to pin 34 in PLCC.
*
*
- 2 -
W78C154
PIN DESCRIPTION
P0.0-P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0-P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port. Pins P1.0 to P1.5 have internal pull-ups,
while P1.6 and P1.7 are open-drain configured. External pull-ups 4.7K to 10K resistor are required for
P1.6 and P1.7 while P1 is used as a output port. Pins P1.0 and P1.1 also serve as T2 (Timer 2
external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0-P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0-P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
T0 Timer 0 Input
P3.4
P3.5
P3.6
T1 Timer 1 Input
WR Data Write Strobe
RD Data Read Strobe
P3.7
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78C32 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
Publication Release Date: October 1997
- 3 -
Revision A5
W78C154
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state during
reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
RAM
SFR
256
Bytes
Port 0
Port 1
Alternate
Timer 2
CPU
Port 2
Port 3
Alternate
Data Bus
CORE
Serial
Port
ROM
16K
Timer 0
Timer 1
Bytes
Interrupt
INT 0
INT 1
- 4 -
W78C154
FUNCTION DESCRIPTION
The W78C154 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78C154: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78C154 is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C154 relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C154 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is by a
reset.
Publication Release Date: October 1997
- 5 -
Revision A5
W78C154
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C154 is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
VDD- VSS
VIN
MIN.
-0.3
MAX.
+7.0
UNIT
V
Input Voltage
VSS -0.3
0
VDD +0.3
70
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC CHARACTERISTICS
VCC- VSS = 5V ±10%, TA = 25° C, FOSC. = 20 MHz unless otherwise specified.
PARAMETER
SYM.
TEST
SPECIFICATION
UNIT
CONDITIONS
MIN.
MAX.
5.5
4.5
-
V
Operating Voltage
VDD
IDD
35
mA
Operating Current
No load
VDD = 5.5V
-
-
7
50
mA
mA
V
Idle Current
IIDLE
IPWDN
VIL
Idle mode
VDD = 5.5V .
Power-down mode
VDD = 5.5V
Power Down Current
0
0.2 VDD -0.1
Input Low Voltage
(except EA , P1.6, P1.7)
0
0
0.2 VDD -0.3
0.3 VDD
V
V
VIL1
VIL2
Input Low Voltage EA
Input Low Voltage
P1.6, P1.7
- 6 -
W78C154
DC Characteristics, continued
PARAMETER
SYM.
TEST
SPECIFICATION
UNIT
CONDITIONS
MIN.
MAX.
VIH
0.2 VDD +0.9
VDD +0.2
V
Input High Voltage (except EA ,
P1.6, P1.7)
0.7 VDD
0.7 VDD
-
V
V
V
Input High Voltage XTAL1, RST
Input High Voltage P1.6, P1.7
Output Low Voltage P1, P2, P3
(except P1.6, P1.7)
VIH1
VIH2
VOL
VDD +0.2
6.0
IOL = +1.6 mA
IOL = +3.2 mA
0.45
-
0.45
V
Output Low Voltage
P0, ALE, PESN
VOL1
IOL = +3.0 mA
-
0.4
-
V
V
Output Low Voltage P1.6, P1.7
VOL2
VOH
2.4
IOH = -60 mA
Output High Voltage P1, P2, P3,
ALE, PESN (except P1.6, P1.7)
2.4
-75
37
-
-10
110
-
V
IOH = -800 mA
Output High Voltage P0
(in external bus mode)
VOH1
IIL1
VDD = 5.5V
VIN = 0V
mA
mA
mA
Logical 0 Input Current P1, P2,
P3 (except P1.6, P1.7)
Input Current RST (*1)
VDD = 5.5V
VIN = 5.5V
IIL2
VDD = 5.5V
VIN » 2V (*2)
-650
Logical 1-to-0 Transition Current
P1, P2, P3 (*2)
(except P1.6, P1.7)
ITL
VDD = 5.5V
-10
-10
10
10
mA
mA
Input Leakage Current
P0, EA
IL1
IL2
0V < VIN < 5.5V
VDD = 5.5V
Input Leakage Current
P1.6, P1.7
0V < VIN < 6.0V
Notes:.
*1. The RST pin has an internal pull-down resistor of about 50K to 150 KW.
*2. Pins of P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2V.
Publication Release Date: October 1997
- 7 -
Revision A5
W78C154
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 1.2 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
TCP
FOP,
PARAMETER
Operating Speed
Clock Period
Clock High
SYMBOL
FOP
MIN.
TYP.
MAX.
UNIT
MHz
nS
NOTES
0
-
-
-
-
40
-
1
2
3
3
TCP
25
10
10
TCH
-
nS
Clock Low
TCL
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
TYP.
MAX.
UNIT
nS
NOTES
Address Valid to ALE Low
Address Hold after ALE Low
-
-
-
-
-
-
-
4
1, 4
4
1 TCP -D
1 TCP -D
1 TCP -D
-
TAAH
nS
TAPL
nS
ALE Low to PSEN Low
PSEN Low to Data Valid
TPDA
2 TCP
nS
2
- 8 -
W78C154
Program Fetch Cycle, continued
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
TPDH
0
0
-
1 TCP
nS
nS
nS
nS
3
Data Hold after PSEN High
TPDZ
TALW
TPSW
-
1 TCP
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
-
-
4
4
2 TCP -D
3 TCP -D
PSEN Pulse Width
Notes:
1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "D" ( due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold after RD High
Data Float after RD High
RD Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT NOTES
TDAR
-
nS
nS
nS
nS
nS
1, 2
1
3 TCP -D
3 TCP +D
4 TCP
2 TCP
2 TCP
-
TDDA
TDDH
TDDZ
TDRD
-
-
0
0
-
-
6 TCP
2
6 TCP -D
Notes:
1. Data memory access time is 8 TCP.
2. "D" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
TDAW
-
3 TCP -D
1 TCP -D
1 TCP -D
3 TCP +D
TDAD
TDWD
TDWR
-
-
-
-
-
nS
nS
6 TCP
nS
6 TCP -D
Note: "D" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: October 1997
- 9 -
Revision A5
W78C154
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
T
APL
PSEN
PSW
T
TAAS
A8-A15
TPDA
PORT 2
PORT 0
T
AAH
TPDZ
TPDH,
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
T
T
DAR
DDA
T
T
DDH, DDZ
T
DRD
- 10 -
W78C154
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
T
DWD
T
DAD
T
DWR
T
DAW
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
DATA OUT
TPDH
PORT
INPUT
SAMPLE
Publication Release Date: October 1997
Revision A5
- 11 -
W78C154
APPLICATION NOTE
1. Application
(1) It is recommanded to use port1.6 & port1.7 as an input port due to the port1.6 & port1.7 is an open
drain.
(2) An approximate 4.7K to 10K pull-up resistor is required when port1.6 & port1.7 is used as output
port.
V
DD
V
DD
port1.6
port1.7
port1.6
port1.7
Output Port
Input Port
2. Verification & Emulation
(1) WHC8302 verification board (W78V58B on board) and W78958B emulation chip will check
W78C154 except port1.6 & port1.7 as output mode.
W78V58B
W78V958B
W78C154
Port1.6 & Port1.7
Port1.6 & Port1.7
Port1.6 & Port1.7
Pull-ups
Pull-ups
Open Drain
(2) The specification of W78C154 is exclusive, therefore, the dc characteristics are not fully compatible
with W78V58B and W78958B, however the function is still the same as W78V58B and W78958B.
- 12 -
W78C154
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V
CC
V
CC
31
19
AD0
39
3
4
7
11
12
13
AD0
AD1
AD2
AD0
AD1
AD2
2
A0
A1
A2
A3
A4
A5
A6
A7
A0
5 A1
A2
10
9
8
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
X1
38 AD1
AD2
A1
37
36 AD3
6
A2
A3
A4
AD3 8
9 A3
12
15 A5
16
19
15 AD3
10 u
C1
7
AD4
AD5
AD6
AD7
A4
35
34
33
32
13
14
17
16
17
18
AD4
AD5
AD6
6
AD4
AD5
AD6
R
(*2)
18
9
5
X2
A5
A6
A7
CRYSTAL
4
3
A6
AD718
19 AD7
A7
8.2 K
RESET
INT0
A8 25
A8
A9
1
GND
21 A8
A9
A10
A11
A12
24
21
23
2
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
C2
(*1)
22
11
A9
A10
A11
A12
A13
A14
A15
23
24
25
26
27
12
13
14
15
A10
A11
A12
A13
A14
INT1
T0
T1
74LS373
A13 26
A14
A15
27
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
28 A15
1
2
3
4
5
6
7
8
GND
20
22
CE
OE
RD
WR
PSEN
ALE
TXD
17
16
29
30
11
10
27512
(*1)
Open Drain
Open Drain
RXD
W78C154
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
30P
15P
10P
5P
R
-
-
6.8K
6.8K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A.
2. An approximately 4.7K to 10K pull-ups resistor is required for P1.6 and P1.7 when they are used as output port.
Publication Release Date: October 1997
Revision A5
- 13 -
W78C154
Typical Applicatin Circuits, continued
Expanded External Data Memory and Oscillator
V
CC
V
CC
31
19
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0 10
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1 4
3
A0
A1
39 AD0
AD1
2
5
6
9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
EA
X1
9
8
7
6
5
4
3
A1
38
37 AD2
A2 A2
AD2
AD3
AD4
AD5 14
AD6 17
AD7 18
7
8
13
OSCILLATOR
A3
A3
10 u
AD3
AD4
AD5
36
35
34
A4
12 A4
18
9
X2
15 A5 A5
33 AD6
A6
16
A6
8.2 K
32
AD7
19 A7 A7
A8 25
A9 24
RESET
INT0
GND
1
21
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
A8
A9
11
21
23
A10
A11
22
23
24
25
26
27
28
A10
A11
A12
A13
12
13
14
15
A10
A11
A12
A13
A14
A12 2
74LS373
INT1
T0
T1
26
1
A13
A14
A14
GND
CE
OE
20
22
27
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
17
WR
WR 16
29
20256
PSEN
30
11
10
ALE
TXD
RXD
Open Drain
Open Drain
W78C154
Figure B
- 14 -
W78C154
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.210
Max.
5.334
0.010
0.150
0.016
0.048
0.008
0.254
1
A
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
3.81
3.937 4.064
0.457 0.559
2
A
0.406
1.219
0.203
B
1.27
0.254
52.20
15.24
13.84
2.54
1.372
0.356
52.58
15.494
13.97
2.794
1
B
c
D
E
D
40
21
0.590 0.600
14.986
13.72
0.540
0.090
0.120
0
0.545
0.100
0.550
0.110
1
E
2.286
1
e
0.140 3.048
3.302
0.130
3.556
15
1
E
L
a
15
0
17.01
0.630 0.650
0.670
0.090
16.00
16.51
A
e
S
2.286
1
20
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
A2
A
Base Plane
1
A
.
L
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
e
A
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B 1
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.185
Max.
7
39
4.699
0.020
0.508
A
1
0.145 0.150 0.155 3.683 3.81
3.937
0.813
0.559
A2
0.026 0.028 0.032 0.66
0.022 0.406
0.711
0.457
b
b
c
1
0.016 0.018
H E
GE
E
0.008 0.010 0.014 0.203 0.254
0.356
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
0.648 0.653 0.658
D
E
e
BSC
0.050
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
0.610 0.630
0.610 0.630
0.690 0.700
17
29
GD
E
G
18
28
D
H
c
17.27
0.700
17.53 17.78
0.690
H
L
y
E
0.090 0.100
2.54
0.110 2.296
0.004
2.794
0.10
L
Notes:
A 2
A1
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
q
e
b
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
Seating Plane
y
G D
Publication Release Date: October 1997
Revision A5
- 15 -
W78C154
Package Dimensions, continued
44-pin QFP
H D
D
Dimension in mm
Dimension in inch
Symbol
A
Nom.
---
Nom.
---
Min.
---
Max. Min.
Max.
---
34
44
---
---
0.002
0.075
0.01
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
A
0.081 0.087
2.20
0.45
A
b
c
2
33
1
0.014
0.006
0.394
0.394
0.031
0.520
0.018
0.010
0.398
0.35
0.101
9.9
0.152
10.00
0.254
0.004
0.390
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
D
E
e
9.9
0.398
0.036
0.530
0.530
0.037
10.00
0.80
0.390
0.025
0.510
E
HE
0.635
12.95
12.95
0.65
13.2
13.2
0.8
D
E
H
0.510 0.520
0.025
H
L
L
y
11
0.031
0.051 0.063 0.075
0.003
1.295
1.6
1
12
22
e
b
7
q
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
q
A1
L
See Detail F
y
Seating Plane
L
1
Detail F
44-pin TQFP
H D
D
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
34
44
---
---
---
---
1.20
0.047
0.006
0.041
0.002
0.037
0.004
0.039
0.10
1.00
0.05
0.95
0.15
1.05
1
A
2
A
33
1
0.0039 0.013
0.22
0.090
9.9
0.38
0.015
0.008
0.398
0.32
---
b
c
D
E
e
0.200
0.004
0.390
---
0.394
10.00
10.1
10.1
0.952
12.10
12.10
0.75
---
9.9
0.394
0.031
0.472
0.472
0.024
0.039
0.398
0.390
0.025
0.468
10.00
0.80
E
HE
0.036
0.476
0.635
11.90
11.90
0.45
---
12.00
12.00
0.60
D
H
0.468
0.018
---
0.476
0.030
---
E
H
11
L
1.00
1
L
0.003
7
0.08
7
y
q
12
22
e
b
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
A
A2
A1
q
L
See Detail F
y
Seating Plane
L 1
Detail F
- 16 -
W78C154
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792697
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
TEL: 408-9436666
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: October 1997
Revision A5
- 17 -
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