W78C438C40FL [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78C438C40FL |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总22页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78C438C Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 2
FEATURES................................................................................................................................. 2
PIN CONFIGURATIONS ............................................................................................................ 3
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION ................................................................................................... 7
5.1
5.2
5.3
5.4
5.5
5.6
Dedicated Data and Address Port.................................................................................. 7
Additional I/O Port........................................................................................................... 9
Additional External Interrupt ........................................................................................... 9
Newly Added Special Function Registers .................................................................... 11
Power Reduction Function ........................................................................................... 11
Programming Difference............................................................................................... 12
6.
7.
ELECRICAL CHARACTERISTICS........................................................................................... 13
6.1
6.2
6.3
Absolute Maximum Ratings.......................................................................................... 13
D.C. Characteristics...................................................................................................... 13
A.C. Characteristics...................................................................................................... 14
6.3.1 Clock Input Waveform ....................................................................................................14
6.3.2 Program Fetch Cycle......................................................................................................14
6.3.3 Data Memory Read/Write Cycle .....................................................................................15
TIMING WAVEFORMS............................................................................................................. 16
7.1
7.2
Program Fetch Cycle.................................................................................................... 16
Data Memory Read/Write Cycle................................................................................... 17
8.
9.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 18
8.1 Using 128K × 8 bit External EPROM (W27E010) ........................................................ 18
PACKAGE DIMENSIONS......................................................................................................... 20
9.1
9.2
84-pin PLCC ................................................................................................................. 20
100-pin QFP.................................................................................................................. 21
10.
REVISION HISTORY................................................................................................................ 22
Publication Release Date: December 4, 2006
- 1 -
Revision A6
W78C438C
1. GENERAL DESCRIPTION
The W78C438C is a high-performance single-chip CMOS 8-bit microcontroller that is a derivative of
the W78C58 microcontroller family. The W78C438C is functionally compatible with the W78C32,
except that it provides either a 64 KB program/1 MB data memory address or memory-mapped chip
select logic, five general I/O ports, and four external interrupts.
In the W78C32, two I/O ports, Port 1 and Port 3, are available for general-purpose use (Port 3 also
supports alternative functions), and Port 2 and Port 0 are used as the address bus and data bus,
respectively. To enable Port 0 and Port 2 to also be used as general purpose I/O ports, the
W78C438C provides two dedicated address ports (AP5 and AP6) that serve as address output for 64
KB of memory and one address/data port (DP4) that serves as ROM code input and external RAM
data input/output. Unlike the W78C32, this product does not require an external latch device for
multiplexing low byte addresses. The W78C438C also provides four pins (AP7.0−AP7.3) to support
either 64 KB program/1 MB data memory space or memory-mapped chip select logic, one parallel I/O
port (Port 8) without bit addressing mode, and two additional external interrupts (INT2 , INT3 ) .
The W78C438C is programmed in a manner fully compatible with that used to program the W78C32,
except that the external data RAM is accessed by the "MOVX @Ri" instruction. Address paging is
performed by loading page addresses into the HB (high byte) register, which is not a standard register
in the W78C32, before execution of the "MOVX @Ri" instruction.
2. FEATURES
y
y
y
y
y
y
y
y
y
8-bit CMOS microcontroller
Fully static design
DC to 40 MHz operation
ROM-less operation
256-byte on-chip scratchpad RAM
Either 64 KB program/1 MB data memory address space or 4 memory-mapped chip select pins
One 8-bit data/address port
Two 8-bit and one 4-bit (optional) address ports
Five 8-bit bidirectional I/O ports
− Four 8-bit bit-addressable I/O ports and one 8-bit parallel I/O port
Eight-source, two-level interrupt capability
Three 16-bit timer/counters
y
y
y
y
y
Four external interrupts
One full-duplex serial channel
Built-in power management
− Idle mode
− Power-down mode
y
Packages:
− Lead Free (RoHS) PLCC 84:
W78C438C40PL
− Lead Free (RoHS) PQFP 100: W78C438C40FL
- 2 -
W78C438C
3. PIN CONFIGURATIONS
D
P
4
.
D D
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
4
.
P
4
.
P
0
.
P
0
.
P
0
.
P
0
.
P
0
.
V
D
D
N
C
N
C
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
2
3
4
1
1
1
0
9
8
7
6
5
4
2
1
3
8
4
8
3
8
2
8
1
8
0
7
9
7
8
7
7
7
6
7
5
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
74
P1.5
P1.6
P1.7
RESET
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
INT3
P0.5
P0.6
P0.7
EA
AP5.0
AP5.1
AP5.2
AP5.3
AP5.4
AP5.5
AP5.6
AP5.7
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
W78C438CP
84-pin PLCC
DD
V
VSS
ALE
INT2
RXD, P3.0
VDD
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
PSEN
P2.7
P2.6
P2.5
P2.4
31
32
P2.3
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
4
4
4
5
5
5
5
3
6
7
8
9
0
1
2
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
N
C
A
P
7
.
A
P
7
.
A
P
7
.
A
P
7
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
P
2
.
P
2
.
P
2
.
6
,
7
,
0
1
2
3
,
2
,
1
,
0
,
7
6
5
4
3
2
1
0
/
/
W R
/
/
/
/
R
D
C
S
3
C
S
2
C
S
1
C
S
0
Publication Release Date: December 4, 2006
Revision A6
- 3 -
W78C438C
Pin Configurations, continued
T
2
E
X
,
T
2
,
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
D
P
4
.
P
0
.
P
1
.
P
0
.
P
0
.
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
V
D
D
N
C
N
C
0
0
3
0
1
2
7
6
5
4
3
2
1
3
2
1
4
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
NC
NC
NC
NC
P0.4
P0.5
P0.6
P0.7
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
NC
NC
NC
P1.5
P1.6
P1.7
RESET
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
INT3
INT2
RXD, P3.0
VDD
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
EA
AP5.0
AP5.1
AP5.2
AP5.3
AP5.4
AP5.5
W78C438CF
100-pin PQFP
AP5.6
AP5.7
V DD
SS
V
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
NC
NC
NC
NC
P2.3
NC
NC
NC
NC
3
1
3
3
3
3
3
3
3
8
3
9
4
0
4
4
2
4
4
4
4
4
4
4
5
2
3
4
5
6
7
1
3
4
5
6
7
8
9
0
P
X
V
S
S
N
C
A
P
7
.
A
P
6
.
A
A
X
T
A
L
1
A
P
7
.
A
A
P
7
.
A
A
P
6
.
A
P
6
.
A
A
P
P
2
.
P
3 .
7 ,
/
P
6
.
P
6
.
T
A
L
2
P
7
.
P
6
.
P
6
.
P
2
.
2
.
6 .
0
0
1
2
R
D
3
,
7
6
5
1
,
0
,
2
,
4
3
2
1
/
/
/
/
C
S
3
C
S
1
C
S
0
C
S
2
- 4 -
W78C438C
4. PIN DESCRIPTION
P0.0−P0.7 I/O Port 0
These pins function the same as those in the W78C32, except that a multiplexed address/data bus is
not provided during accesses to external memory.
P1.0−P1.7 I/O Port 1
Functions are the same as in the W78C32.
P2.0−P2.7 I/O Port 2
Functions are the same as in the W78C32, except that an upper address bus is not provided during
accesses to external memory.
P3.0−P3.7 I/O Port 3
Functions are the same as in the W78C32.
DP4.0−DP4.7 Data/Address Bus
DP4 provides multiplexed low-byte address/data during access to external memory.
AP5.0−AP5.7 Address Bus
AP5 outputs the <7:0> address of the external ROM multiplexed with the <7:0> address of the
external data RAM.
AP6.0−AP6.7 Address Bus
AP6 outputs the <15:8> address of the external ROM multiplexed with the <15:8> address of the
external data RAM. During the execution of "MOVX @Ri," the output of AP6 comes from the HB
register, which is the page register for the high byte address, and its address is 0A1H.
AP7.0−AP7.3 Address Bus/Chip Select Pins
Set bit 7 of the EPMA (Extended Program Memory Address) register to determine the functions of port
7. When this bit is "0" (default value), AP7 allows the external memory data to be accessed by
outputting the <19:16> address of the external memory from bits<3:0> of the EPMA register during the
execution of "MOVC A, @A+DPTR" or "MOVX dest, src." At all other times, AP7<3:0> will output 0H.
When this bit is "1," AP7<3:0> (CS3−0) are the chip select pins, which support memory-mapped
peripheral device select, and only one pin is active low at any one time. These pins are decoded by
AP6<7:6>. For details, see the table below.
AP6.7
AP6.6
DESCRIPTION
0
0
1
1
0
1
0
1
AP70: low; others: high
AP71: low; others: high
AP72: low; others: high
AP73: low; others: high
Publication Release Date: December 4, 2006
Revision A6
- 5 -
W78C438C
P8.0−P8.7 I/O Port
Functions are the same as those of Port 1 in the W78C31, except that they are mapped by the P8
register and not bit-addressable. The P8 register is not a standard register in the W78C32. Its address
is at 0A6H.
INT2 , INT3 External Interrupt, Input
Functions are similar to those of external INT0 , INT1 in the W78C32, except that the
functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt
Control) register. The XICON register is bit-addressable but is not a standard register in the W78C32.
Its address is at 0C0H. For details, see the Functional Description below.
EA External Address, Input
Functions same as W78C32.
RST, XTAL1, XTAL2, PSEN, ALE
Functions same as W78C32.
- 6 -
W78C438C
5. FUNCTIONAL DESCRIPTION
The W78C438C is a functional extension of the W78C58 microcontroller. It contains a 256 × 8 RAM,
64 KB program/1 MB data memory address or memory-mapped chip select logic, two 8-bit address
ports, one 8-bit data port, five general I/O ports, four external interrupts, three timers/counters, and
one serial port.
5.1 Dedicated Data and Address Port
The W78C438C provides four general-purpose I/O ports for W78C32 applications; the address and
data bus are separated from Port 0 and Port 2 so that these ports can be used as general-purpose I/O
ports. In this product, DP4 is the data bus for external ROM and RAM, AP5<7:0> are the low byte
address, AP6<7:0> are the high byte address, PSEN enables the external ROM to DP4, and P3.6
( WR) and P3.7 (RD ) are the write/read control signals for the external RAM. The external latch for
multiplexing the low byte address is no longer needed in this product. The W78C438C uses AP5 and
AP6 to support 64 KB external program memory and 64 KB external data memory, just as a standard
W78C32 does.
The W78C438C provides four pins, AP7.3−AP7.0 (CS3−CS0), to support either 64 KB program/1 MB
data memory space or memory-mapped chip select logic. Bit 7 of the EPMA (Extended Program
Memory Address) register, which is described in Table 1 below, determines the functions of these
pins.
When this bit is "0" (the default value), AP7<3:0> support external program/data memory addresses
up to 64 KB/1 MB for applications which need additional external memory to store large amounts of
data.
Although there is 1M bytes memory space, instructions stored here can not be run at full range of this
area except the first 64 Kbytes. It is owing to the fact that during the instruction fetch cycle, AP7<3:0>
always output 0s to address lines A19−A16. This limits the program code to store at address
0−0FFFFH (64K). The rest of the area (10000H−FFFFFH) can be treated as ROM data storage which
can be read by "MOVC A, @A+DPTR" instruction.
When "MOVC A, @A+DPTR" is executed to read the external ROM data or "MOVX dest, src" is
executed to access the external RAM data, AP7<3:0> output address <19:16> from bits <3:0> of the
EPMA (Extended Program Memory Address) register. At other times, AP7<3:0> always output 0H to
ensure the instruction fetch is within the 64K program memory address. Different banks can be
selected by modifying the content of the EPMA register before the execution of "MOVC A, @A+DPTR"
or "MOVX dest, src."
[Example]. Access the external ROM/RAM data from external memory space.
CLR
MOV
MOV
A
; Clear Accumulator.
DPTR, #0H
0A2H, #02
; Clear DPTR.
; Initialize EPMA(0A2H). EPMA.7 = 0: extended memory space
; EPMA.<3:0> = 0010B, the address range: 20000−2FFFFH.
MOVC A, @A+DPTR ; Read the external ROM data from location 20000H.
MOVX A, @DPTR
CLR
MOV
; Read the external RAM data from location 20000H.
A
0A2H, #03H
; EPMA.<3:0> = 0011B, the address range: 30000H−3FFFFH.
MOVC A, @A+DPTR ; Read the external ROM data from location 30000H.
MOVX @DPTR, A
; Write the contents of Accumulator to external RAM data.
; location 30000H.
Publication Release Date: December 4, 2006
- 7 -
Revision A6
W78C438C
(A) EPMA.7 = 0
EPROM
ADDR (20-bit)
W78C438
64K PROGRAM
\ 8
\ 8
\ 4
AP5
P0
AP6
AP7
DP4
P1
P2
DATA AREA
\ 8
OE
PSEN
P8
INT0
INT1
INT2
RAM
ADDR 1MB
(20-bit)
INT3
DATA
P3
RD
WR
WE
OE
When bit 7 of the EPMA is "1," AP7<3:0> are the output pins that support memory-mapped peripheral
chip select logic, which eliminates the need for glue logic. These pins are decoded by AP6<7:6>. Only
one pin is active low at any time. That is, they are active individually with 16K address resolution. For
example, CS0 is active low in the address range from 0000H to 3FFFH, CS1 is active low in the
address range from 4000H to 7FFFH, and so forth.
(B) EPMA.7 = 1
EPROM
ADDR (16-bit)
W78C438
64K PROGRAM
\ 8
\ 8
AP5
AP6
P0
P1
P2
DATA AREA
\ 8
DP4
OE
PSEN
P8
INT0
INT1
INT2
RAM
ADDR (14-bit)
Device
4000h
\ 8
\ 6
Device
Device
C000h
FFFFh
INT3
0000h
8000h
BFFFh
DATA
P3
3FFFh
(16k)
AP7.0
AP7.1
AP7.2
AP7.3
7FFFh
(16k)
RD
(16k)
WR
(16k)
WE
OE
- 8 -
W78C438C
The EPMA register is a nonstandard 8-bit SFR at address 0A2H in the standard W78C32. To
read/write the EPMA register, one can use the "MOV direct" instruction or "read-modify-write"
instructions. Bits <6:4> of the EPMA register are reserved bits, and their output values are 111B if
they are read. The content of EPMA is 70H after a reset. The EPMA register does not support bit-
addressable instructions.
BIT
NAME
FUNCTION
EPMA7 = 0: 64 KB program/1 MB data memory space mode
EPMA7 = 1: memory-mapped chip select mode
7
EPMA7
6
5
4
3
2
1
0
EPMA6
EPMA5
EPMA4
EPMA3
EPMA2
EPMA1
EPMA0
Reserved
Reserved
Reserved
Value of AP7.3
Value of AP7.2
Value of AP7.1
Value of AP7.0
Table 1. Functional Description of EPMA Register
5.2 Additional I/O Port
The W78C438C provides one parallel I/O port, Port 8. Its function is the same as that of Port 1 in the
W78C31, except that it is mapped by the P8 register and is not bit-addressable. The P8 register is not
a standard register in the standard W78C32. Its address is at 0A6H. To read/write the P8 register, one
can use the "MOV direct" instruction or "read-modify-write" instructions.
[Example]: MOV
MOV
0A6H, A
A, 0A6H
; Output data via Port 8.
; Input data via Port 8.
5.3 Additional External Interrupt
The W78C438C provides two additional external interrupts, INT2 and INT3 , whose functions are
similar to those of external interrupts 0 and 1 in the W78C32. The functions (or the status) of these
interrupts are determined by (or shown by) the bits in the XICON (External Interrupt Control) register.
For details, see Table 2. The XICON register is bit-addressable but is not a standard register in the
standard 80C32. Its address is at 0C0H. To set/clear the bit of the XICON register, one can use the
"SETB(CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of XICON. The interrupt
vector addresses and the priority polling sequence within the same level are shown in Table 3.
[Example].
SETB
SETB
SETB
CLR
0C0H
0C3H
0C2H
0C4H
; INT2 is falling-edge triggered.
; INT2 is high-priority.
; Enable INT2 .
; INT3 is low-level triggered.
Publication Release Date: December 4, 2006
Revision A6
- 9 -
W78C438C
BIT ADDR. NAME
FUNCTION
High/low priority level for INT3 is specified when this bit is set/cleared by
software.
7
0C7H
PX3
6
5
0C6H
0C5H
EX3
IE3
Enable/disable interrupt from INT3 when this bit is set/cleared by software.
If IT3 is "1," IE3 is set/cleared automatically by hardware when interrupt is
detected/serviced.
INT3 is falling-edge/low-level triggered when this bit is set/cleared by
software.
4
0C4H
IT3
High/low priority level for INT2 is specified when this bit is set/cleared by
software.
3
2
1
0C3H
0C2H
0C1H
PX2
EX2
IE2
Enable/disable interrupt from INT2 when this bit is set/cleared by software.
If IT2 is "1," IE2 is set/cleared automatically by hardware when interrupt is
detected/serviced.
INT2 is falling-edge/low-level triggered when this bit is set/cleared by
software.
0
0C0H
IT2
Table 2. Functions of XICON Register
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
VECTOR ADDRESS
PRIORITY SEQUENCE
03H
0BH
13H
1BH
0 (Highest)
1
2
3
4
23H
Timer/Counter 2
External Interrupt 2
External Interrupt 3
2BH
33H
3BH
5
6
7 (Lowest)
Table 3. Priority of Interrupts
- 10 -
W78C438C
5.4 Newly Added Special Function Registers
The W78C438C uses four newly defined special function registers, which are described in Table 4. To
read/write these registers, use the "MOV direct" or "read-modify-write" instructions.
R/W
VALUE AFTER
RESET
REGISTER ADDR.
FUNCTION
LENGTH
TYPE
During the execution of "MOVX @Ri,"
the content of HB is output to AP6.
EPMA.7 determines functions of AP7.
1
HB
A1H
A2H
8
R/W
00H
2
3
4
EPMA
P8
8
8
8
R/W
R/W
R/W
70H
0FFH
00H
EPMA.3−EPMA.0 determine values of
AP7<3:0> when EPMA.7 is "0."
A6H The content of P8 is output to port 8.
The bits of XICON determine/show the
XICON
C0H
functions/status of INT2 − INT3 . Bit-
addressable.
Table 4. Newly Added Special Function Registers of the W78C438C
Notes:
1. The instructions used to access these nonstandard registers may cause assembling errors with respect to the 2500 A. D.
assembler, but these errors can be ignored by adding directive ".RAMCHK OFF" ahead these instructions.
2. In the newly added SFR of W78C438C, only XICON register is bit-addressable.
5.5 Power Reduction Function
The W78C438C supports power reduction just as the W78C32 does. The following table shows the
status of the external pins during the idle and power-down modes.
FUNCTION
DP4
AP5, AP6
AP7
P0−P3, P8
ALE, PSEN
Idle
Power Down
1
0
1
0
Port Data
Port Data
Floating
Floating
Address
Address
Note
Note
Note: AP7 is either 0 or a value decoded by AP6<7:6>, depending on the value of EPMA.7.
Publication Release Date: December 4, 2006
Revision A6
- 11 -
W78C438C
5.6 Programming Difference
The W78C438C is programmed in the same way as the W78C32, except that the external data RAM
is accessed by a "MOVX @Ri" instruction. To support address paging, there is an additional 8-bit SFR
"HB" (high byte), which is a nonstandard register, at address 0A1H. During execution of the "MOVX
@Ri" instruction, the contents of HB are output to AP6. The page address is modified by loading the
HB register with a new value before execution of the "MOVX @Ri" instruction. To read/write the HB
register, one can use the "MOV direct" instruction or "read-modify-write" instructions. The HB register
does not support bit-addressable instructions.
[Example].
MOV
MOV
R1, #0H
; R1 = 0.
0A1H, #0FFH ; HB contents FFH.
MOVX A, @R1
; Read the contents of external RAM location FF00H into
; Accumulator.
MOV
0A1H, #12H
; HB contents 12H.
MOVX @R1, A
; Copies the contents of Accumulator into external RAM
; location 1200H.
- 12 -
W78C438C
6. ELECRICAL CHARACTERISTICS
6.1 Absolute Maximum Ratings
PARAMETER
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
SYMBOL
MIN.
-0.3
VSS -0.3
0
MAX.
UNIT
V
V
°C
°C
+7.0
VDD +0.3
70
VDD−VSS
VIN
TOPR
TSTG
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
6.2 D.C. Characteristics
(VDD − VSS = 5V ±10%, TA = 25° C, FOSC = 20 MHz, unless otherwise specified.)
PARAMETER
Oper. Voltage
Oper. Current
Idle Current
SYM.
VDD
TEST CONDITIONS
MIN. TYP. MAX.
UNIT
V
mA
mA
µA
4.5
5
-
-
5.5
20
7
IDD
* No load
Program idle mode
-
-
-
IIDLE
IPWDN
Pwdn Current
Program power-down mode
-
50
INT2 , INT3
Internal pull-high
RESET
Input Leakage
Current
ILK1
ILK2
-300
-10
-
-
+10
µA
µA
Notes 1, 2
Input Leakage
Current
+300
Internal pull-low
Notes 1, 2
Note 1
Input Leakage
Current
Input Leakage
Current
Output Low Voltage
Output High Voltage
ILK3
ILK4
-10
-50
-
-
+10
+10
µA
µA
E, Port 0, DP4
P1, P2, P3, P8
IOL1 = 2 mA
Note 1
VOL1
VOH1
(Port 1, 2, 3, 8)
-
-
-
0.45
-
V
V
2.4
IOH1 = -100 µA (Port 1, 2, 3, 8)
IOL2 = 4mA
Note 3
Note 3
Output Low Voltage
Output High Voltage
VOL2
VOH2
-
-
-
0.45
-
V
V
(ALE, PSEN, P0, DP4)
IOH2 = -400 µA
(ALE, PSEN, P0, DP4)
2.4
Output Low Voltage
Output High Voltage
Input Voltage
VOL3
VOH3
VILT
IOL2 = 2 mA
(AP5, AP6, AP7)
-
-
-
-
-
0.45
-
V
V
V
V
2.4
0
IOH2 = -100 µA (AP5, AP6, AP7)
VDD = 5V ±10%
0.8
Note 4
Input Voltage
VIHT
2.4
VDD = 5V ±10%
Publication Release Date: December 4, 2006
Revision A6
- 13 -
W78C438C
D.C. Characteristics, continued
PARAMETER
SYM.
VILC
VIHC
VILR
VIHR
TEST CONDITIONS
MIN. TYP. MAX.
UNIT
V
Input Voltage
0
-
-
-
-
0.8
VDD = 5V ±10%, XTAL1 Note 5
VDD = 5V ±10%, XTAL1 Note 5
VDD = 5V ±10%, RESET Note 5
VDD = 5V ±10%, RESET Note 5
Note 4
Input Voltage
3.5
0
V
Input Voltage
0.8
V
Note 4
Input Voltage
2.4
V
Notes:
1. 0 < VIN < VDD, for INT2 , INT3, RESET, , Port 0, DP4, P1, P2, P3 and P8 inputs in leakage.
2. Using an internal pull low/high resistor (approx. 30K).
3. ALE, PSEN , P0 and DP4 in external program or data access mode.
4. The maximum input voltage is VDD +0.2V.
5. XTAL1 is a CMOS input and RESET is a Schmitt trigger input.
6.3 A.C. Characteristics
AC specifications are a function of the particular process used to manufacture the product, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation.
6.3.1 Clock Input Waveform
PARAMETER
Operating Speed
Clock Period
Clock High
SYMBOL
FOP
MIN.
0
TYP.
MAX.
UNIT
MHz
nS
NOTES
-
-
-
-
40
-
1
2
3
3
TCP
25
10
10
TCH
-
nS
Clock Low
TCL
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
6.3.2 Program Fetch Cycle
PARAMETER
Address Valid to PSEN Low
PSEN Low to Data Valid
SYMBOL
MIN.
TYP.
MAX.
UNIT
TAPL
2 TCP
-
-
-
nS
TPDV
-
2 TCP
nS
- 14 -
W78C438C
6.3.3 Data Memory Read/Write Cycle
PARAMETER
Address Valid to RD Low
RD Low to Data Valid
Data Hold After RD High
RD Pulse Width
SYMBOL
MIN.
TYP.
MAX.
4 TCP +∆
4 TCP
2 TCP
-
UNIT
TARL
TRDV
TRDQ
TRS
4 TCP
-
nS
-
-
nS
nS
nS
nS
nS
nS
nS
0
-
6 TCP
6 TCP -∆
4 TCP
TAWL
TDWL
TWDQ
TWS
-
4 TCP +∆
Address Valid to WR Low
Data Valid to WR Low
Data Hold After WR High
WR Pulse Width
1 TCP
-
-
-
-
-
1 TCP
6 TCP
6 TCP -∆
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: December 4, 2006
Revision A6
- 15 -
W78C438C
7. TIMING WAVEFORMS
7.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
PSEN
TAPL
AP6<7:0>
AP5<7:0>
address
TPDV
code
DP4<7:0>
address
- 16 -
W78C438C
7.2 Data Memory Read/Write Cycle
S4
S5
S6
S7
S8
S9
S10 S11 S12 S1
S2
S3
XTAL1
PSEN
AP7<3:0>
addr <19:16> out
(When bit7 of EPMA is 0.)
AP6<7:0>
PGM address
PGM address
DPH or HB SFR out
DPL or Ri out
AP5<7:0>
T
ARL
T
RS
RD
T
RDQ
T
RDV
DP4<7:0>
WR
addr.
addr.
data
T
WS
T
AWL
DP4<7:0>
addr.
DATA OUT
T
T
WDQ
DWL
Publication Release Date: December 4, 2006
Revision A6
- 17 -
W78C438C
8. TYPICAL APPLICATION CIRCUITS
8.1 Using 128K × 8 bit External EPROM (W27E010)
1
0
0
9
9
9
8
9
7
9
6
9
5
9
4
9
3
9
2
9
1
9
0
8
9
8
8
8
7
8
6
8
5
8
4
8
3
8
2
8
1
N P
C 1
.
P
1
.
P
1
.
P
1
.
P
1
.
D
P
4
.
D
P
4
.
D D
D
P
4
.
D
P
4
.
D
P
4
.
D V
P
P
0
.
P P
N
C
P
4
.
P
4
.
P
4
.
D 0
D .
0
0
.
0
.
4
3
2
1
0
1
2
3
80
79
78
77
1
2
3
4
5
6
7
8
9
NC
NC
NC
NC
NC
NC
NC
NC
7
6
5
4
3
2
1
0
P0.4 76
P1.5
P1.6
P1.7
RESET
P8.0
75
P0.5
P0.6
P0.7
EA
AP5.0
AP5.1
74
73
72
71
70
10 U
5 V
12
13
A0
O0
11
14
A1
8.2 K
O1
10
15
A2
O2
10 P8.1
11
9
8
17
A3
O3
18
A4
O4
P8.2
7
19
A5
O5
6
20
AP5.2 69
AP5.3 68
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
P8.3
P8.4
P8.5
P8.6
P8.7
INT3
INT2
P3.0, RXD
VDD
P3.1, TXD
P3.2, INT0
P3.3, INT1
P3.4, T0
P3.5, T1
A6
O6
5
21
A7
O7
27
26
23
25
4
A8
A9
67
AP5.4
W27E010
A10
A11
A12
A13
A14
A15
AP5.5 66
W78C438C
65
AP5.6
1
32
31
28
29
3
Vpp
Vcc
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AP5.7
VDD
VSS
ALE
PSEN
P2.7
P2.6
P2.5
P2.4
NC
NC
NC
2
A16
PGM
22
24
GND
CE
OE
16
Vss
P3.6, WR
27 NC
28
29
30
NC
NC
NC
NC
P2.3
A
P
7
.
A
A
P
7
.
A
P
7
.
P
7
.
P
3
.
3
,
2
,
1
,
0
,
A
P
6
.
A
P
6
.
7
,
X
T
A
L
2
X
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
A
P
6
.
/
/
/
/
P
2
.
T
P
P
C C
C
S
1
C
S
0
/
A V
2
.
2
.
N
S
3
S
2
R
D
L
S
S
C
5
0
2
1
7
6
4
3
2
1
0
1
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
5
1
2
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
R
C1
C2
Figure A
- 18 -
W78C438C
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
30P
15P
10P
5P
R
−
−
6.8K
6.8K
Above table shows the reference values for crystal applications.
Notes:
1. For C1, C2, R components refer to Figure A.
2. It is recommended that the crystals be replaced with oscillators for applications above 35 MHz.
Publication Release Date: December 4, 2006
Revision A6
- 19 -
W78C438C
9. PACKAGE DIMENSIONS
9.1 84-pin PLCC
HD
D
1
75
11
84
12
74
Dimension in inches
Dimension in mm
Symbol
A
Nom.
Min.
Max. Min. Nom. Max.
0.185
4.70
0.020
0.51
1
A
0.143 0.148 0.153 3.63 3.76 3.89
A 2
b 1
b
0.026 0.028
0.016 0.018
0.032 0.66
0.022
0.81
0.71
0.46 0.56
0.41
0.006 0.008 0.012 0.15 0.20
0.30
E
c
29.17 29.29 29.41
29.17 29.29 29.41
1.12 1.27 1.42
27.81 28.32 28.83
27.81 28.32 28.83
1.148 1.153 1.158
1.148 1.153
D
E
E
HE
1.158
0.044 0.050 0.056
e
1.095
1.095
1.115 1.135
1.115 1.135
D
G
E
G
30.23
30.23
1.180 1.190 1.200 29.98
30.48
30.48
D
H
1.180
0.090 0.100
1.190
E
1.200 29.98
0.110 2.29
0.004
H
2.54 2.79
L
54
32
y
0.10
10
10
0
0
θ
33
53
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
A
A2
A
4. General appearance spec. should be based
on final visual inspection spec.
e
b
Seating Plane
y
GD
- 20 -
W78C438C
9.2 100-pin QFP
HD
D
100
81
Dimension in inches
Dimension in mm
Symbol
80
1
Min. Nom. Max. Min. Nom. Max.
0.130
3.30
A
0.004
0.10
1
A
0.107 0.112
0.117
0.016
0.010
0.556
0.792
0.032
0.752
2.718
2.845 2.972
A
b
c
D
E
e
2
0.010
0.004
0.254 0.305 0.407
0.101 0.152 0.254
0.012
0.006
14.00
20.00
13.87
19.87
0.546 0.551
0.782 0.787
0.020 0.026
14.13
20.13
0.802
E
HE
0.498 0.65
0.728
0.964
0.039
0.740
0.976
0.047
18.49 18.80 19.10
D
E
H
H
L
0.988 24.49 24.80 25.10
0.055
0.103
0.004
0.991 1.194 1.397
0.087 0.095
2.21
0
2.413 2.616
L
y 1
θ
51
30
0.102
12
0
12
31
50
e
b
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
c
protrusion/intrusion.
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
A
2
A
θ
A 1
See Detail F
L
y
Seating Plane
L 1
Detail F
Publication Release Date: December 4, 2006
Revision A6
- 21 -
W78C438C
10. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
A3
A4
A5
A6
July, 1998
June, 2004
April 19, 2005
July 27, 2005
October 3, 2006
December 4, 2006
-
2
19
2
Initial issued
Revise part number in the item of packages
Add Important Notice
Add Lead free (RoHS) part number
Remove block diagram
Remove all Leaded package parts
2
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 1-408-9436666
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Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
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Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 22 -
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