W78C52DP-24 [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78C52DP-24 |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总18页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary W78C52D
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78C52D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C52 microcontroller
series. The W78C52D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable
I/O port (Port 4) and two additional external interrupts (INT2 , INT3 ), three 16-bit timer/counters, one
watchdog timer and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 8K byte mask ROM for application programs.
The W78C52D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
· Fully static design
· Supply voltage of 4.5V to 5.5V
· DC-40 MHz operation
· 256 bytes of on-chip scratchpad RAM
· 8K bytes of on-chip mask ROM
· 64K bytes program memory address space
· 64K bytes data memory address space
· Four 8-bit bidirectional ports
· Three 16-bit timer/counters
· One full duplex serial port
· Eight-source, two-level interrupt capability
· One extra 4-bit bit-addressable I/O port
· Two additional external interrupts INT2 / INT3
· Watchdog timer
· EMI reduction mode
· Built-in power management
· Code protection
· Packages:
- DIP 40: W78C52D-24/40
- PLCC 44: W78C52DP-24/40
- QFP 44: W78C52DF-24/40
Publication Release Date: December 1998
- 1 -
Revision A1
Preliminary W78C52D
PIN CONFIGURATIONS
40-Pin DIP (W78C52D)
1
VDD
T2, P1.0
T2EX, P1.1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
4
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
WR, P3.6
RD, P3.7
XTAL2
XTAL1
P2.0, A8
VSS
44-Pin QFP (W78C52DF)
44-Pin PLCC (W78C52DP)
/
T
2
E
X
,
I
/
A
D
3
,
A
D
1
,
A
D
2
,
A
D
0
,
N
T
3
,
T
2
E
X
,
I
T
2
,
A
D
1
,
A
D
3
,
A
D
0
,
A
D
2
,
N
T
3
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
3
4
3
2
1
0
1
2
0
2
4
3
2
1
0
1
3
0
2
2
34
43 42 41 40 39 38 37 36 35
44
40
39
6
5
4
3
2
1 44 43 42
41
1
2
33
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
7
8
9
P1.5
P1.6
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
32
31
30
29
28
27
26
25
38
37
36
35
34
33
32
31
3
4
5
P1.7
P1.7
RST
RXD, P3.0
10
11
12
13
14
15
RST
EA
RXD, P3.0
EA
P4.1
6
7
8
9
INT2, P4.3
TXD, P3.1
INT0, P3.2
P4.1
ALE
INT2, P4.3
TXD, P3.1
ALE
PSEN
P2.7, A15
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
INT1, P3.3
T0, P3.4
10
11
12
24
23
P2.6, A14
P2.5, A13
30
29
16
17
P2.6, A14
P2.5, A13
T1, P3.5
13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
V
S
S
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
4
.
6
,
7
,
3
,
0
,
1
,
2
,
4
,
6
,
7
,
0
,
1
,
2
,
3
,
4
,
0
0
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W R
W R
R
D
R
D
- 2 -
Preliminary W78C52D
PIN DESCRIPTION
P0.0 P0.7
-
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0-P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0-P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0-P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
T0 Timer 0 Input
P3.4
P3.5
P3.6
T1 Timer 1 Input
WR Data Write Strobe
RD Data Read Strobe
P3.7
P4.0-P4.3
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins or external interrupt input sources (INT2 / INT3 ).
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.
Publication Release Date: December 1998
- 3 -
Revision A1
Preliminary W78C52D
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state during
reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P1.0
Port 1
Latch
Port
1
~
P1.7
ACC
B
INT2
INT3
Port 0
Latch
P0.0
~
P0.7
Interrupt
Port
0
T1
T2
Timer
2
DPTR
Timer
0
Stack
Pointer
Temp Reg.
PC
PSW
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
~
P3.7
Port 3
Latch
SFR RAM
Address
Port
3
Instruction
Decoder
&
Sequencer
256 bytes
RAM & SFR
P2.0
~
P2.7
Port
2
8K bytes
ROM
Port 2
Latch
Bus & Clock
Controller
Port 4
Latch
P4.0
~
P4.3
Watchdog
Timer
Port
4
Oscillator
Reset Block
Power control
XTAL1 XTAL2 ALE PSEN
RST
VDD
GND
- 4 -
Preliminary W78C52D
FUNCTIONAL DESCRIPTION
The W78C52D architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer
0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer
1 are the same as in the W78C51. Timer 2 is a special feature of the W78C52D: it is a 16-bit
timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2
can operate as either an external event counter or as an internal timer, depending on the setting of
bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate
generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
Clock
The W78C52D is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C52D relatively insensitive to duty
cycle variations in the clock.
Crystal Oscillator
The W78C52D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when VDD = 5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
Publication Release Date: December 1998
- 5 -
Revision A1
Preliminary W78C52D
deglitch the reset line when the W78C52D is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts
INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
VECTOR
ADDRESS SEQUENCE WITHIN
PRIORITY LEVEL
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
TCON.0
1
IE.1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
IE.5
-
6
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
- 6 -
Preliminary W78C52D
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 /
INT3 ).
Example: P4
MOV
REG 0D8H
P4, #0AH
A, P4
; Output data "A" through P4.0- P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
MOV
SETB
P4.0
CLR
P4.1
; Clear bit P4.1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW
CLRW WIDL
PS2
PS1
PS0
Mnemonic: WDTC
ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
Address: 8FH
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
2
4
8
16
32
64
128
256
Publication Release Date: December 1998
Revision A1
- 7 -
Preliminary W78C52D
The time-out period is obtained using the following formula:
1
´ 214 ´ PRESCALER ´ 1000 ´ 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL
IDLE
EXTERNAL
RESET
INTERNAL
14-BIT TIMER
RESET
PRESCALER
OSC
1/12
CLEAR
CLRW
Watchdog Timer Block Diagram
Typical Watchdog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Reduce EMI Emission
Because of the on-chip ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is not needed. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space.
AUXR - Auxiliary Register
Bit:
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
AO
Mnemonic: AUXR
Address: 8Eh
AO:
Turn off ALE signal.
- 8 -
Preliminary W78C52D
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
VCC- VSS
VIN
MIN.
-0.3
MAX.
+7.0
UNIT
V
Input Voltage
VSS -0.3
0
VCC +0.3
70
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
Vss = 0V ; TA = 25° C; unless otherwise specified.
PARAMETER
SYM.
SPECIFICATION
TEST CONDITIONS
MIN.
MAX.
5.5
20
UNIT
Operating Voltage
VDD
IDD
4.5
V
Operating Current
Idle Current
-
-
-
mA
mA
mA
VDD = 5.5V, 20 MHz, no load
VDD = 5.5V, 20 MHz, no load
VDD = 5.5V, no load
IIDLE
IPWDN
Input
IIN
6
Power Down Current
50
Input Current
-50
-10
+10
+10
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
mA
mA
P1, P2, P3, P4
Input Leakage Current
ILK
VSS < VIN < VDD
P0, EA
Input Current
RST
IIN2
ITL
-10
-500
0
+300
-
VDD = 5.5V
0 < VIN < VDD
VDD = 5.5V
VIN = 2V
mA
mA
V
Logic 1-to-0 Transition Current
P1, P2, P3, P4
Input Low Voltage
RST
VIL2
VIL1
VIL3
0.8
0.8
0.8
VDD = 4.5V
Input Low Voltage
P1, P2, P3, P4
Input Low Voltage
XTAL1[*4]
0
V
VDD = 4.5V
VDD = 4.5V
0
V
Publication Release Date: December 1998
Revision A1
- 9 -
Preliminary W78C52D
DC Characteristics, continued
PARAMETER
SYM.
SPECIFICATION
TEST CONDITIONS
MIN.
MAX.
UNIT
Input
Input High Voltage
P1, P2, P3, P4
Input High Voltage
RST
VIH1
2.4
3.5
3.5
VDD
+0.2
VDD
+0.2
VDD
+0.2
V
V
V
VDD = 5.5V
VDD = 5.5V
VDD = 5.5V
VIH2
VIH3
Input High Voltage
XTAL1[*4]
Output
Output Low Voltage
P1, P2, P3, P4
VOL1
-
-
0.45
0.45
V
V
VDD = 4.5V
IOL = +2 mA
VDD = 4.5V
IOL = +4 mA
Output Low Voltage
P0, ALE, PSEN [*4]
VOL2
Sink Current
ISK1
ISK2
4
8
8
mA
mA
VDD = 4.5V
Vin = 0.45V
VDD = 4.5V
VIN = 0.45V
P1, P2, P3, P4
Sink Current
16
P0, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
VOH1
VOH2
2.4
2.4
-
-
V
V
VDD = 4.5V
IOH = -100 mA
VDD = 4.5V
Output High Voltage
P0, ALE, PSEN [*4]
Source Current
P1, P2, P3, P4
Source Current
IOH = -400 mA
ISR1
ISR2
-100
-8
-250
-14
VDD = 4.5V
VIN = 2.4V
VDD = 4.5V
VIN = 2.4V
mA
mA
P0, ALE, PSEN
Notes:
*1. RST pin has an internal pull-down.
*2. Pins of P1 and P3 can source a transition current when they are being externally driven from 1 to 0.
*3. RST is a Schmitt trigger input and XTAL1 is a CMOS input.
*4. P0, P2, ALE and
are tested in the external access mode.
PSEN
- 10 -
Preliminary W78C52D
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
Clock Period
Clock High
SYMBOL
FOP
MIN.
0
TYP.
MAX.
UNIT
MHz
nS
NOTES
-
-
-
-
24
-
1
2
3
3
TCP
25
10
10
TCH
-
nS
Clock Low
TCL
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
TYP.
MAX.
UNIT
nS
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
-
-
-
-
-
-
4
1, 4
4
1 TCP-D
1 TCP-D
1 TCP-D
-
TAAH
nS
TAPL
nS
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
TPDA
-
2 TCP
nS
2
3
TPDH
TPDZ
TALW
TPSW
0
0
-
1 TCP
nS
nS
nS
nS
-
1 TCP
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
-
-
4
4
2 TCP-D
3 TCP-D
PSEN Pulse Width
Notes:
1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "D" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: December 1998
Revision A1
- 11 -
Preliminary W78C52D
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
3 TCP+D
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
TDAR
-
3 TCP-D
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
TDDH
TDDZ
TDRD
-
-
nS
1
0
0
-
-
nS
nS
6 TCP
nS
2
6 TCP-D
Notes:
1. Data memory access time is 8 TCP.
2. "D" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
TDAW
-
3 TCP-D
1 TCP-D
1 TCP-D
6 TCP-D
3 TCP+D
TDAD
TDWD
TDWR
-
-
-
-
-
nS
nS
6 TCP
nS
Note: "D" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 12 -
Preliminary W78C52D
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
DAR
DDA
T
T
DDH,
DDZ
T
T
DRD
T
Publication Release Date: December 1998
Revision A1
- 13 -
Preliminary W78C52D
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
A0-A7
PORT 0
WR
DATA OUT
T
DWD
T
DAD
T
T
DWR
DAW
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
TPDH
DATA OUT
PORT
INPUT
SAMPLE
- 14 -
Preliminary W78C52D
APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V
DD
V
DD
31
19
AD0
39
3
11
AD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
5
A0
A1
A2
A3
A4
A5
A6
A7
A8 25
A9 24
A10
A11
A12
A13
A14
A15
A0
A1
A2
A3
A4
10
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
38 AD1
37 AD2
36 AD3
35 AD4
AD1
AD2
AD3
AD4
AD5
AD6
4
7
8
13
14
17
12
13
15
16
17
18
19
A1
6
8
A2
XTAL1
9
10 u
7
A3
12
6
A4
R
18
9
AD5
AD6
AD7
34
33
32
15 A5
5
XTAL2
A5
CRYSTAL
A6
A7
16
19
4
A6
AD7 18
3
A7
8.2 K
RST
INT0
A8
1
11
GND
A8
A9
21
22
23
24
25
26
27
28
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
21
23
2
26
27
1
A10
A11
A12
A13
A14
A15
12
13
14
15
A10
A11
A12
A13
A14
A15
INT1
T0
T1
74HC373
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
OE
RD
17
16
29
30
11
10
WR
PSEN
ALE
TXD
RXD
27512
W78C52D
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
30P
15P
10P
5P
R
-
-
6.8K
4.7K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
Publication Release Date: December 1998
Revision A1
- 15 -
Preliminary W78C52D
Application Circuits, continued
Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
39 AD0
38 AD1
37 AD2
36 AD3
AD0
AD1
AD2
AD3
AD4
3
4
7
8
10
9
8
7
6
5
4
3
25
24
21
23
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
2
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
EA
XTAL1
A2
6
A3
A4
A5
10 u
OSCILLATOR
9
12
AD4
AD5
AD6
AD7
35
34
33
32
13
18
9
XTAL2
AD5 14
17
15 A5
A6
19 A7
AD6
AD7 18
16
A6
8.2 K
A7
A8
RST
INT0
GND
1
21
A8
A9
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
A9
22
23
24
25
26
27
28
11
A10
A11
A12
A10
A11
A12
A13
12
13
14
15
A10
A11
A12
A13
A14
74HC373
INT1
T0
T1
A13 26
1
A14
A14
1
2
3
4
5
6
7
8
GND
CE
20
22
27
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
OE
RD
17
16
29
30
11
10
WR
WR
20256
PSEN
ALE
TXD
RXD
W78C52D
Figure B
- 16 -
Preliminary W78C52D
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.210
Max.
5.334
0.010
0.150
0.016
0.048
0.008
0.254
1
A
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
3.81
3.937 4.064
0.457 0.559
2
A
0.406
1.219
0.203
B
1.27
1.372
0.356
1
B
0.254
c
D
E
D
52.20 52.58
40
21
15.494
13.97
2.794
15.24
13.84
2.54
0.590 0.600
14.986
13.72
0.540
0.090
0.120
0
0.545
0.100
0.550
0.110
1
E
2.286
1
e
0.140 3.048
3.302
0.130
3.556
15
1
E
L
a
15
0
17.01
0.630 0.650
0.670
0.090
16.00
16.51
A
e
S
2.286
1
20
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
A2
A
Base Plane
1
A
.
L
Seating Plane
B
e1
e
A
a
B 1
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.185
Max.
7
39
4.699
0.020
0.145
0.508
A
1
0.150
3.81
0.711
0.457
0.155 3.683
3.937
0.813
0.559
0.356
A2
0.026 0.028 0.032
0.022
0.66
b
b
c
1
0.406
0.016 0.018
H E
GE
E
0.008 0.010 0.014 0.203 0.254
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
0.648 0.653 0.658
0.050 BSC
D
E
e
0.590
0.590
0.680
0.680
14.99 15.49 16.00
0.610 0.630
0.610 0.630
0.690 0.700
17
29
GD
16.00
17.27 17.53 17.78
14.99 15.49
E
G
18
28
D
H
c
17.27
0.700
17.53 17.78
2.54 2.794
0.10
0.690
H
L
y
E
0.090 0.100
0.110 2.296
0.004
L
Notes:
A 2
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
q
e
b
A1
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
Seating Plane
y
G D
Publication Release Date: December 1998
Revision A1
- 17 -
Preliminary W78C52D
Package Dimensions, continued
44-pin QFP
H D
D
Dimension in mm
Dimension in inch
Symbol
A
Nom.
---
Nom.
---
Min.
---
Max. Min.
Max.
---
34
44
---
---
0.002
0.075
0.01
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
A
0.081 0.087
2.20
0.45
A
b
c
2
33
1
0.014
0.006
0.394
0.394
0.031
0.520
0.520
0.031
0.018
0.010
0.398
0.35
0.101
9.9
0.152
10.00
0.254
0.004
0.390
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
D
E
e
9.9
0.398
0.036
0.530
0.530
0.037
10.00
0.80
0.390
0.025
0.510
E
HE
0.635
12.95
12.95
0.65
13.2
13.2
D
E
H
0.510
0.025
H
L
L
y
11
0.8
1.6
0.051 0.063 0.075
0.003
1.295
1
12
22
e
b
7
q
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A 2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
q
A 1
L
See Detail F
y
Seating Plane
L
1
Detail F
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
http://www.winbond.com.tw/
TEL: 408-9436666
Voice & Fax-on-demand: 886-2-27197006
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 18 -
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