W78E058B40PL [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78E058B40PL |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总36页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78E58B/W78E058B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION ............................................................................................................... 3
2. FEATURES....................................................................................................................................... 3
3. PIN CONFIGURATIONS .................................................................................................................. 4
4. PIN DESCRIPTION .......................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION ......................................................................................................... 6
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
RAM....................................................................................................................................... 6
Timers 0, 1 and 2................................................................................................................... 6
Clock...................................................................................................................................... 7
Crystal Oscillator.................................................................................................................... 7
External Clock........................................................................................................................ 7
Power Management............................................................................................................... 7
Reduce EMI Emission ........................................................................................................... 7
Reset...................................................................................................................................... 7
Port 4 ..................................................................................................................................... 9
5.10 INT2 /INT3 ............................................................................................................................ 9
5.11 Port 4 Base Address Registers ........................................................................................... 11
5.12 In-System Programming (ISP) Mode................................................................................... 13
5.13 In-System Programming Control Register (CHPCON) ....................................................... 15
5.14 F04KBOOT Mode (Boot From LDROM) ............................................................................. 15
6. SECURITY...................................................................................................................................... 19
6.1
6.2
6.3
6.4
Lock Bit ................................................................................................................................ 19
MOVC Inhibit ....................................................................................................................... 19
Encryption............................................................................................................................ 20
Oscillator Control ................................................................................................................. 20
7. ELECTRICAL CHARACTERISTICS............................................................................................... 21
7.1
7.2
7.3
Absolute Maximum Ratings................................................................................................. 21
D.C. Characteristics............................................................................................................. 21
A.C. Characteristics............................................................................................................. 23
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
Clock Input Waveform...........................................................................................................23
Program Fetch Cycle ............................................................................................................23
Data Read Cycle...................................................................................................................24
Data Write Cycle...................................................................................................................24
Port Access Cycle.................................................................................................................24
Publication Release Date: December 4, 2006
- 1 -
Revision A8
W78E58B/W78E058B
8. TIMING WAVEFORMS................................................................................................................... 25
8.1
8.2
8.3
8.4
Program Fetch Cycle........................................................................................................... 25
Data Read Cycle.................................................................................................................. 25
Data Write Cycle.................................................................................................................. 26
Port Access Cycle................................................................................................................ 26
9. TYPICAL APPLICATION CIRCUITS.............................................................................................. 27
9.1
9.2
Expanded External Program Memory and Crystal.............................................................. 27
Expanded External Data Memory and Oscillator ................................................................ 28
10. PACKAGE DIMENSIONS............................................................................................................... 29
10.1 40-pin DIP............................................................................................................................ 29
10.2 44-pin PLCC ........................................................................................................................ 29
10.3 44-pin PQFP........................................................................................................................ 30
11. APPLICATION NOTES................................................................................................................... 31
11.1 In-system Programming Software Examples ...................................................................... 31
12. REVISION HISTORY...................................................................................................................... 36
- 2 -
W78E58B/W78E058B
1. GENERAL DESCRIPTION
The W78E058B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E058B is fully compatible with the standard 8052.
The W78E058B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional
4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78E058B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E058B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
y
y
y
y
y
y
y
y
y
y
y
y
Fully static design 8-bit CMOS microcontroller
32K bytes of in-system programmable Flash EPROM for Application Program (APROM)
4K bytes of auxiliary ROM for Loader Program (LDROM)
512 bytes of on-chip RAM (including 256 bytes of AUX-RAM, software selectable)
64K bytes program memory address space and 64K bytes data memory address space
Four 8-bit bi-directional ports
One 4-bit multipurpose programmable port
Three 16-bit timer/counters
One full duplex serial port
Eight-sources, two-level interrupt capability
Built-in power management
Code protection
Packaged in
− Lead Free (RoHS) DIP 40:
W78E058B40DL
− Lead Free (RoHS) PLCC 44: W78E058B40PL
− Lead Free (RoHS) PQFP 44: W78E058B40FL
Publication Release Date: December 4, 2006
Revision A8
- 3 -
W78E58B/W78E058B
3. PIN CONFIGURATIONS
40-Pin DIP
1
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
2
3
4
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.2
P1.3
5
6
P1.4
P1.5
P1.6
7
8
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
44-Pin QFP
44-Pin PLCC
/
T
2
E
X
,
I
/
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
T
2
E
X
,
N
T
3
,
I
T
2
,
A
D
3
,
A
D
0
,
A
D
1
,
A
D
2
,
N
T
3
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
3
4
3
2
1
0
1
2
0
2
4
3
2
1
0
0
1
2
3
2
34
43 42 41 40 39 38 37 36 35
44
40
39
6
5
4
3
2
1
44 43 42
41
1
2
33
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
P1.7
7
8
9
P1.5
P1.6
P1.7
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
32
31
30
29
28
27
26
25
38
37
36
35
34
33
32
31
3
4
5
RST
10
11
12
13
14
15
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
EA
P4.1
ALE
RXD, P3.0
INT2, P4.3
TXD, P3.1
EA
P4.1
6
7
8
9
ALE
INT0, P3.2
PSEN
P2.7, A15
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
INT1, P3.3
T0, P3.4
10
11
12
24
23
P2.6, A14
P2.5, A13
30
29
16
17
P2.6, A14
P2.5, A13
T1, P3.5
13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
2
.
P
4
.
6
7
0
1
2
3
4
6
7
0
1
3
4
0
2
0
,
/
,
/
,
A
8
,
A
9
,
,
,
,
A
8
,
A
9
,
,
,
,
/
,
/
A
1
1
A
1
2
A
1
0
A
1
0
A
1
1
A
1
2
W
R
R
D
W
R
R
D
- 4 -
W78E58B/W78E058B
4. PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
I
EA
the pin is high.
PROGRAM STORE ENABLE: PSEN enables the external ROM data in the
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
O H
PSEN
ALE
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
O H separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
RST
I L
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
XTAL1
I
external clock.
XTAL2
VSS
O
I
CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential.
VDD
I
POWER SUPPLY: Supply voltage for operation.
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
P0.0 − P0.7
P1.0 − P1.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
I/O H
P2.0 − P2.7
provides the upper address bits for accesses to external memory.
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H PORT 4: A bi-directional I/O. See details below.
P3.0 − P3.7
P4.0 − P4.3
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
Publication Release Date: December 4, 2006
Revision A8
- 5 -
W78E58B/W78E058B
5. FUNCTIONAL DESCRIPTION
The W78E058B architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 512 bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
5.1 RAM
The internal data RAM in the W78E058B is 512 bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways.
y
y
y
RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are
R0, R1 of the selected registers bank.
AUX-RAM 0H − FFH is addressed indirectly as the same way to access external data memory
with the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and
DPTR register. An access to external data memory locations higher than FFH will be performed
with the MOVX instruction in the same way as in the 8051. The AUX-RAM is disable after a reset.
Setting the bit 4 in CHPCON register will enable the access to AUX-RAM. When AUX-RAM is
enabled the instructions of "MOVX @Ri" will always access to on-chip AUX-RAM. When executing
from internal program memory, an access to AUX-RAM will not affect the Ports P0, P2, WR and
RD.
Example,
CHPENR
CHPCON
MOV
REG
REG
F6H
BFH
CHPENR, #87H
MOV
CHPENR, #59H
ORL
MOV
CHPCON, #00010000B ; enable AUX-RAM
CHPENR, #00H
MOV
R0, #12H
MOV
A, #34H
MOVX @R0, A
; Write 34h data to 12h address.
5.2 Timers 0, 1 and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
- 6 -
W78E58B/W78E058B
5.3 Clock
The W78E058B is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E058B relatively insensitive to duty
cycle variations in the clock.
5.4 Crystal Oscillator
The W78E058B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
5.5 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
5.6 Power Management
Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to
the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts INT0 to INT1 when enabled and set to level triggered.
5.7 Reduce EMI Emission
The W78E058B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
5.8 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E058B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
Publication Release Date: December 4, 2006
- 7 -
Revision A8
W78E58B/W78E058B
W78E058B Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
+B
00000000
CHPENR
00000000
+ACC
00000000
+P4
xxxx1111
+PSW
00000000
+T2CON
00000000
XICON
00000000
+IP
RCAP2L RCAP2H
00000000 00000000 00000000 00000000
P4CONA P4CONB SFRAL SFRAH
TL2
TH2
SFRFD
SFRCN
00000000 00000000 00000000 00000000 00000000 00000000
CHPCON
0xx00000
00000000
+P3
00000000
P43AL
P43AH
00000000 00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
P42AL
P42AH
P2ECON
0000xx00
A8
A0
98
90
88
AF
A7
9F
97
8F
87
00000000
00000000
SBUF
xxxxxxxx
P41AL
00000000
TH0
00000000
P40AL
00000000
P41AH
00000000
TH1
00000000
P40AH
00000000
11111111
+TCON
00000000
+P0
TMOD
00000000
SP
TL0
TL1
00000000
DPL
00000000
DPH
PCON
00110000
80
11111111
00000111
00000000
00000000
Notes:
1.The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
- 8 -
W78E58B/W78E058B
5.9 Port 4
Port 4, address D8H, is a 4-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0 − P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt INT3 and INT2 if enabled.
Mode 1: P4.0 − P4.3 are read strobe signals that are synchronized with RD signal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0 − P4.3 are write strobe signals that are synchronized with WRsignal at specified
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0 − P4.3 are read/write strobe signals that are synchronized with RD or WRsignal at
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
5.10 INT2 /INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Publication Release Date: December 4, 2006
- 9 -
Revision A8
W78E58B/W78E058B
Eight-source interrupt information
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
INTERRUPT
SOURCE
VECTOR
SEQUENCE WITHIN
PRIORITY LEVEL
ADDRESS
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
IE.1
TCON.0
1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
6
IE.5
-
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
P4CONB (C3H)
BIT
NAME
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
P43FUN1
P43FUN0
7, 6
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15 − A1) of address bus with the base address
P43CMP1
P43CMP0
register P43AH, P43AL.
5, 4
10: Compare the 14 high bits (A15 − A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15 − A8) of address bus with the base address
register P43AH, P43AL.
P42FUN1
P42FUN0
P42CMP1
P42CMP0
The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
3, 2
1, 0
The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
- 10 -
W78E58B/W78E058B
P4CONA (C2H)
BIT
NAME
FUNCTION
P41FUN1
P41FUN0
P41CMP1
P41CMP0
P40FUN1
P40FUN0
P40CMP1
P40CMP0
The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
7, 6
The P4.1 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
5, 4
3, 2
1, 0
The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.0 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
P2ECON (AEH)
BIT
NAME
FUNCTION
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe
signal.
7
P43CSINV
0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe
signal.
6
5
4
3
2
1
0
P42CSINV The similarity definition as P43SINV.
P41CSINV The similarity definition as P43SINV.
P40CSINV The similarity definition as P43SINV.
-
-
-
-
Reserve
Reserve
0
0
5.11 Port 4 Base Address Registers
P40AH, P40AL
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
P41AH, P41AL
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
Publication Release Date: December 4, 2006
- 11 -
Revision A8
W78E58B/W78E058B
P42AH, P42AL
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
P4 (D8H)
BIT
7
NAME
FUNCTION
-
-
Reserve
Reserve
Reserve
Reserve
6
5
-
4
-
3
P43
P42
P41
P40
Port 4 Data bit which outputs to pin P4.3 at mode 0.
Port 4 Data bit. which outputs to pin P4.2 at mode 0.
Port 4 Data bit. which outputs to pin P4.1at mode 0.
Port 4 Data bit which outputs to pin P4.0 at mode 0.
2
1
0
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H
−1237H and positive polarity, and P4.1 − P4.3 are used as general I/O ports.
MOV P40AH, #12H
MOV P40AL, #34H
; Base I/O address 1234H for P4.0
MOV P4CONA, #00001010B
MOV P4CONB, #00H
MOV P2ECON, #10H
; P4.0 a write strobe signal and address line A0 and A1 are masked.
; P4.1 − P4.3 as general I/O port which are the same as PORT1
; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
Then any instruction MOVX @DPTR, A (with DPTR = 1234H − 1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3 − P4.1.
- 12 -
W78E58B/W78E058B
P4xCSINV
P4 REGISTER
P4.x
DATA I/O
RD_CS
MUX 4->1
WR_CS
READ
WRITE
RD/WR_CS
PIN
P4.x
ADDRESS BUS
P4xFUN0
P4xFUN1
EQUAL
REGISTER
P4xAL
P4xAH
Bit Length
P4.x INPUT DATA BUS
Selectable
comparator
REGISTER
P4xCMP0
P4xCMP1
5.12 In-System Programming (ISP) Mode
The W78E058B equips one 32K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E058B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register. The CHPCON is read-only by default, software must write two specific values 87H,
then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute. The W78E058B achieves all in-system programming operations including enter/exit ISP
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device
needs proper time to complete the ISP operations before awaken from idle mode, software may use
timer interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely. Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
to reset the CPU. The software reset serves as a external reset. This in-system programming feature
makes the job easy and efficient in which the application needs to update firmware frequently. In some
Publication Release Date: December 4, 2006
- 13 -
Revision A8
W78E58B/W78E058B
applications, the in-system programming feature make it possible to easily update the system
firmware without opening the chassis.
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order
byte of address.
SFRFD: The programming data for on-chip ROM in programming mode.
SFRCN: The control byte of on-chip ROM programming mode.
SFRCN (C7)
BIT
NAME
FUNCTION
7
-
Reserve.
On-chip ROM bank select for in-system programming.
0: 32K bytes ROM bank is selected as destination for re-programming.
1: 4K bytes ROM bank is selected as destination for re-programming.
ROM output enable.
6
WFWIN
5
4
OEN
CEN
ROM chip enable.
3, 2, 1, 0
CTRL [3:0] The flash control signals
MODE
WFWIN
CTRL<3:0>
0010
OEN
CEN
SFRAH, SFRAL
X
SFRFD
X
Erase 32KB APROM
Program 32KB APROM
Read 32KB APROM
Erase 4KB LDROM
Program 4KB LDROM
Read 4KB LDROM
0
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0001
Address in
Address in
X
Data in
Data out
X
0000
0010
0001
Address in
Address in
Data in
Data out
0000
- 14 -
W78E58B/W78E058B
5.13 In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT
NAME
FUNCTION
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will
enforce microcontroller reset to initial condition just like power on reset. This
action will re-boot the microcontroller and start to normal operation. To read this
bit in logic-1 can determine that the F04KBOOT mode is running.
SWRESET
(F04KMODE)
7
6
5
-
-
Reserve.
Reserve.
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
Must set to 0.
ENAUXRAM
4
3
2
0
0
Must set to 0.
The Program Location Select.
0: The Loader Program locates at the 32 KB APROM. 4KB LDROM is
destination for re-programming.
1
FBOOTSL
1: The Loader Program locates at the 4 KB memory bank. 32KB APROM is
destination for re-programming.
ROM Programming Enable.
1: enable. The microcontroller enter the in-system programming mode after
entering the idle mode and wake-up from interrupt. During in-system
0
FPROGEN programming mode, the operation of erase, program and read are achieve
when device enters idle mode.
0: disable. The on-chip flash memory is read-only. In-system programmability
is disabled.
5.14 F04KBOOT Mode (Boot From LDROM)
By default, the W78E058B boots from APROM program after a power on reset. On some occasions,
user can force the W78E058B to boot from the LDROM program via following settings. The possible
situation that you need to enter F04KBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this F04KBOOT mode to force the W78E058B jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the
personal computer to force the W78E058B to enter the F04KBOOT mode. After power on of personal
computer, you can release both buttons and finish the in-system programming procedure to update
the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and
PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT
mode.
Publication Release Date: December 4, 2006
- 15 -
Revision A8
W78E58B/W78E058B
F04KBOOT Mode
P4.3
X
P2.7
L
P2.6
L
MODE
FO4KBOOT
FO4KBOOT
L
X
X
The Reset Timing For Entering
F04KBOOT Mode
P2.7
Hi-Z
Hi-Z
P2.6
RST
30 mS
10 mS
- 16 -
W78E58B/W78E058B
The Algorithm of In-System Programming
Part 1:32KB APROM
procedure of entering
START
In-System Programming Mode
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
No
Yes
Setting control registers
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Execute the normal application
program
Setting Timer (about 1.5 us)
and enable timer interrupt
END
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
CPU will be wakened by interrupt and
re-boot from 4KB LDROM to execute
the loader program.
Go
Publication Release Date: December 4, 2006
Revision A8
- 17 -
W78E58B/W78E058B
Part 2: 4KB LDROM
Procedure of Updating
the 32KB APROM
Go
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
PGM
Yes
Yes
Is F04KBOOT Mode?
(CHPCON.7=1)
End of Programming ?
No
No
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Setting Timer and enable Timer
interrupt for wake-up .
(50us for program operation)
Yes
Is currently in the
F04KBOOT Mode ?
No
Software reset CPU and
re-boot from the 32KB
APROM.
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
Get the parameters of new code
(Address and data bytes)
Setting Timer and enable Timer
interrupt for wake-up .
(15 ms for erasing operation)
through I/O ports, UART or
other interfaces.
Setting erase operation mode:
MOV SFRCN,#22H
(Erase 32KB APROM)
Setting control registers for
programming:
Hardware Reset
to re-boot from
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
new 32 KB APROM.
Start Timer and enter IDLE
Mode.
(S/W reset is
MOV SFRCN,#21H
invalid in F04KBOOT
(Erasing...)
Mode)
End of erase
operation. CPU will
be wakened by Timer
interrupt.
END
Executing new code
from address
00H in the 32KB APROM.
PGM
- 18 -
W78E58B/W78E058B
6. SECURITY
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.
Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM
and those operations on it are described below.
The W78E058B has a Security Register that can be accessed in programming mode. Those bits of
the Security Registers can not be changed once they have been programmed from high to low. They
can only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the
LDROM space.
0000h
4KB On-chip ROM
32KB On-chip ROM
Program Memory
Program Memory
Security Bits
B2 B1 B0
LDROM
B7 Reserved
0FFFh
7FFFh
APROM
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1: no restriction.
Reserved
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
B07: Osillator Control
FFFFh
Security Register
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Register
6.1 Lock Bit
This bit is used to protect the customer's program code in the W78E058B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Security Register can not be accessed again.
6.2 MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
Publication Release Date: December 4, 2006
- 19 -
Revision A8
W78E58B/W78E058B
6.3 Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
6.4 Oscillator Control
W78E058B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and
C1, C2 may need some adjustment while running at lower gain.
- 20 -
W78E58B/W78E058B
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER
DC Power Supply
SYMBOL
MIN.
-0.3
MAX.
+6.0
UNIT
V
VDD − VSS
VIN
Input Voltage
VSS -0.3
0
VDD +0.3
70
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
7.2 D.C. Characteristics
(VDD−VSS = 5V ±10%, TA = 25° C, Fosc = 20 MHz, unless otherwise specified.)
SPECIFICATION
PARAMETER
Operating Voltage
SYM.
TEST CONDITIONS
MIN.
MAX.
UNIT
VDD
IDD
4.5
5.5
V
RST = 1, P0 = VDD
No load
Operating Current
Idle Current
-
-
20
6
mA
mA
µA
µA
µA
µA
µA
VDD = 5.5V
Idle mode
IIDLE
IPWDN
IIN1
VDD = 5.5V
Power-down mode
VDD = 5.5V
Power Down Current
-
50
Input Current
VDD = 5.5V
-50
-10
-10
-500
+10
+300
+10
-
P1, P2, P3, P4
VIN = 0V or VDD
Input Current
RST
VDD = 5.5V
IIN2
0V < VIN < VDD
Input Leakage Current
P0, EA
VDD = 5.5V
ILK
0V < VIN < VDD
Logic 1 to 0 Transition Current
P1, P2, P3, P4
VDD = 5.5V
VIN = 2.0V
[*4]
ITL
Input Low Voltage
VIL1
0
0
0.8
0.8
V
V
VDD = 4.5V
VDD = 4.5V
P0, P1, P2, P3, P4,
Input Low Voltage
RST
V IL2
Publication Release Date: December 4, 2006
Revision A8
- 21 -
W78E58B/W78E058B
D.C. Characteristics, continued
SPECIFICATION
MAX.
PARAMETER
SYM.
TEST CONDITIONS
UNIT
MIN.
Input Low Voltage
XTAL1[*4]
V IL3
VIH1
VIH2
VIH3
VOL1
0
0.8
V
V
V
V
V
VDD = 4.5V
VDD = 5.5V
VDD = 5.5V
VDD = 5.5V
Input High Voltage
P0, P1, P2, P3, P4,
2.4
3.5
3.5
-
VDD +0.2
VDD +0.2
VDD +0.2
0.45
Input High Voltage
RST
Input High Voltage
XTAL1[*4]
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
P0, ALE, PSEN[*3]
VDD = 4.5V
IOL = +2 mA
VDD = 4.5V
IOL = +4 mA
VOL2
-
0.45
V
Sink current
P1, P3, P4
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
VIN = 0.45V
VDD = 4.5V
IOH = -100 µA
Isk1
Isk2
4
12
20
-
mA
mA
V
Sink current
P0, P2, ALE, PSEN
10
2.4
Output High Voltage
P1, P2, P3, P4
VOH1
Output High Voltage
P0, ALE, PSEN[*3]
VDD = 4.5V
VOH2
Isr1
2.4
-120
-8
-
V
IOH = -400 µA
Source Current
P1, P2, P3, P4
Source Current
VDD = 4.5V
VIN = 2.4V
-250
-20
µA
mA
VDD = 4.5V
VIN = 2.4V
Isr2
P0, P2, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
- 22 -
W78E58B/W78E058B
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
7.3.1 Clock Input Waveform
XTAL1
T
CH
T
CL
F
T
CP
OP,
PARAMETER
Operating Speed
Clock Period
Clock High
Clock Low
SYMBOL
FOP
MIN.
0
25
10
10
TYP.
MAX.
40
-
UNIT
MHz
nS
nS
nS
NOTES
-
-
-
-
1
2
3
3
TCP
TCH
TCL
-
-
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
7.3.2 Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
SYMBOL
TAAS
TAAH
MIN.
1 TCP-∆
1 TCP-∆
1 TCP-∆
-
TYP.
MAX.
UNIT
nS
nS
NOTES
-
-
-
-
-
-
-
-
-
4
1, 4
4
2
3
TAPL
nS
ALE Low to PSEN Low
TPDA
TPDH
TPDZ
TALW
TPSW
2 TCP
1 TCP
1 TCP
nS
nS
nS
nS
nS
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
0
0
2 TCP
3 TCP
-
-
4
4
2 TCP-∆
3 TCP-∆
PSEN Pulse Width
Notes:
1. P0.0 − P0.7, P2.0 − P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: December 4, 2006
Revision A8
- 23 -
W78E58B/W78E058B
7.3.3 Data Read Cycle
PARAMETER
SYMBOL
TDAR
MIN.
TYP.
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
1
-
3 TCP-∆
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
-
-
nS
TDDH
0
0
-
-
nS
TDDZ
nS
TDRD
6 TCP
nS
2
6 TCP-∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
7.3.4 Data Write Cycle
PARAMETER
ALE Low to WR Low
SYMBOL
TDAW
MIN.
TYP.
MAX.
UNIT
nS
-
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
3 TCP+∆
TDAD
-
-
-
-
-
nS
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
TDWD
nS
TDWR
6 TCP
nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
7.3.5 Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
nS
-
-
-
-
-
-
TPDH
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 24 -
W78E58B/W78E058B
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
A0-A7
Code A0-A7
Code
Data
Data
A0-A7
8.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
TDDA
TDDH, TDDZ
TDRD
Publication Release Date: December 4, 2006
Revision A8
- 25 -
W78E58B/W78E058B
8.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
DAD
TDWD
T
TDWR
TDAW
8.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
T
PDS
T
T
PDA
PDH
PORT
DATA OUT
INPUT
SAMPLE
- 26 -
W78E58B/W78E058B
9. TYPICAL APPLICATION CIRCUITS
9.1 Expanded External Program Memory and Crystal
V
DD
AD0
39
31
19
3
4
7
11
12
13
AD0
AD1
AD2
AD0
AD1
AD2
2
A0
A0
A1
A2
A3
A4
A5
A6
A7
10
9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
38 AD1
37 AD2
5 A1
6 A2
9 A3
A1
8
A2
XTAL1
AD3
AD4
AD5
36
35
34
AD3 8
AD4 13
AD5 14
7
15 AD3
16 AD4
17 AD5
10 u
C1
A3
12
15
A4
A5
6
A4
R
18
9
5
XTAL2
RST
A5
CRYSTAL
33 AD6
32 AD7
17
16 A6
18
AD6
4
AD6
A6
19
3
19 AD7
AD7 18
A7
A7
8.2 K
A8 25
A9 24
A8
1
11
GND
21
22
23
24
25
26
27
28
A8
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C2
A9
A10 21
A10
A11
A12
A13
A14
A15
INT0
12
13
14
15
A11
A10
A11
A12
A13
A14
A15
23
A12 2
A13 26
A14 27
INT1
74LS373
T0
T1
A15
1
1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
20
22
GND
2
3
4
5
6
7
8
CE
OE
RD
WR
17
16
29
30
27512
PSEN
ALE
11
10
TXD
RXD
W78E58B/W78E058B
Figure A
CRYSTAL
6 MHz
C1
47P
30P
15P
5P
C2
R
47P
30P
10P
5P
-
-
-
16 MHz
24 MHz
40MHz
6.8K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
Publication Release Date: December 4, 2006
Revision A8
- 27 -
W78E58B/W78E058B
9.2 Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39
3
4
AD0
A0
A1
A2
A3
A4
A5
A6
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
2
5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
38 AD1
9
8
AD2
AD3
37
36
6
7
XTAL1
8
9
7
OSCILLATOR
10 u
13
14
17
18
12
15
16
6
35 AD4
34 AD5
18
9
5
AD5
AD6
AD7
XTAL2
AD6
AD7
4
33
32
19 A7
3
8.2 K
25
RST
INT0
INT1
T0
T1
GND
A8
1
11
21
A9 24
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
22 A9
21
23
2
A10
A11
A12
A13
A14
A10
A11
A12
A13
12
13
14
15
23 A10
24 A11
25 A12
74LS373
26
1
26
A13
A14
CE
OE
WR
27
28
A14
1
2
3
4
5
6
7
8
GND
20
22
27
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
17
16
29
30
11
10
20256
PSEN
ALE
TXD
RXD
W78E58B/W78E058B
Figure B
- 28 -
W78E58B/W78E058B
10. PACKAGE DIMENSIONS
10.1 40-pin DIP
Dimension in inchDimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
5.334
0.210
A
A
0.010
0.150 0.155 0.160 3.81 3.937 4.064
0.254
1
A
2
0.016 0.018
0.406 0.457 0.559
1.219 1.27 1.372
0.022
0.054
B
0.050
0.048
0.008
1
B
0.010 0.014 0.203 0.254 0.356
2.055 2.070
c
D
52.20 52.58
D
E
40
21
15.494
13.97
0.610
15.24
0.590 0.600
14.986
13.72 13.84
0.540
0.545 0.550
E
e
L
a
1
0.110
0.090 0.100
2.286 2.54 2.794
1
3.048 3.302
0
0.120 0.130 0.140
15
3.556
15
1
E
0
17.01
2.286
0.630 0.650 0.670 16.00 16.51
0.090
e
A
S
Notes:
1
20
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
S
c
A2
A
L
Base Plane
1
A
.
are determined at the mold parting line.
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
eA
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B1
10.2 44-pin PLCC
HD
D
1
6
44
40
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
7
39
0.185
4.699
0.508
3.683 3.81 3.937
A
0.020
A
1
0.145 0.150
0.026 0.028
0.155
A2
b1
0.032 0.66
0.813
0.559
0.356
0.711
0.406
0.018 0.022
0.016
0.457
b
HE
GE
E
0.008 0.010 0.014 0.203 0.254
c
16.46 16.59 16.71
16.46 16.59 16.71
0.658
0.648 0.653 0.658
D
E
e
0.653
0.648
0.050 BSC
1.27
14.99 15.49 16.00
0.630
BSC
0.590
17
29
0.610
GD
16.00
14.99 15.49
0.590
0.680
0.680
0.610 0.630
0.690 0.700
0.690 0.700
G
H
E
17.27 17.53 17.78
18
28
D
c
17.27
0.110 2.296
0.004
17.53 17.78
2.54 2.794
0.10
H
E
0.090 0.100
L
y
L
Notes:
A2
A1
A
1. Dimension D & E do not include interlead
flash.
θ
2. Dimension b1 does not include dambar
protrusion/intrusion.
e
b
b1
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
Seating Plane
y
GD
Publication Release Date: December 4, 2006
Revision A8
- 29 -
W78E58B/W78E058B
10.3 44-pin PQFP
HD
D
Dimension in mm
Dimension in inch
Min. Nom. Max. Min. Nom. Max.
Symbol
34
44
---
---
---
---
---
---
A
0.002 0.01
0.02
0.25
2.05
0.05
0.5
1
A
0.075 0.081 0.087 1.90
2.20
0.45
A
b
c
D
E
e
2
33
1
0.01
0.014
0.006
0.25
0.018
0.010
0.35
0.101 0.152 0.254
0.004
0.390
0.394 0.398
0.394 0.398
0.031 0.036
10.00
10.00
0.80
9.9
9.9
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
0.390
0.025
E
HE
0.635
0.510 0.520
0.520
0.025 0.031
0.530 12.95 13.2
H
H
L
D
E
13.2
0.510
0.530 12.95
11
0.8
1.6
0.037
0.65
0.051 0.063 0.075 1.295
0.003
1
L
y
12
22
e
b
0
7
0
θ
Notes:
1. Dimension D & E do not include interlead
c
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
A1
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
θ
L
See Detail F
y
Seating Plane
L
1
Detail F
- 30 -
W78E58B/W78E058B
11. APPLICATION NOTES
11.1 In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78E058B ROM
microcontroller. In this example, microcontroller will boot from 32KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 32KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 32KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 32KB APROM.
EXAMPLE 1:
;*******************************************************************************************************************
;* Example of 32K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON EQU
CHPENR EQU
BFH
F6H
C4H
C5H
C6H
C7H
SFRAL
SFRAH
SFRFD
SFRCN
EQU
EQU
EQU
EQU
ORG
0H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR
TR0
; TR0 = 0, STOP TIMER0
MOV
MOV
RETI
TL0, R6
TH0, R7
;************************************************************************
;* 32K APROM MAIN PROGRAM
;************************************************************************
ORG100H
MAIN_32K:
MOV A, P1
; SCAN P1.0
ANL A, #01H
CJNE A, #01H, PROGRAM_32K; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE
PROGRAM_32K:
MOV CHPENR, #87H
; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
MOV CHPENR, #59H
MOV CHPCON, #03H
Publication Release Date: December 4, 2006
Revision A8
- 31 -
W78E58B/W78E058B
MOV TCON, #00H
MOV IP, #00H
; TR = 0 TIMER0 STOP
; IP = 00H
MOV IE, #82H
; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
; TL0 = F0H
; TH0 = FFH
MOV TH0, R7
MOV TMOD, #01H
MOV TCON, #10H
MOV PCON, #01H
; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 32KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
.
; User's application program
.
.
.
EXAMPLE 2:
;******************************************************************************************************************************
Example of 4 KB LDROM program: This loader program will erase the 32KB APROM first, then reads the new ;*
code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON
CHPENR
SFRAL
EQU
EQU
EQU
EQU
EQU
EQU
BFH
F6H
C4H
C5H
C6H
C7H
SFRAH
SFRFD
SFRCN
ORG 000H
LJMP 100H
; JUMP TO MAIN PROGRAM
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0
MOV TL0, R6
MOV TH0, R7
RETI
; TR0 = 0, STOP TIMER0
;************************************************************************
;* 4KB LDROM MAIN PROGRAM
;************************************************************************
ORG 100H
- 32 -
W78E58B/W78E058B
MAIN_4K:
MOV SP, #C0H
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV A, CHPCON
ANL A, #80H
CJNE A, #80H, UPDATE_32K ; CHECK F04KBOOT MODE ?
MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE
MOV TCON, #00H
MOV TMOD, #01H
MOV IP, #00H
; TCON = 00H, TR = 0 TIMER0 STOP
; TMOD = 01H, SET TIMER0 A 16BIT TIMER
; IP = 00H
MOV IE, #82H
; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H
MOV PCON, #01H
; TCON = 10H, TR0 = 1, GO
; ENTER IDLE MODE
UPDATE_32K:
MOV CHPENR, #00H ; DISABLE CHPCON WRITE-ATTRIBUTE
MOV TCON, #00H
MOV IP, #00H
; TCON = 00H , TR = 0 TIM0 STOP
; IP = 00H
MOV IE, #82H
; IE = 82H, TIMER0 INTERRUPT ENABLED
; TMOD = 01H, MODE1
MOV TMOD, #01H
MOV R6, #E0H
; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7, #B1H
MOV TL0, R6
MOV TH0, R7
ERASE_P_4K:
MOV SFRCN, #22H ; SFRCN(C7H) = 22H ERASE 32K
MOV TCON, #10H
MOV PCON, #01H
; TCON = 10H, TR0 = 1,GO
; ENTER IDLE MODE (FOR ERASE OPERATION)
;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H
MOV SFRAH, #0H
MOV SFRAL, #0H
MOV R6, #FEH
MOV R7, #FFH
MOV TL0, R6
; READ 32KB APROM MODE
; START ADDRESS = 0H
; SET TIMER FOR READ OPERATION, ABOUT 1.5 µS.
MOV TH0, R7
BLANK_CHECK_LOOP:
SETB TR0
; ENABLE TIMER 0
; ENTER IDLE MODE
; READ ONE BYTE
MOV PCON, #01H
MOV A, SFRFD
CJNE A, #FFH, BLANK_CHECK_ERROR
Publication Release Date: December 4, 2006
Revision A8
- 33 -
W78E58B/W78E058B
INC SFRAL
; NEXT ADDRESS
MOV A, SFRAL
JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A, SFRAH
CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH
JMP PROGRAM_32KROM
BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $
;*******************************************************************************
;* RE-PROGRAMMING 32KB APROM BANK
;*******************************************************************************
PROGRAM_32KROM:
MOV DPTR, #0H
MOV R2, #00H
MOV R1, #00H
MOV DPTR, #0H
MOV SFRAH, R1
; THE ADDRESS OF NEW ROM CODE
; TARGET LOW BYTE ADDRESS
; TARGET HIGH BYTE ADDRESS
; EXTERNAL SRAM BUFFER ADDRESS
; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 32K)
MOV R6, #BEH
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
; SET TIMER FOR PROGRAMMING, ABOUT 50 µS.
PROG_D_32K:
MOV SFRAL, R2
MOVX A, @DPTR
; SFRAL(C4H) = LOW BYTE ADDRESS
; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?
; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE
; SFRFD(C6H) = DATA IN
MOV SFRFD, A
MOV TCON, #10H
MOV PCON, #01H
INC DPTR
; TCON = 10H, TR0 = 1,GO
; ENTER IDLE MODE (PRORGAMMING)
INC R2
CJNE R2, #0H, PROG_D_32K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, PROG_D_32K
;*****************************************************************************
; * VERIFY 32KB APROM BANK
;*****************************************************************************
MOV R4, #03H
MOV R6, #FEH
MOV R7, #FFH
MOV TL0, R6
; ERROR COUNTER
; SET TIMER FOR READ VERIFY, ABOUT 1.5 µS.
MOV TH0, R7
MOV DPTR, #0H
MOV R2, #0H
MOV R1, #0H
MOV SFRAH, R1
; The start address of sample code
; Target low byte address
; Target high byte address
; SFRAH, Target high address
MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)
- 34 -
W78E58B/W78E058B
READ_VERIFY_32K:
MOV SFRAL, R2
MOV TCON, #10H
MOV PCON, #01H
INC R2
; SFRAL(C4H) = LOW ADDRESS
; TCON = 10H, TR0 = 1,GO
MOVX A, @DPTR
INC DPTR
CJNE A, SFRFD, ERROR_32K
CJNE R2, #0H, READ_VERIFY_32K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, READ_VERIFY_32K
;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H
MOV CHPENR, #59H
MOV CHPCON, #83H
; CHPENR = 87H
; CHPENR = 59H
; CHPCON = 83H, SOFTWARE RESET.
ERROR_32K:
DJNZ R4, UPDATE_32K ; IF ERROR OCCURS, REPEAT 3 TIMES.
.
.
.
.
; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
Publication Release Date: December 4, 2006
Revision A8
- 35 -
W78E58B/W78E058B
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A3
March, 2002
-
2
Formerly issued
A4
June, 2004
Revise part number in the item of packages
Add Important Notice
A5
April 20, 2005
June 7, 2005
October 3, 2006
December 4, 2006
34
3
A6
Add Lead Free (RoHS) parts
Remove block diagram
A7
A8
3
Remove all Leaded package parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 1-408-9436666
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
- 36 -
相关型号：
W78E065A40PL
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44
WINBOND
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