W78E52B40FL [WINBOND]
Microcontroller, 8-Bit, FLASH, 8051 CPU, 40MHz, CMOS, PQFP44;
| 型号： | W78E52B40FL |
| 厂家： | 
WINBOND |
| 描述： | Microcontroller, 8-Bit, FLASH, 8051 CPU, 40MHz, CMOS, PQFP44 微控制器 |
| 文件： | 总27页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78E52B Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1.
2.
3.
4.
5.
6.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
6.1
6.2
6.3
6.4
6.5
6.6
Timers 0, 1, and 2........................................................................................................... 7
New Defined Peripheral.................................................................................................. 7
Watchdog Timer ............................................................................................................. 9
Clock............................................................................................................................. 11
Power Management...................................................................................................... 11
Reset............................................................................................................................. 11
7.
ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 12
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Read Operation ............................................................................................................ 12
Output Disable Condition.............................................................................................. 12
Program Operation ....................................................................................................... 12
Program Verify Operation............................................................................................. 12
Erase Operation............................................................................................................ 12
Erase Verify Operation ................................................................................................. 12
Program/Erase Inhibit Operation.................................................................................. 13
8.
SECURITY BITS....................................................................................................................... 14
8.1
8.2
8.3
Lock Bit ......................................................................................................................... 14
MOVC Inhibit................................................................................................................. 14
Encryption..................................................................................................................... 14
9.
ELECTRICAL CHARACTERISTICS......................................................................................... 15
9.1
9.2
9.3
Absolute Maximum Ratings.......................................................................................... 15
D.C. Characteristics...................................................................................................... 15
A.C. Characteristics...................................................................................................... 17
10.
TIMING WAVEFORMS............................................................................................................. 20
10.1 Program Fetch Cycle.................................................................................................... 20
10.2 Data Read Cycle........................................................................................................... 20
10.3 Data Write Cycle........................................................................................................... 21
Publication Release Date: July 1, 2005
- 1 -
Revision A5
W78E52B
10.4 Port Access Cycle......................................................................................................... 21
10.5 Program Operation ....................................................................................................... 22
TYPICAL APPLICATION CIRCUITS ........................................................................................ 23
11.1 Expanded External Program Memory and Crystal....................................................... 23
11.2 Expanded External Data Memory and Oscillator ......................................................... 24
PACKAGE DIMENSIONS......................................................................................................... 25
12.1 40-pin DIP..................................................................................................................... 25
12.2 44-pin PLCC ................................................................................................................. 25
12.3 44-pin PQFP ................................................................................................................. 26
REVISION HISTORY................................................................................................................ 27
11.
12.
13.
- 2 -
W78E52B
1. GENERAL DESCRIPTION
The W78E52B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E52B is fully compatible with the standard 8051.
The W78E52B contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware
watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78E52B allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.
The W78E52B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
x
x
x
x
x
x
x
x
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 4.5V to 5.5V
256 bytes of on-chip scratchpad RAM
8 KB On-chip Flash EPROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 /INT3
(available on 44-pin PLCC/QFP package)
x
x
x
x
x
x
x
x
Three 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
Eight sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
− DIP 40:
W78E52B-40
− PLCC 44: W78E52BP-40
− PQFP 44: W78E52BF-40
− Lead Free (RoHS) DIP 40:
W78E052B40DL
− Lead Free (RoHS) PLCC 44: W78E052B40PL
− Lead Free (RoHS) PQFP 44: W78E052B40FL
Publication Release Date: July 1, 2005
Revision A5
- 3 -
W78E52B
3. PIN CONFIGURATIONS
40-Pin DIP (W78E52B)
1
2
3
4
5
6
7
8
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78E52BP)
44-Pin QFP (W78E52BF)
/
/
T
2
E
X
,
I
T
2
E
X
,
I
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
N
T
3
,
A
D
3
,
A
D
0
,
A
D
1
,
A
D
2
,
N
T
3
,
T
2
,
T
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
V
D
D
4
3
2
1
0
1
2
3
0
2
3
4
3
2
1
0
0
1
2
2
34
43 42 41 40 39 38 37 36
44
35
40
6
5
4
3
2
1
44 43 42
41
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
1
2
3
4
5
6
7
8
9
33
32
7
8
9
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
P4.1
ALE
PSEN
P2.7, A15
39
38
P1.5
P1.6
P1.7
31
30
29
28
27
26
25
37
36
35
34
33
32
31
10
11
12
13
14
15
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
10
24
16
17
30
P2.6, A14
P2.5, A13
11
23
29
T1, P3.5
13 14 15 16 17 18 19 20 21 22
12
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
0
,
1
,
3
,
4
,
2
,
0
6
,
7
,
0
,
1
,
3
,
4
,
2
,
0
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
W R
W R
R
D
R
D
- 4 -
W78E52B
4. PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
EA
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
PSEN
performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
ALE
RST
the address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
XTAL1
clock.
XTAL2
VSS
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The Port 0 is also an open-
drain port and external pull-ups need to be connected while in programming.
P0.0−P0.7
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P1.0−P1.7
P2.0−P2.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
P3.0−P3.7
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR(P3.6) : External Data Memory Write Strobe
RD(P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
P4.0-P4.3
(INT2 /INT3 ).
Publication Release Date: July 1, 2005
- 5 -
Revision A5
W78E52B
5. BLOCK DIAGRAM
P1.0
Port
1
~
Port 1
Latch
P1.7
ACC
B
INT2
INT3
P0.0
Port 0
Latch
Interrupt
Port
0
~
T2
T1
P0.7
Timer
2
DPTR
Timer
0
Stack
Pointer
PSW
Temp Reg.
PC
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
Port 3
Latch
Port
SFR RAM
Address
~
3
P3.7
Instruction
Decoder
&
Sequencer
256 bytes
RAM & SFR
P2.0
Port
~
2
Port 2
Latch
ROM
P2.7
Bus & Clock
Controller
Port 4
Latch
P4.0
~
Port
4
Watchdog
Timer
P4.3
Oscillator
Reset Block
Power control
Vss
Vcc
ALE PSEN
XTAL2
XTAL1
RST
- 6 -
W78E52B
6. FUNCTIONAL DESCRIPTION
The W78E52B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
6.1 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
6.2 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Publication Release Date: July 1, 2005
- 7 -
Revision A5
W78E52B
Eight-source interrupt information:
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
VECTOR
INTERRUPT SOURCE
ADDRESS
SEQUENCE WITHIN
PRIORITY LEVEL
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
IE.1
IE.2
IE.3
IE.4
TCON.0
1
2
3
4
5
6
-
TCON.2
-
-
-
IE.5
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
REG 0D8H
P4, #0AH
A, P4
P4,#00000001B ; Set bit P4.0
P4,#11111101B ; Clear bit P4.1
MOV
MOV
ORL
ANL
; Output data "A" through P4.0−P4.3.
; Read P4 status to Accumulator.
Reduce EMI Emission
Because of on-chip ROM, when a program is running in internal ROM space, the ALE will be unused.
The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is
useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is
located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E52B allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
- 8 -
W78E52B
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
AO: Turn off ALE output.
Power-off Flag
***PCON - Power control (87H)
-
GF1
GF0
PD
IDL
-
-
POF
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
IDL:
Power down mode bit. Set it to enter power down mode.
Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
6.3 Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
PS2
1
PS1
0
PS0
ENW CLRW WIDL
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
Publication Release Date: July 1, 2005
- 9 -
Revision A5
W78E52B
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
OSC
× 214 ×PRESCALER×1000×12 mS
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
E N W
W ID L
ID L E
E X T E R N A L
R E S E T
IN T E R N A L
R E S E T
1 4 -B IT T IM E R
C L E A R
P R E S C A L E R
O S C
1 /1 2
C L R W
W a tch d o g T im er B lo ck D ia g ra m
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
19.66 mS
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
- 10 -
W78E52B
6.4 Clock
The W78E52B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78E52B relatively insensitive to duty
cycle variations in the clock. The W78E52B incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.
6.5 Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
6.6 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E52B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
Publication Release Date: July 1, 2005
- 11 -
Revision A5
W78E52B
7. ON-CHIP FLASH EPROM CHARACTERISTICS
The W78E52B has several modes to program the on-chip ROM. All these operations are configured
by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2), OECTRL(P3.3),
CE(P3.6), OE (P3.7), A0(P1.0) and VPP(EA ). Moreover, the A15−A0(P2.7−P2.0, P1.7−P1.0) and the
D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these operations.
7.1 Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
7.2 Output Disable Condition
When the OE is set to high, no data output appears on the D7... D0.
7.3 Program Operation
This operation is used to program the data to Flash EPROM and the security bits. Program operation
is done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.
7.4 Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
7.5 Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the ROM
cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to Vep
level, CE set to low, and OE set to high.
7.6 Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if Vpp = Vep(14.5V), CE is high and OE
is low.
- 12 -
W78E52B
7.7 Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6( CE ) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
P3.0
(A9
P3.1
(A13
P3.2
(A14
P3.3
(OE
P3.6
P3.7
P2, P1
(A15.. A0) (D7.. D0)
P0
EA
(VPP)
OPERATIONS
NOTE
(CE) ( OE )
CTRL) CTRL) CTRL) CTRL)
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
Address Data Out
Output Disable
Program
Program Verify
X
Hi-Z
VCP Address Data In
VCP Address Data Out @3
Data In
0FFH
A0:0,
Erase
1
0
0
0
0
1
VEP
@4
others: X
Erase Verify
Program/Erase
Inhibit
1
0
0
0
0
0
0
1
1
0
1
VEP
Address Data Out @5
VCP/
VEP
X
X
X
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip ROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
Publication Release Date: July 1, 2005
Revision A5
- 13 -
W78E52B
8. SECURITY BITS
During the on-chip Flash EPROM operation mode, the ROM can be programmed and verified
repeatedly. Until the code inside the ROM is confirmed OK, the code can be protected. The protection
of ROM and those operations on it are described below.
The W78E52B has a Security Register which can not be accessed in normal mode. These registers
can only be accessed from the Flash EPROM operation mode. Those bits of the Security Register can
not be changed once they have been programmed from high to low. They can only be reset through
erase-all operation. The Security Register is addressed in the Flash EPROM operation mode by
address #0FFFFh.
0000h
8KB On-chip ROM
Program Memory
1FFFh
Security Bits
B2 B1 B0
Reserved
B7
Reserved
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
Security Register
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
0FFFFh
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Register
8.1 Lock Bit
This bit is used to protect the customer's program code in the W78E52B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Special Setting Register can not be accessed again.
8.2 MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
8.3 Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
- 14 -
W78E52B
+5V
+5V
V
DD
V
DD
PGM DATA
PGM DATA
A0 to A7
P1
P0
A0 to A7
P1
P0
V
IL
V
IL
V
IL
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
V
V
CP
CP
V
IL
V
IL
V
IL
V
V
IL
IL
V
V
IL
IL
RST
V
IH
RST
V
IH
V
V
IH
IL
V
IH
V
IH
PSEN
PSEN
V
IH
V
IL
X'tal1
X'tal2
Vss
X'tal1
X'tal2
Vss
A8 to A15
A8 to A15
P2
P2
Programming Configuration
Programming Verification
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
DC Power Supply
SYMBOL
VDD−VSS
VIN
MIN.
-0.3
MAX.
+7.0
UNIT
V
V
Input Voltage
VSS -0.3
0
VDD +0.3
70
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2 D.C. Characteristics
(VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.)
SPECIFICATION
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
MIN.
4.5
-
-
MAX.
5.5
20
Operating Voltage
Operating Current
Idle Current
VDD
IDD
IIDLE
V
mA
mA
No load VDD = 5.5V
Idle mode VDD = 5.5V
Power-down mode
VDD = 5.5V
6
Power Down Current
IPWDN
-
50
µA
µA
Input Current
P1, P2, P3
VDD = 5.5V
VIN = 0V or VDD
IIN1
-50
+10
Publication Release Date: July 1, 2005
Revision A5
- 15 -
W78E52B
DC Characteristics, continued
SPECIFICATION
PARAMETER
SYMBOL
TEST CONDITIONS
UNIT
MIN.
MAX.
Logical 1-to-0 Transition
Current P1, P2, P3 (*1)
Input Current
VDD = 5.5V
VIN = 2.0V (*1)
VDD = 5.5V
VIN = VDD
VDD = 5.5V
0V < VIN < VDD
ITL
-550
-
µA
µA
µA
V
IIN2
-10
-10
-
+300
+10
0.45
0.45
-
RST (*2)
Input Leakage Current
ILK
P0, EA
Output Low Voltage
P1, P2, P3
VDD = 4.5V
IOL1 = +2 mA
VOL1
VOL2
VOH1
VOH2
VIL1
Output Low Voltage
VDD = 4.5V
IOL2 = +4 mA
-
V
V
V
V
V
ALE,
, P0 (*3)
INT1
VDD = 4.5V
IOH1 = -100 µA
VDD = 4.5V
Output High Voltage
P1, P2, P3
2.4
2.4
0
Output High Voltage
-
ALE, PSEN , P0 (*3)
Input Low Voltage
(Except RST)
IOH2 = -400 µA
VDD = 4.5V
VDD = 4.5V
0.8
0.8
Input Low Voltage
RST (*4)
VIL2
0
Input Low Voltage
VIL3
VDD = 4.5V
VDD = 4.5V
0
0.8
V
XTAL1 (*4)
Input High Voltage
(Except RST)
Sink Current
P1, P2, P3, P4
Input High Voltage
RST (*4)
VIH1
ISK1
2.4
4
VDD +0.2
12
V
mA
V
VDD = 4.5V
VS = 0.45V
0.67
VDD
VIH2
VIH3
VDD = 4.5V
VDD = 4.5V
VDD +0.2
VDD +0.2
Input High Voltage
XTAL1 (*4)
0.67
VDD
V
Sink Current
VDD = 4.5V
VS = 0.45V
ISK2
ISR1
ISR2
8
-100
-8
16
-250
-14
mA
uA
(*3)
P0, ALE, PSEN
Source Current
P1, P2, P3, P4
Source Current
VDD = 4.5V
VS = 2.4V
VDD = 4.5V
V = 2.4V
mA
(*3)
P0, ALE, PSEN
- 16 -
W78E52B
Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2V.
*2. RST pin has an internal pull-down resistor.
*3. P0, ALE, PSEN are in the external access memory mode.
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
9.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
Clock Period
Clock High
Clock Low
SYMBOL
FOP
MIN.
TYP.
MAX.
UNIT
MHz
nS
nS
nS
NOTES
0
-
-
-
-
40
-
-
1
2
3
3
TCP
25
10
10
TCH
TCL
-
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Publication Release Date: July 1, 2005
Revision A5
- 17 -
W78E52B
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold from ALE Low
SYMBOL
TAAS
TAAH
MIN.
1 TCP -∆
1 TCP -∆
1 TCP -∆
-
TYP.
MAX.
UNIT
NOTES
-
-
-
-
-
-
nS
nS
nS
4
1, 4
4
TAPL
ALE Low to PSEN Low
TPDA
TPDH
TPDZ
TALW
TPSW
-
2 TCP
nS
nS
nS
nS
nS
2
3
R E S
Low to Data Valid
0
0
-
-
1 TCP
1 TCP
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
-
-
4
4
2 TCP -∆
3 TCP -∆
PSEN Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
SYMBOL
TDAR
MIN.
TYP.
MAX.
UNIT
nS
NOTES
1, 2
1
-
3 TCP -∆
3 TCP +∆
4 TCP
2 TCP
2 TCP
-
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
-
-
nS
TDDH
0
0
-
-
nS
TDDZ
nS
TDRD
6 TCP
nS
2
6 TCP -∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
SYMBOL
TDAW
MIN.
TYP.
MAX.
UNIT
nS
-
3 TCP -∆
1 TCP -∆
1 TCP -∆
6 TCP -∆
3 TCP +∆
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
TDAD
-
-
-
-
-
nS
TDWD
nS
TDWR
6 TCP
nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
- 18 -
W78E52B
Port Access Cycle
PARAMETER
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
nS
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
-
-
-
-
-
-
TPDH
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Program Operation
PARAMETER
VPP Setup Time
SYMBOL
TVPS
TDS
MIN.
2.0
2.0
2.0
2.0
0
TYP.
MAX.
UNIT
µS
-
-
-
-
-
-
-
-
-
-
Data Setup Time
Data Hold Time
µS
TDH
µS
Address Setup Time
Address Hold Time
TAS
µS
TAH
µS
CE Program Pulse Width for Program
Operation
TPWP
290
300
310
µS
OECTRL Setup Time
OECTRL Hold Time
TOCS
TOCH
TOES
2.0
2.0
2.0
-
-
-
-
-
-
µS
µS
µS
nS
OE Setup Time
TDFP
TOEV
0
-
-
-
130
150
OE High to Output Float
Data Valid from OE
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the PSEN pin must pull in VIH status.
Publication Release Date: July 1, 2005
- 19 -
Revision A5
W78E52B
10. TIMING WAVEFORMS
10.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
T
ALW
T
APL
PSEN
T
PSW
T
AAS
PORT 2
PORT 0
T
PDA
T
AAH
T
T
PDH, PDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
10.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
TDDA
TDDH, TDDZ
TDRD
- 20 -
W78E52B
Timing Waveforms, continued
10.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
T
DATA OUT
T
DWD
T
DAD
T
DWR
DAW
10.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDH
TPDA
PORT
DATA OUT
INPUT
SAMPLE
Publication Release Date: July 1, 2005
Revision A5
- 21 -
W78E52B
Timing Waveforms, continued
10.5 Program Operation
Program
Program
Verify
Read Verify
V
IH
P2, P1
(A15... A0)
Address Stable
Address Valid
V
IL
TAS
V
P3.6
(CE)
IH
T
PWP
V
IL
TAH
V
P3.3
IH
T
OCS
(OECTRL)
V
IL
TOCH
P3.7
(OE)
V
IH
T
OES
V
IL
TDFP
TDH
V
IH
P0
(A7... A0)
OUT
D
Data In
Data Out
V
IL
TDS
Vcp
TOEV
Vpp
V
IH
T
VPS
- 22 -
W78E52B
11. TYPICAL APPLICATION CIRCUITS
11.1 Expanded External Program Memory and Crystal
V
DD
V
DD
31
19
AD0
39
AD0
AD1
AD2
AD3
3
4
7
8
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
5
A0
A1
A2
A3
A4
A0
A1
A2
A3
A4
A5
A6
A7
10
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
38 AD1
37 AD2
36 AD3
A1
6
8
A2
XTAL1
9
10 u
7
A3
AD4
AD5
AD6
AD7
12
35
34
33
32
AD4 13
6
A4
R
18
9
14
15 A5
AD5
5
XTAL2
RST
A5
CRYSTAL
16
19
A6
A7
AD6 17
4
A6
3
AD7 18
A7
8.2 K
A8 25
A9 24
A8
1
11
GND
A8
21
22
23
24
25
26
27
28
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
A10
21
23
2
A9
A10
A11
A12
A13
A14
A15
INT0
12
13
A11
A12
A13
A14
A15
A10
A11
A12
A13
A14
A15
INT1
74373
26
27
1
14
15
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
OE
RD
WR
17
16
29
30
11
10
27512
PSEN
ALE
TXD
RXD
W78E52B
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
R
-
30P
15P
10P
5P
-
6.8K
4.7K
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
Publication Release Date: July 1, 2005
Revision A5
- 23 -
W78E52B
Typical Application Circuits, continued
11.2 Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
A0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39 AD0
AD1
3
4
7
8
11
12
13
15
16
17
18
19
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
2
5
A0
A1
A2
A3
A4
A5
10
9
AD0
AD1
AD2
AD3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
38
A1
37 AD2
A2
6
8
XTAL1
A3
AD3
AD4
AD5
OSCILLATOR
36
35
34
9
10 u
7
A4
12
15
AD4 13
AD5 14
AD6 17
AD7 18
6
18
9
A5
5
XTAL2
33 AD6
32 AD7
A6
16 A6
4
8.2 K
A7
19
A7
3
A8
25
24
21
23
2
RST
INT0
GND
1
11
21
A8
A9
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
OC
G
22
A9
A10
A11
A12
A13
A14
A10
A11
A12
A13
12
13
14
23
24
25
26
27
28
A10
A11
A12
A13
A14
74373
INT1
T0
T1
26
1
15
A14
CE
OE
20
22
27
GND
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
17
WR
16
29
20256
PSEN
30
11
10
ALE
TXD
RXD
7
8
W78E52B
Figure B
- 24 -
W78E52B
12. PACKAGE DIMENSIONS
12.1 40-pin DIP
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
A
5.334
0.210
0.010
0.150 0.155 0.160 3.81
0.254
A
A
B
B
c
D
E
E
e1
L
1
3.937 4.064
2
0.016 0.018
0.406 0.457 0.559
1.219 1.27 1.372
0.022
0.054
0.050
0.048
0.008
1
1
0.010 0.014 0.203 0.254 0.356
D
2.055 2.070
52.58
15.494
13.97
52.20
15.24
40
21
0.610
0.590 0.600
14.986
13.72 13.84
2.286
0.540
0.545 0.550
0.110
0.090 0.100
2.54 2.794
3.048 3.302
0
0.120 0.130 0.140
15
3.556
15
1
E
0
a
0.630 0.650 0.670 16.00 16.51 17.01
0.090
e
A
2.286
S
Notes:
1
20
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
A2
A
L
Base Plane
1
A
.
are determined at the mold parting line.
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
eA
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B 1
12.2 44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
7
39
0.185
4.699
A
0.020
0.508
A
1
0.145 0.150 0.155 3.683 3.81 3.937
A2
b1
b
0.026 0.028
0.016 0.018
0.032 0.66
0.406
0.813
0.559
0.356
0.711
0.457
0.022
HE
GE
E
0.008 0.010 0.014 0.203 0.254
c
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
D
E
0.648 0.653
0.658
0.050 BSC
e
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
17
29
0.610
0.630
GD
0.610 0.630
0.700
G
H
H
E
0.690
0.690 0.700
18
28
D
c
L E
y
0.090 0.100
2.54 2.794
0.10
0.110 2.296
0.004
L
Notes:
A2
A1
A
1. Dimension D & E do not include interlead
flash.
θ
2. Dimension b1 does not include dambar
protrusion/intrusion.
e
b
b1
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
Seating Plane
y
GD
Publication Release Date: July 1, 2005
Revision A5
- 25 -
W78E52B
Package Dimensions, continued
12.3 44-pin PQFP
HD
D
Dimension in mm
Dimension in inch
Min. Nom. Max. Min. Nom. Max.
Symbol
34
44
---
---
---
---
---
---
A
0.002 0.01
0.02
0.25
2.05
0.05
0.5
1
A
0.075 0.081 0.087 1.90
2.20
0.45
A2
b
33
1
0.01
0.014
0.006
0.25
0.018
0.010
0.35
0.101 0.152 0.254
0.004
0.390
c
0.394 0.398
0.394 0.398
0.031 0.036
10.00
10.00 10.1
9.9
9.9
10.1
D
E
e
0.390
0.025
E
HE
0.80
0.952
13.45
13.45
0.95
1.905
0.08
7
0.635
0.510 0.520
0.520
0.025 0.031
0.530 12.95 13.2
H
H
L
D
E
13.2
0.510
0.530 12.95
11
0.8
1.6
0.037
0.65
0.063 0.075 1.295
0.003
0.051
0
1
L
y
12
22
e
b
θ
7
0
Notes:
1. Dimension D & E do not include interlead
c
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
A1
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
θ
L
See Detail F
y
Seating Plane
L 1
Detail F
- 26 -
W78E52B
13. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A2
A3
A4
A5
December, 2000
June, 2004
-
3
Initial issued
Revise part number in the item of packages
Add Important Notice
April 20, 2005
July 1, 2005
26
3
Add lead free (RoHS) part number
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Publication Release Date: July 1, 2005
Revision A5
- 27 -
相关型号：
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