W78E54B-24/40 [WINBOND]
Microcontroller, 8-Bit, EEPROM, 40MHz, CMOS, PDIP40, DIP-40;
| 型号： | W78E54B-24/40 |
| 厂家： | 
WINBOND |
| 描述： | Microcontroller, 8-Bit, EEPROM, 40MHz, CMOS, PDIP40, DIP-40 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总24页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78E54B
8-BIT FLASH MICROCONTROLLER
GENERAL DESCRIPTION
The W78E54B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E54B is fully compatible with the standard 8051. The
W78E54B contains an 16K bytes FLASH ROM (Multiple-Time Programmable ROM); a 256 bytes RAM;
four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit
timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by eight
sources two-level interrupt capability. To facilitate programming and verification, the FLASH-ROM inside
the W78E54B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security.
The W78E54B microcontroller has two power reduction modes, idle mode and power-down mode, both of
which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power consumption.
The external clock can be stopped at any time and in any state without affecting the processor.
FEATURES
· Fully static design 8-bit CMOS microcontroller
· Wide supply voltage of 4.5V to 5.5V
· 256 bytes of on-chip scratchpad RAM
· 16 KB electrically erasable/programmable FLASH-ROM
· 64 KB program memory address space
· 64 KB data memory address space
· Four 8-bit bi-directional ports
· One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
· Three 16-bit timer/counters
· One full duplex serial port(UART)
· Watchdog Timer
· Eight sources, two-level interrupt capability
· EMI reduction mode
· Built-in power management
· Code protection mechanism
· Packages:
- DIP 40: W78E54B-24/40
- PLCC 44: W78E54BP-24/40
- PQFP 44: W78E54BF-24/40
Publication Release Date: January 1999
- 1 -
Revision A2
W78E54B
PIN CONFIGURATIONS
40-Pin DIP (W78E54B)
1
VDD
T2, P1.0
T2EX, P1.1
P1.2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
4
P1.3
P1.4
5
6
P1.5
7
P1.6
8
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
INT1, P3.3
T0, P3.4
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
P2.0, A8
VSS
44-Pin PLCC (W78E54BP)
44-Pin QFP (W78E54BF)
/
/
T
2
E
X
,
I
T
2
E
X
,
I
A
D
0
,
A
D
1
,
A
D
2
,
A
D
3
,
N
T
3
,
A
D
1
,
A
A
D
3
,
N
T
3
,
A
D
0
,
T
2
,
T
2
,
D
2
,
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
P
4
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
4
.
P
0
.
P
0
.
V
D
D
V
D
D
4
3
2
1
0
0
1
2
3
2
4
3
2
1
0
1
3
2
0
2
43 42 41 40 39 38 37 36
34
33
32
44
35
40
39
38
6
5
4
3
2
1
44 43 42 41
1
2
3
4
5
6
7
8
9
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
7
8
9
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
31
30
29
28
27
26
25
37
36
35
34
33
32
P1.7
10
11
12
13
14
15
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
EA
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
EA
P4.1
ALE
P4.1
ALE
PSEN
P2.7, A15
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
INT1, P3.3
T0, P3.4
T1, P3.5
31
30
29
10
11
24
23
P2.6, A14
P2.5, A13
16
17
P2.6, A14
P2.5, A13
12 13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
4
.
P
2
.
P
2
.
P
2
.
P
2
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
0
,
1
,
2
,
3
,
4
,
0
6
,
7
,
0
,
1
,
3
,
4
,
0
2
,
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
W R
W R
R
D
R
D
- 2 -
W78E54B
PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of external
ROM. It should be kept high to access internal ROM. The ROM address and data will not
EA
be presented on the bus if EA pin is high and the program counter is within on-chip ROM
area.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE
RST
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates the
address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running resets the
device.
XTAL1
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2
VSS
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
POWER SUPPLY: Supply voltage for operation.
P0.0- P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
P1.0- P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0- P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the
upper address bits for accesses to external memory.
P3.0- P3.7 PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4)
T1(P3.5)
: Timer 0 External Input
: Timer 1 External Input
WR(P3.6) :External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
P4.0- P4.3 PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
(INT2 /INT3 ).
Publication Release Date: January 1999
- 3 -
Revision A2
W78E54B
- 4 -
W78E54B
BLOCK DIAGRAM
P1.0
~
Port
1
Port 1
Latch
P1.7
ACC
B
INT2
INT3
P0.0
~
P0.7
Port 0
Latch
Interrupt
Port
0
T2
T1
Timer
2
DPTR
Temp Reg.
PC
Timer
0
Stack
Pointer
PSW
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
~
P3.7
Port
3
Port 3
Latch
SFR RAM
Address
Instruction
Decoder
&
Sequencer
256 bytes
RAM & SFR
P2.0
~
P2.7
Port
2
Port 2
Latch
ROM
Bus & Clock
Controller
Port 4
Latch
P4.0
~
P4.3
Port
4
Watchdog
Timer
Oscillator
Reset Block
Power control
Vss
ALE PSEN
XTAL1 XTAL2
RST
Vcc
FUNCTIONAL DESCRIPTION
The W78E54B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control
functions for timers 0 and 1. The T2CON register provides control functions for Timer 2. RCAP2H and
RCAP2L are used as reload/capture registers for Timer 2.
Publication Release Date: January 1999
- 5 -
Revision A2
W78E54B
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature of
the W78E54B: it is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like
Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload,
and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers
0 and 1.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown
by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable but is
not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the XICON
register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the EX2 bit of
XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
TCON.0
1
IE.1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
IE.5
-
6
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
- 6 -
W78E54B
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
REG 0D8H
P4, #0AH
A, P4
MOV
MOV
SETB
CLR
; Output data "A" through P4.0- P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
P4.0
P4.1
; Clear bit P4.1
3. Reduce EMI Emission
Because of on-chip FLASH-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it is
useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which is
located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E54B allows user to diminish the gain of on-chip oscillator amplifiers by using programmer
to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency above 24 MHz. The value of R and C1,C2 may
need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
-
-
POF
GF1
GF0
PD
IDL
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
IDL:
Power down mode bit. Set it to enter power down mode.
Idle mode bit. Set it to enter idle mode.
Publication Release Date: January 1999
Revision A2
- 7 -
W78E54B
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can be
used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system
monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the system
clock. The divider output is selectable and determines the time-out interval. When the time-out occurs, a
system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a system
monitor. This is important in real-time control applications. In case of power glitches or electro-magnetic
interference, the processor may begin to execute errant code. If this is left unchecked the entire system
may crash. The watchdog time-out selection will result in different time-out values depending on the
clock speed. The Watchdog timer will be disabled on reset. In general, software should restart the
Watchdog timer to put it into a known state. The control bits that support the Watchdog timer are
discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW
CLRW
WIDL
PS2
PS1
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled under
IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
´ 214 ´ PRESCALER´ 1000 ´ 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer , prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
- 8 -
W78E54B
ENW
WIDL
IDLE
EXTERNAL
RESET
INTERNAL
RESET
14-BIT TIMER
CLEAR
PRESCALER
OSC
1/12
CLRW
Watchdog Timer Block Diagram
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Clock
The W78E54B is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E54B relatively insensitive to duty cycle
variations in the clock. The W78E54B incorporates a built-in crystal oscillator. To make the oscillator
work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be
connected from each pin to ground. An external clock source should be connected to pin XTAL1. Pin
XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal
oscillator.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal clock
to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
Publication Release Date: January 1999
- 9 -
Revision A2
W78E54B
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a
reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E54B is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ON-CHIP FLASH ROM CHARACTERISTICS
The W78E54B has several modes to program the on-chip FLASH-ROM. All these operations are
configured by the pins RST, ALE, PSEN, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE(P3.7), A0(P1.0) and VPP(EA ). Moreover, the A15- A0(P2.7- P2.0,
P1.7- P1.0) and the D7- D0(P0.7- P0.0) serve as the address and data bus respectively for these
operations.
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
Program Operation
This operation is used to program the data to FLASH ROM and the security bits. Program operation is
done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.
Program Verify Operation
All the programming data must be checked after program operations. This operation should be performed
after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the FLASH
ROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to Vep
level, CE set to low, and OE set to high.
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if Vpp = Vep (14.5V), CE is high and OE
is low.
Program/Erase Inhibit Operation
- 10 -
W78E54B
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(CE ) = VIH, P3.7(OE) = VIH, erasing or programming of non-targeted chips is inhibited. So, except
for the P3.6 and P3.7 pins, the individual chips may have common inputs.
Company/Device ID Read Operation
This operation is supported for FLASH ROM programmer to get the company ID or device ID on the
W78E54B.
OPERATIONS P3.0
(A9
P3.1 P3.2 P3.3 P3.6
P3.7
EA
P2,P1
P0
NOTE
(A13
(A14
(OE
(VPP) (A15..A0) (D7..D0)
(CE ) (OE)
CTRL) CTRL) CTRL) CTRL)
Read
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
Address Data Out
Output Disable
Program
1
X
Hi-Z
VCP
VCP
VEP
Address
Data In
Program Verify
Erase
Address Data Out
@3
@4
A0:0,
others: X
Data In
0FFH
Erase Verify
1
0
0
0
0
0
0
1
1
0
1
VEP
Address Data Out
@5
Program/Erase
Inhibit
X
VCP/
VEP
X
X
Company ID
Device ID
1
1
0
0
0
0
0
0
0
0
0
0
1
1
A0 = 0
A0 = 1
Data Out
Data Out
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip FLASH-ROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
SECURITY BITS
During the on-chip FLASH-ROM operation mode, the FLASH-ROM can be programmed and verified
repeatedly. Until the code inside the FLASH-ROM is confirmed OK, the code can be protected. The
protection of FLASH ROM and those operations on it are described below.
The W78E54B has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in normal mode. These registers can only be
accessed from the FLASH-ROM operation mode. Those bits of the Security Registers can not be
changed once they have been programmed from high to low. They can only be reset through erase-all
operation. The contents of the Company ID and Device ID registers have been set in factory. Both
Publication Release Date: January 1999
- 11 -
Revision A2
W78E54B
registers are addressed by the A0 address line during the same specific condition. The Security Register
is addressed in the FLASH-ROM operation mode by address #0FFFFh.
D7 D6 D5 D4 D3 D2 D1 D0
Company ID (#DAH)
Device ID (#61H)
Security Bits
0000h
3FFFh
1
1
0
1
1
0
1
0
16KBFLASHROM
Program Memory
0
1
1
0
0
0
0
1
Reserved B2 B1 B0
B7
Reserved
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
Security Register
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
0FFFFh
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits. Reserved bits must be kept in logic 1.
Special Setting Registers
Lock bit
This bit is used to protect the customer's program code in the W78E54B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
FLASH ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space will
always be able to access the ROM data in both internal and external memory. If this bit is logic 1, there
are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
- 12 -
W78E54B
+5V
+5V
V DD
P0
VDD
P0
PGM DATA
V CP
PGM DATA
V CP
A0 to A7
P1
A0 to A7
P1
V
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
V
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
IL
IL
V IL
V IL
V IL
V IL
V IH
V IL
VIL
V
ALE
RST
V
IL
IL
VIL
RST
V IH
V IH
V IH
V IH
V IH
V IL
PSEN
PSEN
X'tal1
X'tal2
X'tal1
X'tal2
A8 to A15
P2
A8 to A15
P2
Vss
Vss
Programming Configuration
Programming Verification
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
MIN.
-0.3
MAX.
+7.0
UNIT
VDD- VSS
VIN
V
Input Voltage
VSS -0.3
0
VDD +0.3
70
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC CHARACTERISTICS
VCC- VSS = 5V ±10%, TA = 25° C, unless otherwise specified.
PARAMETER
SYMBOL
TEST CONDITIONS
SPECIFICATION
UNIT
MIN.
4.5
-
MAX.
5.5
Operating Voltage
VDD
IDD
-
V
Operating Current
No load, VDD = 5.5V,
RST = 1
20
mA
Idle Current
IIDLE
Idle mode VDD = 5.5V
Power-down mode
VDD = 5.5V
-
-
6
mA
Power Down Current
IPWDN
50
mA
Input Current
IIN1
ITL
VDD = 5.5V
-50
+10
-
mA
mA
P1, P2, P3, P4
VIN = 0V or VDD
Logical 1-to-0 Transition
VDD = 5.5V
-550
(*1)
(*1)
Current P1, P2, P3
, P4
VIN = 2.0V
Publication Release Date: January 1999
Revision A2
- 13 -
W78E54B
Input Current
IIN2
VDD = 5.5V
VIN = VDD
-10
+300
mA
(*2)
RST
- 14 -
W78E54B
DC Characteristics, continued
PARAMETER
SYMBOL
TEST CONDITIONS
SPECIFICATION
UNIT
MIN.
MAX.
Input Leakage Current
ILK
VDD = 5.5V
-10
+10
mA
0V < VIN < VDD
P0, EA
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
VOL1
VOL2
VDD = 4.5V
IOL1 = +2 mA
VDD = 4.5V
IOL2 = +4 mA
-
-
0.45
0.45
V
V
(*3)
ALE, PSEN, P0
Output High Voltage
P1, P2, P3, P4
VOH1
VOH2
VDD = 4.5V
2.4
2.4
-
-
V
V
IOH1 = -100 mA
VDD = 4.5V
Output High Voltage
(*3)
IOH2 = -400 mA
ALE, PSEN, P0
Input Low Voltage
(Except RST)
VIL1
VIL2
VIL3
VIH1
ISK1
VIH2
VIH3
ISK2
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
VDD = 4.5V
0
0
0.8
0.8
V
V
Input Low Voltage
(*4)
RST
Input Low Voltage
0
0.8
V
(*4)
XTAL1
Input High Voltage
(Except RST)
2.4
4
VDD +0.2
12
V
Sink Current
VDD = 4.5V
Vs = 0.45V
VDD = 4.5V
mA
V
P1, P2, P3, P4
Input High Voltage
0.67 VDD VDD +0.2
0.67 VDD VDD +0.2
(*4)
RST
Input High Voltage
VDD = 4.5V
V
(*4)
XTAL1
Sink Current
VDD = 4.5V
Vs = 0.45V
8
16
mA
(*3)
P0, ALE, PSEN
Source Current
P1, P2, P3, P4
Source Current
ISR1
ISR2
VDD = 4.5V
Vs = 2.4V
VDD = 4.5V
Vs = 2.4V
-100
-8
-250
-14
uA
mA
(*3)
P0, ALE, PSEN
Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2V.
*2. RST pin has an internal pull-down resistor.
*3. P0, ALE, PSEN are in the external access memory mode.
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
Publication Release Date: January 1999
- 15 -
Revision A2
W78E54B
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings of
the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can
be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less
than a ±20 nS variation. The numbers below represent the performance expected from a 0.6micron
CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
FOP
TCP
TCH
TCL
0
-
-
-
-
40
-
MHz
nS
1
2
3
3
Clock Period
Clock High
Clock Low
25
10
10
-
nS
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
TAAS
TAAH
TAPL
1 TCP -D
1 TCP -D
1 TCP -D
-
-
-
-
-
-
nS
nS
nS
4
1, 4
4
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
TPDA
TPDH
TPDZ
-
0
0
-
2 TCP
1 TCP
1 TCP
nS
nS
nS
2
3
-
-
Data Float after PSEN High
ALE Pulse Width
TALW
TPSW
2 TCP -D
3 TCP -D
2 TCP
3 TCP
-
-
nS
nS
4
4
PSEN Pulse Width
Notes:
1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "D" (due to buffer driving delay and wire loading) is 20 nS.
- 16 -
W78E54B
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
TDAR
3 TCP -D
-
3 TCP +D
nS
nS
nS
nS
nS
1, 2
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
TDDH
TDDZ
TDRD
-
-
4 TCP
2 TCP
2 TCP
-
1
0
0
-
-
6 TCP -D
6 TCP
2
Notes:
1. Data memory access time is 8 TCP.
2. "D" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
3 TCP -D
-
3 TCP +D
nS
nS
nS
nS
TDAD
TDWD
TDWR
1 TCP -D
1 TCP -D
6 TCP -D
-
-
-
-
-
6 TCP
Note: "D" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Program Operation
PARAMETER
VPP Setup Time
SYMBOL
TVPS
TDS
MIN.
2.0
2.0
2.0
2.0
0
TYP.
MAX.
UNIT
mS
-
-
-
-
-
-
-
-
-
-
Data Setup Time
Data Hold Time
mS
TDH
mS
Address Setup Time
Address Hold Time
TAS
mS
TAH
mS
Publication Release Date: January 1999
Revision A2
- 17 -
W78E54B
Program Operation, continued
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TPWP
290
300
310
mS
CE Program Pulse Width for
Program Operation
TOCS
TOCH
TOES
2.0
2.0
2.0
-
-
-
-
-
-
mS
mS
mS
OECTRL Setup Time
OECTRL Hold Time
OE Setup Time
TDFP
TOEV
0
-
-
-
130
150
nS
nS
OE High to Output Float
Data Valid from OE
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the PSEN pin must pull in VIH status.
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
Code
A0-A7
Data
Code
A0-A7
Data
A0-A7
- 18 -
W78E54B
Timing Waveforms, continued
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
T DDA
TDDH, T DDZ
TDRD
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
PORT 0
WR
A0-A7
DATA OUT
T DWD
T
DAD
TDAW
T DWR
Publication Release Date: January 1999
Revision A2
- 19 -
W78E54B
Timing Waveforms, continued
Port Access Cycle
S5
S6
S1
XTAL1
ALE
T
T
TPDA
PDS
PDH
PORT
DATA OUT
INPUT
SAMPLE
Program Operation
Program
Program
Verify
Read Verify
V
P2, P1
(A15... A0)
IH
Address Stable
Address Valid
V
IL
TAS
P3.6
(CE)
V
IH
TPWP
V
IL
TAH
V
P3.3
(OECTRL)
IH
TOCS
V
IL
TOCH
P3.7
(OE)
V
IH
TOES
V
IL
TDFP
TDH
V
P0
(A7... A0)
IH
Data In
DOUT
Data Out
V
IL
TDS
Vcp
TOEV
Vpp
V
IH
TVPS
- 20 -
W78E54B
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V
DD
V
DD
31
19
AD0
39
AD0 3
AD1 4
11 AD0
O0
2 A0
5 A1
6 A2
A3
12 A4
A0 10
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
EA
38 AD1
37 AD2
36 AD3
A1
A2
A3
A4
A5
A6
A7
A8
9
8
12 AD1
O1
A1
7
8
13
13
15
16
AD2
AD3
AD4
AD2
AD3
AD4
A2
XTAL1
O2
O3
O4
O5
O6
O7
9
10 u
7
A3
AD4
AD5
AD6
AD7
35
34
33
32
6
A4
R
18
9
A5
A6
A7
AD514
AD617
AD718
15
16
19
5
17 AD5
18 AD6
19 AD7
XTAL2
RST
A5
CRYSTAL
4
A6
3
A7
8.2 K
25
A8
1
GND
21 A8
A9 24
A1021
A1123
A12 2
A1326
A1427
A15 1
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
22
23
24
25
26
11
A9
A10
A11
A12
A13
A14
A15
INT0
12
13 INT1
14
15
A10
A11
A12
A13
74373
T0
T1
27 A14
28 A15
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
OE
27512
W78E54B
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
30P
15P
10P
5P
R
-
-
6.8K
4.7K
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
Publication Release Date: January 1999
Revision A2
- 21 -
W78E54B
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
AD0
AD1 4
AD2
AD3 8
13
AD4
AD5 14
AD6 17
AD7 18
A0 10
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39 AD0
38 AD1
3
2
5
6
9
A0
A1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
D0
D1
D2
D3
D4
D5
D6
D7
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
EA
9
8
7
6
5
4
3
A1
AD2
A2 A2
37
36 AD3
AD4
7
XTAL1
OSCILLATOR
A3
A4
10 u
A3
12 A4
35
34 AD5
18
9
XTAL2
15 A5 A5
P0.6 33 AD6
P0.7 32 AD7
A6
16
19 A7
A6
A7
8.2 K
A8 25
RST
INT0
GND
1
P2.0 21 A8
A9
A10
24
21
OC
G
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
A9
11
22
12
A11 23
A12 2
A13 26
A14 1
23 A10
24 A11
13
14
15
74373
INT1
T0
T1
25
26 A13
27 A14
A12
A14
GND
20
CE
OE
1
2
3
4
5
6
P2.7 28
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
22
27
RD
17
WR
WR 16
29
PSEN
30
20256
ALE
11
10
7
8
TXD
RXD
W78E54B
Figure B
- 22 -
W78E54B
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
0.210
5.334
0.010
0.254
1
A
A
0.155 0.160
0.018 0.022
0.050 0.054
0.150
0.016
3.81
3.937 4.064
0.457 0.559
2
0.406
B
0.048
0.008
1.219
0.203
1.27
0.254 0.356
52.20 52.58
1.372
1
B
0.010 0.014
2.055 2.070
c
D
D
E
40
21
0.610
15.24 15.494
13.84 13.97
0.590 0.600
0.540 0.545
14.986
13.72
2.286
0.550
1
E
e
0.090 0.100 0.110
0.120 0.130 0.140
2.54
2.794
1
3.048
0
E
1
3.302 3.556
15
L
a
0
15
0.630 0.650 0.670
0.090
16.00 16.51
17.01
2.286
A
e
S
1
20
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
A2
A
Base Plane
A1
.
L
Seating Plane
B
e 1
e A
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B
1
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
0.185
4.699
7
39
A
A
A
b
b
c
D
E
e
G
G
H
H
L
y
0.020
0.508
1
2
1
0.145 0.150 0.155 3.683
3.81 3.937
0.026 0.028 0.032
0.016 0.018 0.022
0.66 0.711 0.813
0.406
0.559
0.457
H E
E
G
E
0.008 0.010 0.014 0.203 0.254 0.356
0.648 0.653 0.658 16.46 16.59 16.71
0.648 0.653 0.658 16.46 16.59 16.71
0.050 BSC
0.590
1.27
BSC
14.99 15.49 16.00
0.610 0.630
17
29
D
0.590 0.610 0.630 14.99 15.49 16.00
0.680 0.690 0.700 17.27 17.53 17.78
E
D
18
28
c
0.680 0.690 0.700 17.27 17.53 17.78
E
0.090 0.100 0.110 2.296
0.004
2.54 2.794
0.10
L
Notes:
A
2
1
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
q
e
b
A
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
Seating Plane
y
G D
Publication Release Date: January 1999
Revision A2
- 23 -
W78E54B
Package Dimensions, continued
44-pin PQFP
H D
D
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
44
34
---
---
---
---
---
---
0.002
0.01
0.02
0.05
1.90
0.25
0.25
2.05
0.5
1
A
A
0.075 0.081
0.01 0.014
0.087
2.20
0.45
2
33
1
0.018
0.010
0.35
b
c
D
E
e
0.004 0.006
0.390 0.394
0.101
9.9
0.152
0.254
10.1
0.398
0.398
10.00
10.00
0.390
0.394
9.9
10.1
E
HE
0.025 0.031
0.510 0.520
0.952
0.036
0.530
0.635
12.95
0.80
13.2
13.2
0.8
13.45
13.45
D
H
0.510
0.520
0.530
0.037
0.075
12.95
0.65
E
H
11
0.025 0.031
0.95
L
0.063
1.295
0.051
0
1.6
1.905
0.08
1
L
0.003
7
y
q
12
22
e
b
0
7
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A 2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
q
A1
L
See Detail F
y
Seating Plane
on final visual inspection spec.
L 1
Detail F
Headquarters
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
123 Hoi Bun Rd., Kwun Tong,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
Winbond Microelectronics Corp.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
http://www.winbond.com.tw/
TEL: 408-9436666
FAX: 408-5441798
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 24 -
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