W78E54M [WINBOND]
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, TQFP-44;
| 型号： | W78E54M |
| 厂家： | 
WINBOND |
| 描述： | Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQFP44, TQFP-44 时钟 微控制器 外围集成电路 |
| 文件： | 总23页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78E54
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78E54 is an 8-bit microcontroller that is functionally compatible with the W78C54, except that
the mask ROM is replaced by a flash EEPROM with a size of 16 KB. To facilitate programming and
verification, the flash EEPROM inside the W78E54 allows the program memory to be programmed
and read electronically. Once the code is confirmed, the user can protect the code for security.
The W78E54 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the
market. It is functionally compatible with the industry-standard 80C52 microcontroller series, except
that one extra 4-bit bit-addressable I/O port (Port 4) and two additional external interrupts (INT2 ,
INT3 ).
The W78E54 contains four 8-bit bidirectional and bit-addressable I/O ports, three 16-bit
timer/counters, and a serial port. These peripherals are supported by a eight-source, two-level
interrupt capability. There are 256 bytes of RAM and an 16 KB flash EEPROM for application
programs.
The W78E54 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
· 8-bit CMOS microcontroller
· Fully static design
· Low standby current at full supply voltage
· DC-40 MHz operation
· 256 bytes of on-chip scratchpad RAM
· 16 KB electrically erasable/programmable EPROM
· 64 KB program memory address space
· 64 KB data memory address space
· Four 8-bit bidirectional ports
· One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
· Three 16-bit timer/counters
· One full duplex serial port
· Boolean processor
· Eight-source, two-level interrupt capability
· Built-in power management
· Code protection mechanism
· Packages:
- DIP 40: W78E54-16/24/40
- PLCC 44: W78E54P-16/24/40
- QFP 44: W78E54F-16/24/40
- TQFP 44: W78E54M-16/24/40
Publication Release Date: November 1997
- 1 -
Revision A2
W78E54
PIN CONFIGURATIONS
40-Pin DIP (W78E54)
1
VCC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
4
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78E54P)
44-Pin QFP/TQFP (W78E54F/W78E54M))
/
/
T
2
E
X
,
I
T
I
A
D
3
,
A
D
0
,
A
D
1
,
A
D
2
,
N
T
3
,
2
E
X
,
A
D
1
,
A
D
3
,
N
T
3
,
A
D
0
,
A
D
2
,
T
2
,
T
2
,
P
1
.
P
1
.
P
1
.
P
0
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
4
.
P
0
.
V
C
C
V
C
C
4
3
2
1
0
1
3
0
2
2
1
0
3
4
3
2
0
1
2
2
34
33
43 42 41 40
38 37 36
35
39
44
40
39
38
6
5
4
3
2
1
44 43 42
41
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
1
2
7
8
9
P1.5
P1.6
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
P1.7
RST
32
31
30
29
28
27
26
25
3
4
5
37
36
35
34
33
32
31
P1.7
10
11
12
13
14
15
RST
RXD, P3.0
EA
EA
P4.1
RXD, P3.0
INT2, P4.3
6
7
8
9
INT2, P4.3
TXD, P3.1
P4.1
ALE
TXD, P3.1
INT0, P3.2
ALE
INT0, P3.2
PSEN
P2.7, A15
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
INT1, P3.3
T0, P3.4
10
11
12
24
23
P2.6, A14
P2.5, A13
16
17
30
29
P2.6, A14
P2.5, A13
T1, P3.5
13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
3
,
0
,
1
,
2
,
4
,
0
6
,
7
,
0
,
1
,
3
,
4
,
2
,
0
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W R
W R
R
D
R
D
- 2 -
W78E54
PIN DESCRIPTION
The W78E54 has two operating modes, normal and flash. In normal mode, the W78E54 corresponds
to the W78C54. In flash mode, the user (the maker of the flash EEPROM writer) can access the flash
EEPROM.
P0.7-P0.0 Port 0, Bits 7-0
MODE
DESCRIPTION
Normal
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
Flash
This port provides the data bus during access to the flash EEPROM.
P1.7
-
P1.0 Port 1, Bits 7
-
0
MODE
DESCRIPTION
Normal
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins
P1.0 and P1.1 also serve as T2 (Timer 2 external input) and T2EX (Timer 2
capture/reload trigger), respectively.
Flash
This port provides the low-order address bus during access to the flash EEPROM.
P2.7
-
P2.0 Port 2, Bits 7
-
0
MODE
DESCRIPTION
Normal
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port
also provides the upper address bits for accesses to external memory..
Flash
This port provides the high-order address bus during access to the flash EEPROM.
P3.7
-
P3.0 Port 3, Bits 7
-
0
MODE
DESCRIPTION
Normal
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits
have alternate functions.
Flash
P3.3- P3.0 and P3.7- P3.6 are the flash mode configuration pins, Input.
P3.3- P3.0 and P3.7- P3.6 are configured to select or execute the flash operations. For
details, see Flash Operations.
P4.3
-
P4.0 Port 4, Bits 3
-
0 (available on 44-pin PLCC/QFP package)
MODE
DESCRIPTION
Normal
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O pins or external interrupt input sources
(INT2 /INT3 ).
Publication Release Date: November 1997
- 3 -
Revision A2
W78E54
Flash
No function in this mode.
EA/VPP
MODE
DESCRIPTION
EA External Access, Input, active low.
Normal
,
This pin forces the processor to execute a program from the external ROM. When the
internal flash EEPROM is accessed as in the W78C54, this pin should be kept high.
Flash
VPP, Program Power supply pin, Input.
This pin accepts the high voltage (12V) needed for programming the flash EEPROM.
RST
MODE
DESCRIPTION
Normal
RST, Reset, Input, active high.
This pin resets the processor. It must be kept high for at least two machine cycles in
order to be recognized by the processor.
Flash
Flash mode configuration pin, Input, active high.
RST is used to configure the flash operations. For details, see Flash Operations.
ALE
MODE
DESCRIPTION
Normal
Address Latch Enable, Output, active high.
ALE,
ALE is used to enable the address latch that separates the address from the data on
Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is skipped
during external data memory accesses. ALE goes to a high impedance state with a
weak pull-up during reset state.
Flash
Flash mode configuration pin, Input, active low.
ALE is used to configure the flash operations. For details, see Flash Operations.
PSEN
MODE
DESCRIPTION
Normal
PSEN Program Store Enable, Output, active low.
,
enables the external ROM onto the Port 0 address/data bus during fetch and
This pin
MOVC operations. PSEN goes to a high impedance state with a weak pull-up during
reset state
Flash
Flash mode configuration pin, Input, active high.
PSEN is used to configure the flash operations. For details, see Flash Operations.
XTAL1
MODE
DESCRIPTION
- 4 -
W78E54
Normal
Flash
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external
clock.
Connect to VSS.
XTAL2
MODE
Normal
Flash
DESCRIPTION
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
No function in this mode.
VSS, VCC
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
Publication Release Date: November 1997
Revision A2
- 5 -
W78E54
P1.0
~
P1.7
Port
1
Port 1
Latch
ACC
B
INT2
INT3
P0.0
~
P0.7
Port 0
Latch
Interrupt
Port
0
T2
T1
Timer
2
DPTR
Timer
0
Stack
Pointer
PSW
Temp Reg.
PC
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
~
P3.7
Port 3
Latch
Port
3
SFR RAM
Address
Instruction
Decoder
&
Sequencer
256 bytes
RAM & SFR
P2.0
~
P2.7
Port
2
Port 2
Latch
Bus & Clock
Controller
Port 4
Latch
P4.0
~
P4.3
Port
4
Oscillator
Reset Block
Power control
Vss
Vcc
ALE PSEN
XTAL2
RST
XTAL1
- 6 -
W78E54
FUNCTIONAL DESCRIPTION
The W78E54 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78E54: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78E54 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E54 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78E54 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
Publication Release Date: November 1997
- 7 -
Revision A2
W78E54
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
- 8 -
W78E54
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E54 is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
Option Setting
Users write programs into the W78E54 by using the Winbond proprietary writer. The writer programs
the data into an internal 16 KB region and reads the data back for verification. After confirming that
the program is correct, the user can lock the data so that they can no longer be read.
Lock Bit
This bit is used to protect the customer data in the W78E54. It may be turned on after the
programmer finishes the programming and verify sequence. Once this bit is set to logic 0, no flash
data can be accessed again.
MOVC Execute
This bit is used to restrict the region accessible to the MOVC instruction. It can prevent the program
from being downloaded using this instruction if the program needs to jump outside to get data. When
this bit is set to logic 0, a MOVC instruction in external program memory space will be able to
access code in the external memory, but it will not be able to access code in the internal memory. A
MOVC instruction in internal program memory space will always be able to access code in both
internal and external memory. If this bit is logic 1, there are no restrictions on the MOVC instruction.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2/ INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
Publication Release Date: November 1997
Revision A2
- 9 -
W78E54
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
VECTOR
ADDRESS SEQUENCE WITHIN
PRIORITY LEVEL
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
TCON.0
1
IE.1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
IE.5
-
6
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
REG 0D8H
P4, #0AH
A, P4
MOV
MOV
SETB
CLR
; Output data "A" through P4.0- P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
P4.0
P4.1
; Clear bit P4.1
3. Reduce EMI Emission
Because of the large on-chip flash EEPROM, when a program is running in internal ROM space, the
ALE will be unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI
emission if it is useless. Turning off the ALE signal transition only requires setting the bit 0 of the
- 10 -
W78E54
AUXR SFR, which is located at 08Eh. When ALE is turned off, it will be reactivated when the program
accesses external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will
turn off again after it has been completely accessed or the program returns to internal ROM code
space..
The AO bit in the AUXR register, when set, disables the ALE output.
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
GF1
GF0
PD
IDL
SMOD
-
POF
SMOD:
POF:
Double baud rate bit. When set to a 1, the baud rate is doubled when the serial port is
being used in either modes 1, 2, 3.
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
Power down mode bit. Set it to enter power down mode.
Idle mode bit. Set it to enter idle mode.
IDL:
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Flash Operations
In normal operation, the W78E54 is functionally compatible with the W78C54. In the flash operating
mode, the flash EEPROM can be programmed and verified repeatedly. Once the code inside the
flash EEPROM is confirmed, the code can be protected. The flash EEPROM and the operations on it
are described below.
All of the operations are configured by the pins RST, ALE, PSEN, A9CTRL (P3.0), A13CTRL (P3.1),
A14CTRL (P3.2), OECTRL (P3.3), CE (P3.6), OE (P3.7), A0 (P1.0) and VPP (EA ). In these
operations, A15 to A0 (P2.7 to P2.0, P1.7 to P1.0) and D7 to D0 (P0.7 to P0.0) serve as the address
and data bus, respectively.
Read Operation
This operation enables customers to read their codes and the option bits. The data will not be valid if
the lock bit is programmed to low.
Publication Release Date: November 1997
- 11 -
Revision A2
W78E54
Program Operation
This operation is used to program data to the flash EEPROM and the option bits. Programming is
initiated when VPP reaches VCP (12.5V) level, CE is set to low, and OE is set to high.
Program Verify Operation
All data must be checked after programming. This operation should be performed after each byte is
programmed, and it will ensure a substantial program margin.
OPERATION
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
P2, P1
P0
NOTES
EA
(A9
CTRL)
(A13
CTRL)
(A14
CTRL)
(OE
CTRL)
(A15 TO A0) (D7 TO D0)
(
)
(
)
OE
CE
(VPP)
Read
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIH
VCP
VCP
Address
Address
Address
Data Out
Data In
1, 2
1, 2
3
Program
Program Verify
Data Out
Notes:
1. During all of these operations, RST = VIH, ALE = VIL, and PSEN = VIH.
2. VCP = 12V, VIH = VDD, VIL = Vss.
3. The program verify operation should follow the programming operaion.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
VDD- VSS
VIN
MIN.
-0.3
MAX.
UNIT
+7.0
VDD +0.3
70
V
V
Input Voltage
VSS -0.3
0
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of
the device.
+5V
+5V
V
V
DD
DD
PGM DATA
PGM DATA
A0 to A7
P1
P0
A0 to A7
P1
P0
V
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
V
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
IL
IL
IL
IL
IH
IL
IL
IL
IL
IL
IL
IH
V
V
V
V
CP
IL
CP
IL
V
V
V
V
V
V
V
V
V
V
ALE
RST
V
V
RST
V
V
IH
IH
IH
IH
PSEN
PSEN
X'tal1
X'tal2
Vss
X'tal1
X'tal2
Vss
A8 to A15
P2
A8 to A15
P2
Programming Configuration
Programming Verification
- 12 -
W78E54
DC CHARACTERISTICS
(VDD-VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
4.5
-
MAX.
5.5
Operating Voltage
Operating Current
VDD
IDD
V
20
mA
No load
VDD = 5.5V
Idle mode
Idle Current
IIDLE
IPWDN
IIN1
-
6
mA
mA
mA
mA
mA
mA
VDD = 5.5V
Power-down mode
VDD = 5.5V
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
0 < VIN < VDD
VDD = 5.5V
0V <VIN < VDD
VDD = 5.5V
VIN =2.0V
Power Down Current
-
50
Input Current
P1, P2, P3, P4
Input Current
RST
-50
-10
-10
-500
+10
+300
+10
-200
IIN2
Input Leakage Current
P0, /EA
ILK
Logic 1 to 0 Transition
Current
ITL [*4]
P1, P2, P3, P4
Input Low Voltage
VIL1
0
0.8
V
VDD = 4.5V
P0, P1, P2, P3, P4, EA
Input Low Voltage
RST
VIL2
VIL3
VIH1
0
0
0.8
0.8
V
V
V
VDD = 4.5V
VDD = 4.5V
VDD = 5.5V
Input Low Voltage
XTAL1[*4]
Input High Voltage
2.4
VDD +0.2
P0, P1, P2, P3, P4, EA
Input High Voltage
RST
VIH2
VIH3
VOL1
3.5
3.5
-
VDD +0.2
VDD +0.2
0.45
V
V
V
VDD = 5.5V
VDD = 5.5V
Input High Voltage
XTAL1 [*4]
Output Low Voltage
P1, P2, P3, P4
VDD = 4.5V
IOL = +2 mA
Publication Release Date: November 1997
Revision A2
- 13 -
W78E54
DC Characteristics, continued
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
Output Low Voltage
P0, ALE, PSEN [*3]
VOL2
-
0.45
V
VDD = 4.5V
IOL = +4mA
Sink Current
P1, P2, P3, P4
Sink Current
ISK1
ISK2
4
12
20
mA
mA
VDD = 4.5V
Vs = 0.45V
VDD = 4.5V
Vs = 0.45V
10
P0, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
VOH1
VOH2
2.4
2.4
-
-
V
V
VDD = 4.5V
IOH = -100 mA
VDD = 4.5V
Output High Voltage
IOH = -400 mA
P0, ALE, PSEN [*3]
Source Current
P1, P2, P3, P4
Source Current
ISR1
ISR2
-120
-8
-250
-14
VDD = 4.5V
Vs = 2.4V
VDD = 4.5V
Vs = 2.4V
mA
mA
P0, ALE, PSEN
Notes:
1. RST pin is a Schmitt trigger input. RST has internal pull-low resistors of about 30 KW.
3. P0, ALE and /PSEN are tested in the external access mode.
4. XTAL1 is a CMOS input.
5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN approximates to 2V.
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.8 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
- 14 -
W78E54
PARAMETER
Operating Speed
SYMBOL
FOP
MIN.
0
TYP.
MAX.
UNIT
MHz
nS
NOTES
-
-
-
-
40
-
1
2
3
3
Clock Period
Clock High
Clock Low
TCP
25
10
10
TCH
-
nS
TCL
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
TYP.
MAX.
UNIT
nS
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
-
-
-
-
-
4
1, 4
4
1 TCP -D
TAAH
-
nS
1 TCP -D
TAPL
-
nS
1 TCP -D
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
TPDA
TPDH
TPDZ
TALW
TPSW
-
2 TCP
1 TCP
1 TCP
-
nS
2
0
0
-
nS
3
-
nS
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
nS
4
4
2 TCP -D
3 TCP -D
-
nS
PSEN Pulse Width
Notes:
1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "D" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT NOTE
S
TDAR
TDDA
TDDH
TDDZ
TDRD
-
nS
nS
nS
nS
nS
1, 2
1
3 TCP -D
3 TCP +D
4 TCP
2 TCP
2 TCP
-
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
-
-
0
0
-
-
6 TCP
2
6 TCP -D
Notes:
1. Data memory access time is 8 TCP.
2. "D" (due to buffer driving delay and wire loading) is 20 nS.
Publication Release Date: November 1997
Revision A2
- 15 -
W78E54
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
-
nS
nS
nS
nS
3 TCP -D
1 TCP -D
1 TCP -D
6 TCP -D
3 TCP +D
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
TDAD
TDWD
TDWR
-
-
-
-
-
6 TCP
Note: "D" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
TPDS
TPDH
TPDA
-
-
-
-
-
-
nS
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Program Operation
PARAMETER
VPP Setup Time
SYMBOL
TVPS
TDS
MIN.
2.0
2.0
2.0
2.0
0
TYP.
MAX.
UNIT
mS
-
-
Data Setup Time
Data Hold Time
-
-
mS
TDH
-
-
mS
Address Setup Time
Address Hold Time
TAS
-
-
-
-
mS
TAH
mS
TPWP
295
300
305
mS
CE Program Pulse Width for
Program Operation
TOPWP
295
300
305
mS
CE Program Pulse Width for
Program Operation
TOCS
TOCH
TOES
2.0
2.0
2.0
-
-
-
-
-
-
mS
mS
mS
nS
OECTRL Setup Time
OECTRL Hold Time
OE Setup Time
TDFP
TOEV
0
-
-
-
130
150
OE High to Output Float
Data Valid from OE
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and
the PSEN pin must pull in VIH status.
- 16 -
W78E54
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
TDDA
TDDH, TDDZ
TDRD
Publication Release Date: November 1997
Revision A2
- 17 -
W78E54
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
TDWD
TDAD
TDWR
TDAW
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
TPDH
DATA OUT
PORT
INPUT
SAMPLE
- 18 -
W78E54
Timing Waveforms, continued
Program Operation
Program
Program
Verify
Read Verify
V
IH
P2, P1
(A15... A0)
Address Stable
Address Valid
V
IL
TAS
V
P3.6
(CE)
IH
T
PWP
V
IL
TAH
V
P3.3
(OECTRL)
IH
T
OCS
V
IL
TOCH
P3.7
(OE)
V
IH
T
OES
V
IL
TDFP
TDH
V
IH
P0
(A7... A0)
DOUT
Data In
Data Out
V
IL
TDS
Vcp
TOEV
Vpp
V
IH
T
VPS
Publication Release Date: November 1997
Revision A2
- 19 -
W78E54
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V
CC
V
CC
31
19
AD0
AD1
AD2
39
38
37
AD0 3
11 AD0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
2 A0
10
9
8
7
6
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
EA
A1
A2
A3
A4
A5
4
7
8
13
14
17
18
5
6
12
13
15
16
17
18
19
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD1
AD2
AD3
AD4
AD5
AD6
AD7
O1
O2
O3
O4
O5
O6
O7
XTAL1
36 AD3
9
10 u
C1
AD4
AD5
AD6
AD7
35
34
33
32
12
15
R
18
9
5
XTAL2
RST
CRYSTAL
16 A6
4
19
A7
3
8.2 K
25
24
1
GND
A8
A9
A10
A11
A12
21
22
23
24
25
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
C2
A10 21
11
INT0
A11
A12
23
2
12
13
14
15
INT1
T0
T1
74LS373
A13 26
A1427
26 A13
A14
28 A15
A15
1
27
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
OE
RD
WR
PSEN
ALE
TXD
RXD
17
16
29
30
11
10
27512
W78E54
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
30P
15P
10P
5P
R
-
-
6.8K
4.7K
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 20 -
W78E54
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V
CC
V
CC
31
19
10
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
A2
A3
A4
A5
A6
A7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
39 AD0
AD1
3
4
2
5
A0
A1
A2
A3
A4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
9
8
7
6
5
4
3
38
37 AD2
36 AD3
7
6
XTAL1
OSCILLATOR
10 u
8
13
9
12
15 A5
16
19 A7
AD4
35
18
9
AD5
34
AD5 14
XTAL2
33
32
A6
AD6
AD7
17
AD6
AD7 18
8.2 K
A8 25
A9 24
RST
INT0
GND
1
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
A8
A9
OC
G
11
21
23
2
26
1
A10
A11
A12
A13
A14
22
23
24
25
26
27
28
12
A10
A11
A12
A13
A14
13
14
15
74LS373
INT1
T0
T1
GND
CE
OE
20
22
27
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
17
WR
WR 16
29
20256
PSEN
30
11
10
ALE
TXD
RXD
W78E54
Figure B
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inches
Dimension in mm
Symbol
Nom.
Nom.
Min.
Max.
0.210
Min.
Max.
5.334
A
A
A
B
B
c
0.010
0.150
0.016
0.048
0.008
0.254
3.81
1
2
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
3.937
0.457
1.27
4.064
0.559
1.372
0.356
52.58
15.494
13.97
2.794
0.406
1.219
0.203
1
0.254
52.20
15.24
13.84
2.54
D
D
E
E 1
40
21
0.590
0.540
0.090
0.600
0.545
0.100
14.986
13.72
2.286
0.550
0.110
e
L
a
1
0.140
15
3.048
0
3.302
E1
0.120
0
0.130
3.556
15
17.01
0.630
0.650
0.670
0.090
16.00
16.51
e A
S
2.286
20
1
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
2
A
A
L
A1
Base Plane
Seating Plane
.
B
B
e
1
A
e
a
1
Publication Release Date: November 1997
Revision A2
- 21 -
W78E54
Package Dimensions, continued
44-pin PLCC
H
D
D
1
6
44
40
Dimension in inches
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max.
0.185
Min.
Max.
4.699
7
39
0.020
0.145
0.026
0.508
3.683
0.66
A
A
b
b
c
D
E
e
1
2
1
0.150
0.028
3.81
3.937
0.813
0.559
0.356
16.71
16.71
0.155
0.032
0.022
0.014
0.711
0.406
0.203
16.46
16.46
0.016
0.008
0.018
0.010
0.457
0.254
H E
G E
E
16.59
16.59
0.648
0.648
0.653
0.653
0.658
0.658
0.050
BSC
1.27
BSC
0.590
0.590
0.680
0.680
0.090
14.99
14.99
17.27
17.27
2.296
15.49
15.49
17.53
17.53
2.54
16.00
16.00
17.78
17.78
2.794
0.10
17
29
0.610
0.610
0.690
0.690
0.100
0.630
0.630
0.700
0.700
0.110
0.004
G
G
H
H E
L
D
E
D
18
28
c
y
L
Notes:
A
2
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
q
e
b
A 1
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
y
Seating Plane
G
D
44-pin QFP
H D
Dimension in mm
Dimension in inch
Symbol
D
Nom.
---
Nom.
---
Min.
---
Max. Min.
Max.
---
34
44
---
---
A
A
A
b
0.002
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
2
0.081 0.087
2.20
0.45
0.075
0.01
33
1
0.014
0.006
0.394
0.394
0.031
0.520
0.520
0.031
0.018
0.010
0.398
0.35
0.101
9.9
0.152
10.00
0.254
0.004
0.390
c
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
D
E
e
H
H
L
9.9
0.398
0.036
0.530
0.530
0.037
10.00
0.80
0.390
0.025
0.510
E
HE
0.635
12.95
12.95
0.65
13.2
13.2
D
0.510
0.025
E
11
0.8
1.6
0.051 0.063 0.075
0.003
1.295
1
L
y
12
22
e
b
7
0
0
q
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A 2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
q
1
A
L
y
See Detail F
Seating Plane
L
1
Detail F
- 22 -
W78E54
Package Dimensions, continued
44-pin TQFP
H D
D
Dimension in inch
Dimension in mm
Symbol
A
Min. Nom. Max. Min. Nom. Max.
34
44
---
---
---
0.047
---
1.20
0.002
0.037
0.004
0.039
0.006
0.041
0.10
1.00
0.05
0.95
0.15
1.05
1
A
2
A
33
1
0.0039 0.013
0.22
0.090
9.9
0.38
0.015
0.008
0.398
0.32
---
b
c
D
E
e
0.200
0.004
0.390
---
0.394
10.00
10.1
10.1
0.952
12.10
12.10
0.75
---
9.9
0.394
0.031
0.472
0.472
0.024
0.039
0.398
0.390
0.025
0.468
10.00
0.80
E
HE
0.036
0.476
0.635
11.90
11.90
0.45
---
12.00
12.00
0.60
D
H
0.468
0.018
---
0.476
0.030
---
E
H
11
L
1.00
1
L
0.003
7
0.08
7
y
q
12
22
e
b
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
A
A 2
A 1
q
L
See Detail F
y
Seating Plane
L 1
Detail F
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
Rm. 803, World Trade Square, Tower II,
123 Hoi Bun Rd., Kwun Tong,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
FAX: 886-3-5792697
http://www.winbond.com.tw/
TEL: 408-9436666
FAX: 408-5441798
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
Publication Release Date: November 1997
Revision A2
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