W78L032A24FL [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78L032A24FL |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总18页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78L32/W78L032A/W78M032A
8-BIT MICROCONTROLLER
Table of Content-
1.
GENERAL DESCRIPTION ......................................................................................................... 2
FEATURES................................................................................................................................. 2
PIN CONFIGURATIONS ............................................................................................................ 3
PIN DESCRIPTION..................................................................................................................... 4
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 8
DC CHARACTERISTICS............................................................................................................ 8
AC CHARACTERISTICS.......................................................................................................... 10
TIMING WAVEFORMS............................................................................................................. 12
TYPICAL APPLICATION CIRCUITS ........................................................................................ 14
PACKAGE DIMENSIONS......................................................................................................... 16
REVISION HISTORY................................................................................................................ 18
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Publication Release Date: March 7, 2006
- 1 -
Revision A5
W78L32/W78L032A/W78M032A
1. GENERAL DESCRIPTION
The W78L32 microcontroller supplies a wider frequency range and supply voltages than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C32 microcontroller
series.
The W78L32 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78L32 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
y
y
y
y
y
y
y
y
y
y
y
y
y
Fully static design
Supply voltage of 1.8V to 5.5V
Low power consumption at full supply voltage
DC-24 MHz operation
256 bytes of on-chip scratchpad RAM
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
Three 16-bit timer/counters
One full duplex serial port
Boolean processor
Six-source, two-level interrupt capability
Built-in power management
Packages:
− DIP 40:
W78L32-24
− PLCC 44: W78L32P-24
− QFP 44: W78L32F-24
− Lead Free (RoHS) DIP 40:
W78L032A24DL, W78M032A24DL
− Lead Free (RoHS) PLCC 44: W78L032A24PL, W78M032A24PL
− Lead Free (RoHS) PQFP 44: W78L032A24FL, W78M032A24FL
- 2 -
W78L32/W78L032A/W78M032A
3. PIN CONFIGURATIONS
40-Pin DIP (W78L32)
1
2
3
4
5
6
7
8
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78L32P)
44-Pin QFP (W78L32F)
T
2
E
X
,
T
A
D
1
,
A
D
2
,
A
D
3
,
A
D
0
,
2
E
X
,
A
D
1
,
A
D
3
,
A
D
0
,
A
D
2
,
T
2
,
T
2
,
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
0
.
V
D
D
V
D
D
N
C
N
C
3
4
3
2
1
0
0
1
2
4
3
2
1
0
0
1
2
3
34
33
43 42 41 4039 38 37 36
44
35
40
6
5
4
3
2
1 44 43 42
41
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
1
2
3
4
5
6
7
8
9
7
8
9
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
P1.5
P1.6
P1.7
RST
39
38
32
31
30
29
28
27
26
25
37
36
35
34
33
32
31
10
11
12
13
14
15
RXD, P3.0
NC
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
RXD, P3.0
NC
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
10
11
24
16
17
30
23
29
T1, P3.5
12 13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
N
C
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
N
C
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
6
,
7
,
0
,
1
,
2
,
3
,
4
,
6
,
7
,
0
,
1
,
3
,
4
,
2
,
/
/
A
8
A
9
A
1
1
A
1
2
A
1
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
W R
W R
R
D
R
D
Publication Release Date: March 7, 2006
Revision A5
- 3 -
W78L32/W78L032A/W78M032A
4. PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
T0 Timer 0 Input
T1 Timer 1 Input
P3.4
P3.5
P3.6
WR Data Write Strobe
RD Data Read Strobe
P3.7
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78L32 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
- 4 -
W78L32/W78L032A/W78M032A
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
Publication Release Date: March 7, 2006
- 5 -
Revision A5
W78L32/W78L032A/W78M032A
5. BLOCK DIAGRAM
RAM
256
SFR
Bytes
Port 0
Port 1
Alternate
Timer 2
Port 2
CPU
Port 3
Data Bus
Alternate
CORE
Serial
Port
Timer 0
Interrupt
Timer 1
INT 0
INT 1
- 6 -
W78L32/W78L032A/W78M032A
6. FUNCTIONAL DESCRIPTION
The W78L32 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the W78L32: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78L32 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78L32 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78L32 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when VDD = 5V.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
Publication Release Date: March 7, 2006
- 7 -
Revision A5
W78L32/W78L032A/W78M032A
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78L32 is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
SYMBOL
VCC−VSS
VIN
MIN.
-0.3
VSS -0.3
0
MAX.
+7.0
VCC +0.3
70
UNIT
V
V
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. DC CHARACTERISTICS
(VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)
PECIFICATION
PARAMETER
SYM.
UNIT
TEST CONDITIONS
MIN.
1.8
MAX.
5.5
20
3
Operating Voltage
Operating Current
VDD
IDD
V
-
-
-
-
-
-
mA
mA
mA
mA
µA
No load, VDD = 5.5V, 20 MHz
No load, VDD = 2.0V, 16 MHz
VDD = 5.5V, Fosc = 20 MHz
VDD = 2.0V, Fosc =16 MHz
VDD = 5.5V, Fosc = 20 MHz
Idle Current
IIDLE
6
1.5
50
20
Power Down Current
IPWDN
VDD = 2.0V, Fosc = 16 MHz
VDD = 5.5V
µA
Input Current
P1, P2, P3
Input Current
RST
IIN1
IIN2
-50
-10
+10
µA
µA
VIN = 0V or VDD
VDD = 5.5V
0 < VIN < VDD
+300
Input Leakage Current
VDD = 5.5V
0V < VIN < VDD
ILK
-10
+10
-
µA
µA
P0,
Logic 1 to 0 Transition
VDD = 5.5V
VIN = 2.0V
Current
ITL [*4]
-500
P1, P2, P3
- 8 -
W78L32/W78L032A/W78M032A
DC Characteristics, continued
PARAMETER
PECIFICATION
SYM.
UNIT
TEST CONDITIONS
MIN.
0
MAX.
0.8
Input Low Voltage
VIL1
V
V
V
V
V
V
V
VDD = 4.5V
VDD = 2.0V
VDD = 4.5V
VDD = 2.0V
VDD = 4.5V
VDD = 2.0V
VDD = 5.5V
0
0.5
P0, P1, P2, P3, EA
Input Low Voltage
RST
Input Low Voltage
XTAL1 [*4]
VIL2
VIL3
VIH1
0
0
0.8
0.3
0
0.8
0
0.6
Input High Voltage
2.4
VDD +0.2
1.4
VDD +0.2
V
VDD = 2.0V
P0, P1, P2, P3,
Input High Voltage
RST
Input High Voltage
XTAL1 [*4]
Output Low Voltage
P1, P2, P3
Output Low Voltage
VIH2
VIH3
VOL1
VOL2
3.5
1.7
3.5
1.6
-
VDD +0.2
VDD +0.2
VDD +0.2
VDD +0.2
0.45
V
V
V
V
V
V
V
VDD = 5.5V
VDD = 2.0V
VDD = 5.5V
VDD = 2.0V
VDD = 4.5V, IOL = +2 mA
VDD = 2.0V, IOL = +1 mA
VDD = 4.5V, IOL = +4 mA
-
-
0.25
0.45
-
0.25
V
VDD = 2.0V, IOL = +2 mA
P0, ALE, PSEN [*3]
Sink Current
P1, P2, P3
ISK1
ISK2
4
1.8
8
9
5.4
16
mA
mA
mA
VDD = 4.5V, Vin = 0.45V
VDD = 2.0V, Vin = 0.45V
VDD = 4.5V, Vin = 0.45V
Sink Current
4.5
2.4
1.4
2.4
1.4
9
-
-
mA
V
V
VDD = 2.0V, Vin = 0.45V
P0, ALE, PSEN
Output High Voltage
P1, P2, P3
VOH1
VOH2
VDD = 4.5V, IOH = -100 µA
VDD = 2.0V, IOH = -8 µA
VDD = 4.5V, IOH = -400 µA
Output High Voltage
-
V
-
V
VDD = 2.0V, IOH = -200 µA
VDD = 4.5V,Vin = 2.4V
VDD = 2.0V,Vin = 1.4V
VDD = 4.5V,Vin = 2.4V
VDD = 2.0V,Vin = 1.4V
P0, ALE, PSEN [*3]
Source Current
P1, P2, P3
ISR1
ISR2
-100
-12
-8
-250
-30
-16
µA
µA
mA
Source Current
-1.4
-2.4
mA
P0, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*3. P0, ALE and /PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0.
Publication Release Date: March 7, 2006
Revision A5
- 9 -
W78L32/W78L032A/W78M032A
9. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
Clock Period
Clock High
SYMBOL
FOP
MIN.
0
41.7
20
TYP.
MAX.
24
-
UNIT
MHz
nS
nS
nS
NOTES
-
-
-
-
1
2
3
3
TCP
TCH
TCL
-
-
Clock Low
20
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
SYMBOL
TAAS
TAAH
TAPL
TPDA
MIN.
TYP.
-
-
-
-
-
-
MAX.
UNIT
nS
nS
nS
nS
nS
NOTES
-
-
-
4
1, 4
4
2
3
1 TCP-∆
1 TCP-∆
1 TCP-∆
-
0
0
2 TCP
1 TCP
1 TCP
-
TPDH
TPDZ
TALW
TPSW
nS
nS
2 TCP
4
4
2 TCP-∆
3 TCP-∆
3 TCP
-
nS
PSEN Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
- 10 -
W78L32/W78L032A/W78M032A
Data Read Cycle
PARAMETER
SYMBOL
TDAR
MIN.
TYP.
MAX.
3 TCP+∆
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
1
-
3 TCP-∆
ALE Low to RD Low
RD Low to Data Valid
Data Hold after RD High
Data Float after RD High
RD Pulse Width
TDDA
-
-
nS
TDDH
0
0
-
-
nS
TDDZ
nS
TDRD
6 TCP
nS
2
6 TCP-∆
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
TDAW
TDAD
TDWD
TDWR
-
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
3 TCP+∆
ALE Low to WR Low
-
-
-
-
-
nS
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
nS
6 TCP
nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: March 7, 2006
- 11 -
Revision A5
W78L32/W78L032A/W78M032A
10. TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH,
A0-A7
TPDZ
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
A0-A7
DATA
PORT 0
RD
TDDA
TDAR
TDDH, TDDZ
TDRD
- 12 -
W78L32/W78L032A/W78M032A
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
T
DWD
T
DAD
T
T
DAW
DWR
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDH
TPDA
DATA OUT
PORT
INPUT
SAMPLE
Publication Release Date: March 7, 2006
Revision A5
- 13 -
W78L32/W78L032A/W78M032A
11. TYPICAL APPLICATION CIRCUITS
Using External Program Memory and Crystal
V
DD
AD0
AD1
AD2
AD3
AD4
11
12
13
15
16
17
18
19
AD0
31
19
39
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
2
5
6
A0
A1
A2
A0
A1
A2
A3
A4
A5
A6
A7
10
9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
38 AD1
A1
AD2
AD3
AD4
AD5
37
36
35
34
8
A2
XTAL1
9 A3
10 u
7
A3
A4
A5
A6
A7
12
15
16
19
13
6
A4
R
18
9
AD5
14
5
XTAL2
RST
A5
CRYSTAL
C2
AD6
33 AD6
32 AD7
17
4
A6
AD7
18
3
A7
8.2 K
A8 25
A8
1
GND
11
21
A8
A9
A10
A11
A12
24
21
23
2
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
22 A9
23
A10
A11
A12
A13
A14
A15
INT0
12
13
14
15
A10
24
25
26
27
28
A11
A12
A13
A14
A15
INT1
74LS373
A1326
A1427
T0
T1
A15
1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
OE
RD 17
16
WR
29
PSEN
30
27512
ALE
11
TXD
10
RXD
W78L32
Figure A
CRYSTAL
C1
C2
R
16 MHz
24 MHz
30P
15P
30P
15P
-
-
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 14 -
W78L32/W78L032A/W78M032A
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V
DD
31
19
10
11
12
13
15
16
17
18
19
39
38
37
36
35
34
3
4
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
2
5
A0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
A0
A1
A2
A3
A4
A5
A6
A7
AD0
AD1
AD2
AD3
AD4
AD5
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D0
D1
D2
D3
D4
D5
D6
D7
EA
9
8
A1
6
7
A2
XTAL1
OSCILLATOR
8
9
7
10 u
A3
13
14
17
12
15
16
19
6
A4
18
9
XTAL2
RST
5
A5
33 AD6
32 AD7
4
A6
8.2 K
AD7 18
3
A7
25
A8
GND
1
11
A8
A9
P2.0 21
OC
G
24
21
23
2
A9
22
P2.1
A10
A11
A12
A13
A14
A10
A11
A12
12 INT0
P2.2 23 A10
13
A11
P2.3
24
74LS373
INT1
14
26
P2.4 25 A12
A13
A14
CE
OE
WR
T0
15
T1
P2.5 26
A13
1
P2.6
27 A14
1
GND 20
22
P2.7 28
P1.0
2
P1.1
RD
WR
3
4
5
6
17
27
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
16
29
30
11
20256
PSEN
ALE
7
8
TXD
RXD
10
W78L32
Figure B
Publication Release Date: March 7, 2006
Revision A5
- 15 -
W78L32/W78L032A/W78M032A
12. PACKAGE DIMENSIONS
40-pin DIP
Dimension in inchDimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
5.334
0.210
A
A
0.010
0.150 0.155 0.160 3.81 3.937 4.064
0.254
1
A
2
0.016 0.018
0.406 0.457 0.559
1.219 1.27 1.372
0.022
0.054
B
0.050
0.048
0.008
1
B
0.010 0.014 0.203 0.254 0.356
2.055 2.070
c
D
52.20 52.58
D
E
40
21
15.494
13.97
0.610
15.24
0.590 0.600
14.986
13.72 13.84
0.540
0.545 0.550
E
e1
L
1
0.110
0.140
15
0.090 0.100
2.286 2.54 2.794
3.048 3.302
3.556
0.120
0
0.130
1
E
0
15
a
17.01
2.286
0.630 0.650 0.670 16.00 16.51
0.090
e
A
S
Notes:
1
20
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
A2
A
L
Base Plane
1
A
.
are determined at the mold parting line.
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
eA
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
a
B1
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
7
39
0.185
4.699
A
A
0.020
0.508
1
0.145 0.150 0.155 3.683 3.81 3.937
A2
b 1
b
0.026 0.028
0.016 0.018
0.032 0.66
0.406
0.813
0.559
0.356
0.711
0.457
0.022
HE
GE
E
0.008 0.010 0.014 0.203 0.254
c
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
D
0.648 0.653
0.658
E
0.050 BSC
e
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
17
29
0.610
0.630
GD
0.610 0.630
0.690 0.700
0.690 0.700
G
H
H
E
18
28
D
c
L E
y
0.090 0.100
2.54 2.794
0.10
0.110 2.296
0.004
L
Notes:
A2
A1
A
1. Dimension D & E do not include interlead
flash.
θ
2. Dimension b1 does not include dambar
protrusion/intrusion.
e
b
b 1
3. Controlling dimension: Inches
Seating Plane
y
4. General appearance spec. should be based
on final visual inspection spec.
G D
- 16 -
W78L32/W78L032A/W78M032A
Package Dimensions, continued
44-pin QFP
HD
D
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
34
44
---
0.002 0.01 0.02
0.081 0.087
---
---
---
---
---
A
A
A
b
0.25
0.05
0.5
1
2
0.075
0.01 0.014
1.90 2.05 2.20
0.25 0.45
0.101 0.152 0.254
33
1
0.018
0.010
0.35
0.006
0.004
0.390
c
0.394 0.398
0.394 0.398
0.031 0.036
10.00
10.00
9.9
9.9
10.1
10.1
D
E
e
0.390
0.025
E
HE
0.80 0.952
0.635
0.510 0.520
13.45
0.530 12.95 13.2
D
H
H
L
13.2 13.45
0.520 0.530 12.95
0.510
E
11
0.025 0.031
0.65
0.8
0.95
1.905
0.08
7
0.037
0.051 0.063 0.075 1.295 1.6
0.003
1
L
y
12
22
e
7
b
0
0
θ
Notes:
1. Dimension D & E do not include interlead
c
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
A
A2
A1
3. Controlling dimension: Millimeter
θ
4. General appearance spec. should be based
on final visual inspection spec.
L
See Detail F
y
Seating Plane
L1
Detail F
Publication Release Date: March 7, 2006
Revision A5
- 17 -
W78L32/W78L032A/W78M032A
13. REVISION HISTORY
VERSION
DATE
PAGE
REASONS FOR CHANGE
A2
A3
A4
A5
October 2000
April 20, 2005
December 21, 2005
March 7, 2006
-
16
2
2
Add Important Notice
Add lead-free(RoHS) parts
Add 2nd lead-free(RoHS) parts
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 18 -
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