W78LE52 [WINBOND]
8-BIT MTP MICROCONTROLLER; 8位MTP单片机
| 型号： | W78LE52 |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MTP MICROCONTROLLER |
| 文件： | 总22页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary W78LE52
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE52 is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78LE52 is fully compatible with the standard 8051.
The W78LE52 contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes
RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-
bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by
eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM
inside the W78LE52 allows the program memory to be programmed and read electronically. Once the
code is confirmed, the user can protect the code for security.
The W78LE52 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
· Fully static design 8-bit CMOS microcontroller
· Wide supply voltage of 2.4V to 5.5V
· 256 bytes of on-chip scratchpad RAM
· 8 KB electrically erasable/programmable MTP-ROM
· 64 KB program memory address space
· 64 KB data memory address space
· Four 8-bit bi-directional ports
· One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
· Three 16-bit timer/counters
· One full duplex serial port(UART)
· Watchdog Timer
· Eight sources, two-level interrupt capability
· EMI reduction mode
· Built-in power management
· Code protection mechanism
· Packages:
- DIP 40: W78LE52-24
- PLCC 44: W78LE52P-24
- PQFP 44: W78LE52F-24
Publication Release Date: January 1999
- 1 -
Revision A1
Preliminary W78LE52
PIN CONFIGURATIONS
40-Pin DIP (W78LE52)
1
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
2
T2EX, P1.1
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78LE52P)
44-Pin QFP (W78LE52F)
/
/
T
2
E
X
,
I
T
2
E
X
,
I
A
D
3
,
A
D
0
,
A
D
1
,
A
D
2
,
N
T
3
,
A
D
1
,
A
D
3
,
A
D
0
,
A
D
2
,
N
T
3
,
T
2
,
T
2
,
P
0
.
P
1
.
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
P
1
.
P
1
.
P
0
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
V
D
D
V
D
D
1
0
3
4
3
2
0
1
2
2
4
3
2
1
0
1
3
0
2
2
34
33
43 42 41 40 39 38 37 36
44
35
40
39
38
6
5
4
3
2
1
44 43 42
41
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
1
2
7
8
9
P1.5
P1.6
P1.7
RST
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
P1.7
32
31
30
29
28
27
26
25
3
4
5
6
7
8
9
37
36
35
34
33
32
31
10
11
12
13
14
15
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
RXD, P3.0
INT2, P4.3
TXD, P3.1
EA
EA
P4.1
P4.1
ALE
ALE
INT0, P3.2
INT0, P3.2
PSEN
P2.7, A15
PSEN
P2.7, A15
INT1,
INT1, P3.3
T0, P3.4
T1, P3.5
10
11
12
24
23
P2.6, A14
P2.5, A13
T0, P3.4
T1, P3.5
16
17
30
29
P2.6, A14
P2.5, A13
13 14 15 16 17 18 19 20 21 22
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
2
,
A
1
0
P
4
.
6
,
7
,
0
,
1
,
3
,
4
,
2
,
0
6
,
7
,
0
,
1
,
3
,
4
,
0
/
/
A
8
A
9
A
1
0
A
1
1
A
1
2
/
/
A
8
A
9
A
1
1
A
1
2
W R
W R
R
D
R
D
- 2 -
Preliminary W78LE52
PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
EA
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PSEN
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ALE
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2
VSS
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
P0.0- P0.7
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
P1.0- P1.7
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P2.0- P2.7
P3.0- P3.7
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) :External Data Memory Write Strobe
RD(P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are
P4.0- P4.3
alternative function pins. It can be used as general I/O port or external interrupt input
sources (INT2 /INT3 ).
Publication Release Date: January 1999
- 3 -
Revision A1
Preliminary W78LE52
BLOCK DIAGRAM
P1.0
Port
1
~
Port 1
Latch
P1.7
ACC
B
INT2
INT3
P0.0
~
P0.7
Port 0
Latch
Interrupt
Port
0
T2
T1
Timer
2
DPTR
Timer
0
Stack
Pointer
PSW
Temp Reg.
PC
ALU
Timer
1
Incrementor
Addr. Reg.
UART
P3.0
~
P3.7
Port 3
Latch
Port
3
SFR RAM
Address
Instruction
Decoder
&
Sequencer
256 bytes
RAM & SFR
P2.0
~
P2.7
Port
2
Port 2
Latch
ROM
Bus & Clock
Controller
Port 4
Latch
P4.0
~
P4.3
Port
4
Watchdog
Timer
Oscillator
Reset Block
Power control
Vss
Vcc
ALE PSEN
XTAL2
RST
XTAL1
FUNCTIONAL DESCRIPTION
The W78LE52 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78LE52: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
- 4 -
Preliminary W78LE52
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
VECTOR
ADDRESS SEQUENCE WITHIN
PRIORITY LEVEL
POLLING
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
TCON.0
1
IE.1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
IE.5
-
6
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
Publication Release Date: January 1999
Revision A1
- 5 -
Preliminary W78LE52
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
REG 0D8H
P4, #0AH
A, P4
P4.0
P4.1
MOV
MOV
SETB
CLR
; Output data "A" through P4.0- P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
; Clear bit P4.1
3. Reduce EMI Emission
Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space. The
AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from
oscillation circuitry, W78LE52 allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 24MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
GF1
GF0
PD
IDL
-
-
POF
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
Power down mode bit. Set it to enter power down mode.
Idle mode bit. Set it to enter idle mode.
IDL:
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
- 6 -
Preliminary W78LE52
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW CLRW WIDL
Mnemonic: WDTC
PS2
PS1
PS0
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2- 0 as follows:
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
´ 214 ´ PRESCALER´ 1000´ 12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
Publication Release Date: January 1999
- 7 -
Revision A1
Preliminary W78LE52
ENW
WIDL
IDLE
EXTERNAL
RESET
INTERNAL
RESET
14-BIT TIMER
CLEAR
PRESCALER
OSC
1/12
CLRW
Watchdog Timer Block Diagram
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Clock
The W78LE52 is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78LE52 relatively insensitive to duty
cycle variations in the clock. The W78LE52 incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
- 8 -
Preliminary W78LE52
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78LE52 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ON-CHIP MTP ROM CHARACTERISTICS
The W78LE52 has several modes to program the on-chip MTP-ROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE(P3.6), OE (P3.7), A0(P1.0) and VPP(EA ). Moreover, the A15- A0(P2.7- P2.0,
P1.7- P1.0) and the D7- D0(P0.7- P0.0) serve as the address and data bus respectively for these
operations.
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
Program Operation
This operation is used to program the data to MTP ROM and the security bits. Program operation is
done when the Vpp is reach to Vcp (12.5V) level, CE set to low, and OE set to high.
Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the MTP
ROM cells and the security bits from 0 to 1. This erase operation is done when the Vpp is reach to
Vep level, CE set to low, and OE set to high.
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if Vpp = Vep(14.5V), CE is high and
OE is low.
Publication Release Date: January 1999
- 9 -
Revision A1
Preliminary W78LE52
PROGRAM/ERASE INHIBIT OPERATION
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(CE) = VIH, P3.7( OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
COMPANY/DEVICE ID READ OPERATION
This operation is supported for MTP ROM programmer to get the company ID or device ID on the
W78LE52.
OPERATIONS P3.0 P3.1 P3.2 P3.3 P3.6 P3.7
(A9 (A13 (A14 (OE
CTRL) CTRL) CTRL) CTRL)
P2,P1
P0
NOTE
EA
(A15..A0) (D7..D0)
(VPP)
(CE) ( OE )
Read
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
Address Data Out
Output Disable
Program
1
X
Hi-Z
Address Data In
Address Data Out @3
VCP
VCP
VEP
Program Verify
Erase
A0:0,
others: X
Data In
0FFH
@4
Erase Verify
1
0
0
0
0
0
0
1
1
0
1
VEP
Address Data Out @5
Program/Erase
Inhibit
X
VCP/
VEP
X
X
Company ID
Device ID
Notes:
1
1
0
0
0
0
0
0
0
0
0
0
1
1
A0 = 0 Data Out
A0 = 1 Data Out
1. All these operations happen in RST = VIH, ALE = VIL and
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
= VIH.
PSEN
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip MTP-ROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
SECURITY BITS
During the on-chip MTP-ROM operation mode, the MTP-ROM can be programmed and verified
repeatedly. Until the code inside the MTP-ROM is confirmed OK, the code can be protected. The
protection of MTP ROM and those operations on it are described below.
The W78LE52 has several Special Setting Registers, including the Security Register and
Company/Device ID Registers, which can not be accessed in normal mode. These registers can only
be accessed from the MTP-ROM operation mode. Those bits of the Security Registers can not be
changed once they have been programmed from high to low. They can only be reset through erase-
all operation. The contents of the Company ID and Device ID registers have been set in factory. Both
registers are addressed by the A0 address line during the same specific condition. The Security
Register is addressed in the MTP-ROM operation mode by address #0FFFFh.
- 10 -
Preliminary W78LE52
D7 D6 D5 D4 D3 D2 D1 D0
Company ID (#DAH)
Device ID (#E0H)
Security Bits
0000h
1
1
0
1
1
0
1
0
8KB MTP ROM
Program Memory
1
1
1
0
0
0
0
0
1FFFh
Reserved
B2 B1 B0
B7
Reserved
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
Security Register
0FFFFh
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Registers
Lock bit
This bit is used to protect the customer's program code in the W78LE52. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
Publication Release Date: January 1999
- 11 -
Revision A1
Preliminary W78LE52
+5V
+5V
V
DD
V
DD
PGM DATA
PGM DATA
A0 to A7
P1
P0
A0 to A7
P1
P0
EA/Vpp
V
IL
V
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
IL
V
V
CP
CP
V
IL
V
IL
V
IL
ALE
RST
V
IL
V
IL
V
IL
V
IL
V
IL
RST
V
IH
V
IH
V
IL
V
IH
V
IH
V
IH
PSEN
V
IH
PSEN
V
IL
X'tal1
X'tal2
Vss
X'tal1
X'tal2
Vss
A8 to A15
A8 to A15
P2
P2
Programming Configuration
Programming Verification
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
MIN.
-0.3
MAX.
+7.0
UNIT
V
VDD- VSS
VIN
Input Voltage
VSS -0.3
0
VDD +0.3
70
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
VSS = 0V, TA = 25° C, unless otherwise specified.
PARAMETER
SYM.
SPECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
5.5
20
Operating Voltage
Operating Current
VDD
IDD
2.4
V
-
mA
mA
mA
mA
mA
mA
mA
No load VDD = 5.5V
-
3
No load VDD = 2.4V
Idle Current
IIDLE
-
6
VDD = 5.5V, Fosc = 20 MHz
VDD = 2.4V, Fosc = 12 MHz
VDD = 5.5V, Fosc = 20 MHz
VDD = 2.4V, Fosc = 12 MHz
-
-
1.5
50
Power Down Current
IPWDN
-
20
Input Current
P1, P2, P3, P4
Input Current
RST
IIN1
IIN2
-50
+10
VDD = 5.5V
VIN = 0V or VDD
VDD = 5.5V
-10
+300
mA
0 < VIN < VDD
- 12 -
Preliminary W78LE52
DC Characteristics, continued
PARAMETER
SYM.
PECIFICATION
UNIT
TEST CONDITIONS
MIN.
MAX.
Input Leakage Current
ILK
-10
+10
VDD = 5.5V
0V < VIN < VDD
mA
mA
P0, EA
[*4]
Logic 1 to 0 Transition Current
P1, P2, P3, P4
ITL
-500
-
VDD = 5.5V
VIN = 2.0V
VDD = 4.5V
VDD = 2.4V
Input Low Voltage
VIL1
0
0
0.8
0.5
V
V
P0, P1, P2, P3, P4, EA
Input Low Voltage
RST[*1]
VIL2
VIL3
VIH1
0
0
0.8
0.3
V
V
V
V
V
V
VDD = 4.5V
VDD = 2.4V
VDD = 4.5V
VDD = 2.4V
VDD = 5.5V
VDD = 2.4V
Input Low Voltage
XTAL1 [*3]
0
0.8
0
0.6
Input High Voltage
2.4
1.4
VDD +0.2
VDD +0.2
P0, P1, P2, P3, P4,EA
Input High Voltage
RST[*1]
VIH2
VIH3
VOL1
VOL2
3.5
1.7
3.5
1.6
-
VDD +0.2
VDD +0.2
VDD +0.2
VDD +0.2
0.45
V
V
V
V
V
V
V
V
VDD = 5.5V
VDD = 2.4V
Input High Voltage
XTAL1 [*3]
VDD = 5.5V
VDD = 2.4V
Output Low Voltage
P1, P2, P3, P4
VDD = 4.5V, IOL = +2 mA
VDD = 2.4V, IOL = +1 mA
VDD = 4.5V, IOL = +4 mA
VDD = 2.4V, IOL = +2 mA
-
0.25
Output Low Voltage
-
0.45
-
0.25
P0, ALE, PSEN [*2]
Sink Current
ISK1
ISK2
4
1.8
8
12
5.4
16
9
mA
mA
mA
mA
VDD = 4.5V, Vin = 0.45V
VDD = 2.4V, Vin = 0.45V
VDD = 4.5V, Vin = 0.45V
VDD = 2.4V, Vin = 0.45V
P1, P2, P3, P4
Sink Current
4.0
P0, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
VOH1
VOH2
2.4
1.4
2.4
1.4
-
-
-
-
V
V
V
V
VDD = 4.5V, IOH = -100 mA
VDD = 2.4V, IOH = -8 mA
VDD = 4.5V, IOH = -400 mA
VDD = 2.4V, IOH = -200 mA
Output High Voltage
P0, ALE, PSEN [*2]
Source Current
P1, P2, P3, P4
ISR1
ISR2
-100
-10
-8
-250
-30
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
mA
mA
Source Current
-14
mA
mA
-1.0
-2.4
P0, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and /PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
Publication Release Date: January 1999
Revision A1
- 13 -
Preliminary W78LE52
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will
usually experience less than a ±20 nS variation. The numbers below represent the performance
expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
FOP
TCP
TCH
TCL
0
-
-
-
-
24
-
MHz
nS
1
2
3
3
Clock Period
Clock High
Clock Low
25
10
10
-
nS
-
nS
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
TYP.
MAX.
UNIT
nS
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
-
-
-
-
-
-
4
1, 4
4
1 TCP -D
1 TCP -D
1 TCP -D
-
TAAH
nS
TAPL
nS
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
TPDA
-
2 TCP
nS
2
3
TPDH
TPDZ
TALW
TPSW
0
0
-
1 TCP
nS
nS
nS
nS
-
1 TCP
Data Float after PSEN High
ALE Pulse Width
2 TCP
3 TCP
-
-
4
4
2 TCP -D
3 TCP -D
PSEN Pulse Width
Notes:
1. P0.0- P0.7, P2.0- P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "D" (due to buffer driving delay and wire loading) is 20 nS.
- 14 -
Preliminary W78LE52
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
3 TCP +D
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
TDAR
-
3 TCP -D
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
TDDH
TDDZ
TDRD
-
-
nS
1
0
0
-
-
nS
nS
6 TCP
nS
2
6 TCP -D
Notes:
1. Data memory access time is 8 TCP.
2. "D" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
MIN.
TYP.
MAX.
UNIT
TDAW
-
nS
nS
nS
nS
3 TCP -D
1 TCP -D
1 TCP -D
6 TCP -D
3 TCP +D
TDAD
TDWD
TDWR
-
-
-
-
-
6 TCP
Note: "D" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
TYP.
MAX.
UNIT
nS
1 TCP
0
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Program Operation
PARAMETER
VPP Setup Time
SYMBOL
TVPS
TDS
MIN.
2.0
TYP.
MAX.
UNIT
mS
-
-
-
-
-
-
-
-
Data Setup Time
Data Hold Time
2.0
mS
TDH
2.0
mS
Address Setup Time
TAS
2.0
mS
Publication Release Date: January 1999
Revision A1
- 15 -
Preliminary W78LE52
Program Operation, continued
PARAMETER
SYMBOL
TAH
MIN.
0
TYP.
-
MAX.
-
UNIT
mS
Address Hold Time
TPWP
290
300
310
mS
CE Program Pulse Width for
Program Operation
TOCS
TOCH
TOES
2.0
2.0
2.0
-
-
-
-
-
-
mS
mS
mS
nS
OECTRL Setup Time
OECTRL Hold Time
OE Setup Time
TDFP
TOEV
0
-
-
-
130
150
OE High to Output Float
Data Valid from OE
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status, and
the PSEN pin must pull in VIH status.
TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
- 16 -
Preliminary W78LE52
Timing Waveforms, continued
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
TDAR
TDDA
TDDH, TDDZ
TDRD
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
TDWD
TDAD
TDWR
TDAW
Publication Release Date: January 1999
Revision A1
- 17 -
Preliminary W78LE52
Timing Waveforms, continued
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
TPDH
DATA OUT
PORT
INPUT
SAMPLE
Program Operation
Program
Program
Verify
Read Verify
V
IH
P2, P1
(A15... A0)
Address Stable
Address Valid
V
IL
TAS
V
P3.6
(CE)
IH
T
PWP
V
IL
TAH
V
P3.3
(OECTRL)
IH
T
OCS
V
TOCH
IL
P3.7
(OE)
V
IH
T
OES
V
IL
TDFP
TDH
V
P0
(A7... A0)
IH
OUT
D
Data In
Data Out
V
IL
TDS
Vcp
TOEV
Vpp
V
IH
T
VPS
- 18 -
Preliminary W78LE52
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
V
DD
V
DD
31
19
AD0
AD1
39
38
3
11
AD0
AD1
AD2
AD3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
5
A0
A1
A2
A3
A4
A5
A6
A7
A8 25
A9 24
A10
A11
A12
A13
A14
A15
A0
A1
A2
A3
A4
10
9
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
4
7
8
12
13
15
16
17
18
19
A1
37 AD2
6
8
A2
XTAL1
36 AD3
9
12
10 u
7
A3
AD4
AD5
AD6
AD7
35
34
33
32
AD4 13
6
A4
R
18
9
14
17
18
15 A5
16 A6
AD5
AD6
AD7
5
XTAL2
RST
A5
CRYSTAL
4
A6
19
3
A7
A7
8.2 K
A8
1
GND
A8
A9
A10
A11
A12
A13
A14
A15
21
22
23
24
25
26
27
28
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
C1
C2
21
23
2
26
27
1
11
A10
A11
A12
A13
A14
A15
INT0
12
13
14
15
INT1
T0
T1
74373
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
22
CE
OE
RD
WR
17
16
29
30
11
10
27512
PSEN
ALE
TXD
RXD
W78LE52
Figure A
CRYSTAL
16 MHz
24 MHz
33 MHz
40 MHz
C1
30P
15P
10P
5P
C2
R
30P
15P
10P
5P
-
-
6.8K
4.7K
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
Publication Release Date: January 1999
Revision A1
- 19 -
Preliminary W78LE52
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
AD0
AD1
AD2
AD3
AD4 13
AD5 14
A0
A1
A2
A3
3
4
7
8
2
5
6
9
10
9
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
A2
A3
A4
A5
A6
A7
A8
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
39 AD0
AD1
37 AD2
36 AD3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
EA
38
8
XTAL1
7
6
5
4
3
25
OSCILLATOR
10 u
12 A4
AD4
AD5
AD6
AD7
35
34
33
32
18
9
15 A5
A6
19 A7
XTAL2
17
AD6
AD7 18
16
8.2 K
RST
INT0
GND
1
21
A9 24
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A8
A9
OC
G
21
11
A10
A11 23
A12
A13 26
22
23
24
25
26
27
28
A10
A11
A12
A13
12
13
14
15
A10
A11
A12
A13
A14
2
74373
INT1
T0
T1
1
A14
A14
GND 20
CE
OE
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
22
27
RD
17
16
29
30
11
10
WR
WR
20256
PSEN
ALE
TXD
RXD
W78LE52
Figure B
- 20 -
Preliminary W78LE52
PACKAGE DIMENSIONS
40-pin DIP
Dimension in inch
Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.210
Max.
5.334
0.010
0.150
0.016
0.048
0.008
0.254
1
A
0.155
0.018
0.050
0.010
2.055
0.160
0.022
0.054
0.014
2.070
0.610
3.81
3.937 4.064
0.457 0.559
2
A
0.406
1.219
0.203
B
1.27
1.372
0.356
1
B
0.254
c
D
E
D
52.20 52.58
40
21
15.494
13.97
2.794
15.24
13.84
2.54
0.590 0.600
14.986
13.72
0.540
0.090
0.120
0
0.545
0.100
0.550
0.110
1
E
2.286
1
e
0.140 3.048
3.302
0.130
3.556
15
1
E
L
a
15
0
17.01
0.630 0.650
0.670
0.090
16.00
16.51
A
e
S
2.286
1
20
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
A2
A
Base Plane
1
A
.
L
Seating Plane
B
e1
e
A
a
B 1
44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Symbol
A
Nom.
Nom.
Min.
Max. Min.
0.185
Max.
7
39
4.699
0.020
0.145
0.508
A
1
0.150
3.81
0.711
0.457
0.155 3.683
3.937
0.813
0.559
0.356
A2
0.026 0.028 0.032
0.022
0.66
b
b
c
1
0.406
0.016 0.018
H E
GE
E
0.008 0.010 0.014 0.203 0.254
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
0.648 0.653 0.658
0.050 BSC
D
E
e
0.590
0.590
0.680
0.680
14.99 15.49 16.00
0.610 0.630
0.610 0.630
0.690 0.700
17
29
GD
16.00
17.27 17.53 17.78
14.99 15.49
E
G
18
28
D
H
c
17.27
0.700
17.53 17.78
2.54 2.794
0.10
0.690
H
L
y
E
0.090 0.100
0.110 2.296
0.004
L
Notes:
A 2
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
q
e
b
A1
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
Seating Plane
y
G D
Publication Release Date: January 1999
Revision A1
- 21 -
Preliminary W78LE52
Package Dimensions, continued
44-pin PQFP
H D
D
Dimension in mm
Dimension in inch
Symbol
A
Nom.
---
Nom.
---
Min.
---
Max. Min.
Max.
---
34
44
---
---
0.002
0.075
0.01
0.01
0.02
0.25
2.05
0.05
1.90
0.25
0.5
1
A
0.081 0.087
2.20
0.45
A
b
c
2
33
1
0.014
0.006
0.394
0.394
0.031
0.520
0.520
0.031
0.018
0.010
0.398
0.35
0.101
9.9
0.152
10.00
0.254
0.004
0.390
10.1
10.1
0.952
13.45
13.45
0.95
1.905
0.08
7
D
E
e
9.9
0.398
0.036
0.530
0.530
0.037
10.00
0.80
0.390
0.025
0.510
E
HE
0.635
12.95
12.95
0.65
13.2
13.2
D
E
H
0.510
0.025
H
L
L
y
11
0.8
1.6
0.051 0.063 0.075
0.003
1.295
1
12
22
e
b
7
q
0
0
Notes:
1. Dimension D & E do not include interlead
flash.
c
2. Dimension b does not include dambar
protrusion/intrusion.
A
A 2
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
q
A 1
L
See Detail F
y
Seating Plane
L
1
Detail F
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
http://www.winbond.com.tw/
TEL: 408-9436666
Voice & Fax-on-demand: 886-2-27197006
FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
- 22 -
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