W79E532A40FL_技术文档

W79E532/W79L532 Data Sheet

8-BIT MICROCONTROLLER

Table of Contents-

1.

2.

3.

4.

5.

6.

7.

8.

GENERAL DESCRIPTION .................................................................................................................... 2

FEATURES............................................................................................................................................ 2

PIN CONFIGURATIONS ....................................................................................................................... 3

PIN DESCRIPTION ............................................................................................................................... 4

BLOCK DIAGRAM................................................................................................................................. 5

FUNCTIONAL DESCRIPTION .............................................................................................................. 6

MEMORY ORGANIZATION .................................................................................................................. 8

INSTRUCTION .................................................................................................................................... 26

8.1

Instruction Timing .......................................................................................................... 26

9.

POWER MANAGEMENT..................................................................................................................... 32

10. INTERRUPTS...................................................................................................................................... 35

11. PROGRAMMABLE TIMERS/COUNTERS .......................................................................................... 37

11.1

11.2

11.3

11.4

Timer/Counters 0 & 1..................................................................................................... 37

Timer/Counter 2............................................................................................................. 40

Pulse Width Modulated Outputs (PWM)........................................................................ 43

Watchdog Timer ............................................................................................................ 46

12. SERIAL PORT..................................................................................................................................... 50

12.1

12.2

Framing Error Detection ................................................................................................ 54

Multiprocessor Communications ................................................................................... 55

13. TIMED ACCESS PROTECTION ......................................................................................................... 56

14. H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH) ....................................................... 58

15. IN-SYSTEM PROGRAMMING ............................................................................................................ 59

15.1

15.2

The Loader Program Locates at LDFlash Memory ....................................................... 59

The Loader Program Locates at APFlash Memory....................................................... 59

16. H/W WRITER MODE........................................................................................................................... 59

17. SECURITY BITS.................................................................................................................................. 60

18. ELECTRICAL CHARACTERISTICS.................................................................................................... 61

18.1

18.2

18.3

Absolute Maximum Ratings........................................................................................... 61

DC Characteristics......................................................................................................... 61

A.C. Characteristics....................................................................................................... 63

19. TYPICAL APPLICATION CIRCUITS ................................................................................................... 68

20. PACKAGE DIMENSIONS.................................................................................................................... 69

21. APPLICATION NOTE.......................................................................................................................... 71

22. REVISION HISTORY........................................................................................................................... 76

Publication Release Date: November 21, 2005

- 1 -

Revision A5

W79E532/W79L532

1. GENERAL DESCRIPTION

The W79E(L)532 is a fast 8051 compatible microcontroller with a redesigned processor core without

wasted clock and memory cycles. As a result, it executes every 8051 instruction faster than the

original 8051 for the same crystal speed. Typically, the instruction executing time of W79E(L)532 is

1.5 to 3 times faster than that of traditional 8051, depending on the type of instruction. In general, the

overall performance is about 2.5 times better than the original for the same crystal speed. Giving the

same throughput with lower clock speed, power consumption has been improved. Consequently, the

W79E(L)532 is a fully static CMOS design; it can also be operated at a lower crystal clock. The

W79E(L)532 contains In-System Programmable (ISP) 128 KB bank-addressed Flash EPROM; 4KB

auxiliary Flash EPROM for loader program; on-chip 1 KB MOVX SRAM; power saving modes.

2. FEATURES

•

8-bit CMOS microcontroller

High speed architecture of 4 clocks/machine cycle

Pin compatible with standard 80C52

Instruction-set compatible with MCS-51

Four 8-bit I/O Ports; Port 0 has internal pull-up resisters enabled by software

One extra 4-bit I/O port, chip select

Three 16-bit Timers

7 interrupt sources with two levels of priority

On-chip oscillator and clock circuitry

One enhanced full duplex serial port

Dual 64KB In-System Programmable Flash EPROM banks (APFlash0 and APFlash1)

4KB Auxiliary Flash EPROM for loader program (LDFlash)

256 bytes scratch-pad RAM

1 KB on-chip SRAM for MOVX instruction

Programmable Watchdog Timer

6 channels of 8 bit PWM

Software Reset

Software programmable access cycle to external RAM/peripherals

Code protection

Packages:

− DIP 40:

W79E532A40DN, W79L532A25DN

− PLCC 44: W79E532A40PN, W79L532A25PN

− QFP 44: W79E532A40FN, W79L532A25FN

− Lead Free (RoHS)DIP 40:

W79E532A40DL, W79L532A25DL

− Lead Free (RoHS)PLCC 44: W79E532A40PL, W79L532A25PL

− Lead Free (RoHS)QFP 44: W79E532A40FL, W79L532A25FL

- 2 -

W79E532/W79L532

PACKAGE

OPERATING

FREQUENCY

OPERATING

VOLTAGE

DEVICE

NORMAL

LEAD FREE(RoHS)

W79E532

W79L532

up to 40MHz 4.5V ~ 5.5V

up to 25MHz 3.0V ~ 5.5V

DIP44, PLCC44, QFP44 DIP44, PLCC44, QFP44

3. PIN CONFIGURATIONS

T2, PWM0, P1.0

T2EX, PWM1, P1.1

PWM2, P1.2

PWM3, P1.3

PWM4, P1.4

PWM5, P1.5

P1.6

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

VDD

2

AD0, P0.0

AD1, P0.1

AD2, P0.2

AD3, P0.3

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

3

4

5

6

7

P1.7

8

RST

9

RXD, P3.0

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

10

11

12

13

14

15

16

17

18

19

20

ALE

PSEN

P2.7, A15

P2.6, A14

P2.5, A13

P2.4, A12

P2.3, A11

P2.2, A10

P2.1, A9

P2.0, A8

T1, P3.5

WR, P3.6

RD, P3.7

T1, P3.5

XTAL2

XTAL1

PWM5, P1.5

P1.6

7

39

38

37

36

35

34

33

32

31

30

29

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

PWM5, P1.5

P1.6

1

33

32

31

30

29

28

27

26

25

24

23

P0.4, AD4

P0.5, AD5

P0.6, AD6

P0.7, AD7

EA

8

2

P1.7

9

P1.7

3

RST

10

11

12

13

14

15

16

17

RST

4

RXD, P3.0

P4.3

RXD, P3.0

P4.3

5

PLCC 44-pin

QFP 44-pin

P4.1

6

P4.1

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

ALE

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4

T1, P3.5

7

ALE

PSEN

8

PSEN

P2.7, A15

P2.6, A14

P2.5, A13

9

P2.7, A15

P2.6, A14

P2.5, A13

10

11

Publication Release Date: November 21, 2005

Revision A5

- 3 -

W79E532/W79L532

4. PIN DESCRIPTION

SYMBOL TYPE

DESCRIPTIONS

EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM

I

EA

address and data will not be present on the bus if EA pin is high and the

program counter is within 128 KB area. Otherwise they will be present on the

bus.

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the

O

Port 0 address/data bus during fetch and MOVC operations. When internal

PSEN

ROM access is performed, no PSEN strobe signal outputs from this pin.

ADDRESS LATCH ENABLE: ALE is used to enable the address latch that

separates the address from the data on Port 0.

ALE

RST

O

I

RESET: A high on this pin for two machine cycles while the oscillator is running

resets the device.

CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an

external clock.

XTAL1

I

XTAL2

VSS

O

I

CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

GROUND: Ground potential

VDD

I

POWER SUPPLY: Supply voltage for operation.

PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a

multiplexed low order address/data bus during accesses to external memory.

I/O

P0.0 − P0.7

Port 0 has internal pull-up resisters enabled by software.

PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have

alternate functions which are described below:

I/O

P1.0 − P1.7

P2.0 − P2.7

T2(P1.0): Timer/Counter 2 external count input

T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control

PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also

provides the upper address bits for accesses to external memory.

PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have

alternate functions, which are described below:

RXD(P3.0) : Serial Port 0 input

TXD(P3.1) : Serial Port 0 output

INT0 (P3.2) : External Interrupt 0

I/O

P3.0 − P3.7

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input

T1(P3.5) : Timer 1 External Input

WR(P3.6) : External Data Memory Write Strobe

RD(P3.7) : External Data Memory Read Strobe

PORT 4: Port 4 is a 4-bit bi-directional I/O port. The P4.3 also provides the

alternate function REBOOT which is H/W reboot from LD flash.

I/O

P4.0 − P4.3

* Note: TYPE I : input, O: output, I/O: bi-directional.

- 4 -

W79E532/W79L532

5. BLOCK DIAGRAM

P1.0

Port 1

Port

1

ACC

Port 0

P0.0

Latch

B

P1.7

Port

0

Latch

P0.7

PWM

T1 Register

T2 Register

Interrupt

DPTR

Stack

Pointer

PSW

Temp Reg.

ALU

Timer

2

PC

Address

Bus

Incrementor

Timer

0

Addr. Reg.

SFR RAM Address

Timer

1

Instruction

Decoder

&

Flash EPROM1

Flash EPROM2

Sequencer

256 bytes

RAM & SFR

1 UARTs

P2.0

P2.7

Port

2

1KB SRAM

Port 2

Latch

Port 3

Latch

Port

3

Bus & lock

Controller

P3.0

P3.7

Port 4

Latch

Power control

P4.0

P4.3

Port

4

&

Power monitor

Oscillator

Reset Block

Watchdog Timer

CC

XTAL1 XTAL2 ALE

RST

V

GND

PSEN

Publication Release Date: November 21, 2005

Revision A5

- 5 -

W79E532/W79L532

6. FUNCTIONAL DESCRIPTION

The W79E(L)532 is 8052 pin compatible and instruction set compatible. It includes the resources of

the standard 8052 such as four 8-bit I/O Ports, three 16-bit timer/counters, full duplex serial port and

interrupt sources.

The W79E(L)532 features a faster running and better performance 8-bit CPU with a redesigned core

processor without wasted clock and memory cycles. it improves the performance not just by running at

high frequency but also by reducing the machine cycle duration from the standard 8052 period of

twelve clocks to four clock cycles for the majority of instructions. This improves performance by an

average of 1.5 to 3 times. It can also adjust the duration of the MOVX instruction (access to off-chip

data memory) between two machine cycles and nine machine cycles. This flexibility allows the

W79E(L)532 to work efficiently with both fast and slow RAMs and peripheral devices. In addition, the

W79E(L)532 contains on-chip 1KB MOVX SRAM, the address of which is between 0000H and

03FFH. It only can be accessed by MOVX instruction; this on-chip SRAM is optional under software

control.

The W79E(L)532 is an 8052 compatible device that gives the user the features of the original 8052

device, but with improved speed and power consumption characteristics. It has the same instruction

set as the 8051 family. While the original 8051 family was designed to operate at 12 clock periods per

machine cycle, the W79E(L)532 operates at a much reduced clock rate of only 4 clock periods per

machine cycle. This naturally speeds up the execution of instructions. Consequently, the W79E(L)532

can run at a higher speed as compared to the original 8052, even if the same crystal is used. Since

the W79E(L)532 is a fully static CMOS design, it can also be operated at a lower crystal clock, giving

the same throughput in terms of instruction execution, yet reducing the power consumption.

The 4 clocks per machine cycle feature in the W79E(L)532 is responsible for a three-fold increase in

execution speed. The W79E(L)532 has all the standard features of the 8052, and has a few extra

peripherals and features as well.

I/O Ports

The W79E(L)532 has four 8-bit ports and one extra 4-bit port. Port 0 can be used as an Address/Data

bus when external program is running or external memory/device is accessed by MOVC or MOVX

instruction. In these cases, it has strong pull-ups and pull-downs, and does not need any external pull-

ups. Otherwise it can be used as a general I/O port with open-drain circuit. Port 2 is used chiefly as

the upper 8-bits of the Address bus when port 0 is used as an address/data bus. It also has strong

pull-ups and pull-downs when it serves as an address bus. Port 1 and 3 act as I/O ports with alternate

functions. Port 4 serves as a general purpose I/O port as Port 1 and Port 3.

Serial I/O

The W79E(L)532 has one enhanced serial ports that are functionally similar to the serial port of the

original 8052 family. However the serial ports on the W79E(L)532 can operate in different modes in

order to obtain timing similarity as well. The serial port has the enhanced features of Automatic

Address recognition and Frame Error detection.

- 6 -

W79E532/W79L532

Timers

The W79E(L)532 has three 16-bit timers that are functionally similar to the timers of the 8052 family.

When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing

the user with the option of operating in a mode that emulates the timing of the original 8052. The

W79E(L)532 has an additional feature, the watchdog timer. This timer is used as a System Monitor or

as a very long time period timer.

Interrupts

The Interrupt structure in the W79E(L)532 is slightly different from that of the standard 8052. Due to

the presence of additional features and peripherals, the number of interrupt sources and vectors has

been increased. The W79E(L)532 provides 7 interrupt resources with two priority level, including 2

external interrupt sources, timer interrupts, serial I/O interrupts.

Power Management

Like the standard 80C52, the W79E(L)532 also has IDLE and POWER DOWN modes of operation. In

the IDLE mode, the clock to the CPU core is stopped while the timers, serial port and interrupts clock

continue to operate. In the POWER DOWN mode, all the clock are stopped and the chip operation is

completely stopped. This is the lowest power consumption state.

On-chip Data SRAM

The W79E(L)532 has 1K Bytes of data space SRAM which is read/write accessible and is memory

mapped. This on-chip MOVX SRAM is reached by the MOVX instruction. It is not used for executable

program memory. There is no conflict or overlap among the 256 bytes Scratchpad RAM and the 1K

Bytes MOVX SRAM as they use different addressing modes and separate instructions. The on-chip

MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After a reset, the DME0 bit is

cleared such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H − FFFFH

access to the external memory.

Publication Release Date: November 21, 2005

- 7 -

Revision A5

W79E532/W79L532

7. MEMORY ORGANIZATION

The W79E(L)532 separates the memory into two separate sections, the Program Memory and the

Data Memory. The Program Memory is used to store the instruction op-codes, while the Data Memory

is used to store data or for memory mapped devices.

Program Memory

The Program Memory on the standard 8052 can only be addressed to 64 Kbytes long. By invoking the

banking methodology, W79E(L)532 can extend to two 64KB flash EPROM banks, APFlash0 and

APFlash1. There are on-chip ROM banks which can be used similarly to that of the 8052. All

instructions are fetched for execution from this memory area. The MOVC instruction can also access

this memory region. There is an auxiliary 4KB Flash EPROM bank (LDFlash) resided user loader

program for In-System Programming (ISP). Both APFlashs allow serial or parallel download according

to user loader program in LDFlash.

Data Memory

The W79E(L)532 can access up to 64Kbytes of external Data Memory. This memory region is

accessed by the MOVX instructions. Unlike the 8051 derivatives, the W79E(L)532 contains on-chip

1K bytes MOVX SRAM of Data Memory, which can only be accessed by MOVX instructions. These

1K bytes of SRAM are between address 0000H and 03FFH. Access to the on-chip MOVX SRAM is

optional under software control. When enabled by software, any MOVX instruction that uses this area

will go to the on-chip RAM. MOVX addresses greater than 03FFH automatically go to external

memory through Port 0 and 2. When disabled, the 1KB memory area is transparent to the system

memory map. Any MOVX directed to the space between 0000H and FFFFH goes to the expanded

bus on Port 0 and 2. This is the default condition. In addition, the W79E(L)532 has the standard 256

bytes of on-chip Scratchpad RAM. This can be accessed either by direct addressing or by indirect

addressing. There are also some Special Function Registers (SFRs), which can only be accessed by

direct addressing. Since the Scratchpad RAM is only 256 bytes, it can be used only when data

contents are small. In the event that larger data contents are present, two selections can be used.

One is on-chip MOVX SRAM, the other is the external Data Memory. The on-chip MOVX SRAM can

only be accessed by a MOVX instruction, the same as that for external Data Memory. However, the

on-chip RAM has the fastest access times.

FFh

FFFFh

Indirect

Addressing

RAM

SFRs

Direct

Addressing

64K Bytes

On-chip

64K Bytes

On-chip

80h

7Fh

64 K

Program

Memory

Direct &

Indirect

Addressing

RAM

Program

Memory

Bytes

External

Data

00h

Memory

APFlash0

APFlash1

0FFFh

03FFh

0000h

4K Bytes

1K Bytes

On-chip SRAM

LDFlash

0000h

Figure 1. Memory Map

- 8 -

W79E532/W79L532

Special Function Registers

The W79E(L)532 uses Special Function Registers (SFRs) to control and monitor peripherals and their

Modes.

The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some

of the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular

bit without changing the others. The SFRs that are bit addressable are those whose addresses end in

0 or 8. The W79E(L)532 contains all the SFRs present in the standard 8052. However, some

additional SFRs have been added. In some cases unused bits in the original 8052 have been given

new functions. The list of SFRs is as follows. The table is condensed with eight locations per row.

Empty locations indicate that there are no registers at these addresses. When a bit or register is not

implemented, it will read high.

Table 1. Special Function Register Location Table

F8

F0

E8

E0

D8

D0

C8

C0

B8

B0

A8

A0

98

90

88

80

EIP

B

EIE

ACC

WDCON

PSW

T2CON

PWMP

T2MOD

SADEN

PWM0

PWM1

PWMCON1 PWM2

PWM3

RCAP2L

RCAP2H

PWM5

TL2

TH2

PWMCON2 PWM4

TA

PMR

STATUS

IP

P3

IE

SADDR

XRAMAH

SBUF

ROMCON SFRAL

SFRAH

P4

SFDFD

SFRCN

P2

P4CSIN

P42AL

P4CONA

TL0

SCON0

P1

P42AH

P4CONB

TL1

P43AL

P40AL

TH0

P43AH

P40AH

TH1

CHPCON

P41AH

P41AL

TCON

P0

TMOD

SP

CKCON

DPL

DPH

PCON

Note: The SFRs in the column with dark borders are bit-addressable.

Publication Release Date: November 21, 2005

Revision A5

- 9 -

W79E532/W79L532

A brief description of the SFRs is shown follows.

Port 0

Bit:

7

6

5

4

3

2

1

0

P0.7

P0.6

P0.5

P0.4

P0.3

P0.2

P0.1

P0.0

Mnemonic: P0

Address: 80h

Port 0 is an open-drain bi-directional I/O port. This port also provides a multiplexed low order

address/data bus during accesses to external memory. Besides, it has internal pull-up resisters

enabled by setting P0UP of P4CSIN (A2H) to high.

Stack Pointer

Bit:

7

6

5

4

3

2

1

0

SP.7

SP.6

SP.5

SP.4

SP.3

SP.2

SP.1

SP.0

Mnemonic: SP

Address: 81h

The Stack Pointer stores the Scratchpad RAM address where the stack begins. In other words, it

always points to the top of the stack.

Data Pointer Low

Bit:

7

6

5

4

3

2

1

0

DPL.7 DPL.6 DPL.5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0

Mnemonic: DPL

Address: 82h

This is the low byte of the standard 8052 16-bit data pointer.

Data Pointer High

Bit:

7

6

5

4

3

2

1

0

DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0

Mnemonic: DPH

Address: 83h

This is the high byte of the standard 8052 16-bit data pointer.

Power Control

Bit:

7

6

5

-

4

-

3

2

1

0

SMOD0

SM0D

GF1

GF0

PD

IDL

Mnemonic: PCON

Address: 87h

SMOD : This bit doubles the serial port baud rate in mode 1, 2, and 3 when set to 1.

SMOD0: Framing Error Detection Enable: When SMOD0 is set to 1, then SCON.7 indicates a Frame

Error and acts as the FE flag. When SMOD0 is 0, then SCON.7 acts as per the standard

8052 function.

GF1-0: These two bits are general purpose user flags.

- 10 -

W79E532/W79L532

PD:

Setting this bit causes the W79E(L)532 to go into the POWER DOWN mode. In this mode all

the

clocks are stopped and program execution is frozen.

IDL:

Setting this bit causes the W79E(L)532 to go into the IDLE mode. In this mode the clocks to

the

CPU are stopped, so program execution is frozen. But the clock to the serial, timer and

interrupt blocks is not stopped, and these blocks continue operating.

Timer Control

Bit:

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Mnemonic: TCON

Address: 88h

TF1: Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when

the program does a timer 1 interrupt service routine. Software can also set or clear this bit.

TR1: Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.

TF0: Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when

the program does a timer 0 interrupt service routine. Software can also set or clear this bit.

TR0: Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.

IE1:

Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is

cleared by hardware when the service routine is vectored to only if the interrupt was edge

triggered. Otherwise it follows the pin.

IT1:

IE0:

Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered

external inputs.

Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is

cleared by hardware when the service routine is vectored to only if the interrupt was edge

triggered. Otherwise it follows the pin.

IT0:

Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered

external inputs.

Timer Mode Control

Bit:

7

6

5

4

3

2

1

0

GATE

M1

M0

GATE

M1

M0

C / T

TIMER1

TIMER0

Address: 89h

Mnemonic: TMOD

GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and

TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.

Publication Release Date: November 21, 2005

- 11 -

Revision A5

W79E532/W79L532

C / T : Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set

, the timer counts high-to-low edges of the Tx pin.

M1, M0: Mode Select bits:

M1

0

M0

0

MODE

Mode 0: 8-bits with 5-bit prescale.

Mode 1: 18-bits, no prescale.

0

1

0

Mode 2: 8-bits with auto-reload from THx

1

Mode 3: (Timer 0) TL0 is an 8-bit timer/counter controlled by the standard Timer 0

control bits. TH0 is a 8-bit timer only controlled by Timer 1 control bits. (Timer 1)

Timer/counter is stopped.

Timer 0 LSB

Bit:

7

6

5

4

3

2

1

0

TL0.7

TL0.6

TL0.5

TL0.4

TL0.3

TL0.2

TL0.1

TL0.0

Mnemonic: TL0

Address: 8Ah

TL0.7−0: Timer 0 LSB

Timer 1 LSB

Bit:

7

6

5

4

3

2

TL1.2

1

0

TL1.7

TL1.6

TL1.5

TL1.4

TL1.3

TL1.1

TL1.0

Mnemonic: TL1

Address: 8Bh

TL1.7−0: Timer 1 LSB

Timer 0 MSB

Bit:

7

6

5

4

3

2

TH0.2

1

0

TH0.7

TH0.6

TH0.5

TH0.4

TH0.3

TH0.1 TH0.0

Mnemonic: TH0

Address: 8Ch

TH0.7−0: Timer 0 MSB

Timer 1 MSB

Bit:

7

6

5

4

3

2

TH1.2

1

0

TH1.7

TH1.6

TH1.5

TH1.4

TH1.3

TH1.1 TH1.0

Mnemonic: TH1

TH1.7−0: Timer 1 MSB

Address: 8Dh

- 12 -

W79E532/W79L532

Clock Control

Bit:

7

6

5

4

3

2

1

0

WD1

WD0

T2M

T1M

T0M

MD2

MD1

MD0

Mnemonic: CKCON

Address: 8Eh

WD1−0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog

timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time-

out period.

WD1 WD0

Interrupt time-out

Reset time-out

2¹⁷+ 512

2¹⁷

2²⁰

2²³

2²⁶

0

1

0

1

0

1

2²⁰+ 512

2²³+ 512

2²⁶+ 512

T2M: Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to

0 it uses a divide by 12 clock.

T1M: Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to

0 it uses a divide by 12 clock.

T0M: Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when set to

0 it uses a divide by 12 clock.

MD2−0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX

instruction. Using a variable MOVX length enables the user to access slower external

memory devices or peripherals without the need for external circuits. The RD or WR strobe

will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX

instruction is always in 2 machine cycles regardless of the stretch setting. By default, the

stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be

selected.

MD2 MD1 MD0 Stretch value MOVX duration

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

2 machine cycles

3 machine cycles (Default)

4 machine cycles

5 machine cycles

6 machine cycles

7 machine cycles

8 machine cycles

9 machine cycles

Publication Release Date: November 21, 2005

Revision A5

- 13 -

W79E532/W79L532

Port 1

Bit:

7

6

5

4

3

2

1

0

P1.7

P1.6

P1.5

P1.4

P1.3

P1.2

P1.1

P1.0

Mnemonic: P1

Address: 90h

P1.7−0: General purpose I/O port. Most instructions will read the port pins in case of a port read

access, however in case of read-modify-write instructions, the port latch is read. Some pins

also have alternate input or output functions. This alternate functions are described below:

P1.0 : T2

External I/O for Timer/Counter 2

P1.1 : T2EX

Timer/Counter 2 Capture/Reload Trigger

Port 4 Control Register A

Bit:

7

6

5

4

3

2

1

0

P41M1 P41M0 P41C1 P41C0 P40M1 P40M0 P40C1 P40C0

Mnemonic: P4CONA

Address: 92h

Port 4 Control Register B

Bit:

7

6

5

4

3

2

1

0

P43M1 P43M0 P43C1 P43C0 P42M1 P42M0 P42C1 P42C0

Mnemonic: P4CONB Address: 93h

BIT NAME

FUNCTION

P4xM1, P4xM0

Port 4 alternate modes.

=00: Mode 0. P4.x is a general purpose I/O port which is the same as Port 1.

=01: Mode 1. P4.x is a Read Strobe signal for chip select purpose. The address

range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0.

=10: Mode 2. P4.x is a Write Strobe signal for chip select purpose. The address

range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0.

=11: Mode 3. P4.x is a Read/Write Strobe signal for chip select purpose. The

address range depends on the SFR P4xAH, P4xAL and bits P4xC1, P4xC0

P4xC1, P4xC0

Port 4 Chip-select Mode address comparison:

=00: Compare the full address (16 bits length) with the base address registers

P4xAH and P4xAL.

=01: Compare the 15 high bits (A15-A1) of address bus with the base address

registers P4xAH and P4xAL.

=10: Compare the 14 high bits (A15-A2) of address bus with the base address

registers P4xAH and P4xAL.

=11: Compare the 8 high bits (A15-A8) of address bus with the base address

registers P4xAH and P4xAL.

- 14 -

W79E532/W79L532

P4.0 Base Address Low Byte Register

Bit:

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Mnemonic: P40AL

P4.0 Base Address High Byte Register

Address: 94h

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: P40AH

P4.1 Base Address Low Byte Register

Address: 95h

Bit:

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Mnemonic: P41AL

P4.1 Base Address High Byte Register

Address: 96h

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: P41AH

Serial Port Control

Bit:

Address: 97h

7

6

5

4

3

2

1

0

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

Mnemonic: SCON

Address: 98h

SM0/FE: Serial port 0, Mode 0 bit or Framing Error Flag: The SMOD0 bit in PCON SFR determines

whether this bit acts as SM0 or as FE. The operation of SM0 is described below. When

used

as FE, this bit will be set to indicate an invalid stop bit. This bit must be manually cleared in

software to clear the FE condition.

SM1:

Serial port Mode bit 1:

SM0

SM1

Mode

Description

Synchronous

Asynchronous 10

Asynchronous 11

Length

8

Baud rate

4/12 Tclk

Variable

64/32 Tclk

Variable

0

1

0

1

0

1

0

1

2

3

SM2: Multiple processors communication. Setting this bit to 1 enables the multiprocessor

communication feature in mode 2 and 3. In mode 2 or 3, if SM2 is set to 1, then RI will not be

activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = 1, then RI will not be

activated if a valid stop bit was not received. In mode 0, the SM2 bit controls the serial port

clock. If set to 0, then the serial port runs at a divide by 12 clock of the oscillator. This gives

Publication Release Date: November 21, 2005

- 15 -

Revision A5

W79E532/W79L532

compatibility with the standard 8052. When set to 1, the serial clock become divide by 4 of the

oscillator clock. This results in faster synchronous serial communication.

REN: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.

TB8: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software

as desired.

RB8: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2 = 0, RB8 is the stop bit

that was received. In mode 0 it has no function.

TI:

Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or

at the beginning of the stop bit in all other modes during serial transmission. This bit must be

cleared by software.

RI:

Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or

halfway through the stop bits time in the other modes during serial reception. However the

restrictions of SM2 apply to this bit. This bit can be cleared only by software.

Serial Data Buffer

Bit:

7

6

5

4

3

2

1

0

SBUF.7 SBUF.6 SBUF.5 SBUF.4 SBUF.3 SBUF.2 SBUF.1 SBUF.0

Mnemonic: SBUF Address: 99h

SBUF.7-0: Serial data on the serial port 0 is read from or written to this location. It actually consists of

two separate internal 8-bit registers. One is the receive resister, and the other is the

transmit buffer. Any read access gets data from the receive data buffer, while write access

is to the transmit data buffer.

P4.2 Base Address Low Byte Register

Bit:

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Mnemonic: P42AL

P4.2 Base Address High Byte Register

Address: 9Ah

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: P42AH

P4.3 Base Address Low Byte Register

Address: 9Bh

Bit:

7

6

5

4

3

2

1

0

A7

A6

A5

A4

A3

A2

A1

A0

Mnemonic: P43AL

P4.3 Base Address High Byte Register

Address: 9Ch

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: P43AH

Address: 9Dh

- 16 -

W79E532/W79L532

ISP Control Register

Bit:

7

6

-

5

4

-

3

-

2

-

1

0

SWRST/HWB

LDAP

LDSEL

ENP

Mnemonic: CHPCON

Address: 9Fh

SWRST/HWB: Set this bit to launch a whole device reset that is same as asserting high to RST pin,

micro controller will be back to initial state and clear this bit automatically. To read this

bit, its alternate function to indicate the ISP hardware reboot mode is invoking when

read it in high.

LDAP: This bit is Read Only. High: device is executing the program in LDFlash. Low: device is

executing the program in APFlashs.

LDSEL: Loader program residence selection. Set to high to route the device fetching code from

LDFlash.

ENP: In System Programming Mode Enable. Set this be to launch the ISP mode. Device will operate

ISP procedures, such as Erase, Program and Read operations, according to correlative SFRs

settings. During ISP mode, device achieves ISP operations by the way of IDLE state. In the

other words, device is not indeed in IDLE mode is set bit PCON.1 while ISP is enabled. Clear

this bit to disable ISP mode, device get back to normal operation including IDLE state.

Software Reset

Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFlash after time

out.

Port 2

Bit:

7

6

5

4

3

2

1

0

P2.7

P2.6

P2.5

P2.4

P2.3

P2.2

P2.1

P2.0

Mnemonic: P2

Address: A0h

P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper

address bits for accesses to external memory.

Port 4 Chip-select Polarity

Bit:

7

6

5

4

3

-

2

-

1

-

0

P43INV P42INV P42INV P40INV

Mnemonic: P4CSIN

P0UP

Address: A2h

P4xINV: The active polarity of P4.x when set it as chip-select signal. High = Active High. Low = Active

Low.

P0UP: Enable Port 0 weak pull up.

Publication Release Date: November 21, 2005

- 17 -

Revision A5

W79E532/W79L532

Port 4

Bit:

7

-

6

-

5

-

4

-

3

2

1

0

P4.3

P4.2

P4.1

P4.0

Mnemonic: P4

Address: A5h

P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups. Port 4 can not use bit-addressable

instruction (SETB or CLR).

Interrupt Enable

Bit:

7

6

5

4

3

2

1

0

EA

ES1

ET2

ES

ET1

EX1

ET0

EX0

Mnemonic: IE

Global enable. Enable/disable all interrupts.

ET2: Enable Timer 2 interrupt.

ES: Enable Serial Port 0 interrupt.

Address: A8h

EA:

ET1: Enable Timer 1 interrupt

EX1: Enable external interrupt 1

ET0: Enable Timer 0 interrupt

EX0: Enable external interrupt 0

Slave Address

Bit:

7

6

5

4

3

2

1

0

Mnemonic: SADDR

Address: A9h

SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to

which the slave processor is designated.

ROM Banking Control

Bit:

7

-

6

-

5

-

4

-

3

2

1

0

EN128K DCP12 DCP11 DCP10

Address: ABh

Mnemonic: ROMCON

EN128K: On-chip ROM banking enable. Set this bit to enable APFlash0 and APFlash1 by banking

mechanism. The P1.x is selected to be the auxiliary highest address line A16.

DCP1x: A16 selection. By default, P1.7 is defined as A16.

A16

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

DCP12

DCP11

DCP10

0

1

0

1

0

1

0

1

0

1

0

1

- 18 -

W79E532/W79L532

ISP Address Low Byte

Bit:

7

6

5

4

3

2

1

A1

0

A7

A6

A5

A4

A3

A2

A0

Mnemonic: SFRAL

Address: ACh

Low byte destination address for In System Programming operation. SFRAH and SFRAL address a

specific ROM byte for erasure, programming or read.

ISP Address High Byte

Bit:

7

6

5

4

3

2

1

0

A15

A14

A13

A12

A11

A10

A9

A8

Mnemonic: SFRAH

Address: ADh

High byte destination address for In System Programming operation. SFRAH and SFRAL address a

specific ROM byte for erasure, programming or read.

ISP Data Buffer

Bit:

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Mnemonic: SFRFD

Address: AEh

In ISP mode, read/write a specific byte ROM content must go through SFRFD register.

ISP Operation Modes

Bit:

7

6

5

4

3

2

1

0

BANK WFWIN NOE

NCE

CTRL3 CTRL2 CTRL1 CTRL0

Mnemonic: SFRCN

Address: AFh

BANK: Select APFlash banks for ISP. Set it 1 access to APFlash1, clear it to APFlash0.

WFWIN: Destination ROM bank for programming, erasure and read. 0 = APFlashx, 1 = LDFlash.

NOE: Flash EPROM output enable.

NCE: Flash EPROM chip enable.

CTRL[3:0]: Mode Selection.

SFRAH,

SFRAL

ISP Mode

BANK

WFWIN

NOE

NCE

CTRL<3:0>

SFRFD

Erase 4KB LDFlash

Erase 64K APFlash0

Erase 64K APFlash1

Program 4KB LDFlash

0

1

0

1

0

1

0

0010

0001

X

Address in

Data in

Publication Release Date: November 21, 2005

Revision A5

- 19 -

W79E532/W79L532

Continued

SFRAH,

SFRAL

ISP Mode

BANK

WFWIN

NOE

NCE

CTRL<3:0>

SFRFD

Program 64KB APFlash0

Program 64KB APFlash1

Read 4KB LDFlash

0

1

0

1

0

1

0

1

0

0001

0000

Address in

Data in

Data out

Read 64KB APFlash0

Read 64KB APFlash1

Port 3

Bit:

7

6

5

4

3

2

1

0

P3.7

P3.6

P3.5

P3.4

P3.3

P3.2

P3.1

P3.0

Mnemonic: P3

Address: B0h

P3.7-0: General purpose I/O port. Each pin also has an alternate input or output function. The

alternate functions are described below.

P3.7

RD

Strobe for read from external RAM

P3.6

P3.5

P3.4

WR

T1

T0

Strobe for write to external RAM

Timer/counter 1 external count input

Timer/counter 0 external count input

P3.3

INT1 External interrupt 1

INT0 External interrupt 0

P3.2

P3.1

P3.0

TxD

RxD

Serial port 0 output

Serial port 0 input

Interrupt Priority

Bit:

7

-

6

-

5

4

3

2

1

0

PT2

PS

PT1

PX1

PT0

PX0

Mnemonic: IP

Address: B8h

IP.7:

PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.

PS: This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.

This bit is un-implemented and will read high.

PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.

PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.

PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.

PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

- 20 -

W79E532/W79L532

Slave Address Mask Enable

Bit:

7

6

5

4

3

2

1

0

Mnemonic: SADEN

Address: B9h

SADEN: This register enables the Automatic Address Recognition feature of the Serial port 0. When

a bit in the SADEN is set to 1, the same bit location in SADDR will be compared with the

incoming serial data. When SADEN.n is 0, then the bit becomes a "don't care" in the

comparison. This register enables the Automatic Address Recognition feature of the Serial

port 0. When all the bits of SADEN are 0, interrupt will occur for any incoming address.

Power Management Register

Bit:

7

-

6

-

5

-

4

-

3

-

2

1

-

0

ALE-OFF

DME0

Mnemonic: PMR

Address: C4h

ALE0FF: This bit disables the expression of the ALE signal on the device pin during all on-board

program and data memory accesses. External memory accesses will automatically enable

ALE independent of ALEOFF.

0 = ALE expression is enable; 1 = ALE expression is disable

DME0: This bit determines the on-chip MOVX SRAM to be enabled or disabled. Set this bit to 1 will

enable the on-chip 1KB MOVX SRAM.

Status Register

Bit:

7

-

6

5

4

-

3

-

2

-

1

-

0

-

HIP

LIP

Mnemonic: STATUS

Address: C5h

HIP: High Priority Interrupt Status. When set, it indicates that software is servicing a high priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

LIP: Low Priority Interrupt Status. When set, it indicates that software is servicing a low priority

interrupt. This bit will be cleared when the program executes the corresponding RETI

instruction.

Timed Access

Bit:

7

6

5

4

3

2

1

0

TA.7

TA.6

TA.5

TA.4

TA.3

TA.2

TA.1

TfA.0

Mnemonic: TA

Address: C7h

TA: The Timed Access register controls the access to protected bits. To access protected bits, the

user must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.

Now a window is opened in the protected bits for three machine cycles, during which the user can

write to these bits.

Publication Release Date: November 21, 2005

- 21 -

Revision A5

W79E532/W79L532

Timer 2 Control

Bit:

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK EXEN2

TR2

C / T2 CP / RL2

Mnemonic: T2CON

Address: C8h

TF2: Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is

equal to the capture register in down count mode. It can be set only if RCLK and TCLK are

both 0. It is cleared only by software. Software can also set or clear this bit.

EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will

cause this flag to set based on the CP / RL2, EXEN2 and DCEN bits. If set by a negative

transition, this flag must be cleared by software. Setting this bit in software or detection of a

negative transition on T2EX pin will force a timer interrupt if enabled.

RCLK: Receive Clock Flag: This bit determines the serial port 0 time-base when receiving data in

serial modes 1 or 3. If it is 0, then timer 1 overflow is used for baud rate generation, otherwise

timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.

TCLK: Transmit Clock Flag: This bit determines the serial port 0 time-base when transmitting data in

modes 1 and 3. If it is set to 0, the timer 1 overflow is used to generate the baud rate clock

otherwise timer 2 overflow is used. Setting this bit forces timer 2 in baud rate generator mode.

EXEN2: Timer 2 External Enable. This bit enables the capture/reload function on the T2EX pin if

Timer 2 is not generating baud clocks for the serial port. If this bit is 0, then the T2EX pin will

be ignored, otherwise a negative transition detected on the T2EX pin will result in capture or

reload.

TR2: Timer 2 Run Control. This bit enables/disables the operation of timer 2. Clearing this bit will

halt the timer 2 and preserve the current count in TH2, TL2.

C / T2 : Counter/Timer Select. This bit determines whether timer 2 will function as a timer or a counter.

Independent of this bit, the timer will run at 2 clocks per tick when used in baud rate generator

mode. If it is set to 0, then timer 2 operates as a timer at a speed depending on T2M bit

(CKCON.5), otherwise it will count negative edges on T2 pin.

CP / RL2: Capture/Reload Select. This bit determines whether the capture or reload function will be

used for timer 2. If either RCLK or TCLK is set, this bit will be ignored and the timer will

function in an auto-reload mode following each overflow. If the bit is 0 then auto-reload will

occur when timer 2 overflows or a falling edge is detected on T2EX pin if EXEN2 = 1. If

this bit is 1, then timer 2 captures will occur when a falling edge is detected on T2EX pin if

EXEN2 = 1.

Timed 2 Mode Control

Bit:

7

-

6

-

5

-

4

-

3

2

-

1

-

0

T2CR

DCEN

Mnemonic: T2MOD

Address: C9h

T2CR: Timer 2 Capture Reset. In the Timer 2 Capture Mode this bit enables/disables hardware

automatically reset Timer 2 while the value in TL2 and TH2 have been transferred into the

capture register.

DCEN: Down Count Enable: This bit, in conjunction with the T2EX pin, controls the direction that

timer 2 counts in 16-bit auto-reload mode.

- 22 -

W79E532/W79L532

Timer 2 Capture LSB

Bit:

7

6

5

4

3

2

1

0

RCAP2L.7

RCAP2L.6 RCAP2L.5 RCAP2L.4 RCAP2L.3 RCAP2L.2 RCAP2L.1 RCAP2L.0

Mnemonic: RCAP2L

Address: CAh

RCAP2L: This register is used to capture the TL2 value when a timer 2 is configured in capture mode.

RCAP2L is also used as the LSB of a 16-bit reload value when timer 2 is configured in auto-

reload mode.

Timer 2 Capture MSB

Bit:

7

6

5

4

3

2

1

0

RCAP2H.7 RCAP2H.6 RCAP2H.5 RCAP2H.4 RCAP2H.3 RCAP2H.2 RCAP2H.1 RCAP2H.0

Mnemonic: RCAP2H

Address: CBh

RCAP2H: This register is used to capture the TH2 value when a timer 2 is configured in capture

mode.

RCAP2H is also used as the MSB of a 16-bit reload value when timer 2 is configured in

auto-reload mode.

Timer 2 LSB

Bit:

7

6

5

4

3

2

1

0

TL2.7

TL2.6

TL2.5

TL2.4

TL2.3

TL2.2

TL2.1

TL2.0

Mnemonic: TL2

Timer 2 LSB

Timer 2 MSB

Address: CCh

TL2:

Bit:

7

6

5

4

3

2

TH2.2

1

0

TH2.7

TH2.6

TH2.5

TH2.4

TH2.3

TH2.1 TH2.0

Mnemonic: TH2

Address: CDh

TH2: Timer 2 MSB

Program Status Word

Bit:

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

F1

P

Mnemonic: PSW

Address: D0h

CY:

Carry flag: Set for an arithmetic operation which results in a carry being generated from the

ALU. It is also used as the accumulator for the bit operations.

AC:

F0:

Auxiliary carry: Set when the previous operation resulted in a carry from the high order nibble.

User flag 0: General purpose flag that can be set or cleared by the user.

RS.1-0: Register bank select bits:

Publication Release Date: November 21, 2005

Revision A5

- 23 -

W79E532/W79L532

RS1

RS0

Register bank

Address

00-07h

08-0Fh

10-17h

18-1Fh

0

1

0

1

0

1

0

1

2

3

OV:

Overflow flag: Set when a carry was generated from the seventh bit but not from the 8th bit as

a result of the previous operation, or vice-versa.

F1:

P:

User Flag 1: General purpose flag that can be set or cleared by the user by software.

Parity flag: Set/cleared by hardware to indicate odd/even number of 1's in the accumulator.

Watchdog Control

Bit:

7

-

6

5

-

4

-

3

2

1

0

POR

WDIF

WTRF

EWT

RWT

Mnemonic: WDCON

Address: D8h

POR: Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read

or written by software. A write by software is the only way to clear this bit once it is set.

WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit

to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit

indicates that the time-out period has elapsed. This bit must be cleared by software.

WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a

reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.

This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer

will have no affect on this bit.

EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.

RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also

helps in resetting the watchdog timer before a time-out occurs. Failing to set the EWT before

time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog

timer reset will be generated if EWT is set. This bit is self-clearing by hardware.

The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer

reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1

by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.

All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed

Access procedure to write. The remaining bits have unrestricted write accesses. Please refer TA

register description.

TA

EG

C7H

WDCON

CKCON

REG D8H

REG 8EH

MOV TA, #AAH

MOV TA, #55H

SETB WDCON.0

ORL CKCON, #11000000B

MOV TA, #AAH

; Reset watchdog timer

; Select 26 bits watchdog timer

- 24 -

W79E532/W79L532

MOV TA, #55H

ORL WDCON, #00000010B

; Enable watchdog

Accumulator

Bit:

7

6

5

4

3

2

1

0

ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0

Mnemonic: ACC

Address: E0h

ACC.7-0: The A (or ACC) register is the standard 8052 accumulator.

Extended Interrupt Enable

Bit:

7

-

6

-

5

-

4

3

-

2

-

1

-

0

-

EWDI

Mnemonic: EIE

Address: E8h

EIE.7-5: Reserved bits, will read high

EWDI: Enable Watchdog timer interrupt

B Register

Bit:

7

6

5

4

3

2

1

0

B.7

B.6

B.5

B.4

B.3

B.2

B.1

B.0

Mnemonic: B

Address: F0h

B.7-0: The B register is the standard 8052 register that serves as a second accumulator.

Extended Interrupt Priority

Bit:

7

-

6

-

5

-

4

3

-

2

-

1

-

0

-

PWDI

Mnemonic: EIP

Address: F8h

EIP.7-5: Reserved bits.

PWDI: Watchdog timer interrupt priority.

Publication Release Date: November 21, 2005

Revision A5

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W79E532/W79L532

8. INSTRUCTION

The W79E(L)532 executes all the instructions of the standard 8032 family. The operation of these

instructions, their effect on the flag bits and the status bits is exactly the same. However, timing of

these instructions is different. The reason for this is two fold. Firstly, in the W79E(L)532, each machine

cycle consists of 4 clock periods, while in the standard 8032 it consists of 12 clock periods. Also, in the

W79E(L)532 there is only one fetch per machine cycle i.e. 4 clocks per fetch, while in the standard

8032 there can be two fetches per machine cycle, which works out to 6 clocks per fetch.

The advantage the W79E(L)532 has is that since there is only one fetch per machine cycle, the

number of machine cycles in most cases is equal to the number of operands that the instruction has.

In case of jumps and calls there will be an additional cycle that will be needed to calculate the new

address. But overall the W79E(L)532 reduces the number of dummy fetches and wasted cycles,

thereby improving efficiency as compared to the standard 8032.

8.1 Instruction Timing

The instruction timing for the W79E(L)532 is an important aspect, especially for those users who wish

to use software instructions to generate timing delays. Also, it provides the user with an insight into the

timing differences between the W79E(L)532 and the standard 8032. In the W79E(L)532 each machine

cycle is four clock periods long. Each clock period is designated a state. Thus each machine cycle is

made up of four states, C1, C2 C3 and C4, in that order. Due to the reduced time for each instruction

execution, both the clock edges are used for internal timing. Hence it is important that the duty cycle of

the clock be as close to 50% as possible to avoid timing conflicts. As mentioned earlier, the

W79E(L)532 does one op-code fetch per machine cycle. Therefore, in most of the instructions, the

number of machine cycles needed to execute the instruction is equal to the number of bytes in the

instruction. Of the 256 available op-codes, 128 of them are single cycle instructions. Thus more than

half of all op-codes in the W79E(L)532 are executed in just four clock periods. Most of the two-cycle

instructions are those that have two byte instruction codes. However there are some instructions that

have only one byte instructions, yet they are two cycle instructions. One instruction which is of

importance is the MOVX instruction. In the standard 8032, the MOVX instruction is always two

machine cycles long. However in the W79E(L)532, the user has a facility to stretch the duration of this

instruction from 2 machine cycles to 9 machine cycles. The RD and WR strobe lines are also

proportionately elongated. This gives the user flexibility in accessing both fast and slow peripherals

without the use of external circuitry and with minimum software overhead. The rest of the instructions

are either three, four or five machine cycle instructions. Note that in the W79E(L)532, based on the

number of machine cycles, there are five different types, while in the standard 8032 there are only

three. However, in the W79E(L)532 each machine cycle is made of only 4 clock periods compared to

the 12 clock periods for the standard 8032. Therefore, even though the number of categories has

increased, each instruction is at least 1.5 to 3 times faster than the standard 8032 in terms of clock

periods.

- 26 -

W79E532/W79L532

Single Cycle

C4

C1

C2

C3

CLK

ALE

PSEN

AD7-0

A7-0

Data_ in D7-0

Address A15-8

PORT 2

Figure 3. Single Cycle Instruction Timing

Operand Fetch

Instruction Fetch

C1

C2

C3

C4

C1

C2

C3

C4

CLK

ALE

PSEN

AD7-0

PC

OP-CODE

PC+1

OPERAND

Address A15-8

PORT 2

Figure 4. Two Cycle Instruction Timing

Publication Release Date: November 21, 2005

Revision A5

- 27 -

W79E532/W79L532

Instruction Fetch

Operand Fetch

C1

C2

C3

C4

C1

C2

C3

C4

C1

C2

C3

C4

CLK

ALE

PSEN

AD7-0

A7-0

OP-CODE

A7-0

OPERAND

A7-0

OPERAND

PORT 2

Address A15-8

Figure 5. Three Cycle Instruction Timing

Instruction Fetch

Operand Fetch

C1

C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

AD7-0

OP-CODE

A7-0 OPERAND

Address A15-8

OPERAND

A7-0

OPERAND

A7-0

Port 2

Address A15-8

Figure 6. Four Cycle Instruction Timing

- 28 -

W79E532/W79L532

Operand Fetch

Instruction Fetch

Operand Fetch

C1

C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

OPERAND

OP-CODE

OPERAND

A7-0

AD7-0

Address A15-8

PORT 2

Figure 7. Five Cycle Instruction Timing

8.1.1 External Data Memory Access Timing

The timing for the MOVX instruction is another feature of the W79E(L)532. In the standard 8032, the

MOVX instruction has a fixed execution time of 2 machine cycles. However in the W79E(L)532, the

duration of the access can be varied by the user.

The instruction starts off as a normal op-code fetch of 4 clocks. In the next machine cycle, the

W79E(L)532 puts out the address of the external Data Memory and the actual access occurs here.

The user can change the duration of this access time by setting the STRETCH value. The Clock

Control SFR (CKCON) has three bits that control the stretch value. These three bits are M2-0 (bits 2-0

of CKCON). These three bits give the user 8 different access time options. The stretch can be varied

from 0 to 7, resulting in MOVX instructions that last from 2 to 9 machine cycles in length. Note that the

stretching of the instruction only results in the elongation of the MOVX instruction, as if the state of the

CPU was held for the desired period. There is no effect on any other instruction or its timing. By

default, the Stretch value is set at 1, giving a MOVX instruction of 3 machine cycles. If desired by the

user the stretch value can be set to 0 to give the fastest MOVX instruction of only 2 machine cycles.

Table 4. Data Memory Cycle Stretch Values

RD OR WR

MACHINE

CYCLES

STROBE

WIDTH

STROBE

WIDTH

STROBE

WIDTH

M2

M1

M0

IN CLOCKS

@ 25 MHZ

80 nS

@ 40 MHZ

50 nS

0

1

0

1

0

2

3 (default)

4

2

4

8

160 nS

320 nS

100 nS

200 nS

Publication Release Date: November 21, 2005

Revision A5

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W79E532/W79L532

Continued

RD OR WR

MACHINE

CYCLES

STROBE

WIDTH

STROBE

WIDTH

STROBE

WIDTH

M2

M1

M0

IN CLOCKS

@ 25 MHZ

480 nS

@ 40 MHZ

300 nS

400 nS

500 nS

600 nS

700 nS

0

1

0

1

0

1

0

1

5

6

7

8

9

12

16

20

24

28

640 nS

800 nS

960 nS

1120 nS

Second

Machine cycle

Next Instruction

Machine Cycle

Last Cycle

First

Machine cycle

MOVX instruction cycle

of Previous

Instruction

C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

WR

A0-A7

D0-D7

A0-A7

D0-D7

PORT 0

Next Inst.

Address

MOVX Data

Address

MOVX Inst.

Address

MOVX Inst

.

MOVX Data out

A15-A8

Next Inst. Read

A15-A8

PORT 2

Figure 8. Data Memory Write with Stretch Value = 0

- 30 -

W79E532/W79L532

Last Cycle

First

Second

Third

Next Instruction

Machine Cycle

of Previous Machine Cycle Machine Cycle Machine Cycle

Instruction

MOVX instruction cycle

C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

WR

A0-A7

D0-D7

A0-A7

D0-D7

A0-A7

D0-D7

A0-A7

D0-D7

PORT 0

MOVX Inst.

Address

Next Inst.

Address

MOVX Data

Address

MOVX Data out

Next Inst.

Read

MOVX Inst.

A15-A8

PORT 2

Figure 9. Data Memory Write with Stretch Value = 1

First

Second

Third

Fourth

Machine Cycle

Last Cycle

Machine Cycle

of Previous

Instruction

MOVX instruction cycle

C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4 C1 C2 C3 C4

CLK

ALE

PSEN

WR

A0-A7

D0-D7

PORT 0

MOVX Inst.

Address

Next Inst.

Address

MOVX Data

Address

MOVX Data out

Next Inst.

Read

MOVX Inst.

A15-A8

PORT 2

Figure 10. Data Memory Write with Stretch Value = 2

Publication Release Date: November 21, 2005

Revision A5

- 31 -

W79E532/W79L532

9. POWER MANAGEMENT

The W79E(L)532 has several features that help the user to control the power consumption of the

device. The power saving features are basically the POWER DOWN mode and the IDLE mode of

operation.

Idle Mode

The user can put the device into idle mode by writing 1 to the bit PCON.0. The instruction that sets the

idle bit is the last instruction that will be executed before the device goes into Idle Mode. In the Idle

mode, the clock to the CPU is halted, but not to the Interrupt, Timer, Watchdog timer and Serial port

blocks. This forces the CPU state to be frozen; the Program counter, the Stack Pointer, the Program

Status Word, the Accumulator and the other registers hold their contents. The ALE and PSEN pins are

held high during the Idle state. The port pins hold the logical states they had at the time Idle was

activated. The Idle mode can be terminated in two ways. Since the interrupt controller is still active, the

activation of any enabled interrupt can wake up the processor. This will automatically clear the Idle bit,

terminate the Idle mode, and the Interrupt Service Routine(ISR) will be executed. After the ISR,

execution of the program will continue from the instruction which put the device into Idle mode.

The Idle mode can also be exited by activating the reset. The device can be put into reset either by

applying a high on the external RST pin, a Power on reset condition or a Watchdog timer reset. The

external reset pin has to be held high for at least two machine cycles i.e. 8 clock periods to be

recognized as a valid reset. In the reset condition the program counter is reset to 0000h and all the

SFRs are set to the reset condition. Since the clock is already running there is no delay and execution

starts immediately. In the Idle mode, the Watchdog timer continues to run, and if enabled, a time-out

will cause a watchdog timer interrupt which will wake up the device. The software must reset the

Watchdog timer in order to preempt the reset which will occur after 512 clock periods of the time-out.

When the W79E(L)532 is exiting from an Idle mode with a reset, the instruction following the one

which put the device into Idle mode is not executed. So there is no danger of unexpected writes.

Power Down Mode

The device can be put into Power Down mode by writing 1 to bit PCON.1. The instruction that does

this will be the last instruction to be executed before the device goes into Power Down mode. In the

Power Down mode, all the clocks are stopped and the device comes to a halt. All activity is completely

stopped and the power consumption is reduced to the lowest possible value. In this state the ALE and

PSEN pins are pulled low. The port pins output the values held by their respective SFRs.

The W79E(L)532 will exit the Power Down mode with a reset or by an external interrupt pin enabled

as level detect. An external reset can be used to exit the Power down state. The high on RST pin

terminates the Power Down mode, and restarts the clock. The program execution will restart from

0000h. In the Power down mode, the clock is stopped, so the Watchdog timer cannot be used to

provide the reset to exit Power down mode.

The W79E(L)532 can be woken from the Power Down mode by forcing an external interrupt pin

activated, provided the corresponding interrupt is enabled, while the global enable(EA) bit is set and

the external input has been set to a level detect mode. If these conditions are met, then the low level

on the external pin re-starts the oscillator. Then device executes the interrupt service routine for the

corresponding external interrupt. After the interrupt service routine is completed, the program

execution returns to the instruction after the one which put the device into Power Down mode and

continues from there.

- 32 -

W79E532/W79L532

Table 5. Status of external pins during Idle and Power Down

PROGRAM

ALE

PORT0

PORT1

PORT2

PORT3

MODE

PSEN

MEMORY

Internal

External

Internal

External

Idle

1

0

1

0

Data

Float

Data

Float

Data

Address

Data

Power Down

Data

Reset Conditions

The user has several hardware related options for placing the W79E(L)532 into reset condition. In

general, most register bits go to their reset value irrespective of the reset condition, but there are a few

flags whose state depends on the source of reset. The user can use these flags to determine the

cause of reset using software. There are two ways of putting the device into reset state. They are

External reset and Watchdog reset.

External Reset

The device continuously samples the RST pin at state C4 of every machine cycle. Therefore the RST

pin must be held for at least 2 machine cycles to ensure detection of a valid RST high. The reset

circuitry then synchronously applies the internal reset signal. Thus the reset is a synchronous

operation and requires the clock to be running to cause an external reset.

Once the device is in reset condition, it will remain so as long as RST is 1. Even after RST is

deactivated, the device will continue to be in reset state for up to two machine cycles, and then begin

program execution from 0000h. There is no flag associated with the external reset condition. However

since the other two reset sources have flags, the external reset can be considered as the default reset

if those two flags are cleared.

The software must clear the POR flag after reading it, otherwise it will not be possible to correctly

determine future reset sources. If the power fails, i.e. falls below Vrst, then the device will once again

go into reset state. When the power returns to the proper operating levels, the device will again

perform a power on reset delay and set the POR flag.

Watchdog Timer Reset

The Watchdog timer is a free running timer with programmable time-out intervals. The user can clear

the watchdog timer at any time, causing it to restart the count. When the time-out interval is reached

an interrupt flag is set. If the Watchdog reset is enabled and the watchdog timer is not cleared, then

512 clocks from the flag being set, the watchdog timer will generate a reset . This places the device

into the reset condition. The reset condition is maintained by hardware for two machine cycles. Once

the reset is removed the device will begin execution from 0000h.

Publication Release Date: November 21, 2005

- 33 -

Revision A5

W79E532/W79L532

Reset State

Most of the SFRs and registers on the device will go to the same condition in the reset state. The

Program Counter is forced to 0000h and is held there as long as the reset condition is applied.

However, the reset state does not affect the on-chip RAM. The data in the RAM will be preserved

during the reset. However, the stack pointer is reset to 07h, and therefore the stack contents will be

lost. The RAM contents will be lost if the V_DDfalls below approximately 2V, as this is the minimum

voltage level required for the RAM to operate normally. Therefore after a first time power on reset the

RAM contents will be indeterminate. During a power fail condition, if the power falls below 2V, the

RAM contents are lost.

After a reset most SFRs are cleared. Interrupts and Timers are disabled. The Watchdog timer is

disabled if the reset source was a POR. The port SFRs have FFh written into them which puts the port

pins in a high state. Port 0 floats as it does not have on-chip pull-ups.

Table 6. SFR Reset Value

SFR NAME

P0

RESET VALUE

11111111b

00000111b

00000000b

010xx0x0b

000x0000b

00000000b

00xx0000b

00000000b

00000001b

11111111b

00000000b

00000111b

00000000b

SFR NAME

IE

RESET VALUE

00000000b

11111111b

x0000000b

00000000b

00000x00b

00000000b

11111111b

00000000b

0x0x0xx0b

00000000b

xxx00000b

00000000b

SP

SADDR

P3

DPL

DPH

IP

PMR

SADEN

T2CON

T2MOD

RCAP2L

RCAP2H

TL2

STATUS

PC

PCON

TCON

TMOD

TL0

TH2

TL1

TA

TH0

PSW

TH1

WDCON

ACC

CKCON

P1

EIE

P4CONA

P40AL

P41AL

P42AL

P43Al

CHPCON

ROMCON

SFRAH

P4CONB

P40AH

P41AH

P42AH

P43AH

P4CSIN

SFRAL

SFRFD

- 34 -

W79E532/W79L532

Table 6. SFR Reset Value, continued

SFR NAME

SFRCN

SCON

RESET VALUE

00111111b

00000000b

xxxxxxxxb

11111111b

00000000b

SFR NAME

RESET VALUE

xxxx1111b

00000000b

xxx00000b

00000000b

P4

B

SBUF

EIP

P2

PWMCON1

PWM0

PWM2

PWM4

PWMCON2

PWM1

PWM3

PWM5

The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.

External reset

0x0x0xx0b

Watchdog reset

0x0x01x0b

Power on reset

01000000b

WDCON

The POR bit WDCON.6 is set only by the power on reset. The WTRF bit WDCON.2 is set when the

Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit WDCON.1 is

cleared by power on resets. This disables the Watchdog timer resets. A watchdog or external reset

does not affect the EWT bit.

10. INTERRUPTS

The W79E(L)532 has a two priority level interrupt structure with 11 interrupt sources. Each of the

interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the

interrupts can be globally enabled or disabled.

Interrupt Sources

The External Interrupts INT0 and INT1 can be either edge triggered or level triggered, depending on

bits IT0 and IT1. The bits IE0 and IE1 in the TCON register are the flags which are checked to

generate the interrupt. In the edge triggered mode, the INTx inputs are sampled in every machine

cycle. If the sample is high in one cycle and low in the next, then a high to low transition is detected

and the interrupts request flag IEx in TCON is set. The flag bit requests the interrupt. Since the

external interrupts are sampled every machine cycle, they have to be held high or low for at least one

complete machine cycle. The IEx flag is automatically cleared when the service routine is called. If the

level triggered mode is selected, then the requesting source has to hold the pin low till the interrupt is

serviced. The IEx flag will not be cleared by the hardware on entering the service routine. If the

interrupt continues to be held low even after the service routine is completed, then the processor may

acknowledge another interrupt request from the same source.

Publication Release Date: November 21, 2005

- 35 -

Revision A5

W79E532/W79L532

The Timer 0 and 1 Interrupts are generated by the TF0 and TF1 flags. These flags are set by the

overflow in the Timer 0 and Timer 1. The TF0 and TF1 flags are automatically cleared by the

hardware when the timer interrupt is serviced. The Timer 2 interrupt is generated by a logical OR of

the TF2 and the EXF2 flags. These flags are set by overflow or capture/reload events in the timer 2

operation. The hardware does not clear these flags when a timer 2 interrupt is executed. Software has

to resolve the cause of the interrupt between TF2 and EXF2 and clear the appropriate flag.

The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the

time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is

enabled by the enable bit EIE.4, then an interrupt will occur.

All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated

interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or

clearing a bit in the IE SFR. IE also has a global enable/disable bit EA, which can be cleared to

disable all the interrupts.

Priority Level Structure

There are three priority levels for the interrupts, highest, high and low. The interrupt sources can be

individually set to either high or low levels. Naturally, a higher priority interrupt cannot be interrupted

by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the interrupts

themselves. This hierarchy comes into play when the interrupt controller has to resolve simultaneous

requests having the same priority level. This hierarchy is defined as shown below; the interrupts are

numbered starting from the highest priority to the lowest.

Table 7. Priority structure of interrupts

SOURCE

External Interrupt 0

Timer 0 Overflow

External Interrupt 1

Timer 1 Overflow

Serial Port

FLAG

IE0

VECTOR ADDRESS

0003h

PRIORITY LEVEL

1(highest)

TF0

000Bh

2

IE1

0013h

3

TF1

001Bh

4

RI + TI

TF2 + EXF2

WDIF

0023h

5

6

Timer 2 Overflow

Watchdog Timer

002Bh

0063h

7 (lowest)

- 36 -

W79E532/W79L532

11. PROGRAMMABLE TIMERS/COUNTERS

The W79E(L)532 has three 16-bit programmable timer/counters and one programmable Watchdog

timer. The Watchdog timer is operationally quite different from the other two timers.

11.1 Timer/Counters 0 & 1

The W79E(L)532 has two 16-bit Timer/Counters. Each of these Timer/Counters has two 8 bit registers

which form the 16 bit counting register. For Timer/Counter 0 they are TH0, the upper 8 bits register,

and TL0, the lower 8 bit register. Similarly Timer/Counter 1 has two 8 bit registers, TH1 and TL1. The

two can be configured to operate either as timers, counting machine cycles or as counters counting

external inputs.

When configured as a "Timer", the timer counts clock cycles. The timer clock can be programmed to

be thought of as 1/12 of the system clock or 1/4 of the system clock. In the "Counter" mode, the

register is incremented on the falling edge of the external input pin, T0 in case of Timer 0, and T1 for

Timer 1. The T0 and T1 inputs are sampled in every machine cycle at C4. If the sampled value is high

in one machine cycle and low in the next, then a valid high to low transition on the pin is recognized

and the count register is incremented. Since it takes two machine cycles to recognize a negative

transition on the pin, the maximum rate at which counting will take place is 1/24 of the master clock

frequency. In either the "Timer" or "Counter" mode, the count register will be updated at C3.

Therefore, in the "Timer" mode, the recognized negative transition on pin T0 and T1 can cause the

count register value to be updated only in the machine cycle following the one in which the negative

edge was detected.

The "Timer" or "Counter" function is selected by the " C / T " bit in the TMOD Special Function

Register. Each Timer/Counter has one selection bit for its own; bit 2 of TMOD selects the function for

Timer/Counter 0 and bit 6 of TMOD selects the function for Timer/Counter 1. In addition each

Timer/Counter can be set to operate in any one of four possible modes. The mode selection is done

by bits M0 and M1 in the TMOD SFR.

Time-Base Selection

The W79E(L)532 gives the user two modes of operation for the timer. The timers can be programmed

to operate like the standard 8051 family, counting at the rate of 1/12 of the clock speed. This will

ensure that timing loops on the W79E(L)532 and the standard 8051 can be matched. This is the

default mode of operation of the W79E(L)532 timers. The user also has the option to count in the

turbo mode, where the timers will increment at the rate of 1/4 clock speed. This will straight-away

increase the counting speed three times. This selection is done by the T0M and T1M bits in CKCON

SFR. A reset sets these bits to 0, and the timers then operate in the standard 8051 mode. The user

should set these bits to 1 if the timers are to operate in turbo mode.

Mode 0

In Mode 0, the timer/counters act as a 8 bit counter with a 5 bit, divide by 32 pre-scale. In this mode

we have a 13 bit timer/counter. The 13 bit counter consists of 8 bits of THx and 5 lower bits of TLx.

The upper 3 bits of TLx are ignored.

The negative edge of the clock increments the count in the TLx register. When the fifth bit in TLx

moves from 1 to 0, then the count in the THx register is incremented. When the count in THx moves

from FFh to 00h, then the overflow flag TFx in TCON SFR is set. The counted input is enabled only if

TRx is set and either GATE = 0 or INTx = 1. When C / T is set to 0, then it will count clock cycles,

Publication Release Date: November 21, 2005

- 37 -

Revision A5

W79E532/W79L532

and if C / T is set to 1, then it will count 1 to 0 transitions on T0 (P3.4) for timer 0 and T1 (P3.5) for

timer 1. When the 13 bit count reaches 1FFFh the next count will cause it to roll-over to 0000h. The

timer overflow flag TFx of the relevant timer is set and if enabled an interrupts will occur. Note that

when used as a timer, the time-base may be either clock cycles/12 or clock cycles/4 as selected by

the bits TxM of the CKCON SFR.

T0M = CKCON.3

(T1M = CKCON.4)

Timer 1 functions are shown in brackets

M1,M0 = TMOD.1,TMOD.0

(M1,M0 = TMOD.5,TMOD.4)

C/T = TMOD.2

1/4

1

(C/T = TMOD.6)

osc

00

0

1

0

1/12

0

4

7

0

7

T0 = P3.4

01

(T1 = P3.5)

TL0

(TL1)

TH0

(TH1)

TR0 = TCON.4

(TR1 = TCON.6)

GATE = TMOD.3

(GATE = TMOD.7)

TFx

Interrupt

INT0 = P3.2

TF0

(INT1 = P3.3)

(TF1)

Figure 11. Timer/Counter Mode 0 & Mode 1

Mode 1

Mode 1 is similar to Mode 0 except that the counting register forms a 16 bit counter, rather than a 13

bit counter. This means that all the bits of THx and TLx are used. Roll-over occurs when the timer

moves from a count of FFFFh to 0000h. The timer overflow flag TFx of the relevant timer is set and if

enabled an interrupt will occur. The selection of the time-base in the timer mode is similar to that in

Mode 0. The gate function operates similarly to that in Mode 0.

Mode 2

In Mode 2, the timer/counter is in the Auto Reload Mode. In this mode, TLx acts as a 8 bit count

register, while THx holds the reload value. When the TLx register overflows from FFh to 00h, the TFx

bit in TCON is set and TLx is reloaded with the contents of THx, and the counting process continues

from here. The reload operation leaves the contents of the THx register unchanged. Counting is

enabled by the TRx bit and proper setting of GATE and INTx pins. As in the other two modes 0 and 1

mode 2 allows counting of either clock cycles (clock/12 or clock/4) or pulses on pin Tn.

- 38 -

W79E532/W79L532

T0M = CKCON.3

(T1M = CKCON.4)

Timer 1 functions are shown in brackets

1/4

C/T = TMOD.2

(C/T = TMOD.6)

0

1

0

TL0

osc

(TL1)

1/12

Interrupt

0

7

TFx

TF0

1

T0 = P3.4

(T1 = P3.5)

(TF1)

TR0 = TCON.4

(TR1 = TCON.6)

GATE = TMOD.3

(GATE = TMOD.7)

TH0

(TH1)

INT0 = P3.2

(INT1 = P3.3)

Figure 12. Timer/Counter Mode 2.

Mode 3

Mode 3 has different operating methods for the two timer/counters. For timer/counter 1, mode 3 simply

freezes the counter. Timer/Counter 0, however, configures TL0 and TH0 as two separate 8 bit count

registers in this mode. The logic for this mode is shown in the figure. TL0 uses the Timer/Counter 0

control bits C / T , GATE, TR0, INT0 and TF0. The TL0 can be used to count clock cycles (clock/12

or clock/4) or 1-to-0 transitions on pin T0 as determined by C/T (TMOD.2). TH0 is forced as a clock

cycle counter (clock/12 or clock/4) and takes over the use of TR1 and TF1 from Timer/Counter 1.

Mode 3 is used in cases where an extra 8 bit timer is needed. With Timer 0 in Mode 3, Timer 1 can

still be used in Modes 0, 1 and 2., but its flexibility is somewhat limited. While its basic functionality is

maintained, it no longer has control over its overflow flag TF1 and the enable bit TR1. Timer 1 can still

be used as a timer/counter and retains the use of GATE and INT1 pin. In this condition it can be

turned on and off by switching it out of and into its own Mode 3. It can also be used as a baud rate

generator for the serial port.

Publication Release Date: November 21, 2005

- 39 -

Revision A5

W79E532/W79L532

11.2 Timer/Counter 2

Timer/Counter 2 is a 16 bit up/down counter which is configured by the T2MOD register and controlled

by the T2CON register. Timer/Counter 2 is equipped with a capture/reload capability. As with the

Timer 0 and Timer 1 counters, there exists considerable flexibility in selecting and controlling the

clock, and in defining the operating mode. The clock source for Timer/Counter 2 may be selected for

either the external T2 pin (C/T2 = 1) or the crystal oscillator, which is divided by 12 or 4 (C/T2 = 0).

The clock is then enabled when TR2 is a 1, and disabled when TR2 is a 0.

T0M = CKCON.3

1/4

1

C/T = TMOD.2

0

TL0

osc

0

1/12

Interrupt

0

7

TF0

1

T0 = P3.4

TR0 = TCON.4

GATE = TMOD.3

INT0 = P3.2

TH0

Interrupt

0

7

TF1

TR1 = TCON.6

Figure 13. Timer/Counter 0 Mode 3

Capture Mode

The capture mode is enabled by setting the CP / RL2 bit in the T2CON register to a 1. In the capture

mode, Timer/Counter 2 serves as a 16 bit up counter. When the counter rolls over from FFFFh to

0000h, the TF2 bit is set, which will generate an interrupt request. If the EXEN2 bit is set, then a

negative transition of T2EX pin will cause the value in the TL2 and TH2 register to be captured by the

RCAP2L and RCAP2H registers. This action also causes the EXF2 bit in T2CON to be set, which will

also generate an interrupt. Setting the T2CR bit (T2MOD.3), the W79E(L)532 allows hardware to reset

timer 2 automatically after the value of TL2 and TH2 have been captured.

- 40 -

W79E532/W79L532

T2M = CKCON.5

1

1/4

C/T2 = T2CON.1

osc

0

T2CON.7

1/12

0

TL2

TH2

TF2

1

T2 = P1.0

TR2 = T2CON.2

Timer 2

Interrupt

T2EX = P1.1

RCAP2L RCAP2H

EXEN2 = T2CON.3

EXF2

T2CON.6

Figure 14. 16-Bit Capture Mode

Auto-reload Mode, Counting up

The auto-reload mode as an up counter is enabled by clearing the CP / RL2 bit in the T2CON register

and clearing the DCEN bit in T2MOD register. In this mode, Timer/Counter 2 is a 16 bit up counter.

When the counter rolls over from FFFFh, a reload is generated that causes the contents of the

RCAP2L and RCAP2H registers to be reloaded into the TL2 and TH2 registers. The reload action also

sets the TF2 bit. If the EXEN2 bit is set, then a negative transition of T2EX pin will also cause a

reload. This action also sets the EXF2 bit in T2CON.

T2M = CKCON.5

1/4

1

C/T2 = T2CON.1

0

osc

T2CON.7

1/12

0

TL2

TH2

TF2

1

T2 = P1.0

TR2 = T2CON.2

Timer 2

Interrupt

T2EX = P1.1

RCAP2L RCAP2H

EXF2

EXEN2 = T2CON.3

T2CON.6

Figure 15. 16-Bit Auto-reload Mode, Counting Up

Publication Release Date: November 21, 2005

Revision A5

- 41 -

W79E532/W79L532

Auto-reload Mode, Counting Up/Down

Timer/Counter 2 will be in auto-reload mode as an up/down counter if CP / RL2 bit in T2CON is

cleared and the DCEN bit in T2MOD is set. In this mode, Timer/Counter 2 is an up/down counter

whose direction is controlled by the T2EX pin. A 1 on this pin cause the counter to count up. An

overflow while counting up will cause the counter to be reloaded with the contents of the capture

registers. The next down count following the case where the contents of Timer/Counter equal the

capture registers will load an FFFFh into Timer/Counter 2. In either event a reload will set the TF2 bit.

A reload will also toggle the EXF2 bit. However, the EXF2 bit can not generate an interrupt while in

this mode.

Down Counting Reload Value

0FFh 0FFh

T2M = CKCON.5

C/T = T2CON.1

1/4

1

osc

0

.7

T2CON

1/12

Timer 2

Interrupt

0

TL2

TH2

TF2

1

T2 = P1.0

TR2 = T2CON.2

RCAP2L RCAP2H

Up Counting Reload Value

EXF2

T2CON.6

T2EX = P1.1

DCEN = 1

Figure 16. 16-Bit Auto-reload Up/Down Counter

Baud Rate Generator Mode

The baud rate generator mode is enabled by setting either the RCLK or TCLK bits in T2CON register.

While in the baud rate generator mode, Timer/Counter 2 is a 16 bit counter with auto reload when the

count rolls over from FFFFh. However, rolling over does not set the TF2 bit. If EXEN2 bit is set, then a

negative transition of the T2EX pin will set EXF2 bit in the T2CON register and cause an interrupt

request.

Timer1

Overflow

1/2

C/T2=T2CON.1

0

Fosc

0

1

SMOD=

PCON.7

Timer2

RCLK=

Overflow T2CON.5

TL2 TH2

1

0

T2=P1.0

Rx Clock

Tx Clock

1/16

TCLK=

T2CON.4

TR2=T2CON.2

1

0

1/16

RCAP2L RCAP2H

T2EX=P1.1

Timer2

Interrupt

EXF2

T2CON.6

EXEN2=T2CON.3

Figure 17. Baud Rate Generator Mode

- 42 -

W79E532/W79L532

11.3 Pulse Width Modulated Outputs (PWM)

There are six pulse width modulated output channels to generate pulses of programmable length and

interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for

the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts

modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of six registers:

PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater

than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3, PWM4 or PWM5 output is

set HIGH. If the contents of these registers are equal to, or less than the counter value, the output will

be LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2,

PWM3, PWM4 and PWM5. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in

increments of 1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3, ENPWM4 and ENPWM5 bit will

enable or disable PWM output.

Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be

proportional to the contents of PWM0/1/2/3/4/5.

PWM0/1/2/3/4/5 output is given by:

The repetition frequency f^pwm, at the

f

osc

f

pwm

=

2×(1+ PWMP)×255

Prescaler division factor = PWM + 1

(PWMn)

PWMn high/low ratio of PWMn =

255 - (PWMn)

This gives a repetition frequency range of 123 Hz to 31.4K Hz ( fosc = 16M Hz). By loading the PWM

registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level,

respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the

PWM registers when they are loaded with FFH.

When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4, PWM5) is loaded with a new value,

the associated output updated immediately. It does not have to wait until the end of the current

counter period. There is weakly pulled high on PWM output.

Publication Release Date: November 21, 2005

- 43 -

Revision A5

W79E532/W79L532

PWM0 Register

PWM1 Register

PWM2 Register

PWM3 Register

PWM4 Register

PWM5 Register

PWM0 Buffer

overflow

+

PWM0OE

PWM0

P1.0

Fosc

1/2

PWMP

8-bit Up Counter

-

ENPWM0

ENPWM1

ENPWM2

ENPWM3

ENPWM4

ENPWM5

PWM1 Buffer

+

PWM1OE

PWM1

P1.1

overflow

8-bit Up Counter

-

PWM2 Buffer

+

PWM2OE

PWM2

P1.2

overflow

8-bit Up Counter

-

PWM3 Buffer

+

PWM3OE

PWM3

P1.3

overflow

8-bit Up Counter

-

PWM4 Buffer

+

PWM4OE

PWM4

P1.4

overflow

8-bit Up Counter

-

PWM5 Buffer

+

PWM5OE

PWM5

P1.5

overflow

8-bit Up Counter

-

FIGURE 1 PWM DIAGRAM

Please refer as below code.

mov pwmcon1, #00110011b

mov pwmcon2, #00000101b

mov pwmp, #40h

; enable pwm3, 2, 1, 0

; enable pwm4

; Fpwm = XT/(2*(1+pwmp)*255)

mov pwm0, #14h

; duty cycle high/low = pwm0/(255-pmw0)

mov pwm1, #18h

mov pwm2, #20h

mov pwm3, #b0h

mov pwm4, #40h

mov pwmcon1, #11111111b

; output enable pwm3, 2, 1, 0

PWM3 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM3

Address: DEH

- 44 -

W79E532/W79L532

PWM2 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM2

PWM Control 1 Register

Address: DDH

Bit:

7

6

5

4

3

2

1

0

PWM3OE

PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENWPM0

Mnemonic: PWMCON1

Address: DCH

PWM3OE: Output enable for PWM3

PWM2OE: Output enable for PWM2

ENPWM3: Enable PWM3

ENPWM2: Enable PWM2

PWM1OE: Output enable for PWM1

PWM0OE: Output enable for PWM0

ENPWM1: Enable PWM1

ENPWM0: Enable PWM0

PWM1 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM1

Address: DBH

PWM0 Register

Bit:

7

6

1

Mnemonic: PWM0

PWMP Register

Address: DAH

1

Bit:

7

6

Mnemonic: PWMP

Address: D9H

PWM4 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM4

Address: CFH

Publication Release Date: November 21, 2005

Revision A5

- 45 -

W79E532/W79L532

PWM Control 2 Register

Bit:

7

-

6

-

5

-

4

-

3

2

1

0

PWM5

OE-

PWM4 ENWP ENWP

OE

M5

M4

Mnemonic: PWMCON2

Address: CEH

PWM5OE: Output enable for PWM5

PWM4OE: Output enable for PWM4

ENPWM5: Enable for PWM5

ENPWM4: Enable for PWM4

PWM5 Register

Bit:

7

6

5

4

3

2

1

0

Mnemonic: PWM5

Address: C3H

11.4 Watchdog Timer

The Watchdog timer is a free-running timer which can be programmed by the user to serve as a

system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the

system clock. The divider output is selectable and determines the time-out interval. When the time-out

occurs a flag is set, which can cause an interrupt if enabled, and a system reset can also be caused if

it is enabled. The interrupt will occur if the individual interrupt enable and the global enable are set.

The interrupt and reset functions are independent of each other and may be used separately or

together depending on the users software.

XT

0

16

19

22

25

WD1,WD0

Time-out

Interrupt

WDIF

EWDI(EIE.4)

17

20

23

00

01

WTRF

10

11

512 clock

delay

Reset

Reset Watchdog

RWT (WDCON.0)

Enable Watchdog timer reset

EWT(WDCON.1)

Figure 19. Watchdog Timer

- 46 -

W79E532/W79L532

The Watchdog timer should first be restarted by using RWT. This ensures that the timer starts from a

known state. The RWT bit is used to restart the watchdog timer. This bit is self clearing, i.e. after

writing a 1 to this bit the software will automatically clear it. The watchdog timer will now count clock

cycles. The time-out interval is selected by the two bits WD1 and WD0 (CKCON.7 and CKCON.6).

When the selected time-out occurs, the Watchdog interrupt flag WDIF (WDCON.3) is set. After the

time-out has occurred, the watchdog timer waits for an additional 512 clock cycles. If the Watchdog

Reset EWT (WDCON.1) is enabled, then 512 clocks after the time-out, if there is no RWT, a system

reset due to Watchdog timer will occur. This will last for two machine cycles, and the Watchdog timer

reset flag WTRF (WDCON.2) will be set. This indicates to the software that the watchdog was the

cause of the reset.

When used as a simple timer, the reset and interrupt functions are disabled. The timer will set the

WDIF flag each time the timer completes the selected time interval. The WDIF flag is polled to detect a

time-out and the RWT allows software to restart the timer. The Watchdog timer can also be used as a

very long timer. The interrupt feature is enabled in this case. Every time the time-out occurs an

interrupt will occur if the global interrupt enable EA is set.

The main use of the Watchdog timer is as a system monitor. This is important in real-time control

applications. In case of some power glitches or electro-magnetic interference, the processor may

begin to execute errant code. If this is left unchecked the entire system may crash. Using the

watchdog timer interrupt during software development will allow the user to select ideal watchdog

reset locations. The code is first written without the watchdog interrupt or reset. Then the watchdog

interrupt is enabled to identify code locations where interrupt occurs. The user can now insert

instructions to reset the watchdog timer which will allow the code to run without any watchdog timer

interrupts. Now the watchdog timer reset is enabled and the watchdog interrupt may be disabled. If

any errant code is executed now, then the reset watchdog timer instructions will not be executed at

the required instants and watchdog reset will occur.

The watchdog time-out selection will result in different time-out values depending on the clock speed.

The reset, when enabled, will occur 512 clocks after the time-out has occurred.

Table 9. Time-out values for the Watchdog timer

WATCHDOG NUMBER OF

TIME

@ 1.8432 MHZ

TIME

@ 10 MHZ

TIME

@ 25 MHZ

WD1

WD0

INTERVAL

CLOCKS

17

0

1

0

1

0

1

131072

71.11 mS

568.89 mS

13.11 mS

104.86 mS

838.86 mS

6710.89 mS

5.24 mS

41.94 mS

2

20

2

23

1048576

8388608

67108864

4551.11 mS

36408.88 mS

335.54 mS

2684.35 mS

2

26

2

The Watchdog timer will de disabled by a power-on/fail reset. The Watchdog timer reset does not

disable the watchdog timer, but will restart it. In general, software should restart the timer to put it into

a known state.

The control bits that support the Watchdog timer are discussed below.

Publication Release Date: November 21, 2005

- 47 -

Revision A5

W79E532/W79L532

Watchdog Control

WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the

watchdog timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the

global interrupt enable is set and other interrupt requirements are met). Software or any reset

can clear this bit.

WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.

This bit is useful for determined the cause of a reset. Software must read it, and clear it

manually. A Power-fail reset will clear this bit. If EWT = 0, then this bit will not be affected by

the watchdog timer.

EWT: WDCON.1 - Enable Watchdog timer Reset. This bit when set to 1 will enable the Watchdog

timer reset function. Setting this bit to 0 will disable the Watchdog timer reset function, but will

leave the timer running.

RWT: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog timer and to

restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will

automatically clear it. If the Watchdog timer reset is enabled, then the RWT has to be set by

the user within 512 clocks of the time-out. If this is not done then a Watchdog timer reset will

occur.

Clock Control

WD1, WD0: CKCON.7, CKCON.6 - Watchdog Timer Mode select bits. These two bits select the time-

out interval for the watchdog timer. The reset time is 512 clock longer than the interrupt

time-out value.

17

The default Watchdog time-out is 2 clocks, which is the shortest time-out period. The EWT, WDIF

and RWT bits are protected by the Timed Access procedure. This prevents software from accidentally

enabling or disabling the watchdog timer. More importantly, it makes it highly improbable that errant

code can enable or disable the watchdog timer. Please refer as below demo program.

org

63h

mov TA,#AAH

mov TA,#55H

clr

jnb

WDIF

execute_reset_flag,bypass_reset

$

; Test if CPU need to reset.

; Wait to reset

jmp

bypass_reset:

mov

TA,#AAH

TA,#55H

RWT

mov

setb

reti

org 300h

- 48 -

W79E532/W79L532

start:

mov

ckcon,#01h

ckcon,#61h

ckcon,#81h

ckcon,#c1h

; select 2 ^ 17 timer

; select 2 ^ 20 timer

; select 2 ^ 23 timer

; select 2 ^ 26 timer

;

mov TA,#aah

mov TA,#55h

mov WDCON,#00000011B

setb

jmp

EWDI

ea

$

; wait time out

Publication Release Date: November 21, 2005

Revision A5

- 49 -

W79E532/W79L532

12. SERIAL PORT

Serial port in the W79E(L)532 is a full duplex port. The W79E(L)532 provides the user with additional

features such as the Frame Error Detection and the Automatic Address Recognition. The serial ports

are capable of synchronous as well as asynchronous communication. In Synchronous mode the

W79E(L)532 generates the clock and operates in a half duplex mode. In the asynchronous mode, full

duplex operation is available. This means that it can simultaneously transmit and receive data. The

transmit register and the receive buffer are both addressed as SBUF Special Function Register.

However any write to SBUF will be to the transmit register, while a read from SBUF will be from the

receive buffer register. The serial port can operate in four different modes as described below.

Mode 0

This mode provides synchronous communication with external devices. In this mode serial data is

transmitted and received on the RXD line. TXD is used to transmit the shift clock. The TxD clock is

provided by the W79E(L)532 whether the device is transmitting or receiving. This mode is therefore a

half duplex mode of serial communication. In this mode, 8 bits are transmitted or received per frame.

The LSB is transmitted/received first. The baud rate is fixed at 1/12 or 1/4 of the oscillator frequency.

This baud rate is determined by the SM2 bit (SCON.5). When this bit is set to 0, then the serial port

runs at 1/12 of the clock. When set to 1, the serial port runs at 1/4 of the clock. This additional facility

of programmable baud rate in mode 0 is the only difference between the standard 8051 and the

W79E(L)532.

The functional block diagram is shown below. Data enters and leaves the Serial port on the RxD line.

The TxD line is used to output the shift clock. The shift clock is used to shift data into and out of the

W79E(L)532 and the device at the other end of the line. Any instruction that causes a write to SBUF

will start the transmission. The shift clock will be activated and data will be shifted out on the RxD pin

till all 8 bits are transmitted. If SM2 = 1, then the data on RxD will appear 1 clock period before the

falling edge of shift clock on TxD. The clock on TxD then remains low for 2 clock periods, and then

goes high again. If SM2 = 0, the data on RxD will appear 3 clock periods before the falling edge of

shift clock on TxD. The clock on TxD then remains low for 6 clock periods, and then goes high again.

This ensures that at the receiving end the data on RxD line can either be clocked on the rising edge of

the shift clock on TxD or latched when the TxD clock is low.

OSC

Internal

Data Bus

RXD

P3.0 Alternate

Output Function

PARIN

SOUT

Write to

SBUF

LOAD

CLOCK

12

4

TX SHIFT

TI

TX START

TX CLOCK

Transmit Shift Register

Serial Port Interrupt

SM2

SERIAL

RI

0

1

CONTROLLE

SHIFT

CLOCK

TXD

P3.1 Alternate

Output function

RX

CLOCK

LOAD SBUF

RI

RX

START

REN

RX SHIFT

Read SBUF

SBUF

CLOCK

SIN

RXD

PAROUT

SBUF

Internal

P3.0 Alternate

Iutput function

Data Bus

Receive Shift Register

Figure 20. Serial Port Mode 0

- 50 -

W79E532/W79L532

The TI flag is set high in C1 following the end of transmission of the last bit. The serial port will receive

data when REN is 1 and RI is zero. The shift clock (TxD) will be activated and the serial port will latch

data on the rising edge of shift clock. The external device should therefore present data on the falling

edge on the shift clock. This process continues till all the 8 bits have been received. The RI flag is set

in C1 following the last rising edge of the shift clock on TxD. This will stop reception, till the RI is

cleared by software.

Mode 1

In Mode 1, the full duplex asynchronous mode is used. Serial communication frames are made up of

10 bits transmitted on TXD and received on RXD. The 10 bits consist of a start bit (0), 8 data bits (LSB

first), and a stop bit (1). On receive, the stop bit goes into RB8 in the SFR SCON. The baud rate in this

mode is variable. The serial baud can be programmed to be 1/16 or 1/32 of the Timer 1 overflow.

Since the Timer 1 can be set to different reload values, a wide variation in baud rates is possible.

Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at C1 following

the first roll-over of divide by 16 counter. The next bit is placed on TxD pin at C1 following the next

rollover of the divide by 16 counter. Thus the transmission is synchronized to the divide by 16 counter

and not directly to the write to SBUF signal. After all 8 bits of data are transmitted, the stop bit is

transmitted. The TI flag is set in the C1 state after the stop bit has been put out on TxD pin. This will

be at the 10th rollover of the divide by 16 counter after a write to SBUF.

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,

with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD

line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the

divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of

the divide by 16 counter.

The 16 states of the counter effectively divide the bit time into 16 slices. The bit detection is done on a

best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and 10th counter states. By

using a majority 2 of 3 voting system, the bit value is selected. This is done to improve the noise

rejection feature of the serial port. If the first bit detected after the falling edge of RxD pin is not 0, then

this indicates an invalid start bit, and the reception is immediately aborted. The serial port again looks

for a falling edge in the RxD line. If a valid start bit is detected, then the rest of the bits are also

detected and shifted into the SBUF.

After shifting in 8 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded

and RI is set. However certain conditions must be met before the loading and setting of RI can be

done.

1. RI must be 0 and

2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.

Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to

looking for a 1-to-0 transition on the RxD pin.

Publication Release Date: November 21, 2005

- 51 -

Revision A5

W79E532/W79L532

Timer 1

Overflow

Transmit Shift Register

Timer 2 Overflow

(for Serial Port 0 only)

STOP

Internal

Data Bus

PARIN

Write to

SBUF

SOUT

2

TXD

START

LOAD

SMOD=

(SMOD_1)

CLOCK

0

1

TX START TX SHIFT

TX CLOCK

TCLK

0

1

16

TI

Serial Port

Interrupt

RCLK

SERIAL

RI

CONTROLLER

16

RX CLOCK

LOAD

SAMPLE

RX

Read

SBUF

1-TO-0

DETECTOR

SBUF

RX SHIFT

START

CLOCK

SIN

Internal

Data

Bus

SBUF

RB8

PAROUT

D8

BIT

DETECTOR

RXD

Receive Shift Register

Figure 21. Serial Port Mode 1

Mode 2

This mode uses a total of 11 bits in asynchronous full-duplex communication. The functional

description is shown in the figure below. The frame consists of one start bit (0), 8 data bits (LSB first),

a programmable 9th bit (TB8) and a stop bit (0). The 9th bit received is put into RB8. The baud rate is

programmable to 1/32 or 1/64 of the oscillator frequency, which is determined by the SMOD bit in

PCON SFR. Transmission begins with a write to SBUF. The serial data is brought out on to TxD pin at

C1 following the first roll-over of the divide by 16 counter. The next bit is placed on TxD pin at C1

following the next rollover of the divide by 16 counter. Thus the transmission is synchronized to the

divide by 16 counter, and not directly to the write to SBUF signal. After all 9 bits of data are

transmitted, the stop bit is transmitted. The TI flag is set in the C1 state after the stop bit has been put

out on TxD pin. This will be at the 11th rollover of the divide by 16 counter after a write to SBUF.

Reception is enabled only if REN is high. The serial port actually starts the receiving of serial data,

with the detection of a falling edge on the RxD pin. The 1-to-0 detector continuously monitors the RxD

line, sampling it at the rate of 16 times the selected baud rate. When a falling edge is detected, the

divide by 16 counter is immediately reset. This helps to align the bit boundaries with the rollovers of

the divide by 16 counter. The 16 states of the counter effectively divide the bit time into 16 slices. The

bit detection is done on a best of three basis. The bit detector samples the RxD pin, at the 8th, 9th and

10th counter states. By using a majority 2 of 3 voting system, the bit value is selected. This is done to

improve the noise rejection feature of the serial port.

- 52 -

W79E532/W79L532

TB8

OSC

D8

Internal

Data Bus

STOP

PARIN

Write to

SBUF

2

SOUT

TXD

START

LOAD

SMOD=

(SMOD_1)

CLOCK

0

1

TX

SHIFT

TX START

Transmit Shift Register

TX CLOCK

16

TI

SERIAL

Serial Port

Interrupt

CONTROLLER

RI

16

RX CLOCK

LOAD

SBUF

RX SHIFT

SAMPLE

Read

SBUF

1-TO-0

DETECTOR

RX START

Internal

CLOCK

PAROUT

SBUF

RB8

Receive Shift Register

Data

Bus

BIT

DETECTOR

SIN

D8

RXD

Figure 22. Serial Port Mode 2

If the first bit detected after the falling edge of RxD pin, is not 0, then this indicates an invalid start bit,

and the reception is immediately aborted. The serial port again looks for a falling edge in the RxD line.

If a valid start bit is detected, then the rest of the bits are also detected and shifted into the SBUF.

After shifting in 9 data bits, there is one more shift to do, after which the SBUF and RB8 are loaded

and RI is set. However certain conditions must be met before the loading and setting of RI can be

done.

1. RI must be 0 and

2. Either SM2 = 0, or the received stop bit = 1.

If these conditions are met, then the stop bit goes to RB8, the 8 data bits go into SBUF and RI is set.

Otherwise the received frame may be lost. After the middle of the stop bit, the receiver goes back to

looking for a 1-to-0 transition on the RxD pin.

Mode 3

This mode is similar to Mode 2 in all respects, except that the baud rate is programmable. The user

must first initialize the Serial related SFR SCON before any communication can take place. This

involves selection of the Mode and baud rate. The Timer 1 should also be initialized if modes 1 and 3

are used. In all four modes, transmission is started by any instruction that uses SBUF as a destination

register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1. This will generate a

clock on the TxD pin and shift in 8 bits on the RxD pin. Reception is initiated in the other modes by the

incoming start bit if REN = 1. The external device will start the communication by transmitting the start

bit.

Publication Release Date: November 21, 2005

- 53 -

Revision A5

W79E532/W79L532

Timer 1

Overflow

Timer 2 Overflow

(for Serial Port 0 only)

STOP

D8

TB8

Internal

Data Bus

PARIN

Write to

SBUF

SOUT

2

TXD

START

LOAD

SMOD=

(SMOD_1)

CLOCK

0

1

Transmit Shift Register

TX START TX SHIFT

TX CLOCK

TCLK

0

1

16

TI

Serial Port

Interrupt

RCLK

SERIAL

RI

CONTROLLER

16

RX CLOCK

SAMPLE

LOAD

SBUF

RX

Read

1-TO-0

DETECTOR

START

SBUF

RX SHIFT

CLOCK

SIN

Internal

Data

Bus

SBUF

PAROUT

BIT

DETECTOR

D8

RB8

RXD

Receive Shift Register

Figure 23. Serial Port Mode 3

Table 10. Serial Ports Modes

FRAME

SIZE

STAR

T BIT

STOP

9TH BIT

FUNCTION

SM1

SM0

MODE

TYPE

BAUD CLOCK

BIT

No

1

0

1

0

1

0

1

0

1

2

3

Synch.

Asynch.

4 or 12 TCLKS

Timer 1 or 2

32 or 64 TCLKS

Timer 1 or 2

8 bits

No

1

None

0, 1

10 bits

11 bits

1

0, 1

12.1 Framing Error Detection

A Frame Error occurs when a valid stop bit is not detected. This could indicate incorrect serial data

communication. Typically the frame error is due to noise and contention on the serial communication

line. The W79E(L)532 has the facility to detect such framing errors and set a flag which can be

checked by software.

The Frame Error FE(FE_1) bit is located in SCON.7. This bit is normally used as SM0 in the standard

8051 family. However, in the W79E(L)532 it serves a dual function and is called SM0/FE. There are

actually two separate flags, one for SM0 and the other for FE. The flag that is actually accessed as

SCON.7 is determined by SMOD0 (PCON.6) bit. When SMOD0 is set to 1, then the FE flag is

indicated in SM0/FE. When SMOD0 is set to 0, then the SM0 flag is indicated in SM0/FE.

The FE bit is set to 1 by hardware but must be cleared by software. Note that SMOD0 must be 1 while

reading or writing to FE. If FE is set, then any following frames received without any error will not clear

the FE flag. The clearing has to be done by software.

- 54 -

W79E532/W79L532

12.2 Multiprocessor Communications

Multiprocessor communications makes use of the 9th data bit in modes 2 and 3. In the W79E(L)532,

the RI flag is set only if the received byte corresponds to the Given or Broadcast address. This

hardware feature eliminates the software overhead required in checking every received address, and

greatly simplifies the software programmer task.

In the multiprocessor communication mode, the address bytes are distinguished from the data bytes

by transmitting the address with the 9th bit set high. When the master processor wants to transmit a

block of data to one of the slaves, it first sends out the address of the targeted slave (or slaves). All

the slave processors should have their SM2 bit set high when waiting for an address byte. This

ensures that they will be interrupted only by the reception of a address byte. The Automatic address

recognition feature ensures that only the addressed slave will be interrupted. The address comparison

is done in hardware not software.

The addressed slave clears the SM2 bit, thereby clearing the way to receive data bytes. With SM2 =

0, the slave will be interrupted on the reception of every single complete frame of data. The

unaddressed slaves will be unaffected, as they will be still waiting for their address. In Mode 1, the 9th

bit is the stop bit, which is 1 in case of a valid frame. If SM2 is 1, then RI is set only if a valid frame is

received and the received byte matches the Given or Broadcast address.

The Master processor can selectively communicate with groups of slaves by using the Given Address.

All the slaves can be addressed together using the Broadcast Address. The addresses for each slave

are defined by the SADDR and SADEN SFRs. The slave address is an 8-bit value specified in the

SADDR SFR. The SADEN SFR is actually a mask for the byte value in SADDR. If a bit position in

SADEN is 0, then the corresponding bit position in SADDR is don't care. Only those bit positions in

SADDR whose corresponding bits in SADEN are 1 are used to obtain the Given Address. This gives

the user flexibility to address multiple slaves without changing the slave address in SADDR.

The following example shows how the user can define the Given Address to address different slaves.

Slave 1:

SADDR1010 0100

SADEN1111 1010

Given 1010 0x0x

Slave 2:

SADDR1010 0111

SADEN1111 1001

Given 1010 0xx1

The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don't care, while for slave 2 it

is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (1010

0000). Similarly the bit 1 position is 0 for slave 1 and don't care for slave 2. Hence to communicate

only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master

wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit

1 = 0. The bit 3 position is don't care for both the slaves. This allows two different addresses to select

both slaves (1010 0001 and 1010 0101).

The master can communicate with all the slaves simultaneously with the Broadcast Address. This

address is formed from the logical ORing of the SADDR and SADEN SFRs. The zeros in the result

are defined as don't cares In most cases the Broadcast Address is FFh. In the previous case, the

Broadcast Address is (1111111X) for slave 1 and (11111111) for slave 2.

Publication Release Date: November 21, 2005

- 55 -

Revision A5

W79E532/W79L532

The SADDR and SADEN SFRs are located at address A9h and B9h respectively. On reset, these two

SFRs are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXX

XXXX(i.e. all bits don't care). This effectively removes the multiprocessor communications feature,

since any selectivity is disabled.

13. TIMED ACCESS PROTECTION

The W79E(L)532 has several new features, like the Watchdog timer, on-chip ROM size adjustment,

wait state control signal and Power on/fail reset flag, which are crucial to proper operation of the

system. If left unprotected, errant code may write to the Watchdog control bits resulting in incorrect

operation and loss of control. In order to prevent this, the W79E(L)532 has a protection scheme which

controls the write access to critical bits. This protection scheme is done using a timed access.

In this method, the bits which are to be protected have a timed write enable window. A write is

successful only if this window is active, otherwise the write will be discarded. This write enable window

is open for 3 machine cycles if certain conditions are met. After 3 machine cycles, this window

automatically closes. The window is opened by writing AAh and immediately 55h to the Timed

Access(TA) SFR. This SFR is located at address C7h. The suggested code for opening the timed

access window is

TA

REG 0C7h

;define new register TA, located at 0C7h

MOV TA, #0AAh

MOV TA, #055h

When the software writes AAh to the TA SFR, a counter is started. This counter waits for 3 machine

cycles looking for a write of 55h to TA. If the second write (55h) occurs within 3 machine cycles of the

first write (AAh), then the timed access window is opened. It remains open for 3 machine cycles,

during which the user may write to the protected bits. Once the window closes the procedure must be

repeated to access the other protected bits.

Examples of Timed Assessing are shown below.

Example 1: Valid access

MOV TA, #0AAh

MOV TA, #055h

3 M/C

Note: M/C = Machine Cycles

MOV WDCON, #00h 3 M/C

Example 2: Valid access

MOV TA, #0AAh

3 M/C

1 M/C

2 M/C

MOV TA, #055h

NOP

SETB EWT

Example 3: Valid access

MOV TA, #0Aah

MOV TA, #055h

3 M/C

ORL

WDCON, #00000010B 3M/C

- 56 -

W79E532/W79L532

Example 4: Invalid access

MOV TA, #0AAh

MOV TA, #055h

NOP

3 M/C

1 M/C

2 M/C

NOP

CLR

POR

Example 5: Invalid Access

MOV TA, #0AAh

NOP

MOV TA, #055h

SETB EWT

3 M/C

1 M/C

3 M/C

2 M/C

In the first three examples, the writing to the protected bits is done before the 3 machine cycle window

closes. In Example 4, however, the writing to the protected bit occurs after the window has closed,

and so there is effectively no change in the status of the protected bit. In Example 5, the second write

to TA occurs 4 machine cycles after the first write, therefore the timed access window in not opened at

all, and the write to the protected bit fails.

Publication Release Date: November 21, 2005

- 57 -

Revision A5

W79E532/W79L532

14. H/W REBOOT MODE (BOOT FROM 4K BYTES OF LDFLASH)

The W79E(L)532 boots from APFlash program (64K bytes) by default at the external reset. On some

occasions, user can force W79E(L)532 to boot from the LDFlash program (4K bytes) at the external

reset. The settings for this special mode is as follow. It is necessary to add 10K resistor on these P2.6,

P2.7 and P4.3 pins.

Reboot Mode

OPTION BITS

Bit4 L

RST

H

P4.3

X

P2.7

L

P2.6

L

MODE

REBOOT

Bit5 L

H

L

X

The Reset Timing For Entering

REBOOT Mode

P2.7

Hi-Z

P2.6

RST

20 US

10 mS

Notes:

1. The possible situation that you need to enter REBOOT mode is when the APFlash program can not run normally and

W79E(L)532 can not jump to LDFlash to execute on chip programming function. Then you can use this REBOOT mode to

force the CPU jump to LDFlash and run on chip programming procedure. When you design your system, you can connect

the pins P26, P27 to switches or jumpers. For example in a CD ROM system, you can connect the P26 and P27 to PLAY

and EJECT buttons on the panel. When the APFlash program is fail to execute the normal application program. User can

press both two buttons at the same time and then switch on the power of the personal computer to force the W79E(L)532 to

enter the REBOOT mode. After power on of personal computer, you can release both PLAY and EJECT button. And re-run

the on chip programming procedure to let the APFlash have the normal program code. Then you can back to normal

condition of CD ROM.

2: In application system design, user must take care the P4.3, P2, P3, ALE, /EA and /PSEN pin value at reset to avoid

W79E(L)532 entering the programming mode or REBOOT mode in normal operation.

- 58 -

W79E532/W79L532

15. IN-SYSTEM PROGRAMMING

15.1 The Loader Program Locates at LDFlash Memory

CPU is Free Run at APFlash memory. CHPCON register had been set #03H value before CPU has

entered idle state. CPU will switch to LDFlash memory and execute a reset action. H/W reboot mode

will switch to LDFlash memory, too. Set SFRCN register where it locates at user's loader program to

update APFlash bank 0 or bank 1 memory. Set a SWRESET (CHPCON.7) to switch back APFlash

after CPU has updated APFlash program. CPU will restart to run program from reset state.

15.2 The Loader Program Locates at APFlash Memory

CPU is Free Run at APFlash memory. CHPCON register had been set #01H value before CPU has

entered idle state. Set SFRCN register to update LDFlash or another bank of APFlash program. CPU

will continue to run user's APFlash program after CPU has updated program. Please refer

demonstrative code to understand other detail description.

16. H/W WRITER MODE

This mode is for the writer to write / read Flash EPROM operation. A general user may not enter this

mode.

The Timing For Entering Flash EPROM

Mode on the Programmer

EA

Hi-Z

PSEN

ALE

Hi-Z

P2.7

P2.6

P3.7

P3.6

RST

Hi-Z

10ms

300ms

Publication Release Date: November 21, 2005

Revision A5

- 59 -

W79E532/W79L532

17. SECURITY BITS

1. Using device programmer, the Flash EPROM can be programmed and verified repeatedly. Until the

code inside the Flash EPROM is confirmed OK, the code can be protected. The protection of Flash

EPROM and those operations on it are described below. The W79E(L)532 has Special Setting

Register which can be accessed by device programmer. The register can only be accessed from

the Flash EPROM operation mode. Those bits of the Security Registers can not be changed once

they have been programmed from high to low. They can only be reset through erase-all operation.

If you needn’t have ISP function, please don’t fill “FF” code on LD memory. The writer always writes

AP and LD flashs every time.

B3

B4

Security Bits

B2 B1 B0

B7 B6 B5

B7 : 1 -> XT > 24M hz, 0: XT < 24M hz.

B5 : 0 -> Eable H/W reboot with P4.3

B4 : 0 -> Enable H/W reboot with P2.6, P2.7

B1 : 0 -> MOVC Inhibited

B0 : 0 -> Data out lock

Default 1 for each bit.

Option Bits

B0: Lock bit

This bit is used to protect the customer's program code in the W79E(L)532. It may be set after the

programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the

Flash EPROM data and Special Setting Registers can not be accessed again.

B1: MOVC Inhibit

This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC

instruction in external program memory from reading the internal program code. When this bit is set to

logic 0, a MOVC instruction in external program memory space will be able to access code only in the

external memory, not in the internal memory. A MOVC instruction in internal program memory space

will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,

there are no restrictions on the MOVC instruction.

B4: H/W Reboot with P2.6 and P2.7

If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H, P2.6 = L and P2.7 = L

state. CPU will start from LDFlash to update the user’s program.

B5: H/W Reboot with P4.3

If this bit is set to logic 0, enable to reboot 4k LDFlash mode while RST =H and P4.3 = L state. CPU

will start from LDFlash to update the user’s program

B7: Select clock freqency.

If clock freqency is over 24M hz, then set this bit is H. If clock frequency is less than 24M hz, then

clear this bit.

- 60 -

W79E532/W79L532

18. ELECTRICAL CHARACTERISTICS

18.1 Absolute Maximum Ratings

PARAMETER

DC Power Supply

SYMBOL

VDD − VSS

VIN

CONDITION

RATING

+7.0

UNIT

V

-0.3

VSS -0.3

0

Input Voltage

VDD +0.3

+70

V

Operating Temperature

Storage Temperatute

TA

°C

Tst

-55

+150

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

18.2 DC Characteristics

(TA = 25°C, unless otherwise specified.)

SPECIFICATION

PARAMETER

Operating Voltage

Operating Current

SYM.

VDD

IDD

TEST CONDITIONS

MIN.

MAX.

UNIT

3.0

5.5

V

Fosc < = 25 MHz

30

10

13

5

mA

μA

VDD = 5.5V, Fosc = 20 MHz

VDD = 3.3V, Fosc = 12 MHz

VDD = 5.5V, Fosc=20 MHz

VDD = 3.3V, Fosc=12 MHz

VDD = 3.3 ~ 5.5V

-

Idle Current

IIDLE

Power Down Current

IPWDN

IIN1

-

10

Input Current

P1, P2, P3

VDD = 3.3 ~ 5.5V

VIN = 0V or VDD

-50

+10

μA

-

900

500

VDD = 5.5V, 0<VIN<VDD

VDD = 3.3V, 0<VIN<VDD

μA

Input Current RST^[*1]

IIN2

ILK

Input Leakage Current

P0, EA

VDD = 3.3 ~ 5.5V

0V<VIN<VDD

-10

+10

μA

-500

-200

-50

0.8

0.5

0.8

0.5

0.8

0.5

VDD = 5.5V VIN = 2.0V

VDD = 3.3V VIN = 1.0V

VDD = 4.5V

μA

V

Logic 1 to 0 Transition

Current P1, P2, P3

[*4]

ITL

-250

0

Input Low Voltage

P0, P1, P2, P3, EA

VIL1

VIL2

VIL3

V

VDD =3.3V

V

VDD = 4.5V

Input Low Voltage

RST^[*1]

V

VDD = 3.3V

V

VDD = 4.5V

Input Low Voltage

XTAL1^[*3]

V

VDD = 3.3V

Publication Release Date: November 21, 2005

Revision A5

- 61 -

W79E532/W79L532

DC Characteristics, continued

SPECIFICATION

PARAMETER

SYM.

VIH1

VIH2

VIH3

Isk1

Isk2

Isr1

TEST CONDITIONS

MIN.

2.4

1.8

3.0

2.0

3.5

2.0

6

MAX.

VDD +0.2

9

UNIT

V

VDD = 5.5V

VDD = 3.3V

VDD = 5.5V

VDD = 3.3V

VDD = 5.5V

VDD = 3.3V

Input High Voltage

P0, P1, P2, P3, EA

Input High Voltage RST

Input High Voltage

XTAL1^[*3]

Sink current

P1, P3

mA

uA

VDD = 4.5V, VOL = 0.45

VDD = 3.3V, VOL = 0.4

VDD = 4.5V , VOL = 0.45V

VDD = 3.3V, VOL=0.4

3.8

10

7

Sink current

14

6.5

-200

-100

-10

9.5

P0,P2, ALE, PSEN

Source current

-360

VDD = 4.5V, VOL = 2.4V

VDD = 3.3V, VOL = 1.4V

VDD = 4.5V, VOL = 2.4V

P1, P2 (I/O), P3

-220

uA

Source current

-14

mA

Isr2

P0,P2 (address), ALE,

PSEN

-6

-9

mA

VDD = 3.3V, VOL = 1.4V

-

0.45

0.4

V

VDD = 4.5V, IOL = +6 mA

VDD = 3.3V, IOL = +3.8 mA

VDD = 4.5V, IOL = +10 mA

Output Low Voltage

P1, P2 (I/O), P3

VOL1

VOL2

Output Low Voltage

P0, P2(address), ALE,

PSEN ^[*2]

0.45

-

0.4

V

VDD = 3.3V, IOL = +6.5 mA

2.4

1.4

2.4

1.4

-

V

VDD = 4.5V, IOH = -200 μA

VDD = 3.3V, IOL = -100 uA

VDD = 4.5V, IOH = -10mA

VDD = 3.3V, IOL = -6 mA

Output High Voltage

P1, P3

VOH1

VOH2

Output High Voltage

P0, P2, ALE, PSEN ^[*2]

Notes:

*1. RST pin is a Schmitt trigger input.

*2. P0, ALE and PSEN are tested in the external access mode.

*3. XTAL1 is a CMOS input.

*4. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0. The transition

current reaches its maximum value when VIN approximates to 2V.

- 62 -

W79E532/W79L532

18.3 A.C. Characteristics

t_CLCL

t_CLCH

t_CLCX

Clock

t_CHCL

t_CHCX

Note: Duty cycle is 50%.

External Clock Characteristics

PARAMETER

Clock High Time

Clock Low Time

Clock Rise Time

Clock Fall Time

SYMBOL

MIN.

TYP.

MAX.

UNITS

nS

NOTES

t_CHCX

t_CLCX

t_CLCH

t_CHCL

12

-

nS

10

nS

-

nS

Publication Release Date: November 21, 2005

Revision A5

- 63 -

W79E532/W79L532

18.3.1 A.C. Specification

PARAMETER

VARIABLE

CLOCK

MIN.

VARIABLE

CLOCK

MAX.

SYMBOL

UNITS

Oscillator Frequency

1/t_CLCL

t_LHLL

0

40

MHz

nS

ALE Pulse Width

1.5t_CLCL- 5

0.5t_CLCL- 5

Address Valid to ALE Low

Address Hold After ALE Low

t_AVLL

nS

t_LLAX1

nS

Address Hold After ALE Low for

MOVX Write

t_LLAX2

0.5t_CLCL- 5

nS

ALE Low to Valid Instruction In

ALE Low to PSEN Low

t_LLIV

t_LLPL

t_PLPH

2.5t_CLCL- 20

nS

0.5t_CLCL- 5

2.0t_CLCL- 5

PSEN Pulse Width

t_PLIV

t_PXIX

2.0t_CLCL- 20

nS

PSEN Low to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction Float After PSEN

Port 0 Address to Valid Instr. In

Port 2 Address to Valid Instr. In

0

t_PXIZ

t_CLCL- 5

t_AVIV1

t_AVIV2

t_PLAZ

t_RHDX

t_RHDZ

t_RLAZ

3.0t_CLCL- 20

3.5t_CLCL- 20

0

PSEN Low to Address Float

Data Hold After Read

Data Float After Read

t_CLCL- 5

0.5t_CLCL- 5

RD Low to Address Float

- 64 -

W79E532/W79L532

18.3.2 MOVX Characteristics Using Strech Memory Cycle

VARIABLE

PARAMETER

SYMBOL

CLOCK

MIN.

CLOCK

MAX.

UNITS

STRECH

1.5t_CLCL- 5

t

_MCS= 0

Data Access ALE Pulse Width

t_LLHL2

t_LLAX2

t_RLRH

nS

2.0t_CLCL- 5

t_MCS>0

Address Hold After ALE Low for

MOVX write

0.5t_CLCL- 5

2.0t_CLCL- 5

t_MCS- 10

t

_MCS= 0

RD Pulse Width

WR Pulse Width

t_MCS>0

2.0t_CLCL- 5

t_MCS- 10

t

_MCS= 0

t_WLWH

nS

t_MCS>0

2.0t_CLCL- 20

t_MCS- 20

t

_MCS= 0

t_RLDV

t_RHDX

t_RHDZ

nS

RD Low to Valid Data In

Data Hold after Read

t_MCS>0

0

t_CLCL- 5

t

_MCS= 0

Data Float after Read

2.0t_CLCL- 5

2.5t_CLCL- 5

t_MCS+ 2t_CLCL- 40

3.0t_CLCL- 20

2.0t_CLCL- 5

0.5t_CLCL+ 5

1.5t_CLCL+ 5

t_MCS>0

t

_MCS= 0

ALE Low to Valid Data In

Port 0 Address to Valid Data In

t_LLDV

t_AVDV1

t_LLWL

nS

t_MCS>0

t

_MCS= 0

t_MCS>0

0.5t_CLCL- 5

1.5t_CLCL- 5

t

_MCS= 0

ALE Low to RD or WR Low

t_MCS>0

t_CLCL- 5

t

_MCS= 0

Port 0 Address to RD or WR

Low

t_AVWL

nS

2.0t_CLCL- 5

t_MCS>0

1.5t_CLCL- 5

2.5t_CLCL- 5

t

_MCS= 0

Port 2 Address to RD or WR

Low

t_AVWL2

nS

t_MCS>0

-5

t

_MCS= 0

Data Valid to WR Transition

Data Hold after Write

t_QVWX

1.0t_CLCL- 5

t_CLCL- 5

2.0t_CLCL- 5

t_MCS>0

t

_MCS= 0

t_WHQX

t_RLAZ

nS

t_MCS>0

0.5t_CLCL- 5

RD Low to Address Float

RD or WR high to ALE high

0

10

t

_MCS= 0

t_WHLH

1.0t_CLCL- 5

1.0t_CLCL+ 5

t_MCS>0

Note: t_MCSis a time period related to the Stretch memory cycle selection. The following table shows the time period of t_MCS

for each selection of the Stretch value.

Publication Release Date: November 21, 2005

- 65 -

Revision A5

W79E532/W79L532

M2

0

M1

0

M0

0

MOVX CYCLES

2 machine cycles

3 machine cycles

4 machine cycles

5 machine cycles

6 machine cycles

7 machine cycles

8 machine cycles

9 machine cycles

T_MCS

0

1

4 t_CLCL

8 t_CLCL

12 t_CLCL

16 t_CLCL

20 t_CLCL

24 t_CLCL

28 t_CLCL

0

1

0

1

0

1

0

1

0

1

Explanation of Logics Symbols

In order to maintain compatibility with the original 8051 family, this device specifies the same

parameter for each device, using the same symbols. The explanation of the symbols is as follows.

t

Time

A

D

L

Address

C

H

Clock

Input Data

Logic level low

Logic level high

I

Instruction

P

R

PSEN

Q

Output Data

RD signal

V

X

Valid

W

Z

WR signal

Tri-state

No longer a valid state

18.3.3 Program Memory Read Cycle

t_LHLL

t_LLIV

ALE

t_AVLL

t_PLPH

t_PLIV

t_LLPL

PSEN

t_PXIZ

t_PLAZ

t_PXIX

t_LLAX1

ADDRESS

A0-A7

INSTRUCTION

IN

ADDRESS

A0-A7

PORT 0

PORT 2

t_AVIV1

t_AVIV2

ADDRESS A8-A15

- 66 -

W79E532/W79L532

18.3.4 Data Memory Read Cycle

t_LLDV

ALE

t_WHLH

t_LLWL

PSEN

t_RLRH

t_RLDV

t_LLAX1

t_AVLL

t_AVWL1

RD

t_RHDZ

t_RLAZ

t_RHDX

PORT 0 INSTRUCTION

IN

ADDRESS

A0-A7

DATA

IN

ADDRESS

A0-A7

t_AVDV1

t_AVDV2

PORT 2

ADDRESS A8-A15

18.3.5 Data Memory Write Cycle

ALE

PSEN

WR

t_WHLH

t_LLWL

t_WLWH

t_LLAX2

t_AVLL

t_AVWL1

t_WHQX

t_QVWX

PORT 0

ADDRESS

A0-A7

ADDRESS

A0-A7

INSTRUCTION

DATA OUT

IN

t_AVDV2

PORT 2

ADDRESS A8-A15

Publication Release Date: November 21, 2005

Revision A5

- 67 -

W79E532/W79L532

19. TYPICAL APPLICATION CIRCUITS

Expanded External Program Memory and Crystal

Vcc

3

4

7

2

5

6

10

9

8

7

6

5

4

3

25

24

21

23

2

26

27

1

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A0

A1

A2

A3

A4

A5

A6

A7

A0

A1

A2

A3

A4

A5

A6

A7

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

EA/VP

X1

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

A0

A1

A2

A3

A4

A5

A6

A7

O0

O1

O2

O3

O4

O5

O6

O7

10u

8

9

13

14

17

18

12

15

16

19

CRYSTAL

R

X2

8.2K

A8

A9

RESET

A8

A9

1

11

AD8

AD9

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

OC

G

A10

A11

A12

A13

A14

A15

A10

A11

A12

A13

A14

A15

AD10

AD11

AD12

AD13

AD14

AD15

INT0

INT1

T0

C1

C2

74F373

T1

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

20

22

CE

OE

RD

WR

PSEN

ALE/P

TXD

27512

RXD

Figure A

CRYSTAL

16 MHz

24 MHz

33 MHz

40 MHz

C1

20P

12P

10P

1P

C2

20P

12P

10P

1P

R

-

3.3K

The above table shows the reference values for crystal applications.

Note: C1, C2, R components refer to Figure A.

Expanded External Data Memory and Oscillator

Vcc

3

4

7

2

5

6

10

9

8

7

6

5

4

3

25

24

21

23

2

26

1

11

12

13

15

16

17

18

19

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

A0

A1

A2

A3

A4

A5

A6

A7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

EA/VP

X1

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

I/O0

10u

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

OSCILLATOR

8

9

13

14

17

18

12

15

16

19

X2

8.2K

RESET

1

11

AD8

AD9

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

OC

G

AD10

AD11

AD12

AD13

AD14

INT0

INT1

T0

74F373

T1

22

27

20

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

OE

WE

CS

RD

WR

PSEN

ALE/P

TXD

Vcc

28

VCC

20256

RXD

Figure B

- 68 -

W79E532/W79L532

20. PACKAGE DIMENSIONS

40-pin DIP

Dimension in inches

Dimension in mm

Min. Nom.

Symbol

A

Min. Nom.

Max.

5.334

0.210

0.010

0.254

1

A

0.150

0.016

0.048

0.008

0.155

0.018

0.050

0.010

2.055

0.160

0.022

0.054

0.014

2.070

0.610

3.81

3.937

0.457

1.27

4.064

0.559

1.372

0.356

52.58

15.494

13.97

2.794

2

A

B

c

D

E

e

L

0.406

1.219

0.203

1

0.254

52.20

15.24

13.84

2.54

D

40

21

0.590

0.540

0.090

0.600

0.545

0.100

14.986

13.72

0.550

0.110

1

2.286

3.048

0

0.120

0

0.130

0.140

15

3.302

3.556

15

1

E

a

0.630

0.650

0.670

0.090

16.00

16.51

17.01

2.286

e

S

A

1

20

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

A

2

A

L

Base Plane

A

1

.

Seating Plane

4. Dimension B1 does not include dambar

protrusion/intrusion.

B

e ₁

e

A

5. Controlling dimension: Inches.

6. General appearance spec. should be based on

final visual inspection spec.

a

1

44-pin PLCC

H

D

6

1

44

40

Dimension in inches

Min. Nom.

Dimension in mm

Min. Nom.

Symbol

A

Max.

4.699

7

39

0.185

0.020

0.145

0.026

0.508

1

A

b

c

D

E

e

0.150

0.028

0.018

0.010

0.653

3.683

0.66

3.81

3.937

0.813

0.559

0.356

16.71

0.155

0.032

0.022

0.014

0.658

2

0.711

1

0.406

0.203

16.46

0.016

0.008

0.648

0.457

0.254

H _E

G

E

16.59

0.050

BSC

1.27

BSC

0.590

0.680

0.090

14.99

17.27

2.296

15.49

17.53

2.54

16.00

17.78

2.794

0.10

17

29

D

E

D

0.610

0.690

0.100

0.630

0.700

0.110

0.004

G

H

L

y

18

28

c

E

L

Notes:

A

2

A

1. Dimension D & E do not include interlead

flash.

2. Dimension b1 does not include dambar

protrusion/intrusion.

θ

e

b

1

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

1

y

Seating Plane

G

D

Publication Release Date: November 21, 2005

Revision A5

- 69 -

W79E532/W79L532

44-pin QFP

H _D

D

Dimension in inch

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

34

44

---

0.5

0.002

0.01

0.02

0.25

2.05

0.05

1.90

0.25

A

b

1

0.081 0.087

2.20

0.45

0.254

0.075

0.01

2

33

1

0.014

0.006

0.394

0.031

0.018

0.010

0.398

0.036

0.530

0.35

0.101 0.152

0.004

0.390

c

10.00

0.80

9.9

10.1

0.952

13.45

0.95

1.905

0.08

7

D

E

e

0.390

0.025

E

HE

0.635

12.95

0.65

0.510 0.520

13.2

0.8

H

L

D

0.520 0.530

0.025 0.031

0.510

E

11

0.037

0.051 0.063 0.075 1.295

0.003

1.6

L

y

1

12

22

e

b

0

7

0

θ

Notes:

1. Dimension D & E do not include interlead

flash.

c

2. Dimension b does not include dambar

protrusion/intrusion.

3. Controlling dimension: Millimeter

4. General appearance spec. should be based

on final visual inspection spec.

A

2

1

A

θ

L

See Detail F

y

Seating Plane

L

1

Detail F

- 70 -

W79E532/W79L532

21. APPLICATION NOTE

In-system Programming Software Examples

This application note illustrates the in-system programmability of the Winbond W79E(L)532 Flash

EPROM microcontroller. In this example, microcontroller will boot from 64 KB APFlash bank and

waiting for a key to enter in-system programming mode for re-programming the contents of 64 KB

APFlash. While entering in-system programming mode, microcontroller executes the loader program

in 4KB LDFlash bank. The loader program erases the 64 KB APFlash then reads the new code data

from external SRAM buffer (or through other interfaces) to update the 64KB APFlash.

If the customer uses the reboot mode to update his program, please enable this b3 or b4 of security

bits from the writer. Please refer security bits for detail descrption

EXAMPLE 1:

;*******************************************************************************************************************

;* Example of 64K APFlash program: Program will scan the P1.0. if P1.0 = 0, enters in-system

;* programming mode for updating the content of APFlash code else executes the current ROM code.

;* XTAL = 24 MHz

;*******************************************************************************************************************

.chip 8052

.RAMCHK OFF

.symbols

CHPCON

TA

SFRAL

SFRAH

SFRFD

SFRCN

EQU

9FH

C7H

ACH

ADH

AEH

AFH

ORG

0H

LJMP 100H

; JUMP TO MAIN PROGRAM

;************************************************************************

;* TIMER0 SERVICE VECTOR ORG = 000BH

;************************************************************************

ORG 00BH

CLR TR0

MOV TL0,R6

MOV TH0,R7

RETI

; TR0 = 0, STOP TIMER0

;************************************************************************

;* 64K APFlash MAIN PROGRAM

;************************************************************************

ORG

100H

MAIN_64K:

MOV A,P1

; SCAN P1.0

ANL A,#01H

CJNE A,#01H,PROGRAM_64K

JMP NORMAL_MODE

; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE

Publication Release Date: November 21, 2005

- 71 -

Revision A5

W79E532/W79L532

PROGRAM_64:

MOV TA, #AAH

; CHPCON register is written protect by TA register.

MOV TA, #55H

MOV CHPCON, #03H

MOV SFRCN, #0H

; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE

MOV TCON, #00H

MOV IP, #00H

; TR = 0 TIMER0 STOP

; IP = 00H

MOV IE, #82H

; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE

MOV R6, #F0H

MOV R7, #FFH

MOV TL0, R6

; TL0 = F0H

; TH0 = FFH

MOV TH0, R7

MOV TMOD, #01H

MOV TCON, #10H

MOV PCON, #01H

; TMOD = 01H, SET TIMER0 A 16-BIT TIMER

; TCON = 10H, TR0 = 1,GO

; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM PROGRAMMING

;************** ******************************************************************

;* Normal mode 64KB APFlash program: depending user's application

;********************************************************************************

NORMAL_MODE:

.

; User's application program

.

EXAMPLE 2:

;***************************************************************************************************************************** ;*

Example of 4KB LDFlash program: This loader program will erase the 64KB APFlash first, then reads the new ;*

code from external SRAM and program them into 64KB APFlash bank. XTAL = 24 MHz

;*****************************************************************************************************************************

.chip 8052

.RAMCHK OFF

.symbols

CHPCON

TA

SFRAL

SFRAH

SFRFD

SFRCN

EQU

9FH

C7H

ACH

ADH

AEH

AFH

ORG 000H

LJMP 100H

; JUMP TO MAIN PROGRAM

;************************************************************************

;* 1. TIMER0 SERVICE VECTOR ORG = 0BH

;************************************************************************

ORG 000BH

CLR TR0

MOV TL0, R6

MOV TH0, R7

RETI

; TR0 = 0, STOP TIMER0

- 72 -

W79E532/W79L532

;************************************************************************

;* 4KB LDFlash MAIN PROGRAM

;************************************************************************

ORG 100H

MAIN_4K:

MOV TA,#AAH

MOV TA,#55H

MOV CHPCON,#03H

MOV SFRCN,#0H

MOV TCON,#00H

MOV TMOD,#01H

MOV IP,#00H

; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.

; TCON = 00H, TR = 0 TIMER0 STOP

; TMOD = 01H, SET TIMER0 A 16BIT TIMER

; IP = 00H

MOV IE,#82H

; IE = 82H, TIMER0 INTERRUPT ENABLED

MOV R6,#F0H

MOV R7,#FFH

MOV TL0,R6

MOV TH0,R7

MOV TCON,#10H

MOV PCON,#01H

; TCON = 10H, TR0 = 1, GO

; ENTER IDLE MODE

UPDATE_64K:

MOV TCON,#00H

MOV IP,#00H

; TCON = 00H , TR = 0 TIM0 STOP

; IP = 00H

MOV IE,#82H

MOV TMOD,#01H

MOV R6,#D0H

; IE = 82H, TIMER0 INTERRUPT ENABLED

; TMOD = 01H, MODE1

; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 ms

DEPENDING ON USER'S SYSTEM CLOCK RATE.

MOV R7,#8AH

MOV TL0,R6

MOV TH0,R7

ERASE_P_4K:

MOV SFRCN,#22H

; SFRCN = 22H, ERASE 64K APFlash0

; SFRCN = A2H, ERASE 64K APFlash1

; TCON = 10H, TR0 = 1,GO

MOV TCON,#10H

MOV PCON,#01H

; ENTER IDLE MODE (FOR ERASE OPERATION)

;*********************************************************************

;* BLANK CHECK

;*********************************************************************

MOV SFRCN,#0H

; SFRCN = 00H, READ 64KB APFlash0

; SFRCN = 80H, READ 64KB APFlash1

; START ADDRESS = 0H

MOV SFRAH,#0H

MOV SFRAL,#0H

MOV R6,#FDH

MOV R7,#FFH

MOV TL0,R6

; SET TIMER FOR READ OPERATION, ABOUT 1.5 μS.

MOV TH0,R7

BLANK_CHECK_LOOP:

SETB TR0

MOV PCON,#01H

MOV A,SFRFD

; ENABLE TIMER 0

; ENTER IDLE MODE

; READ ONE BYTE

CJNE A,#FFH,BLANK_CHECK_ERROR

INC SFRAL

; NEXT ADDRESS

Publication Release Date: November 21, 2005

Revision A5

- 73 -

W79E532/W79L532

MOV A,SFRAL

JNZ BLANK_CHECK_LOOP

INC SFRAH

MOV A,SFRAH

CJNE A,#0H,BLANK_CHECK_LOOP ; END ADDRESS = FFFFH

JMP PROGRAM_64KROM

BLANK_CHECK_ERROR:

JMP $

;*******************************************************************************

;* RE-PROGRAMMING 64KB APFlash BANK

;*******************************************************************************

PROGRAM_64KROM:

MOV R2,#00H

MOV R1,#00H

; TARGET LOW BYTE ADDRESS

; TARGET HIGH BYTE ADDRESS

MOV DPTR,#0H

MOV SFRAH,R1

MOV SFRCN,#21H

; SFRAH, TARGET HIGH ADDRESS

; SFRCN = 21H, PROGRAM 64K APFLASH0

; SFRCN = A1H, PROGRAM 64K APFLASH1

; SET TIMER FOR PROGRAMMING, ABOUT 50 μS.

MOV R6,#9CH

MOV R7,#FFH

MOV TL0,R6

MOV TH0,R7

PROG_D_64K:

MOV SFRAL,R2

; SFRAL = LOW BYTE ADDRESS

CALL GET_BYTE_FROM_PC_TO_ACC

; THIS PROGRAM IS BASED ON USER’S CIRCUIT.

; SAVE DATA INTO SRAM TO VERIFY CODE.

; SFRFD = DATA IN

; TCON = 10H, TR0 = 1,GO

; ENTER IDLE MODE (PRORGAMMING)

MOV @DPTR,A

MOV SFRFD,A

MOV TCON,#10H

MOV PCON,#01H

INC DPTR

INC R2

CJNE R2,#0H,PROG_D_64K

INC R1

MOV SFRAH,R1

CJNE R1,#0H,PROG_D_64K

;*****************************************************************************

; * VERIFY 64KB APFLASH BANK

;*****************************************************************************

MOV R4,#03H

MOV R6,#FDH

MOV R7,#FFH

MOV TL0,R6

; ERROR COUNTER

; SET TIMER FOR READ VERIFY, ABOUT 1.5 μS.

MOV TH0,R7

MOV DPTR,#0H

MOV R2,#0H

; The start address of sample code

; Target low byte address

MOV R1,#0H

; Target high byte address

MOV SFRAH,R1

MOV SFRCN,#00H

; SFRAH, Target high address

; SFRCN = 00H, Read APFlash0

; SFRCN = 80H , Read APFlash1

READ_VERIFY_64K:

- 74 -

W79E532/W79L532

MOV SFRAL,R2

MOV TCON,#10H

MOV PCON,#01H

INC R2

; SFRAL = LOW ADDRESS

; TCON = 10H, TR0 = 1,GO

MOVX A,@DPTR

INC DPTR

CJNE A,SFRFD,ERROR_64K

CJNE R2,#0H,READ_VERIFY_64K

INC R1

MOV SFRAH,R1

CJNE R1,#0H,READ_VERIFY_64K

;******************************************************************************

;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU

;******************************************************************************

MOV TA,#AAH

MOV TA,#55H

MOV CHPCON,#83H

; SOFTWARE RESET. CPU will restart from APFlash0

ERROR_64K:

DJNZ R4,UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.

; IN-SYST PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.

.

Publication Release Date: November 21, 2005

Revision A5

- 75 -

W79E532/W79L532

22. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

A1

June 24, 2004

-

Initial Issued

6

Modify block diagram.

A2

A3

A4

Sep 14, 2004

April 19, 2005

Aug 11, 2005

8

Remove economy mode.

Modify Figure A.

68

76

Add Important Notice

2, 5, 12 Add Port 0 pull-up resisters information

62 Remove encrypt function of Security bits B2 description

2, 3 Add Lead Free package.

-

Add wide voltage device (W79L532)

Add device list.

3

42

44

53

56

61

68

Revise the diagram of timer2 baud rate generator mode.

Revise the diagram of PWM

November 21,

2005

A5

Revise the diagram of serial port mode 2.

Modify the explanation to the TA protection example.

Modify DC characteristic.

Modify application circuit

- 76 -

W79E532/W79L532

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control

instruments, airplane or spaceship instruments, transportation instruments, traffic signal

instruments, combustion control instruments, or for other applications intended to support or

sustain life. Further more, Winbond products are not intended for applications wherein failure

of Winbond products could result or lead to a situation wherein personal injury, death or

severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Winbond for any damages resulting from such improper

use or sales.

Publication Release Date: November 21, 2005

- 77 -

Revision A5


型号：	W79E532A40FL
厂家：	WINBOND
描述：	8-BIT MICROCONTROLLER 8位微控制器微控制器
文件：	总77页 (文件大小：506K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W79E532A40FL [WINBOND]

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