W81282F [WINBOND]

USB Keyboard Controller with 4 Ports Hub; USB键盘控制器具有4端口集线器
W81282F
型号: W81282F
厂家: WINBOND    WINBOND
描述:

USB Keyboard Controller with 4 Ports Hub
USB键盘控制器具有4端口集线器

控制器
文件: 总18页 (文件大小:176K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
W81282F  
USB Keyboard Controller  
with  
4 Ports Hub  
W81282F Data Sheet Revision History  
Pages  
Dates  
Version Version  
on Web  
Main Contents  
1
2
3
4
5
6
7
8
9
10  
n.a.  
08/27/99  
0.50  
n.a.  
First published.  
Please note that all data and specifications are subject to change without notice. All  
the trade marks of products and companies mentioned in this data sheet belong to  
their respective owners.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or  
systems where malfunction of these products can reasonably be expected to result  
in personal injury. Winbond customers using or selling these products for use in such  
applications do so at their own risk and agree to fully indemnify Winbond for any  
damages resulting from such improper use or sales.  
W81282F  
Preliminary  
TABLE OF CONTENTS  
1.  
2.  
GENERAL DESCRIPTION .................................................................................................................1  
APPLICATION BLOCK DIAGRAM....................................................................................................1  
FEATURES ............................................................................................................................................2  
PIN CONFIGURATION .......................................................................................................................3  
PIN DESCRIPTION .............................................................................................................................4  
ABSOLUTE MAXIMUM RATINGS ....................................................................................................8  
ELECTRICAL CHARACTERISTICS..................................................................................................9  
TYPICAL APPLICATION..................................................................................................................11  
HOW TO READ THE TOP MARKING.............................................................................................13  
PACKAGE DIMENSIONS...............................................................................................................14  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
10.  
Publication Release Date: Aug. 1999  
- 1 -  
Revision 0.5  
W81282F  
USB HUB CONTROLLER  
1.  
GENERAL DESCRIPTION  
The W81282F is a highly integrated USB keyboard with 4 port hub controller chip. The W81282F has a  
built-in 21X8 default keyboard matrix, so that it can be directly connected to keyboard with multi-media  
function matrix. The keyboard matrix, vendor ID, and device ID can be easily customized from an  
optional EEPROM or modify firmware to meet any customers' requirement. The 4 USB down-stream  
port can be used to connect various USB peripheral devices, such as printer, modem, speaker,  
camera, mice, and joystick, to system without any external glue logics. The W81282F use 12MHz  
clock input with internal PLL to eliminate EMI effect. The W81282F also built-in ESD/EFT protection  
circuit so it can pass ESD/EFT test without any external glue logics.  
2.  
APPLICATION BLOCK DIAGRAM  
4 PORT USB DOWNLINK  
(Optional)  
ID, Matrix Loadable  
EEPROM  
HOST  
KB MATRIX  
W81282F  
Volume Control  
Publication Release Date: Aug. 1999  
- 1 -  
Revision 0.71  
W81282F  
PRELIMINARY  
3.  
FEATURES  
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
·
Full compliance with USB spec Rev 1.1 and HID Class Definition Rev 1.0  
Embedded microprocessor--8052 ( 6K ROM + 256 Byte RAM)  
Support auto-detected two power source mode between bus power mode and self power mode.  
12-Mhz crystal/oscillator input to lower EMI  
Support Suspend and Resume operation  
Support ACPI features  
Four downstream ports with per port over-current protection  
Single 5V supplied with embedded 5V-3.3V regulator  
Provides the external pull-up resistor control for the up-stream connection.  
Per-port/Global power control optional  
Built-in ESD/EFT protection circuit  
Support 21 X 8 keyboard matrix  
Support consumer control function for multi-media  
Support optional EEPROM for vendor ID, device ID, and KB matrix down load  
Support encoder input for audio volume control  
Provide the external pull-up resistor control for the up-stream connect  
100-pin PQFP  
5V CMOS device  
Publication Release Date: Aug. 1999  
- 2 -  
Revision 0.5  
W81282F  
PRELIMINARY  
4.  
PIN CONFIGURATION  
8 7 7  
0 9 8  
7
7
7 7  
5 4  
7
7 7  
2 1  
7
6 6 6 6 6 6 6 6 6 6 5 5 5 5 5 5 5 5  
5
7
6
3
0
9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1  
DP4  
DM4  
N.C.  
N.C.  
DP3  
DM3  
N.C.  
GND3V  
GND3V  
DP2  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
OVRI4#  
SO03(P04)  
SO18  
SO02(P05)  
SO01(P06)  
VDD  
SO00(P07)  
N.C.  
XTAL2  
XTAL1  
GND  
N.C.  
N.C.  
LEDEN1#  
PLLE  
LEDEN2#  
RB  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
W81282F  
DM2  
N.C.  
N.C.  
DP1  
DM1  
GND3V  
GND3V  
N.C.  
DP0  
DM0  
LEDEN3#  
RA  
LEDEN4#  
1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2  
2
2 3  
9 0  
1
2 3 4 5 6 7 8 9  
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7  
8
Publication Release Date: Aug. 1999  
- 3 -  
Revision 0.5  
W81282F  
PRELIMINARY  
5.  
PIN DESCRIPTION  
Pin  
Number  
Pin Name  
I/O Type  
Pin Function  
Pull  
Up/  
Down  
3.3V Regulator Output. Supplying voltage for all transceivers  
Analog power.  
1
2
3
4
5
VDD3V  
VDDA  
Power1  
Power1  
IOUD2  
Power0  
IUD2T  
-
-
Port 2.6 and function of Scan Out line 14.  
Analog ground.  
SO14 (P26)  
GNDA  
U
-
Input of upstream power status. On self-power mode, connection  
should be controlled by VBUS status.  
VBUS  
-
Port 2.7 and function of Scan Out line 15.  
Keyboard NumLock LED driver. To drive LED directly.  
Port 1.0 and function of Scan In line 0.  
6
7
SO15 (P27)  
LED0#  
IOUD2  
IOU2P  
IOUD2  
IOU2P  
IOUD2  
IOU2P  
IOUD2  
IOU2P  
IOUD2  
Power1  
IOUD2  
IOUD2  
IUD2T  
IOUD2  
O2  
U
O
U
O
U
O
U
O
U
-
8
SI0 (P10)  
LED1#  
Keyboard CapLock LED driver. To drive LED directly.  
Port 1.1 and function of Scan In line 1.  
9
10  
11  
12  
13  
14  
15,16  
17  
18  
19  
20  
21  
22  
23  
24  
SI1 (P11)  
LED2#  
Keboard ScrolLock LED driver. To drive LED directly  
Port 1.2 and function of Scan In line 2.  
SI2 (P12)  
LEDOVR#  
SI3 (P13)  
VDD  
Flag of any downstream port1 over-current. To drive LED directly  
Port 1.3 and function of Scan In line 3.  
Digital supply voltage.  
Port 1.4 and function of Scan In line 4.  
SI4 (P14)  
N.C.  
U
U
-
No connection. This pin should be floated.  
Master reset input. Active high.  
RESET  
INPUT_P  
SO16  
A programmable port and reverse for input application.  
This pin is function of Scan Out line 16.  
U
-
Port 3.3 and reverse for input or output application.  
Port 3.2. This pin is dedicated for internal use.  
P33  
IOUD2  
IOUD2  
IOUD2  
U
U
U
XINT# (P32)  
Port 3.1 and function of serial data line interfacing with external  
EEPROM. If no serial EEPROM present, this pin is used to scan  
ID selection and named IDSEL1  
EESDA/IDSEL1  
(P31)  
Port 1.5 and function of Scan In line 5.  
Port 1.6 and function of Scan In line 6.  
Port 1.7 and function of Scan In line 7.  
25  
26  
27  
SI5 (P15)  
IOUD2  
IOUD2  
IOUD2  
U
U
U
SI6 (P16)  
SI7 (P17)  
Publication Release Date: Aug. 1999  
- 4 -  
Revision 0.5  
W81282F  
PRELIMINARY  
Buspower/Selfpower control setting. This pin should be floated or  
tied to VDD.  
28  
BUSPWR#  
IUD2  
D
This pin is function of Scan Out line 17.  
29  
30  
SO17  
IOU2P  
IUD2  
O
U
Ganged/Individual downstream power switch control setting.  
Default is Individual mode.  
GANGED#  
Downstream port4 LED. Active low when port4 enable.  
31  
32  
33  
34  
35  
36  
LEDEN4#  
RA  
IOU2P  
IUD2  
O
U
O
U
O
U
This pin is a Rotation A input for consumer HID application.  
Downstream port3 LED. Active low when port3 enable.  
This pin is a Rotation B input for consumer HID application.  
Downstream port2 LED. Active low when port2 enable.  
LEDEN3#  
RB  
IOU2P  
IUD2  
LEDEN2#  
PLLE  
IOU2P  
IUD2  
PLL clock generator enable/disable control. It should be tied to  
VDD. (PLLE=1, clock=12MHz ; PLLE=0,clock=48MHz)  
Downstream port1 LED. Active low when port1 enable.  
No connection. This pin should be floated.  
No connection. This pin should be floated.  
Digital ground  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
LEDEN1#  
N.C.  
IOU2P  
IUD2  
O
U
U
-
N.C.  
IUD2  
GND  
Power0  
OSCM  
OSCM  
IUD2  
Clock In. (12MHz when PLLE=1, 48MHz when PLLE=0)  
Clock Out.  
XTAL1  
-
XTAL2  
-
No connection. This pin should be floated.  
Port 0.7 and function of Scan Out line 0.  
Digital supply voltage.  
N.C.  
D
U
-
SO00 (P07)  
VDD  
IOUD2  
Power1  
IOUD2  
IOUD2  
O2  
Port 0.6 and function of Scan Out line 1.  
Port 0.5 and function of Scan Out line 2.  
This pin is function of Scan Out line 18.  
Port 0.4 and function of Scan Out line 3.  
Downstream port4 over-current status input. Active low.  
Port 0.3 and function of Scan Out line 4.  
Downstream port4 power control. Active low.  
Downstream port3 over-current status input. Active low.  
Port 0.2 and function of Scan Out line 5.  
Downstream port3 power control. Active low.  
Port 0.1 and function of Scan Out line 6.  
Up_stream port LED. Active low when up_stream port enable.  
Port 0.0 and function of Scan Out line 7.  
SO01 (P06)  
SO02 (P05)  
SO18  
U
U
-
SO03 (P04)  
OVRI4#  
SO04 (P03)  
UPWEN4#  
OVRI3#  
SO05 (P02)  
UPWEN3#  
SO06 (P01)  
LEDEN0#  
SO07 (P00)  
IOUD2  
IUD2T  
IOUD2  
O2  
U
-
U
-
IUD2T  
IOUD2  
O2  
-
U
-
IOUD2  
IOU2P  
IOUD2  
U
O
U
Publication Release Date: Aug. 1999  
- 5 -  
Revision 0.5  
W81282F  
PRELIMINARY  
Port 3.7.This pin is dedicated for internal use.  
59  
XRD# (P37)  
IOUD2  
U
Downstream port2 over-current status input. Active low.  
Port 3.6.This pin is dedicated for internal use.  
60  
OVRI2#  
IUD2T  
IOUD2  
-
61  
XWR# (P36)  
U
Port 3.5 and reverse for input or output application.  
Downstream port2 power control. Active low.  
Port 3.4 and function of Scan Out line 20.  
This pin is function of Scan Out line 19.  
Digital ground.  
62  
63  
P35  
IOUD2  
O2  
U
-
UPWEN2#  
SO20 (P34)  
SO19  
64  
IOUD2  
O2  
U
-
65  
66,67  
68  
GND  
Power0  
IOUD2  
IOUD2  
IUD2T  
IOUD2  
O2  
-
No connection. This pin should be floated.  
Port 2.0 and function of Scan Out line 8.  
Downstream port1 over-current status input. Active low.  
Port 2.1 and function of Scan Out line 9.  
Downstream port1 power control. Active low.  
Port 2.2 and function of Scan Out line 10.  
N.C.  
U
U
-
69  
SO08 (P20)  
OVRI1#  
SO09 (P21)  
UPWEN1#  
SO10 (P22)  
FWKP5#  
70  
71  
U
-
72  
73  
IOUD2  
IUD2  
U
D
Embedded function wake-up input.  
Can be used for Wake-up hot key.  
Port 2.3 and function of Scan Out line 11.  
74  
75  
SO11 (P23)  
IOUD2  
IOUD2  
U
U
This pin is Port 3.0 and function of serial clock line interfacing  
with external EEPROM. If no serial EEPROM present, this  
pin is used to scan ID selection and named IDSEL0.  
76  
EECLK/IDSEL0  
(P30)  
Port 2.4 and function of Scan Out line 12.  
Port 2.5 and function of Scan Out line 13.  
Ground of port3 and port4 transceivers.  
USB D+ for downstream port4.  
USB D- for downstream port4.  
No connection.  
77  
78  
SO12 (P24)  
IOUD2  
IOUD2  
Power0  
AIO  
AIO  
-
U
U
-
SO13 (P25)  
GND3V  
DP4  
79,80  
81  
-
82  
DM4  
-
83,84  
85  
N.C.  
USB D+ for downstream port3.  
USB D- for downstream port3.  
No connection.  
DP3  
AIO  
AIO  
-
-
-
86  
DM3  
87  
N.C.  
Ground of port1 and port2 transceivers.  
USB D+ for downstream port2.  
USB D- for downstream port2.  
88,89  
90  
GND3V  
DP2  
Power0  
AIO  
AIO  
-
-
-
91  
DM2  
Publication Release Date: Aug. 1999  
- 6 -  
Revision 0.5  
W81282F  
PRELIMINARY  
No connection.  
92,93  
94  
N.C.  
DP1  
-
AIO  
AIO  
Power0  
-
USB D+ for downstream port1.  
USB D- for downstream port1.  
Ground of port0 transceivers.  
No connection.  
-
-
-
95  
DM1  
GND3V  
N.C.  
96,97  
98  
USB D+ for upstream port0.  
USB D- for upstream port0.  
99  
DP0  
AIO  
AIO  
-
-
100  
DM0  
Publication Release Date: Aug. 1999  
- 7 -  
Revision 0.5  
W81282F  
PRELIMINARY  
6.  
ABSOLUTE MAXIMUM RATINGS  
PARAMETER  
LIMIT  
Supply Voltage (Vcc to Vss)  
Analog Input Voltage  
5.5V  
Vss-0.5V to Vcc+0.5V  
Vss-0.5V to Vcc+0.5V  
TBD  
Digital Input Voltage  
Power Dissipation  
Ambient Operating Temperature  
Lead Temperature (Soldering, 10 sec)  
0oC to 70oC  
250oC  
Publication Release Date: Aug. 1999  
- 8 -  
Revision 0.5  
W81282F  
PRELIMINARY  
7.  
ELECTRICAL CHARACTERISTICS  
Operating conditions: VCC = 5V +/-5%, Ta=0o to 70oC  
PARAMETER Symbol  
VCC Supply Current  
Conditions  
Min Max  
Unit  
Icc  
TBD  
mA  
V
Logic Output High  
VOH  
VOL  
Io>24ma  
2.5  
VCC  
0.4  
Logic Output Low  
Io>6ma  
Ta=70oC  
Note 8  
V
Logic Input Leakage Current  
USB CHARACTERISTICS  
10  
uA  
Leakage Current:  
Hi-Z State Output Leakage  
Input Levels:  
ILO  
V< V IN <3.3 V  
|(D+)-(D-)|  
-10  
+10  
uA  
Differential Input Sensitivity  
Single Ended Signal “ 0”  
Differential Common Mode Range  
Output Levels:  
VDI  
0.2  
0.8  
0.8  
V
V
VSE0  
VCM  
2.0  
2.5  
Includes VDI range  
Driver Output Low  
VOLU  
VOHU  
VCRS  
0.3  
3.6  
2.0  
V
V
V
RL of 1.5 kW to 3.6 V  
RL of 15 kW to GND  
Driver Output High  
2.8  
1.3  
Output Signal Crossover Voltage  
Capacitance:  
Transceiver Capacitance  
Full Speed Timings:  
CIN  
Pin to GND  
20  
pF  
Output Rise/Fall Times  
Source Differential Driver Jitter to Next Transition  
/ to Paired Transition  
t R /t F Note 1, 4 (CL= 50 pF)  
4
20  
3.5  
/4  
ns  
ns  
ns  
ns  
ns  
ns  
t DJ1  
/tDJ2  
Note 2, 3  
-3.5  
/-4  
-2  
Differential to EOP transition Skew  
Hub Differential Data Delay(without cable)  
Hub Differential Driver Jitter to Next Transition  
/ to Paired Transition (including cable)  
Data bit width distortion after SOP  
Hub SE0 Delay Relative to t HDD  
Hub EOP Output Width Skew  
t DEOP Note 3  
5
t HDD2 Note 2,3,5  
t HDJ1 Note 2,3,5  
44  
3
-3  
/
t
/ -1  
-5  
/1  
HDJ2  
t SOP Note 3,5  
t EOPD Note 3,5  
t HESK Note 3,5  
5
ns  
ns  
ns  
0
15  
15  
-15  
Low Speed Timings:  
Output Rise/Fall Times  
t R /t F Note 1, 4 (CL= 50 pF) 75  
300  
ns  
Publication Release Date: Aug. 1999  
- 9 -  
Revision 0.5  
W81282F  
PRELIMINARY  
7. ELECTRICAL CHARACTERISTICS, continued  
PARAMETER  
Symbol  
t DJ1  
Conditions  
Note 2, 3  
Min Max  
Unit  
ns  
Source Differential Driver Jitter to Next Transition  
/ to Paired Transition  
-25  
/-14  
-40  
25  
/tDJ2  
/14  
100  
300  
ns  
Differential to EOP transition Skew  
t DEOP Note 3  
ns  
Hub Differential Data Delay(without cable)  
Hub Differential Driver Jitter to Next Transition  
/ to Paired Transition (including cable)  
t HDD2 Note 2,3,5  
t HDJ1 Note 2,3,5  
ns  
-45 45  
ns  
/
t
/ -45 /-45  
HDJ2  
Data bit width distortion after SOP  
Hub SE0 Delay Relative to t HDD  
Hub EOP Output Width Skew  
t SOP Note 3,5  
t EOPD Note 3,5  
t HESK Note 3,5  
-60  
0
60  
ns  
ns  
ns  
200  
-300 300  
Note 1: Measured from 10% to 90% of the data signal.  
Note 2: Timing difference between the differential signals.  
Note 3: Measured at crossover point of differential data signals.  
Note 4: The rising and falling edges should be smoothly transiting(monotonic)  
Note 5: Full Speed timing have a 1.5 kW pull-up to 2.8 V on the D+ (DP) data line.  
Note 6: Low Speed timing have a 1.5 kW pull-up to 2.8 V on the D- (DM) data line.  
Note 7: The maximum load specification is the maximum effective capacitive load allowed that meets  
the target hub VBUS droop of 330 mV.  
Note 8: All other USB Electrical Characteristics refer to USB spec Rev 1.1 7.3.2 and 7.3.3.  
Publication Release Date: Aug. 1999  
- 10 -  
Revision 0.5  
W81282F  
PRELIMINARY  
8.  
TYPICAL APPLICATION  
Publication Release Date: Aug. 1999  
- 11 -  
Revision 0.5  
W81282F  
PRELIMINARY  
W81282F Reference Schematic  
VCC  
CD-  
CD+  
R15  
R16  
30  
30  
C2  
10u  
VCC  
+
C11  
15p  
C10  
15p  
U2  
1
2
3
4
5
6
7
8
9
100  
99  
98  
97  
96  
95  
94  
93  
92  
91  
90  
89  
88  
87  
86  
85  
84  
83  
82  
81  
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
VDD3V  
VDDA  
SO14/P26  
GNDA  
VBUS  
D-  
D+  
NC  
GND3V  
GND3V  
D1-  
D1+  
NC  
NC  
D2-  
D2+  
GND3V  
GND3V  
NC  
D3-  
D3+  
NC  
NC  
D4-  
D4+  
SO14  
R9  
CD1-  
CD1+  
R17  
R18  
30  
30  
10K  
SO15  
C13  
15p  
SO15/P27  
LEDNUM  
SI0  
LEDCAP  
SI1  
LEDSCR  
SI2  
C12  
15p  
LED0#  
SI0/P10  
LED1#  
SI1/P11  
LED2#  
SI2/P12  
LEDOVR#  
SI3/P13  
VDD  
Place R15 ~ R20 & C10 ~ C15  
as close as W81282F  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
CD2-  
CD2+  
R19  
R20  
30  
30  
LEDOVC  
SI3  
C15  
15p  
C14  
15p  
VDD  
SI4  
VCC  
SI4/P14  
PSEN#  
RESET  
INPUT_P  
SO16  
RESET  
SO16  
GND3V  
GND3V  
SO13/P25  
SO12/P24  
IDSEL0/EESCL  
SO11/P23  
FWKP5#  
SO10/P22  
PWEN1#  
SO09/P21  
OCP1#  
SO08/P20  
XALE  
R28 R29 R30 R31  
15K 15K 15K 15K  
R22  
7.5K  
PSDA/P33  
P32/XINT#  
IDSEL1/EESDA  
SI5/P15  
SI6/P16  
SI7/P17  
BUSPWR#  
SO17  
GANGED#  
LEDEN4#  
VOLUME_A  
LEDEN3#  
VOLUME_B  
LEDEN2#  
PLLE  
SO13  
SO12  
EESCL  
USB1  
EESDA  
SI5  
SI6  
L6  
FB  
1
2
3
4
SO11  
CD-  
CD+  
SI7  
SO10  
PWEN1  
SO09  
OCP1  
SO08  
SO17  
GANGED  
C31 47pF  
C30  
+
CT1  
10u  
L5  
VOLA  
C16  
0.1u  
47pF  
FB  
VOLB  
GND  
GND  
SO19  
LEDEN2  
PLLE  
LEDEN1  
SO19  
SO20  
PWEN2  
UP-PORT  
LEDEN1#  
XCVREN  
UC51E  
GND  
XTAL1  
SO20/P34  
PWEN2#  
PSCLK/P35  
XWR#/P36  
OCP2#  
XRD#/P37  
SO07/P00  
LEDEN0#  
SO06/P01  
PWEN3#  
SO05/P02  
OCP3#  
PWEN4#  
SO04/P03  
X1  
X2  
OCP2  
SO07  
LEDEN0  
SO06  
XTAL2  
C8  
ROMEN  
SO00/P07  
VDD  
SO01/P06  
SO02/P05  
SO18  
SO00  
SO01  
SO02  
SO18  
SO03  
OCP4  
CD1-  
CD1+  
USB2  
USB(A)  
0.1u  
SO05  
OCP3  
L1  
FB(30ohm)  
FB(30ohm)  
1
2
3
4
R11  
R12  
SO03/P04  
OCP4#  
SO04  
15K  
15K  
L2  
W81282F-100QFP  
C26  
47pF  
C27  
47pF  
C5  
VCC  
120u  
U4  
C7  
0.1u  
C6  
PWEN1  
FL1  
FL2  
PWEN2  
1
2
3
4
8
7
6
5
PW1  
PW2  
C/A  
F/A  
F/B  
C/B  
O/A  
IN  
GND  
O/B  
C9  
120u  
AIC1526-0  
VCC  
USB3  
USB(A)  
0.1u  
FB(30ohm)  
FB(30ohm)  
L3  
L4  
1
2
3
4
R13  
R14  
15K  
R32  
100K  
R33  
100K  
R34  
100K  
R35  
100K  
R36  
100K  
15K  
CD2-  
CD2+  
C28  
47pF  
C29  
47pF  
SO16  
SO18  
SO19  
GANGED  
PLLE  
VCC  
Option  
SI0  
SI1  
SI2  
SI3  
SI4  
SI5  
SI6  
SI7  
SI0  
LEDNUM  
LEDCAP  
LEDSCR  
SI1  
SI2  
SI3  
SI4  
SI5  
SI6  
SI7  
R7  
D1  
D2  
D3  
LEDEN0  
LEDEN1  
LEDEN2  
EN0  
EN1  
EN2  
470  
R6  
R5  
EESCL  
470  
470  
JP1  
JUMPER  
JP2  
JP3  
JUMPER  
SO00  
SO01  
SO02  
SO03  
SO04  
SO05  
SO06  
SO07  
SO08  
SO09  
SO10  
SO11  
SO12  
SO13  
SO14  
SO15  
SO16  
SO17  
SO18  
SO19  
SO20  
SO00  
SO01  
SO02  
SO03  
SO04  
SO05  
SO06  
SO07  
SO08  
SO09  
SO10  
SO11  
SO12  
SO13  
SO14  
SO15  
SO16  
SO17  
SO18  
SO19  
SO20  
JUMPER  
JP5  
R4  
D7  
LEDOVC  
JP4  
JP6  
OVC  
470  
JUMPER  
JUMPER  
JUMPER  
EESDA  
R1  
D4  
D5  
D6  
LEDNUM  
LEDCAP  
LEDSCR  
NUMLK  
R2  
470  
470  
470  
VCC  
CAPLK  
R3  
SCRLK  
X1  
X2  
+
C1  
10u  
VCC  
Y1  
RESET  
R23  
R24  
R25  
R26  
12M  
C4  
30p  
C3  
30p  
10K  
10K  
10K  
10K  
R8  
8.2K  
OCP3  
OCP4  
R21  
10K  
R27  
OCP1  
OCP2  
FL1  
FL2  
10K  
Option  
VCC  
VCC  
C18  
C17  
0.1u  
U1  
0.1u  
1
2
3
4
8
7
6
5
A0  
A1  
A2  
VCC  
RC  
SCL  
SDA  
inbond  
EESCL  
EESDA  
WINBOND ELECTRONICS CORP_  
VSS  
Title  
Size  
W81282F Reference Schematic  
24LC04B  
Document Number  
282DEMO1.SCH  
Thursday, August 19, 1999 Sheet  
Rev  
1.0  
Date:  
1
of  
1
Publication Release Date: Aug. 1999  
- 12 -  
Revision 0.5  
W81282F  
PRELIMINARY  
9.  
HOW TO READ THE TOP MARKING  
Example: The top marking of W81282F-05  
inbond  
W81282F-05  
732AC27242968  
1st line: Winbond logo  
2nd line: the type number: W81282F-05  
3rd line: the tracking code: 732 A C 2 7242968  
732: packages made in '97, week 19  
A: assembly house ID; A means ASE, S means SPIL ... etc  
C: IC revision; B means version B, C means version C  
2: wafers manufactured in Winbond FAB 2  
7242968: wafer production series lot number  
Publication Release Date: Aug. 1999  
- 13 -  
Revision 0.5  
W81282F  
PRELIMINARY  
10. PACKAGE DIMENSIONS  
(100-pin QFP)  
HD  
D
100  
81  
Dimension in inches Dimension in mm  
Min. Nom. Max. Min. Nom. Max.  
Symbol  
1
80  
0.130  
3.30  
A
0.004  
0.107 0.112 0.117  
0.10  
2.73  
0.25  
0.10  
13.87  
19.87  
0.50  
A 1  
A 2  
2.85  
0.30  
2.97  
0.40  
0.010  
0.004  
0.012 0.016  
0.006  
b
c
D
E
e
HD  
HE  
L
L1  
y
0.15  
0.25  
0.010  
14.00  
20.00  
0.65  
0.546 0.551 0.556  
14.13  
20.13  
0.80  
0.782 0.787  
0.020 0.026  
0.792  
0.032  
0.752  
E
HE  
0.728  
0.964  
0.039  
0.740  
0.976  
18.49 18.80 19.10  
0.988 24.49 24.80 25.10  
0.047 0.055  
1.00  
2.21  
1.20  
2.40  
1.40  
2.62  
0.10  
12  
0.087 0.094 0.103  
0.004  
30  
51  
0
12  
0
q
Notes:  
31  
50  
b
e
1. Dimension D & E do not include interlead  
flash.  
2. Dimension b does not include dambar  
protrusion/intrusion.  
3. Controlling dimension: Millimeters  
4. General appearance spec. should be based  
on final visual inspection spec.  
c
A2  
A1  
A
q
See Detail F  
L
y
Seating Plane  
L1  
Detail F  
Publication Release Date: Aug. 1999  
- 14 -  
Revision 0.5  
W81282F  
PRELIMINARY  
Headquarters  
No. 4, Creation Rd. III  
Science-Based Industrial Park  
Hsinchu, Taiwan  
TEL: 886-35-770066  
Winbond Electronics  
(North America) Corp.  
2730 Orchard Parkway  
San Jose, CA 95134 U.S.A.  
TEL: 1-408-9436666  
Winbond Electronics (H.K.) Ltd.  
Rm. 803, World Trade Square, Tower II  
123 Hoi Bun Rd., Kwun Tong  
Kowloon, Hong Kong  
TEL: 852-27516023-7  
FAX: 852-27552064  
FAX: 886-35-789467  
www: http://www.winbond.com.tw/  
FAX: 1-408-9436668  
Taipei Office  
11F, No. 115, Sec. 3, Min-Sheng East Rd.  
Taipei, Taiwan  
TEL: 886-2-7190505  
FAX: 886-2-7197502  
TLX: 16485 WINTPE  
Please note that all data and specifications are subject to change without notice. All  
the trade marks of products and companies mentioned in this data sheet belong to  
their respective owners.  
Publication Release Date: Aug. 1999  
- 15 -  
Revision 0.5  

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