W83320S [WINBOND]
N-Channel FET Synchronous Buck Regulator Controller; N沟道FET同步降压稳压器控制器
| 型号： | W83320S |
| 厂家： | 
WINBOND |
| 描述： | N-Channel FET Synchronous Buck Regulator Controller |
| 文件： | 总18页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W83320S/W83320G
Winbond
N-Channel FET Synchronous Buck
Regulator Controller
W83320S
W83320G
Publication Release Date: January 10, 2006
- 1 -
Revision 0.51
W83320S/W83320G
W83320S
Data Sheet Revision History
VERSION
PAGES
DATES
VERSION
MAIN CONTENTS
ON WEB
All version before 0.5 are for internal use
only.
1
2
N.A.
N.A.
N.A.
N.A.
0.50
0.51
N.A.
N.A.
Add Pb-free part no :W83320G
Please note that all data and specifications are subject to change without notice. All the trademarks of
products and companies mentioned in this datasheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. Winbond
customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
- 2 -
W83320S/W83320G
Table of Content-
1.
GENERAL DESCRIPTION ......................................................................................................... 4
FEATURES................................................................................................................................. 4
APPLICATIONS.......................................................................................................................... 4
PIN-OUT ..................................................................................................................................... 5
PIN DESCRIPTION..................................................................................................................... 6
INTERNAL BLOCK DIAGRAM ................................................................................................... 7
APPLICATION CIRCUIT............................................................................................................. 9
ELECTRICAL CHARACTERISTICS......................................................................................... 10
TYPICAL PERFORMANCE CHARACTERISTICS................................................................... 11
PACKAGE DIMENSION OUTLINE........................................................................................... 16
ORDERING INSTRUCTION..................................................................................................... 17
HOW TO READ THE TOP MARKING...................................................................................... 17
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Publication Release Date: January 10, 2006
- 3 -
Revision 0.51
W83320S/W83320G
1. GENERAL DESCRIPTION
The W83320S is a high-speed, N-Channel synchronous buck regulator controller optimized for wide
reference input range. The W83320S employs adjustable frequency ranging from 100 KHz to 400 KHz
voltage-mode PWM control architecture. The regulator is biased from a 5V rail and the power for the
high-side MOSFET can be supplied by a separate 12V rail or supplied from the internal charge pump.
A Current limit protection is implemented by monitoring the voltage drop across the switch ON
resistance of the low-side MOSFET. This method can eliminate the requirement of extra current
sensing resistor and avoids false trigger of OC protection when VIN varies efficiently. The adaptive
non-overlapping MOSFET gate drivers help avoid potential shoot-through problems while maintaining
high efficiency. All these together with Power-good flag, enable and soft start features make power
sequencing easy.
2. FEATURES
y
y
y
y
y
y
y
1.8V to 5V power stage input voltage
Providing +/-1.5% reference voltage
Power Good flag
Current limit without sense resistor
Soft start
Switching frequency from 100 kHz to 400 kHz
Tiny plastic SOP-14 package
3. APPLICATIONS
y
y
y
y
DDR SDRAM and AGP core power for Desktop PC
Set-Top Boxes/ Home Gateways
Core Logic Regulators
High-Efficiency Buck Regulation
- 4 -
W83320S/W83320G
4. PIN-OUT
14
LGATE
VDD
ISEN
1
2
3
4
5
6
7
13
12
11
10
9
GND
VDDA
PWOK
GNDA
SS
UGATE
BOOT
BG_REF
VREF
W83320S
8
COMP
FB
Publication Release Date: January 10, 2006
Revision 0.51
- 5 -
W83320S/W83320G
5. PIN DESCRIPTION
PIN
NAME
FUNCTION
Low-Side N-Channel MOSFET Gate Drive Pin. This pin is monitored by the
adaptive shoot-through protection circuitry to determine when the low-side
MOSFET turned off.
1
LGATE
2
3
VDD
+5V supply rail for the lower gate driver and control logic circuit.
VDDA: +5V supply rail for the chip.
VDDA
Power OK. Open drain output. This pin will be opened in following conditions:
1. No over-current detected; 2. VREF_IN >0.6V; 3. FB > 75% of VREF_IN; 4. SS
>3V.
4
5
6
PWROK
GNDA
SS
Ground for analog circuit. Connect it to system ground.
Soft Start Pin. A capacitor should be attached in this pin to ground for soft start
output clamping. This capacitor, along with an internal 12uA current source,
set the output clamp ramp up speed.
Internal Error Amplifier Output Pin. This pin is available for compensation of
the control loop.
7
8
COMP
FB
Inverting Input of the Error Amplifier. This pin is available for compensation of
the control loop.
Non-inverting Input of the Error Amplifier. Voltage on this pin provides
reference input to the PWM control loop.
When the VREF_IN voltage is less than 0.27V, the PWM is shut-down and the
H_DRV and L_DRV are driven low. Due to its wide input range (0 ~ 3.6V), the
VREF_IN voltage can be raised slowly to perform the input clamp function.
Besides, a special function is implemented in this IC to inform the reference
provider of over current alarm. Each time as the OC occurs, VREF_IN will be
short to GND (through 170 ohms) for about 5~10uS. The reference provider
can be aware of the OC condition by detecting this pulse.
9
VREF
10
11
BG_REF Internal Bandgap Reference Voltage Output.
Supply rail for the high-side MOSFET driver. A bootstrap circuit may be used
BOOT
to create a BOOT voltage or a separate 12V supply can be used.
High-Side N-Channel MOSFET Gate Drive Pin. This pin is also monitored by
12
13
UDRV
GND
the adaptive shoot through protection circuitry to determine when the high-side
MOSFET has turned off.
Ground for signal level circuit. Connect it to system ground.
Current limit threshold setting. Connect a resistor (ROCSET) between this pin
and the drain of the low-side MOSFET. An internal 72uA current source will
flow through RISEN and cause a fixed voltage drop on it while the low-side
MOSFET is turned on. In the mean while, the W83320S compares the voltage
drop with the voltage across the low-side MOSFET and determines whether
the current limit has been reached. The equation for over-current limit is:
14
ISEN
ILIM = (72uA * RISEN)/RDSON
- 6 -
W83320S/W83320G
6. INTERNAL BLOCK DIAGRAM
VDDA
POR
VDD
SS
.
72µA
12µA
Soft Start
.
ISEN
Logic
0.6V
Control
Logic
X0.7
BOOT
VREF
FB
.
+
-
Output
Clamp
UGATE
.
.
EA
Gate
.
Control
Logic
+
-
.
COMP
VDD
BG_REF
IREF & VREF
Oscillator
LGATE
GND
GNDA
Publication Release Date: January 10, 2006
Revision 0.51
- 7 -
W83320S/W83320G
Soft-Start
When VDDA and VDD ramp over 4.3V and the voltage at pin VREF ramps over 0.27V; the soft start
capacitor begins to charge through an internal 12uA (IREF/2) current source. The error amplifier (and
the PWM duty) is both output clamped by the voltage on soft-start pin VSS and input clamped by the
voltage on VREF. There are two ways to soft start the power that’s following the rising of the slower one
between VSS or VREF; during soft-start, PWOK is forced to low and the internal Over-Current Protection
is triggered to work. 0.4V to 1.9V of VSS is roughly mapping to 0 to 100% pulse-width. Smaller than
0.27V on VREF will disable the PWM controller and discharge CSS.
MOSFET Gate Drivers
The power for the high-side driver is flowing through the BOOT pin. This voltage can be supplied by a
separate, higher voltage source, or supplied from a local charge pump structure or combination of the
two.
Since the voltage of the low-side MOSFET gate and the high-side MOSFET gate are being monitored
to determine the state of the MOSFET, it should be taken carefully to add external components
between the gate drivers and their respective MOSFET gates. Doing so may interfere with the shoot-
through protection.
Current Limit
Current limit is implemented by sensing the voltage across the low-side MOSFET while it is ON. This
method enhances the converter's efficiency and reduces total cost by eliminating a current sensing
resistor.
While low-side MOSFET is turned on, a constant current of 72uA (IREF X 3) is forced through
ROCSET which is an external resistor connected between phase and ISEN, causing a fixed voltage
drop. This fixed voltage is compared against VDS and if the latter is higher, the chip enters current
limit mode. In the current limit mode both the high-side and low-side MOSFETS are turned off and the
soft start capacitor CSS will be discharged immediately. The VREF is shorted to GND for 5~10uS to
indicate the over current condition. After a 5mS delay, a soft-start cycle is initiated. If the cause of the
over-current is still present after the delay interval, the current limit would be triggered again. The shut
down - delay - soft start cycle will be repeated indefinitely until the over-current event been removed.
Input Tracking
When the VREF voltage is less than 0.3V, the PWM is shut-down and the UGATE and LGATE are
driven low. Due to its wide input range (0 ~ 3.6V), this chip is suitable for reference input tracking
application. But note that the chip will be shut-down when VREF <0.27V, a proper setting of CSS is
needed to clamp the output at initiation of start up and avoid output voltage step-up ( and so a large
inrush current).
IREF and PWM Clock
The Internal reference current (IREF) is determined by the resistor between pin BG_REF pin and
GND (RSET) according to the following equation:
IREF = 1.19V/Rset
The nominal 200 kHz PWM clock can be adjusted ranging form 100 kHz to 400 kHz by changing IREF
according to the following equation:
Freq = 200 KHz * IREF / 24uA;
- 8 -
W83320S/W83320G
7. APPLICATION CIRCUIT
Publication Release Date: January 10, 2006
Revision 0.51
- 9 -
W83320S/W83320G
8. ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP MAX UNITS
VCC SUPPLY CURRENT
Nominal Supply
ICC
EN=VCC; UGATE and LGATE Open
-
3
-
-
mA
V
POWER-ON RESET
Rising VDD
Threshold
-
4.3
Falling VDD
Threshold
-
-
3.7
-
-
V
V
REFIN Enable
0.27
OSCILLATOR
Free Running
Frequency
RSET=49.6K
RSET=49.6K
160
-
200
1.5
240
-
kHz
VP-P
Ramp Amplitude
ΔVOSC
REFERENCE
Reference Voltage
Tolerance
VREF
-1.5
-
-
1.5
-
%
V
Reference Voltage
ERROR AMPLIFIER
DC Gain
1.19
-
-
-
80
5
-
-
-
dB
Gain-Bandwidth
Slew Rate
MHz
V/µS
4
GATE DRIVERS
High-side Gate
Source
IHGATE-SRC
VBOOT=12V,VUGATE=6V
VBOOT=12V,VUGATE=6V
VCC=5V, VLGATE=2.5V
VCC=5V, VLGATE=2.5V
250
600
250
300
-
-
-
-
-
-
-
-
mA
mA
mA
mA
High-side Gate Sink IHGATE-SNK
Low-side Gate
ILGATE-SRC
Source
Low-side Gate Sink
ILGATE-SNK
PROTECTION
ISEN Current
Source
ISEN
ISS
64
10
72
12
80
14
µA
µA
Soft-Start Current
- 10 -
W83320S/W83320G
9. TYPICAL PERFORMANCE CHARACTERISTICS
-
Power start up with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz.
Ch1: VCC
Ch2: VREF
Ch3: VOUT
Ch4: PWROK
-
Power shut down with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200 KHz.
Ch1: VCC
Ch2: VREF
Ch3: VOUT
Ch4: PWROK
Publication Release Date: January 10, 2006
- 11 -
Revision 0.51
W83320S/W83320G
-
High gate switch off with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200
KHz.
Ch1: UGATE
Ch2: LGATE
Ch3: Phase
-
High gate switch off with condition: 2Amp loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200
KHz.
Ch1: UGATE
Ch2: LGATE
Ch3: Phase
- 12 -
W83320S/W83320G
-
High gate switch on with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200
KHz.
Ch1: UGATE
Ch2: LGATE
Ch3: Phase
-
High gate switch on with condition: no loading; CSS=0.1uF; VCC=5V; VOUT=2.5V; f = 200
KHz.
Ch1: UGATE
Ch2: LGATE
Ch3: Phase
Publication Release Date: January 10, 2006
- 13 -
Revision 0.51
W83320S/W83320G
-
Load transient response with condition: 0.5Amp to 5.5Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V;
f = 200 KHz.
Ch1: IOUT
Ch4: VOUT
-
Load transient response with condition: 5.5Amp to 0.5Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V;
f = 200 KHz.
Ch1: VOUT
Ch4: IOUT
- 14 -
W83320S/W83320G
-
Output load transient response with condition: IOUT=2Amp; CSS=0.1uF; VIN=5V; VOUT=2.5V;
f = 200 KHz.
Ch1: VOUT
Ch4: IOUT
-
Regulation efficiency with various loading
Efficiency(Vin=5V,Vout=2.5V)
96
94.34
94.34
92.59
93.9
93.28
94
92
90
88
86
92.59
91.62
90.9
90
1 2 3 4 5 6 7 8 9
Output current(A)
Publication Release Date: January 10, 2006
Revision 0.51
- 15 -
W83320S/W83320G
10. PACKAGE DIMENSION OUTLINE
14L SOP (150mil)
c
8
14
E
HE
L
1
7
O
D
0.25
A
Y
SEATING PLANE
e
GAUGE PLANE
A1
b
Control demensions are in milmeters .
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN.
1.35
MAX.
MIN.
MAX.
0.053
0.069
0.010
0.020
A
A1
b
1.75
0.10
0.33
0.19
0.004
0.013
0.25
0.51
c
0.25
0.008
0.150
0.337
0.010
0.157
0.344
3.80
8.55
E
D
4.00
8.75
e
0.050 BSC
1.27 BSC
6.20
0.10
1.27
8
H
5.80
0.228
0.244
0.004
E
Y
0.40
0
0.016
0
0.050
8
L
θ
- 16 -
W83320S/W83320G
11. ORDERING INSTRUCTION
PART NO.
W83320S
W83320G
PACKAGE
14-pin SOP
14-pin SOP
REMARKS
Operation - Commercial 0~70℃
Operation - Commercial 0~70℃,Pb-free package
12. HOW TO READ THE TOP MARKING
W83320S
2322906Z-N
323GA
W83320G
2322906Z-N
323GA
Left Line: Winbond Logo
1st Line: Part No – W83320S,W83320G(Pb-free part no)
2nd Line: IC Tracking Code
3rd Line: Manufacturing Date Code (X XX) + Assembly Code (X) + IC Version (X)
Publication Release Date: January 10, 2006
Revision 0.51
- 17 -
W83320S/W83320G
Please note that all data and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this data sheet belong to their respective
owners.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
- 18 -
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