W83768 概述
I/O COUPLER I / O耦合器 其他接口集成电路
W83768 规格参数
生命周期: | Obsolete | 零件包装代码: | QFP |
包装说明: | QFP, | 针数: | 48 |
Reach Compliance Code: | unknown | 风险等级: | 5.84 |
接口集成电路类型: | INTERFACE CIRCUIT | JESD-30 代码: | S-PQFP-G48 |
长度: | 10 mm | 标称负供电电压: | -12 V |
功能数量: | 1 | 端子数量: | 48 |
最高工作温度: | 70 °C | 最低工作温度: | |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | QFP |
封装形状: | SQUARE | 封装形式: | FLATPACK |
认证状态: | Not Qualified | 座面最大高度: | 1.78 mm |
标称供电电压: | 5 V | 电源电压1-Nom: | 12 V |
表面贴装: | YES | 温度等级: | COMMERCIAL |
端子形式: | GULL WING | 端子节距: | 0.75 mm |
端子位置: | QUAD | 宽度: | 10 mm |
Base Number Matches: | 1 |
W83768 数据手册
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PDF下载W83768
I/O COUPLER
GENERAL DESCRIPTION
The W83768 is an I/O-coupler chip that includes six line drivers (1488), ten line receivers (1489), two
timers (556), and one 244-type buffer block for game port signals. It also supports a power-down
control circuit to reduce power consumption. This chip is intended for use with an I/O controller, and it
is specifically designed to match the pin assignments of the Winbond Power I/O series. With this
chip, engineers can easily design an all-in-one I/O circuit for personal computer systems without using
any other TTL ICs.
FEATURES
· Six line drivers (1488), ten line receivers (1489), two timers (556), one buffer block for game port
signals
· Supports two RS232 serial ports and one game port control logic circuit
· Power-down control function available
· Four power supplies needed: 0V, +5V, +12V, and -12V
· 48-pin QFP package
PIN CONFIGURATION
/
/
/
/
R
V
O
P
2
R
V
O
P
1
R
V
O
P
3
P
D
C
I
D
R
O
P
5
R
V
I
N
9
R
V
I
N
6
R
V
I
N
7
R
V
I
N
8
G
B
O
0
G
B
O
1
G
N
D
N
36 35 34 33 32 31 30 29 28 27 26 25
-12V
RVIN10
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
RVOP4
DRIN1
DROP4
DRIN2
DRIN3
RVOP5
DROP6
RVIN1
RVIN4
GMRD
DROP2
RVIN3
RVIN2
RVIN5
GMWR
DRIN4
DRIN5
DRIN6
DROP3
DROP1
RVOP6
+5V
1
2
3
/
4
5
6
7
8
9
10 11 12
+
/
/
/
M
R
S
D
0
S
D
1
S
S
G
P
O
1
G
P
O
0
1
2
V
R
V
O
P
1
0
R
V
O
P
7
R
V
O
P
8
R
D D
V
O
P
9
4
5
Publication Release Date: October 1994
Revision A1
- 1 -
W83768
PIN DESCRIPTION
Power Pins
PIN NO.
36
SYMBOL
I/O
DESCRIPTION
GND
VCC
VDD
VSS
-
-
-
-
Ground
48
+5V Power
+12V Power
-12V Power
12
24
Line Drivers
PIN NO.
38
SYMBOL
DRIN1
DRIN2
DRIN3
DRIN4
DRIN5
DRIN6
I/O
DESCRIPTION
I
I
Driver input 1
Driver input 2
Driver input 3
Driver input 4
Driver input 5
Driver input 6
Driver output 1
39
40
I
44
I
45
I
46
I
13
O
DROP1
DROP2
DROP3
DROP4
DROP5
DROP6
18
14
22
27
21
O
O
O
O
O
Driver output 2
Driver output 3
Driver output 4
Driver output 5
Driver output 6
Line Receivers
PIN NO.
20
SYMBOL
RVIN1
RVIN2
RVIN3
RVIN4
RVIN5
RVIN6
RVIN7
RVIN8
RVIN9
I/O
DESCRIPTION
I
I
I
I
I
I
I
I
I
Receiver input 1
Receiver input 2
Receiver input 3
Receiver input 4
Receiver input 5
Receiver input 6
Receiver input 7
Receiver input 8
Receiver input 9
16
17
19
15
28
26
25
29
- 2 -
W83768
Line Receivers, continued
PIN NO.
23
SYMBOL
I/O
I
DESCRIPTION
RVIN10
RVOP1
Receiver input 10
33
I/O
During normal operations, this pin works as receiver output
#1. During power-on reset, this pin is used to select power-
down control (PDC) mode enable level.
When RVOP1 is set to high at power-on, PDC is high
active. When RVOP1 is set to low at power-on, PDC is low
active.
34
35
37
41
47
1
O
O
O
O
O
O
O
O
O
Receiver output 2
Receiver output 3
Receiver output 4
Receiver output 5
Receiver output 6
Receiver output 7
Receiver output 8
Receiver output 9
Receiver output 10
RVOP2
RVOP3
RVOP4
RVOP5
RVOP6
RVOP7
RVOP8
RVOP9
RVOP10
2
3
4
Game Port
PIN NO.
11
SYMBOL
GPO0
I/O
DESCRIPTION
Game port RC constant (open drain)
Game port RC constant (open drain)
Game port button input
I/O
10
GPO1
I/O
31
GBO0
I
I
I
30
GBO1
Game port button input
42
Game port read. This pin is internally pulled-up to make it
convenient to disable the game port.
GMRD
43
I
Game port write
GMWR
Control Signals
PIN NO.
SYMBOL
I/O
DESCRIPTION
5
MR
I
I
Master reset signal input
32
PDCIN
This pin is used to enable/disable the power-down function.
The active level of this pin depends on how pin RVOP1 is
programmed at power-on. If RVOP1 is set high at power-
on, for example, then setting PDCIN to high will cause the
W83768 to enter power-down mode.
Publication Release Date: October 1994
- 3 -
Revision A1
W83768
Data Bus
PIN NO.
SYMBOL
SD0
I/O
O
DESCRIPTION
6
7
8
9
System data bit 0
System data bit 1
System data bit 4
System data bit 5
SD1
O
SD4
O
SD5
O
BLOCK DIAGRAM
GBO0
GBO1
GPO0
GPO1
GPO0'
GPO1'
SD0, SD1
SD4, SD5
74244
556
GMRD
GMWR
LINE DRIVER
1488
DRIN1-6
DROP1-6
RVIN1-10
LINE RECEIVER
1489
RVOP1-10
FUNCTIONAL DESCRIPTION
Block 74244
This 244-type block functions as a buffer for reading game port buttons GBO0 and GBO1 and the
status of block 556 output signals GPO0' and GPO1' on data bits 4, 5, 0, and 1, respectively.
Block 556
This block contains two independent 555-type timing circuits that are used to generate two separate
one-shot signals. With these two one-shot pulses, the RC inputs of the game port can easily be
measured. The GMWR signal is the trigger signal of block 556.
- 4 -
W83768
Line Driver Block 1488
This block contains six line drivers that are designed to serve as an interface between data terminal
equipment and data communications equipment in conformance with the specifications of EIA
standard RS-232C. The power requirements are +12V, 0V, and -12V.
Line Receiver Block 1489
This block contains ten line receivers that are designed to serve as an interface between data
terminal equipment and data communications equipment in conformance with the specifications of
EIA standard RS-232C. The power requirements are +12V, 0V, and -12V.
Power-Down Control Mode
When pin PDCIN is set active (active high or low determined by RVOP1 at power-on reset), the
W83768 enters power-down mode, and all output buffers (SD0, SD1, SD4, SD5, RVOP1- 10 ,
DROP1- 6 ) will enter tri-state to reduce power consumption.
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
0 to 5.5
UNIT
Power Supply Voltage
Input Voltage
GND, VCC
VSS, VDD
V
-13 to 13
-0.5 to 7.0
-12 to 12
0 to 70
Low Voltage
High Voltage
V
Operating Temperature
Storage Temperature
°C
°C
-55 to 150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
Ta = 0° C to +70° C, VCC = 5V, VDD = 12V, VSS = -12V, GND = 0V
PARAMETER
Input low voltage
Input high voltage
Input low voltage
SYMBOL
VIL (TTL)
MIN.
MAX.
NOTES
MR, GMRD, GMWR
MR, GMRD, GMWR
-0.3V
+0.6V
VIH (TTL)
VIL (CMOS)
+2.4V VCC +0.3V
-0.3V 0.2 VCC
DRIN1- 6, GBO0- 1, GPO0- 1,
PDCIN
Publication Release Date: October 1994
Revision A1
- 5 -
W83768
DC Characteristics, continued
PARAMETER
SYMBOL
MIN.
MAX.
NOTES
Input high voltage
VIH (CMOS)
+3.9V
VCC
DRIN1- 6, GBO0- 1, GPO0- 1,
+0.3V
PDCIN
Input low voltage
Input high voltage
Output low voltage
VIL (HI-V)
VIH (HI-V)
VOL
VSS
2V
-
GND
VDD
RVIN1- 10
RVIN1- 10
0.4V
RVOP1- 10 , SD0, SD1, SD4, SD5
RVOP1- 10 , SD0, SD1, SD4, SD5
DROP1- 6
Output high voltage
Output low voltage
Output high voltage
VOH
+2.4V
VSS
-
VOL (HI-V)
VOH (HI-V)
-2V
VDD
+2V
DROP1- 6
CURRENT LEVEL
MIN.
SYMBOL
MAX.
TYP.
IIL
IIH
IOL
IOH
IOL
IOH
MR
-
-
-
-
-
-
-
-
-
-
-
-
-20 mA
-20 mA
-20 mA
3 mA
3 mA
3 mA
PDCIN
GMRD , GMWR
GBO0, GBO1
RVIN1- 10
-
-
-
-
-20 mA
3 mA
-1 mA
-
-
-
-
3 mA
GPO0, GPO1
SD0, SD1, SD4, SD5
-
-
-
-
-
-
1.5 mA
5.5 mA
2 mA
-
2 mA
8 mA
3 mA
-
4 mA
2 mA
6 mA
3 mA
RVOP1- 10
DROP1- 6
-
-
10 mA
10 mA
14 mA
16 mA
AC CHARACTERISTICS
PARAMETER
1488 tpLH
SYMBOL
MIN.
TYP.
60
MAX.
90
UNIT
nS
-
-
DRIN1- 6
1488 tpHL
60
90
nS
DROP1- 6
RVIN1- 10
1489 tpLH
1489 tpHL
-
-
60
60
90
90
nS
nS
RVOP1- 10
tD
SD0, SD1, SD4, SD5
-
90
120
nS
- 6 -
W83768
TIMING WAVEFORMS
Driver Timing
+5V
0V
IN
DRIN1-6
tpLH
tpHL
DROP1-6
OUT
+12V
-12V
Receiver Timing
+12V
IN
RVIN1-10
-12V
tpLH
tpHL
RVOP1-10
OUT
+5V
0V
Timer Timing
GMWR
CV= 3.3V
GPO0
GPO1
GPO0'
GPO1'
T= RC
GMRD
tD
SD0, SD1
SD4, SD5
Floating
Floating
Data Valid
Publication Release Date: October 1994
Revision A1
- 7 -
W83768
PACKAGE DIMENSIONS
48-lead QFP
H D
D
37
48
Dimension in inch
Min. Nom. Max.
Dimension in mm
Min. Nom. Max.
1.78
Symbol
A
0.070
---
---
---
---
---
---
---
0.004
0.10
---
1
A
36
1
0.052 0.057 0.062
1.32
0.28
0.10
9.87
9.87
0.60
1.45
0.33
1.58
0.43
0.25
10.13
2
A
0.011 0.013
0.006
0.017
0.010
b
c
D
E
e
0.15
0.004
E
HE
0.389 0.394 0.399
10.00
0.394 0.399
0.036
10.00 10.13
0.75 0.90
0.389
0.024
0.642
0.642 15.70 16.00 16.30
0.618 0.630
15.70 16.00 16.30
D
H
H
L
L
y
25
12
0.618
0.067 0.075
0.630
E
0.083
0.126
0.006
15
1.70
2.79
1.90
3.00
2.10
3.20
0.118
0.110
---
1
0.15
15
---
---
---
0
---
---
13
24
e
b
0
0
Notes:
c
1. Dimensions D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
A
A
2
A 1
3. Controlling dimension: Millimeters
4. General appearance spec. should be based
on final visual inspection spec.
See Detail F
L
y
Seating Plane
L 1
Detail F
Winbond Electronics (H.K.) Ltd.
Winbond Electronics North America Corp.
Headquarters
Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792646
123 Hoi Bun Rd., Kwun Tong,
Winbond Microelectronics Corp.
Winbond Systems Lab.
Kowloon, Hong Kong
TEL: 852-27516023
FAX: 852-27552064
2730 Orchard Parkway, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-9436668
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-7197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-7190505
FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 8 -
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