W946432AD_技术文档

W946432AD

512K ´ 4 BANKS ´ 32 BITS DDR SDRAM

GENERAL DESCRIPTION

The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access

memory organized as 512K words x 4 banks x 32 bits.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at

the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for

WRITEs.

The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH

and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control

signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well as to both edges of CLK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location

and continue for a programmed number of locations in a programmed sequence. Accesses begin with

the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The

address bits registered coincident with the ACTIVE command are used to select the bank and row to

be accessed. The address bits registered coincident with the READ or WRITE command are used to

select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An

AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at

the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for

concurrent operation, thereby providing high effective bandwidth by hiding row precharge and

activation time.

FEATURES

·Double-data-rate architecture; two data transfers ·Four internal banks for concurrent operation

per clock cycle

·Data mask (DM) for write data

·Bidirectional, data strobe (DQS) is transmitted/

received with data, to be used in capturing data

at the receiver

·Burst lengths: 2, 4, or 8

·CAS Latency: 3

·AUTO PRECHARGE option for each burst

access

·DQS is edge-aligned with data for READs;

center-aligned with data for WRITEs

·Auto Refresh and Self Refresh Modes

·Differential clock inputs (CLK and CLK )

·15.6us Maximum Average Periodic Refresh

Interval

·DLL aligns DQ and DQS transitions with CLK

transitions

·2.5V (SSTL_2 compatible) I/O

·VDDQ = 2.5V ± 0.2V

·Programmable DLL on or DLL off mode

· Commands entered on each positive CLK edge;

data and data mask referenced to both edges of

DQS

·VDD = 2.5V ± 0.2V

PRELIMINARY DATA:9/8/00

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W946432AD

512K ´ 4 BANKS ´ 32 BITS DDR SDRAM

PIN CONFIGURATION

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

DQ3

DD

1

2

3

4

5

6

7

8

9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ28

DDQ

V

Q

V

DQ4

DQ5

DQ27

DQ26

V

SS

Q

VSSQ

DQ6

DQ7

DQ25

DQ24

V

DD

Q

VDDQ

DQ16

DQ17

DQ15

DQ14

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V

SS

Q

VSSQ

DQ18

DQ19

DQ13

DQ12

V

DD

SS

Q

V

DD

SS

DD

Q

V

DQ20

DQ21

DQ11

DQ10

V

SS

Q

VSSQ

DQ22

DQ23

DQ9

DQ8

V

Q

V

Q

DD

DM0

DM2

WE

VREF

DM3

DM1

CLK

CAS

RAS

CS

CLK

CKE

N.C

BA0

BA1

A8/AP

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PRELIMINARY DATA:9/8/00

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W946432AD

PIN DESCRIPTION

PIN NAME

FUNCTION

DESCRIPTION

All address and control input signals are sampled on the crossing of the positive edge of CLK

and negative edge of . Output (read) data is referenced to the crossings of CLK and

Differential clock

input

CLK

(both directions of crossing).

CLK,

CLK

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input

buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and

SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any

bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry.

CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be

CKE

Clock Enable

maintained high throughout READ and WRITE accesses. Input buffers, excluding CLK,

CLK

and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled

during SELF REFRESH.

All commands are masked when

is registered HIGH.

provides for external bank

CS

Chip Select

CS

selection on systems with multiple banks.

is considered part of the command code.

CS

,

RAS CAS

Command Inputs

,

and WE (along with

) define the command being entered.

CS

RAS CAS

WE

DM is an input mask signal for writes data. Input data is masked when DM is sampled HIGH

along with that input data during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input only, the DM loading matches the DQ and DQS loading.

DM

Input Data Mask

Bank Address

BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is

being applied.

BA0, BA1

Provide the row address for ACTIVE commands, and the column address and AUTO

PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array

in the respective bank. A8 is sampled during a PRECHARGE command to determine whether

the PRECHARGE applies to one bank (A8 LOW) or all banks (A8 HIGH). If only one bank is

to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-

code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is

loaded during the MODE REGISTER SET command (MRS or EMRS).

A0-A10

Address Input

DQ

Data Input/Output Data bus

Output with read data, input with write data. Edge-aligned with read data, centered in write

data. Used to capture write data.

DQS

Data Strobe

VDDQ

VSSQ

DQ Power

2.5V ± 0.2V.

Ground.

DQ Ground

Supply Power

VDD

VSS

NC

2.5V ± 0.2V

Ground.

No Connection

No connection

VREF

SSTL_2 reference voltage.

W946432AD

BLOCK DIAGRAM

CLK

DLL

CLK

CLOCK

BUFFER

CKE

CONTROL

SIGNAL

CS

GENERATOR

RAS

CAS

COMMAND

DECODER

COLUMN DECODER

WE

CELL ARRAY

BANK #0

CELL ARRAY

BANK #1

A8

A0

MODE

REGISTER

SENSE AMPLIFIER

ADDRESS

BUFFER

A7,

A9,A10

BA0

BA1

Prefetch Register

DQ0

DQn

DQ

DATA CONTROL

CIRCUIT

BUFFER

COLUMN

COUNTER

REFRESH

COUNTER

DQS

DM

COLUMN DECODER

CELL ARRAY

BANK #2

CELL ARRAY

BANK #3

SENSE AMPLIFIER

NOTE:

The cell array configuration is 2048 * 256 * 32

W946432AD

ABSOLUTE MAXIMUM RATINGS*

SYMBOL

ITEM

RATING

-0.3~ VDD +0.3

-0.3~ VDDQ+0.3

-0.3~4.6

-0.3~3.6

0~70

UNIT

V

NOTES

VIN

Input Voltage

1

VOUT

Output Voltage

V

VDD

Power Supply Voltage

I/O Power Supply Voltage

Operating Temperature

Storage Temperature

V

VDDQ

TOPR

V

°C

W

TSTG

TSOLDER

PD

-55~150

260

Soldering Temperature(10s)

Power Dissipation

1

IOUT

Short Circuit Output Current

50

mA

*Conditions outside the limits listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.

CAPACITANCE (VDDQ = 2.5V, VDD = 2.5 ± 0.2, f 100 MHz, TA = 25 °C)

PARMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Cl1

2.5

3.5

pF

Input Capacitance: CK,

CK

Input Capacitance: All other input-only pins

Input/Output Capacitance: DQ, DQS, DM

Cl2

Cl0

2.5

4.0

3.5

5.5

pF

Note: These parameters are periodically sampled and not 100% tested.

ELECTRICAL CHARACTERISTICS AND DC OPERATING CONDITIONS

(0°C £ TA £ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)

MAX

UNITS

NOTES

PARAMETER/CONDITION

SYMBOL

MIN

Supply Voltage (for devices with VDD of 2.5V)

I/O Supply Voltage

I/O Reference Voltage

I/O Termination Voltage (system)

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

VDD

VDDQ

VREF

2.3

1.15

2.7

1.35

V

3

4

VTT

VREF -0.04

VREF +0.18

-0.3

VREF + 0.04

VDD + 0.3

VREF -0.18

VIH(DC)

VIL(DC)

VIN(DC)

-0.3

VDDQ + 0.3

VDDQ + 0.6

V

Input Voltage Level, CK and

inputs

CK

VID(DC)

5

0.36

Input Differential Voltage, CK and

INPUT LEAKAGE CURRENT

inputs

CK

uA

II

-5

5

£

VDD

Any input 0V

(All other pins not under test = 0V)

VIN

OUTPUT LEAKAGE CURRENT

IOZ

£

VDDQ)

(DQs are disabled; 0V

OUTPUT LEVELS

VOUT

Output High Current (VOUT = 1.95V)

Output Low Current (VOUT = 0.35V)

IOH

IOL

-15.2

15.2

mA

W946432AD

AC OPERATING CONDITIONS

(0°C £ TA £ 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)

PARAMETER/CONDITION

SYMBOL

MIN

VREF +

0.35

MAX

UNITS

NOTES

Input High (Logic 1) Voltage, DQ, DQS and DM signals

V

VIH(AC)

VREF -

0.35

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

V

VIL(AC)

0.7

VDDQ + 0.6

V

5

7

VID(AC)

VIX(AC)

Input Differential Voltage, CK and

inputs

CK

0.5*VDDQ-0.2

0.5*VDDQ+0.2

Input Crossing Point Voltage, CK and

inputs

CK

IDD SPECIFICATIONS AND CONDITIONS

(0°C £ TA £ 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)

MAX

SYMBOL

UNITS

NOTES

OPERATING CURRENT: One Bank; Active-Precharge;

IDD0

TBD

mA

tRC = tRC MIN; tCK = tCK MIN; DQ, DM and DQS inputs changing twice per

clock cyle; address and control inputs changing once per clock cycle

OPERATING CURRENT: One Bank; Active-Read-Precharge;

Burst = 2; tRC = tRC MIN; CL = 3 ; tCK = tCK MIN; IOUT= 0 mA;

IDD1

mA

Address and control inputs changing once per clock cycle

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;

IDD2P

IDD2N

TBD

mA

power-down mode; CKE £ VIL (MAX); tCK = tCK MIN

IDLE STANDBY CURRENT:

³ VIH (MIN); All banks idle;

CS

CKE ³ VIH (MIN); tCK = tCK MIN; Address and other control inputs

changing once per clock cycle

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;

IDD3P

IDD3N

TBD

mA

power-down mode; CKE £ VIL (MAX); tCK = tCK MIN

ACTIVE STANDBY CURRENT:

³ VIH (MIN); CKE ³ VIH (MIN);

CS

One bank; Active-Precharge; tRC = tRAS MAX; tCK = tCK MIN; DQ,

DM and DQS inputs changing twice per clock cycle; address and

other control inputs changing once per clock cycle

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One bank active; Address and control inputs changing once per clock

IDD4R

IDD4W

TBD

mA

cycle; CL = 3 ; tCK = tCK MIN; IOUT = 0 mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One bank active; Address and control inputs changing once per clock

cycle; CL = 3 ; tCK = tCK MIN; DQ, DM and DQS inputs changing

twice per clock cycle

IDD5

IDD6

TBD

mA

AUTO REFRESH CURRENT: tRC = tRFC (MIN)

SELF REFRESH CURRENT: CKE £ 0.2V

W946432AD

512K ´ 4 BANKS ´ 32 BITS DDR SDRAM

AC CHARACTERISTICS

(0°C £ TA £ 70°C; VDDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V)

PARAMETER

-4

-5

-6

UNIT

NOTE

MIN. MAX. MIN. MAX. MIN. MAX.

tAC

tCK

-0.1

0.1

-0.1

0.1

-0.1

0.1

DQ output access time from CLK/

CLK

tDQSCK

DQS output access time from CLK/

CLK

CLK high-level width

CLK low-level width

Clock cycle time

DQ and DM input hold time

DQ and DM input setup time

DQ and DM input pulse width (for each input)

tCH

tCL

tCLK

tDH

tDS

0.45

4

0.5

1

0.55

8

0.45

5

0.5

1.6

0.55

8

0.45

6

0.5

1.6

0.55 tCK

8

ns

8

ns

tCK

tDIPW

tHZ

-0.1

0.1

Data-out high-impedance time from CLK/

CLK

tLZ

tCK

ns

Data-out low-impedance time from CLK/

CLK

DQS-DQ Skew (for DQS and associated DQ

signals)

DQS-DQ Skew (for DQS and all DQ signals)

DQ/DQS output valid time

Write command to first DQS latching transition

DQS input high pulse width

DQS input low pulse width

DQS falling edge to CLK setup time

DQS falling edge hold time from CLK

MODE REGISTER SET command cycle time

Write postamble

tDQSQ

-0.5

0.5

-0.5

0.5

-0.5

0.5

tDQSQA

tDV

tDQSS

tDQSH

tDQSL

tDSS

tDSH

tMRD

tWPST

tWPRE

TIH

-0.5

0.35

0.75

0.35

0.2

2

ns

tCK

1.25 tCK

0.35

0.75

0.4

0.35

0.75

0.4

1.25

0.6

1.25

0.6

tCK

ns

0.4

0.25

1

Write preamble

Address and Control input hold time

Address and Control input setup time

Read preamble

TIS

1

ns

tRPRE

tRPST

tRAS

tRC

tRFC

0.9

0.4

35

1.1

0.6

0.9

1.1

0.9

1.1

tCK

Read postamble

ACTIVE to PRECHARGE command

ACTIVE to ACTIVE/Auto Refresh command period

Auto Refresh to Active/Auto Refresh command

period

35

55

120K

42

60

120K ns

47

ns

47

66

72

ACTIVE to READ or WRITE delay

PRECHARGE command period

ACTIVE bank A to ACTIVE bank B command

Write recovery time

Auto Precharge write recovery + precharge time

Internal Write to Read Command Delay

Exit SELF REFRESH to non-READ command

Exit SELF REFRESH to READ command

Average Periodic Refresh Interval

tRCD

tRP

tRRD

tWR

3

2

5

2

47

200

15

11

10

25

18

12

30

tCK

ns

tDAL

tWTR

tXSNR

tXSRD

tREFI

9

200

tCK

15.6

15.6 us

PRELIMINARY DATA:9/8/00

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W946432AD

512K ´ 4 BANKS ´ 32 BITS DDR SDRAM

NOTES

1. All voltages referenced to VSS.

2. Outputs measured with equivalent load:

VTT

R_T=25 ohms

Rs = 25 ohms

30pF

A.C TEST LOAD

3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level

of the same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.

4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected

to be set equal to VREF, and must track variations in the DC level of VREF.

5. VID is the magnitude of the difference between the input level on CK and the input level on CK .

6. IDD specifications are tested after the device is properly initialized.

7. VIX is the differential clock cross point voltage where input timing measurement is referenced.

CLK

Vix

CLK

VssQ

8. Beyond 8ns tCK, chip maybe in "DLL off" mode

9. WRITE interrupted by READ is not allowed.

Note:

PRELIMINARY DATA:9/8/00

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W946432AD

FUNCTIONAL DESCRIPTION

The W946432AD is a high speed CMOS, dynamic random access memory containing 67,108,864 bits. The

W946432AD is internally configured as a quad bank DRAM.

The W946432AD uses a double data rate architecture to achieve high speed operation. The double data rate

architecture is essentially a 32 prefetch architecture, with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the W946432AD consists of a single 32bit

wide, one clock cycle data transfer at the internal DRAM core and two corresponding 32bit wide, one half

clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed

(BA0, BA1 select the bank; A0-A10 select the row). The address bits registered coincident with the READ or

WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide etailed

information covering device initialization, register definition, command descriptions and device operation.

INITIALIZATION

W986432AD must be powered up and initialized in a predefined manner. Operational procedures other than

those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and

finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch up, which may

cause permanent damage to the device. VREF can be applied any time after VDDQ, but is expected to be

nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied.

CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an

LVCMOS LOW level on CKE during power up is required to guarantee that the DQ and DQS outputs will be

in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power

supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay

prior to applying an executable command.

Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE

should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied.

Next a MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the

DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL,

and to program the operating parameters. 200 clock cycles are required between the DLL reset and any read

command. A PRECHARGE ALL command should be applied, placing the device in the “all banks idle” state.

Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER

SET command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating

parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready

for normal operation.

9

W946432AD

REGISTER DEFINITION

MODE REGISTER

The Mode Register is programmed by the MODE REGISTER SET command (MRS/EMRS) when all banks

are idle and no bursts are in progress.

The Mode Register is used to define the operation specific mode of of the DDR SDRAM. This definition

includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in

Figure1:

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these

additional functionsinclude DLL enable/disable,output drive strength selection. These functions as shown

inFigure1:.

Mode Register must be loaded, and the controller must wait the specified time before initiating the

subsequent operation. Violating either of these requirements will result in unspecified operation.

Figure1:Mode Register Definition

MODE REGISTER DEFINITION

EXTENDED MODE REGISTER DEFINITION

BA0 BA1 A10

A9

A8

A7

A6

A5

A4

A3

3

A2

A1

A0

Address Bus

BA0 BA1 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Address Bus

13

0*

12

0*

10

9

8

7

6

5

4

2

1

0

Extended Mode Register

12

1*

11 10

9

8

7

6

5

4

3

2

1

0

Extended Mode Register

Operating Mode

CAS Latency

BT

Burst Latency

0*

Operating Mode

DS2 DS1 DS0 DLL

* BA0 and BA1

must be 1, 0 to select the

Extended Mode Register (vs. the

base Mode Register).

Burst Latency

must be 0, 0 to select the

Mode Register (vs. the

Extended Mode Register).

A0

0

DLL

A2 A1 A0

A3 = 0

Reserved

A3 = 1

Reserved

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Enable

Disable

2

4

1

4

8

Reserved

A1

0

DS0

Normal

1

Weak (optional)

A3

Burst Type

Sequential

Interleaved

A2

0

DS1

0

1

CAS Latency

Reserved

3

A6 A5 A4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A3

0

DS2

Reserved

1

A3-A0

Valid

-

Operating Mode

Normal Operation

A10-A4

0

-

An-A9

A8 A7 A6-A0

Operating Mode

Normal Operation

All other states reserved

Valid

VS

0

-

0

1

0

-

0

1

-

Normal Operation/Reset DLL

Vendor Specific Test Mode

All other states reserved

-

VS = Vendor Specific

10

W946432AD

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable,

as shown in Table 1: The burst length determines the maximum number of column locations that can be

accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both

the sequential and the interleaved burst types.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively

selected. All accesses for that burst take place with in this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two,

by A2-A7 when the burst length is set to four and by A3-A7 when the burst length is set to eight. The

remaining address bit is used to select the starting location within the block. The programmed burst length

applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to

as the burst type and is selected by bit A3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting

column address, as shown in Table 1:.

Table 1:BURST DEFINITION

Starting Column

Order of Accesses Within a Burst

Burst Length

Address:

Type = Sequential

Type = Interleaved

A0

0

2

0 - 1

1

1 – 0

A1

0

1

A0

0

1

0

1

0–1–2-3

1–2–3–0

2–3–0–1

3–0–1–2

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

4

8

A2

0

1

A1

0

1

0

1

A0

0

1

0

1

0

1

0

1

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

NOTE:

1. For a burst length of two, A1-A7 selects the two-data-element block; A0 selects

the first access within the block.

2. For a burst length of four, A2-A7 selects the four-data-element block; A0-A1

selects the first access within the block.

3. For a burst length of eight, A3-A7 selects the eight-data- element block; A0-A2

selects the first access within the block.

4. Whenever a boundary of the block is reached within a given sequence above, the

following access wraps within the block.

11

W946432AD

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the

availability of the first piece of output data. The latency is set to 3 clocks.

If a READ command is registered at clock edge n, and the latency is 3 clocks, the data will be available

nominally coincident with clock edge n + 3.

Figure2:REQUIRED CAS LATENCIES

REQUIRED CAS LATENCIES

CK

COMMAND READ

NOP

CL=3

NOP

DQS

DQ

DON'T CARE

Burst Length = 4 in the case shown

Shown with nominal tAC, tDQSCK, and tDQSQ

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set command with bits A7-A10 each set

to zero, and bits A0-A6 set to the desired values. A DLL reset is inititated by issuing a Mode Register Set

command with bits A7 and A9-A10 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired

values. A Mode Register Set command issued to reset the DLL should always be followed by a Mode

Register Set command to select normal operating mode.

All other combinations of values for A7-A10 are reserved for future use and/or test modes. Test modes and

reserved states should not be used because unknown operation or incompatibility with future versions may

result.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable isrequiredduringpower-upinitialization,andupon

returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon

exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles

must occur before a READ command can be issued.

Output Drive Strength

DS0, DS1, DS2, TBD

12

W946432AD

COMMANDS

Truth Table provides a quick reference of available commands. This is followed by a verbal description of

each command. The additional Function Truth Tables provide current state/ next state information.

TRUTH TABLE (NOTE 1, 2)

Symbol

Command

Device

State

CKEn-1 CKEn

DM BA0,1

A8

A10,

A9-0

WE

CS

RAS CAS

Idle (3)

H

X

H

L

X

V

L

V

X

V

X

L

H

L

H

L

H

L

ACT

PRE

PREA

WRIT

Bank Active

Any (3)

Any

Bank Precharge

Precharge All

Write

X

H

L

Active (3)

Idle

V

H

L

V

H

L

WRITA Write with Autoprecharge

READ Read

READA Read with Autoprecharge

MRS

EMRS

NOP

BST

DSL

AREF

SELF

V

L

H

L

V

H

V

X

L

L,L

H,L

X

L

Mode Register Set

Extended Mode Register Set

No-Operation

Burst Read Stop

Device Deselect

L

Any

Active (4)

Any

H

X

L

H

X

L

H

L

X

H

Idle

X

Auto-Refresh

Self-Refresh Entry

Idle

X

L

Idle

(S.R)

Idle

Active (5)

Any

H

L

H

L

H

L

X

H

X

H

X

H

X

H

X

H

X

H

X

SELEX Self-Refresh Exit

L

H

L

H

L

X

PD

Power Down Mode Entry

PDEX

Power Down Mode Exit

H

(Power down)

Active

H

X

L

X

WDE

WDD

Data Write Enable

Data Write Disable

Active

H

X

Notes:

(1) V = Valid, X = Don't care, L = Low Level, H = High Level

(2) CKEn signal is input level when commands are provided.

CKEn-1 signal is input level one clock cycle before the command provided.

(3) These are state of bank designated by BA0 BA1 signals.

(4) Applies only to read bursts with autoprecharge disabled; this command should not be used for read

bursts with autoprecharge enabled, and for write bursts.

(5) Power Down Mode can not be entered in the burst cycle.

13

W946432AD

Function TRUTH TABLE (NOTE 1)

CURRENT

STATE

Address Command

ACTION

CS

RAS

CAS

WE

NOTE

H

L

H

L

H

L

H

L

H

L

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

X

H

L

H

L

H

L

X

H

L

H

L

H

L

X

H

L

H

L

H

L

H

L

X

H

L

H

L

H

L

H

L

X

H

L

H

L

X

DSL

NOP

NOP, BST NOP

BA, CA,A8 Read, Read A ILLEGAL

BA, CA,A8 Write, Write A ILLEGAL

BA, RA

BA, A8

X

3

L

Idle

H

L

ACT

ACTIVE (select and activate row)

PRE, PRE A NOP

AREF, SREF Refresh or Self refresh

2

L

Op-Code MRS, EMRS Mode register accessing

X

H

L

X

DSL

NOP

NOP, BST NOP

BA, CA,A8 Read, Read A READ (start READ burst)

BA, CA,A8 Write, Write A WRITE (start WRITE burst)

BA, RA

BA, A8

X

4

3

5

L

Row Active

H

L

ACT

ILLEGAL

PRE, PRE A PRECHARGE

AREF, SREF ILLEGAL

L

Op-Code MRS, EMRS ILLEGAL

X

H

L

X

DSL

NOP

BST

Continue burst to end

Burst stop

BA, CA,A8 Read, Read A Term burst, start new READ burst

BA, CA,A8 Write, Write A ILLEGAL

BA, RA

BA, A8

X

6

3

Read

L

H

L

ACT

ILLEGAL

PRE, PRE A Term burst, PRECHARGE

AREF, SREF ILLEGAL

L

Op-Code MRS, EMRS ILLEGAL

X

H

L

X

DSL

NOP

BST

Continue burst to end

ILLEGAL

BA, CA,A8 Read, Read A ILLEGAL

BA, CA,A8 Write, Write A Term burst, start new READ burst

BA, RA

BA, A8

X

3

6,7

3

Write

L

H

L

ACT

ILLEGAL

PRE, PRE A Term burst, PRECHARGE

AREF, SREF ILLEGAL

8

L

Op-Code MRS, EMRS ILLEGAL

X

H

L

X

DSL

NOP

BST

Continue burst to end

ILLEGAL

BA, CA,A8 Read, Read A ILLEGAL

BA, CA,A8 Write, Write A ILLEGAL

BA, RA

BA, A8

X

Read with

Auto

rpecharge

L

H

L

H

L

H

L

X

H

L

H

L

H

L

H

L

ACT

ILLEGAL

PRE, PRE A ILLEGAL

AREF, SREF ILLEGAL

L

Op-Code MRS, EMRS ILLEGAL

X

H

L

X

DSL

NOP

BST

Continue burst to end

ILLEGAL

Write with

Auto

precharge

BA, CA,A8 Read, Read A ILLEGAL

BA, CA,A8 Write, Write A ILLEGAL

BA, RA

BA, A8

X

L

H

L

ACT

ILLEGAL

PRE, PRE A ILLEGAL

AREF, SREF ILLEGAL

L

Op-Code MRS, EMRS ILLEGAL

14

W946432AD

NOTE:

1. This table applies when CKE n-1 was HIGH and CKE n is HIGH.

2. ILLEGAL if any bank is not idle.

3. ILLEGAL to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of

that bank.

4. ILLEGAL if tRCD is not satisfied.

5. ILLEGAL if tRAS is not satisfied.

6. Must satisfy bust interrupt condition.

7. Must satisfy bus contention, bus turn around, and/ or write recovery requirements

8. Must mask preceding data, which don’t satisfy tWR

Figure3:Simplified State Diagram

SIMPLIFIED STATE DIAGRAM

SELF

REFRESH

SREF

SREFX

MRS/EMRS

MODE

REGISTER

SET

AREF

AUTO

IDLE

REFRESH

PD

PDEX

ACT

POWER

DOWN

ACTIVE

POWERDOWN

PDEX

PD

ROW

ACTIVE

BST

Read

Write

Read

Read A

Write A

Read A

Write A

PRE

Write A

Read A

PRE

POWER

APPLIED

POWER

ON

PRE

CHARGE

PRE

Automatic Sequence

Command Sequence

MRS = Mode Register Set

ACT = Active

EMRS = Extended Mode Register Set

SREF = Enter Self Refresh

SREFX = Exit Self Refresh

AREF = Auto Refresh

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

BST = B nst Read Stpop

PD = Enter Power Down

PDEX = Exit Power Down

15

W946432AD

DESELECT

RAS CAS WE

The Device Deselect command disables the command decoder so that the

inputs are ignored. This command is similar to the No-Operation command.

and Address

NO OPERATION (NOP)

The No Operation Command should be used in cases when the DDR SDRAM is in an idle or a wait state to

prevent the DDR SDRAM from registering any unwanted commands between operations. A No Operation

CS

RAS CAS

WE

, and held high at the rising edge of the clock.

Command is registered when

is low with

,

A No Operation Command will not terminate a previous operation that is still executing, such as a burst read

or write cycle.

MODE REGISTER SET

CS RAS CAS

WE

is at the rising edge of the clock. The mode

Command is registered when

,

, and

registers are loaded by inputs A0-A10. See mode register descriptions in the Register Definition section. The

MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress,

and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE

CS RAS

CAS

WE

, and

The ACTIVE command is registered when

,

is low with

held high at the rising edge

WE

, and held high at the rising edge of

of the clock, used to open a row in a particular bank for a subsequent access.

READ

CS CAS

RAS

The READ command is registered when

,

is low with

the clock, used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the

bank, and the address provided on inputs A0-A7 selects the starting column location.

WRITE

CS CAS WE

RAS

, held high at the rising edge of

The WRITE command is registered when

,

is low with

the clock, used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the

bank, and the address provided on inputs A0-A7 selects the starting column location

PRECHARGE

CS RAS WE

CAS

held high at the rising

The PRECHARGE command is registered when

,

is low with

edge of the clock, used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row access a specified time ( tRP) after the PRECHARGE

command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be

precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any READ or WRITE commands being issued to that bank. A

PRECHARGE command will be treated as a NOP if there is no open row in that bank.

BURST READ STOP

CS WE

The BURST READ STOP command register when

truncate read bursts (with autoprecharge disabled).

is low with RAS CAS held high is used to

AUTO REFRESH

CS RAS CAS

WE

high.

The Auto Refresh command is register when

low with

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t

Care” during an AUTO REFRESH command. The W946432AD requires AUTO REFRESH cycles at an

average periodic interval of 15.6µs (maximum).

16

W946432AD

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute

refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given

DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and

the next AUTO REFRESH command is 9 * 15.6us (140.4us). This maximum absolute interval is short

enough to allow for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles,

without allowing too much drift in tAC between updates.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the

system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external

clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is

disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically

enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be

issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to

CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR

because time is required for the completion of any internal refresh in progress. A simple algorithm for

meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other

command.

OPERATIONS

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank

must be “opened.” This is accomplished by the ACTIVE command, which selects both the bank and the row

to be activated.

The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the

row. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this

command is issued, Read or Write operation can be executed.

After opening a row, a READ or WRITE command may be issued to that row, subject to the tRCD

specification.

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous

active row has been “closed” (precharged). The minimum time interval between successive ACTIVE

commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which

results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE

commands to different banks is defined by tRRD.

PRELIMINARY DATE: 9/8/00

17

.

W946432AD

Figure4:tRCD and tRRD Definition

tRCD and tRRD Definition

CK

COMMAND

ACT

Row

NOP

ACT

Row

NOP

RD/WR

Col

NOP

A0-A10

BA0,BA1

Bank y

Bank x

Bank y

tRRD

tRCD

DON'T CARE

READs

The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is

either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled (A8 = high), the row that

is accessed will start precharge at the completion of the burst. This command cannot be interrupted by any

other command. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is

disabled (A8 = low).

During READ bursts, the valid data-out element from the starting column address will be available following

the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the

next positive or negative clock edge. Figure5: shows general timing. DQS is driven by the DDR SDRAM

along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state

coincident with the last data-out element is known as the read post amble. Upon completion of a burst,

assuming no other commands have been initiated, the DQS will go High-Z.

Data from any READ burst may be concatenated with or truncated with data from a subsequent READ

command. In either case, a continuous flow of data can be maintained. The first data element from the new

burst follows either the last element of a completed burst or the last desired data element of a longer burst

which is being truncated. The new READ command should be issued x cycles after the first READ

command, where x equals the number of desired data element pairs (pairs are required by the 32 prefects

architecture). This is shown in Figure6:. A READ command can be initiated on any clock cycle following a

previous READ command. Non-consecutive READ data is shown for illustration in Figure7:. Full-speed

random read accesses within a page (or pages) can be performed as shown in Figure8:.

Data from any READ burst may be truncated with a BURST READ STOP command, as shown in

Figure9:The BURST READ STOP latency is equal to the read (CAS ) latency.

Data from any READ burst must be completed or truncated before a subsequent WRITE command can be

issued. If truncation is necessary, the BURST READ STOP command must be used, as shown in Figure10:.

A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided

that AUTO PRECHARGE was not activated). The PRECHARGE command should be issued x cycles after

the READ command, where x equals the number of desired data element pairs. Note that part of the row

precharge time is hidden during the access of the last data elements.

PRELIMINARY DATE: 9/8/00

18

.

W946432AD

In the case of a READ being executed to completion, a PRECHARGE command issued at the optimum time

(as described above) provides the same operation that would result from the same READ burst with AUTO

PRECHARGE enabled. The disadvantage of the PRECHARGE command is that it requires that the

command and address buses be available at the appropriate time to issue the command. The advantage of

the PRECHARGE command is that it can be used to truncate bursts.

Figure5:READ BURST – REQUIRED CAS LATENCIES

READ BURST - REQUIRED CAS LATENCIES

CK

COMMAND READ

NOP

Bank,

ADDRESS

Col n

CL=3

DQS

DQ

DO

n

DON'T CARE

DO n = Data Out from column n

Burst Length = 4

Show with nominal tAC, tDQSCK, and tDQSQ

PRELIMINARY DATE: 9/8/00

.

19

W946432AD

Figure6:CONSECUTIVE READ BURSTS – REQUIRED CAS LATENCIES

CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES

CK

COMMAND

ADDRESS

DQS

READ

NOP

READ

NOP

Bank,

Col n

Bank,

Col n

CL=3

DO

DQ

n

b

DON'T CARE

DO n (or b) = Data Out from column n (or column b)

Burst Length = 4

Shown with nominal tAC, tDQSCK, and tDQSQ

Read commands shown must be to the same device

Figure7:NON – CONSECUTIVE READ BURSTS – REQUIRED CAS LATENCIES

NON CONSECUTIVE READ BURSTS - REQUIRED CAS LATENCIES

CK

COMMAND READ

NOP

READ

NOP

Bank,

ADDRESS

Col n

Bank,

Col b

CL=3

DQS

DQ

DO

n

b

DON'T CARE

DO n (or b) = Data Out from column n (or column b)

Burst Length = 4

Shown with nominal tAC, tDQSCK, and tDQSQ

PRELIMINARY DATE: 9/8/00

.

20

W946432AD

Figure8:RANDOM READ ACCESSES – REQUIRED CAS LATENCIES

RANDOM READ ACCESSES - REQUIRED CAS LATENCIES

CK

COMMAND

ADDRESS

DQS

READ

NOP

Bank,

Col n

Bank,

Col x

Bank,

Col b

Bank,

Col g

CL=3

DO DO

DO

x'

DO

b

DO

b'

DO

DQ

n

x

g

n'

DON'T CARE

DO n, etc. = Data Out from column n, etc.

n', etc. = the next Data Out following DO n, etc. according to the programmed burst order

Burst Length = 4

Reads are to active rows in any banks

Shown with nominal tAC, tDQSCK, and tDQSQ

Figure9:BURST READ STOP– REQUIRED CAS LATENCIES

TERMINATING A READ BURST - REQUIRED CAS LATENCIES

CK

COMMAND

ADDRESS

DQS

READ

NOP

BST

NOP

Bank,

Col n

CL=3

DO

DQ

n

DON'T CARE

DO n = Data Out from column n

Cases shown are bursts of 8 terminated after 4 data elements

Shown with nominal tAC, tDQSCK, and tDQSQ

21

W946432AD

Figure10:READ TO WRITE – REQUIRED CAS LATENCIES

READ TO WRITE - REQUIRED CAS LATENCIES

CK

COMMAND

ADDRESS

DQS

READ

BST

NOP

WRITE

NOP

Bank,

Col n

Bank,

Col b

CL=3

tDQSS

DO

DQ

DM

n

DON'T CARE

DO n (or b) = Data Out from column n (or column b)

Burst Length = 4

Data In elements are applied following DI b in the programmed order

Shown with nominal tAC, tDQSCK, and tDQSQ

Figure11:READ TO PRECHARGE – REQUIRED CAS LATENCIES

READ TO PRECHARGE - REQUIRED CAS LATENCIES

CK

COMMAND

ADDRESS

DQS

READ

NOP

PRE

NOP

ACT

t

RP

Bank,

Col n

Bank

Bank,

Row

(a or all)

CL=3

DO

DQ

n

DON'T CARE

DO n (or b) = Data Out from column n Cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8

Shown with nominal tAC, tDQSCK, and tDQSQ

22

W946432AD

WRITEs

The starting column and bank addresses are provided with the WRITE command, and AUTO PRECHARGE

is either enabled or disabled for that access. If AUTO PRECHARGE is enabled (A8=HIGH), the row being

accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is disabled (A8=LOW),

the row will remain open for subsequent accesses.

During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS

following the write command, and subsequent data elements will be registered on successive edges of DQS.

The LOW state on DQS between the WRITE command and the first rising edge is known as the write

preamble; the LOW state on DQS following the last data-in element is known as the write post amble. The

time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with

a relatively wide range (from 75% to 125% of 1 clock cycle), Figure12: show the two extremes of tDQSS for a

burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQS will

remain High-Z and any additional input data will be ignored.

Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In

either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on

any positive edge of clock following the previous WRITE command. The first data element from the new

burst is applied after either the last element of a completed burst or the last desired data element of a longer

burst, which is being truncated. The new WRITE command should be issued x cycles after the first WRITE

command, where x equals the number of desired data element pairs Figure13: show concatenated bursts of

4. An example of non-consecutive WRITEs is shown in. 0 Full-speed random write accesses within a page or

pages can be performed as shown in. Figure15: Data for any WRITE burst may be followed by a subsequent

READ command. To follow a WRITE without truncating the write burst, tWTR should be met as shown in

Figure16:.

Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE

without truncating the write burst, tWR should be met as shown in 0.

Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in

Figure18: Figure19:. Note that only the data-in pairs that are registered prior to the tWR period are written to

the internal array, and any subsequent data-in should be masked with DM, as shown in Figure18: Figure19:.

Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t

RP is met.

POWER-DOWN

Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down

occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs

when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down

deactivates the input and output buffers, excluding CK, CK and CKE. For maximum power savings, the user

has the option of disabling the DLL prior to entering power-down. In that case, the DLL must be enabled after

exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,

power-down duration is limited by the refresh requirements of the device, so in most applications, the self-

refresh mode is preferred over the DLL-disabled power-down mode.

In power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM,

and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is

registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied

one clock cycle later.

23

W946432AD

Figure12:WRITE BURST – DQSS

WRITE BURST - DQSS

T0

T1

T2

T3

T4

T5

T6

T7

CK

COMMAND WRITE

NOP

Bank,

ADDRESS

Col b

t

DQSS

DQS

DQ

DI

b

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

A non-interrupted burst of 4 is shown

A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)

Figure13:WRITE TO WRITE – DQSS

WRITE TO WRITE - DQSS

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9 T10 T11

CK

COMMAND WRITE

NOP

WRITE

NOP

Bank,

ADDRESS

Bank,

Col n

Col b

t

DQSS

DQS

DQ

DI

n

b

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

A non-interrupted burst of 4 is shown

PRELIMINARY DATE: 9/8/00

24

.

W946432AD

Figure14:WRITE TO WRITE DQSS, NON – CONSECUTIVE

WRITE TO WRITE DQSS, NON - CONSECUTIVE

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

COMMAND WRITE

NOP

WRITE

NOP

Bank,

ADDRESS

Bank,

Col n

Col b

DQSS

t

DQS

DQ

DI

n

b

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

A non-interrupted burst of 4 is shown

Each Write command may be to any bank, and may be to the same or different devices

Depending on external components

Figure15:RANDOM WRITE CYCLES – DQSS

RANDOM WRITE CYCLES - DQSS

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

COMMAND

ADDRESS

WRITE

Bank,

Col b

Bank,

Col x

Bank,

Col n

Bank,

Col a

Bank,

Col g

tDQSS

DQS

DQ

DI

b

DI

b'

DI

x

DI

x'

DI

n

DI

n'

DI

a

DI

a'

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

b', etc. = the next Data In following DI b, etc. according to the programmed burst order

Programmed Burst Length = 2, 4 or 8 in cases shown

PRELIMINARY DATE: 9/8/00

25

.

W946432AD

Figure16:WRITE TO READ – DQSS, NON – INTERRUPTING

WRITE TO READ - DQSS, NON - INTERRUPTING

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10 T11

CK

COMMAND

ADDRESS

WRITE

NOP

READ

NOP

tWTR

Bank,

Col b

Bank,

Col n

tDQSS

CL=3

DQS

DQ

DI

b

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

A non-interrupted burst of 4 is shown

tWTR is referenced from the first postive CK edge after the last Data In pair

A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)

The READ andWRITE commands may be to any bank, and may be to the same or different devices

In the case where the READ and WRITE commands are to different devices, tWTR need not be met,

and the READ command can be applied earlier

tWTR = 2 tCK for optional CL = 1.5 (otherwise tWTR = 1 Tck)

Figure17:WRITE TO PRECHARGE - DQSS, NON - INTERRUPTING

WRITE TO PRECHARGE - DQSS, NON-INTERRUPTING

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9 T10 T11

CK

COMMAND WRITE

NOP

PRE

t

WTR

Bank a,

ADDRESS

Bank

Col b

(a or all)

t

DQSS

tRP

DQS

DQ

DI

b

DM

DON'T CARE

DI b, etc. = Data In for column b, etc.

A non-interrupted burst of 4 is shown

tWTR is referenced from the first postive CK edge after the last Data In pair

A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)

PRELIMINARY DATE: 9/8/00

.

26

W946432AD

Figure18:WRITE TO PRECHARGE – DQSS, INTERRUPTING

WRITE TO PRECHARGE - DQSS, INTERRUPTING

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9 T10 T11

CK

COMMAND WRITE

NOP

WTR

PRE

NOP

t

Bank a,

ADDRESS

Bank

(a or all)

Col b

t

DQSS

tRP

*2

DQS

DQ

DI

b

DM

*1

DON'T CARE

DI b = Data In for column b

A interrupted burst of 4 or 8 is shown, 2 data elements are written

1 subsequent element of Data In is applied in the programmed order following DI b

tWTR is referenced from the first postive CK edge after the last desired Data In pair

The PRECHARGE command masks the last two data elements in the burst

A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)

*1 = can be don't care for programmed burst length of 4

*2 = for programmed burst length of 4, DQS becomes don't care at this point

Figure19:WRITE TO PRECHARGE – DQSS, ODD NUMBER OF DATA, INTERRUPTING

WRITE TO PRECHARGE - DQSS, ODD NUMBER OF DATA, INTERRUPTING

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9 T10 T11

CK

COMMAND WRITE

NOP

PRE

NOP

tWTR

Bank a,

ADDRESS

Bank

Col b

(a or all)

tDQSS

tRP

*2

DQS

DQ

DI

b

DM

*1

DON'T CARE

DI b = Data In for column b

A interrupted burst of 4 or 8 is shown, 1 data element is written

tWTR is referenced from the first postive CK edge after the last desired Data In pair

The PRECHARGE command masks the last two data elements in the burst

A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled)

*1 = can be don't care for programmed burst length of 4

*2 = for programmed burst length of 4, DQS becomes don't care at this point

PRELIMINARY DATE: 9/8/00

27

.

W946432AD

Figure20:POWER - DOWN

POWER - DOWN

CK

tIS

CKE

COMMAND VALID

NOP

VALID

No column

access

in progress

Enter power-down

mode

Enter power-down

mode

DON'T CARE

Figure21:DATA INPUT (WRITE) TIMING

tD^DQ^AS^TL^{A INPUT (WRITE) TIMING}

t

DQSH

DQS

DQ

t

DS

t

DH

t

DS

DM

t_DH

DON'T CARE

Dl n = Data In for column n

Burst Length = 4

order following Dl n

PRELIMINARY DATE: 9/8/00

.

28

W946432AD

Figure22:DATA OUTPUT (READ) TIMING

DATA OUTPUT (READ) TIMING

t

DQSQ

nom

t_DQSQ

max

DQS

DQ

t

DV

t

DQSQ

min

1.tDQSQ max occurs when DQS is earliest among DQS signals to transition.

2.tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition.

3.tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions.

4.Burst Length = 4

PRELIMINARY DATE: 9/8/00

.

29

W946432AD

Figure23:POWER – DOWN MODE

POWER- DOWN MODE

tCK

tCH tCL

CK

tIS tIH

tIS

CKE

VALID*

NOP

VALID

COMMAND

t_ISt_IH

ADDR VALID

DQS

DQ

DM

Enter

Exit

Power-Down

Mode

Power-Down

Mode

DON'T CARE

No column accresses are allowed to be in progress at the Power-Down is entered

* = If this command is a PRECHARGE (or if the device is already in the idle state) then the Power-Down

mode shown is Precharge Power Down. If this command is an ACTIVE (or if at least one row is already

active) then the Power-Down mode shown is Active Power Down

30

W946432AD

Figure24:AUTO REFRESH MODE

AUTO REFRESH MODE

tCK

tCH tCL

CK

tIS

t_IH

CKE

tIS tIH

NOP

COMMAND

A0-A7

PRE

NOP

AR

NOP

AR

NOP

ACT

RA

BA

A9,A10

A8

ALL BANKS

ONE BANK

*Bank(s)

tIS tIH

BA0,BA1

DQS

DQ

DM

tRP

tRC

DON'T CARE

* = "Don't Care", if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e. must precharge all active banks)

PRE = PRECHARGE, ACT = ACTIVE, RA ROW Address, BA = BANK Address, AR = AUTOREFRESH

NOP commands are shown for ease of illustration; other valid commands may be possible at these time

DM, DQ and DQS signals are all "Do'nt Care"/High-z for operations shown

31

W946432AD

Figure25:SELF REFRESH MODE

SELF REFRESH MODE

clock must be before

t_CHt_CL

exiting Self Refresh Mode

CK

t_ISt_IHt_IS

t_IS

tCK

CKE

COMMAND

ADDR

t_ISt_IH

VALID

NOP

AR

NOP

VALID

DQS

DQ

DM

tRP*

tXSNR/

t_SNR**

Enter

Self Refresh

Mode

Exit

Self Refresh

Mode

DON'T CARE

* = Device must be in tje "All banks idle" state prior to entering Self Refresh Mode

** = tXNR is required before any non-READ command can be applied, and tSNRD (200 cycles of CLK)

are required befor READ command can be applied.

32

W946432AD

Figure26:READ – WITHOUT AUTO PRECHARGE

READ-WITHOUT AUTO PRECHARGE

tCK

tCH tCL

CK

tIS tIH

CKE

tIS tIH

NOP

COMMAND

A0-A7

READ

NOP

PRE

NOP

ACT

RA

NOP

t_ISt_IH

Col n

A9,A10

RA

t_ISt_IH

ALL BANKS

A8

BA0,BA1

DM

DIS AP

tIS tIH

ONE BANK

*Bank x

Bank x

CL = 3

tRP

tDQSCK

tRPST

tAC/tDQSCK=min

DQS

tRPRE

min

tLZ

min

t_HZ

min

DO

DQ

n

tLZ

min

t_AC

min

t_DQSCK

tAC/tDQSCK=max

DQS

tRPST

tRPRE

max

tHZ

max

DO

n

DQ

tLZ

max

t_AC

max

DON'T CARE

DO n = Data Out from column n

Burst Length = 4

DIS AP = Disable Autoprecharge

* = "Don't Care", if A8 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

33

W946432AD

Figure27:READ - WITH AUTO PRECHARGE

READ-WITH AUTO PRECHARGE

CK

t

CH CL

t

CK

tIS tIH

CKE

COMMAND

A0-A7

tIS tIH

NOP

READ

NOP

ACT

RA

NOP

IS IH

t

Col n

A9,A10

A8

RA

EN AP

IS IH

RA

t

Bank x

BA0,BA1

DM

Bank x

CL = 3

RP

t

tDQSCK

tRPST

AC DQSCK=min

t

/t

tRPRE

min

DQS

tLZ

min

HZ

t

min

DO

DQ

n

tLZ

min

tAC

min

tDQSCK

max

tAC/tDQSCK=max

DQS

tRPST

tRPRE

tHZ

max

DO

n

DQ

LZ

max

t

tAC

max

DON'T CARE

DO n = Data Out from column n

Burst Length = 4

EN AP = Enable Autoprecharge

ACT = ACTIVE, RA = Row Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

34

W946432AD

Figure28:BANK READ ACCESS

BANK READ ACCESS

t_CK

t_CHt_CL

t_ISt_IH

CK

CKE

t_ISt_IH

COMMAND

ACT

RA

NOP

READ

Col n

NOP

PRE

NOP

ACT

RA

A0-A7

A9,A10

RA

tIS tIH

ALL BANKS

A8

RA

tIS tIH

DIS AP

Bank x

ONE BANK

*Bank x

Bank x

BA0,BA1

Bank x

tRC

t_RAS

t_RP

CL=3

tRCD

DM

tDQSCK

min

tRPST

tAC/tDQSCK=min

DQS

tRPRE

tLZ

min

tHZ

min

DO

DQ

n

tLZ

min

t_AC

min

tDQSCK

max

tAC/tDQSCK=max

DQS

tRPST

t_RPRE

tHZ

max

DO

n

DQ

tLZ

max

t_AC

max

DON'T CARE

DO n = Data Out from column n

Burst Length = 4

DIS AP = Disable Autoprecharge

* = "Don't Care", if A8 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

Note that tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)

35

W946432AD

Figure29:WRITE – WITHOUT AUTO PRECHARGE

tCK

tCH tCL

WRITE - WITHOUT AUTO PRECHARGE

CK

t_ISt_IH

tIH

CKE

t_ISt_IH

COMMAND

A0-A7

NOP

WRITE

tIS tIH

NOP

PRE

NOP

ACT

RA

BA

Col n

A9,A10

tIS tIH

ALL BANKS

A8

DIS AP

t_ISt_IH

ONE BANK

*Bank x

BA0,BA1

Bank x

tWR

t_RP

tDSH

tDQSH

t_DQSS=min

t_WPST

t_DQSS

DQS

tWPRES

tWPRE

t_DQSL

DI

n

DQ

DM

t_DSS

t_WPST

t_DQSH

t_DQSS=max

tDQSS

DQS

t_WPRES

t_WPRE

tDQSL

DI

n

DQ

DM

DON'T CARE

DI n = Data IN from column n

Burst Length = 4

DIS AP = Disable Autoprecharge

* = "Don't Care", if A8 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

36

W946432AD

Figure30:WRITE – WITH AUTO PRECHARGE

WRITE - WITH AUTO PRECHARGE

tCH tCL

tCK

CK

IS IH

t

CKE

tIS tIH

NOP

COMMAND

A0-A7

WRITE

tIS tIH

NOP

ACT

RA

BA

Col n

A9,A10

EN AP

IS IH

A8

t

BA0,BA1

Bank x

tDAL

tDSH

_DQSStDQSH

tDSH

tDQSS=min

DQS

tWPST

t

tWPRES

DQSL

t

tWPRE

DI

n

DQ

DM

DSS

t

DSS

t

tDQSH

tDQSS=max

DQS

tWPST

DQSS

t

tWPRES

WPRE

tDQSL

t

DI

n

DQ

DM

DON'T CARE

DI n = Data IN from column n

Burst Length = 4

EN AP = Disable Autoprecharge

ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

37

W946432AD

Figure31:BANK WRITE ACCESS

BANK WRITE ACCESS

t

CK

tCH tCL

CK

t

IS

t

IH

CKE

t

COMMAND

A0-A7

NOP

ACT

NOP

WRITE

Col n

NOP

PRE

t

IS

t

IH

RA

A9,A10

RA

t

IS tIH

ALL BANKS

A8

DIS AP

t

IS

t

IH

ONE BANK

*Bank x

BA0,BA1

Bank x

t

RCD

tRAS

t

WR

t

DSH

WPST

t

DSH

DQSH

t

DQSS

t

DQSS=min

DQS

t

WPRES

t

DQSL

t

WPRE

DI

DQ

DM

n

t

DSS

t

DSS

t

DQSH

t

DQSS=max

DQS

t

WPST

t

DQSS

t

WPRES

WPRE

t

DQSL

t

DI

n

DQ

DM

DON'T CARE

DI n = Data IN from column n

Burst Length = 4

DIS AP = Disable Autoprecharge

* = "Don't Care", if A8 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

38

W946432AD

Figure32:WRITE – DM OPERATION

t

CK

tCH tCL

WRITE - DM OPERATION

CK

t

IS

t

IH

t

IH

CKE

t

COMMAND

A0-A7

NOP

WRITE

IS IH

NOP

PRE

NOP

ACT

RA

BA

t

Col n

A9,A10

IS IH

t

ALL BANKS

A8

DIS AP

IS IH

t

ONE BANK

*Bank x

BA0,BA1

Bank x

t

WR

t

RP

t

DSH

DQSH

tDSH

t

DQSS=min

DQS

tWPST

t

DQSS

t

WPRES

t

DQSL

t

WPRE

DI

DQ

DM

n

t

DSS

t

DSS

t

DQSH

t

DQSS=max

DQS

t

WPST

t

DQSS

t

WPRES

WPRE

t

DQSL

t

DI

n

DQ

DM

DON'T CARE

DI n = Data IN from column n

Burst Length = 4

DIS AP = Disable Autoprecharge

* = "Don't Care", if A8 is HIGH at this point

PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address

NOP commands are shown for ease of illustration; other commands may be valid at these times

39

W946432AD

PACKAGE DIMENSIONS

H

D

E

H

E

e

b

c

A2 A

A1

q

See Detail F

L

y

Seating Plane

L ₁

Controlling dimension

:

Millimeters

Dimension in mm

Dimension in inch

Symbol

Nom

Max

Min

Max Min

A

1

0.002 0.004 0.006 0.05

0.053 0.055 0.057 1.35

0.10 0.15

A

2

A

1.45

1.40

0.009

0.004

0.22

0.013 0.015

0.32

0.38

b

c

0.006

0.008

0.10 0.15

0.20

14.00

20.00

0.65

13.90

19.90

0.498

0.547 0.551 0.555

0.791

0.020 0.026 0.032

14.10

20.10

0.802

D

E

e

0.783 0.787

D

H

0.626

0.862

0.018

0.634

16.00 16.10

0.630

0.866

15.90

0.870 21.90 22.00 22.10

H_E

L

0.024 0.030

0.75

0.45 0.60

1.00

0.039

0.003

7

1

L

y

0.08

7

0

q

40


型号：	W946432AD
厂家：	WINBOND
描述：	512K X 4 BANKS X 32 BITS DDR SDRAM 512K ×4银行×32位DDR SDRAM 动态存储器双倍数据速率
文件：	总40页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W946432AD [WINBOND]

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