W964B6BBN80 [WINBOND]
1M WORD X 16BIT LOW POWER PSEUDO SRAM; 1M字X 16BIT低功耗模拟SRAM
| 型号： | W964B6BBN80 |
| 厂家： | 
WINBOND |
| 描述： | 1M WORD X 16BIT LOW POWER PSEUDO SRAM |
| 文件： | 总30页 (文件大小：888K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W964B6BBN
1M WORD × 16 BIT LOW POWER PSEUDO SRAM
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. PRODUCT OPTIONS ......................................................................................................................... 3
5. Ball DESCRIPTION............................................................................................................................. 4
6. BLOCK DIAGRAM .............................................................................................................................. 5
7. FUNCTION TRUTH TABLE ................................................................................................................ 6
8. ELECTRICAL CHARACTERISTICS................................................................................................... 7
Absolute Maximum Ratings .............................................................................................................. 7
Recommended Operation Conditions............................................................................................... 7
Capacitance ...................................................................................................................................... 8
DC Characteristics ............................................................................................................................ 8
AC Characteristics ............................................................................................................................ 9
Read Operation ..........................................................................................................................................9
Write Operation.........................................................................................................................................11
Power Down and Power Down Program Parameters ...............................................................................13
Other Timing Parameters .........................................................................................................................13
AC Test Conditions...................................................................................................................................13
9. TIMING WAVEFORMS ..................................................................................................................... 14
Read Timing #1 (OE Control Access)............................................................................................ 14
Read Timing #2 (CE1 Control Access) .......................................................................................... 15
Read Timing #2 (CE1 Control Access) .......................................................................................... 16
Read Timing #3 (Address Access after OE Control Access) ........................................................ 17
Read Timing #4 (Address Access after CE1 Control Access)....................................................... 18
Write Timing #1 (CE1 Control) ....................................................................................................... 19
Write Timing #2-1 ( WE Control, Single Write Operation).............................................................. 20
Write Timing #2 ( WE Control, Continuous Write Operation) ......................................................... 21
Read/Write Timing #1-1 (CE1 Control)........................................................................................... 22
Read/Write Timing #1-2 (CE1 Control)........................................................................................... 23
Publication Release Date: March 31, 2003
- 1 -
Revision A1
W964B6BBN
Read (OE Control) / Write ( WE Control) Timing #2-1 .................................................................. 24
Read (OE Control) / Write ( WE Control) Timing #2-2 .................................................................. 25
Power Down Program Timing ......................................................................................................... 26
Power Down Entry and Exit Timing................................................................................................. 26
Power-up Timing #1........................................................................................................................ 26
Power-up Timing #2........................................................................................................................ 27
Standby Entry Timing after Read or Write ...................................................................................... 27
10. PACKAGE DIMENSION.................................................................................................................. 28
TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 28
11. ORDERING INFORMATION........................................................................................................... 29
12. VERSION HISTORY ....................................................................................................................... 30
- 2 -
W964B6BBN
1. GENERAL DESCRIPTION
W964B6BBN is a 16M bits CMOS pseudo static random access memory (Pseudo SRAM), organized
as 1M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175 µm process
technology; W964B6BBN delivers fast access cycle time and low power consumption. It is suitable for
mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and
power dissipation is most concerned
2. FEATURES
• Asynchronous SRAM interface
• Fast access cycle time:
− tRC = 70 nS (-70), 80 nS (-80)
• Low power consumption:
− IDDA1 = 20 mA Max.
• Wide operating conditions:
− VDD = +2.3V to +2.7V
• Temperature
− TA = 0°C to +70°C
− TA = -25°C to +85°C (Extended temperature)
− TA = -40°C to +85°C (Industrial temperature)
− IDDS1 = 70 µA Max.
• Byte write control
3. PRODUCT OPTIONS
PARAMETER
W964B6BBN70
W964B6BBN80
80 nS Min.
70 µA Max.
20 mA
tRC
70 nS Min.
70 µA Max.
20 mA
IDDS1
IDDA1
VDD
2.3V to 2.7V
2.3V to 2.7V
Publication Release Date: March 31, 2003
Revision A1
- 3 -
W964B6BBN
4. BALL CONFIGURATION
Top view
1
2
3
4
5
6
A
B
C
D
E
F
LB
OE
UB
A0
A1
A2
CE2
DQ1
DQ3
DQ9
A3
A4
CE1
DQ2
DQ4
DQ5
DQ6
WE
DQ10 DQ11
A5
A6
VSS
DQ12
DQ13
A17
NC
A14
A12
A9
A7
VDD
VDD
A16
A15
A13
A10
VSS
DQ15 DQ14
DQ16 A19
DQ7
DQ8
NC
G
H
A18
A8
A11
( FBGA48 , 6 x 8mm , pitch 0.75mm )
5. BALL DESCRIPTION
SYMBOL
DESCRIPTION
Address input
A0 − A19
Chip Enable Input 1, Low: Enable
CE1
CE2
Chip Enable Input 2, High: Enable, Low: Enter Power Down mode
Write enable input
WE
OE
Output Enable input
Lower byte write control
Upper byte write control
LB
UB
Data inputs/outputs
Power supply
Ground
I/O0 − I/O15
VDD
VSS
NC
No Connection
- 4 -
W964B6BBN
6. BLOCK DIAGRAM
VDD
VSS
MEMORY
CELL
A0
to
ADDRESS
LATCH &
BUFFER
ROW
DECODER
ARRAY
A18
33,554,432 bits
DQ1
to
INPUT /
OUTPUT
BUFFER
INPUT DATA
LATCH &
OUTPUT
DATA
DQ8
SENSE /
SWITCH
DQ9
to
CONTROL
CONTROL
DQ16
COLUMN /
DECODER
ADDRESS
LATCH &
BUFFER
POWER
CONTROL
CE2
PE
CE1
WE
LB
TIMING
CONTROL
UB
OE
Publication Release Date: March 31, 2003
Revision A1
- 5 -
W964B6BBN
7. FUNCTION TRUTH TABLE
Data
Mode
Note CE2
A0-18 DQ1-8 DQ9-16
IDD
OE
X
UB
X
CE1 WE
LB
X
X
H
L
Retention
Standby
H
X
H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
IDDS
Yes
(Deselect)
Output
*1
H
X
*5
Disable
No Read
Read
H
Valid
Valid
Valid
Valid
Valid
X
H
L
Output
Valid
Output
Valid
H
L
*2
*4
L
IDDA
IDDP
Yes
Input
Write (Upper Byte)
Write (Lower Byte)
Write (Word)
H
L
L
H
L
Invalid
Valid
Input
Valid
L
H
X
Invalid
Input
Input
Valid
L
Valid
Power Down
*3
X
X
X
X
High-Z
High-Z
No/Yes
Notes: L = VIL, H = VIH, X can be either VIL or VIH High-Z = High impedance, KEY = Key Address.
,
*1: Output Disable mode should not be kept longer than 1 µS.
*2: Byte control at Read mode is not supported.
*3: Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IDDP current and data
retention depend on the selection of Power Down Program.
*4: Either or both LB and UB must be Low for Read operation.
*5: Can be either VIL or VIH
but must be valid before Read or Write.
- 6 -
W964B6BBN
8. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER
SYMBOL
VDD
VIN,
VALUE
UNIT
V
-
Voltage of VDD Supply Relative to VSS
Voltage at Any Pin Relative to VSS
Short Circuit Output Current
Storage Temperature
0.5 to +3.6
-0.5 to +3.6
±50
-55 to +125
V
VOUT
IOUT
mA
°C
TSTG
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operation Conditions
(Reference to VSS)
PARAMETER
NOTES
SYMBOL
VDD
VSS
VIH
MIN.
2.3
0
2.0
-0.3
0
MAX.
2.7
0
VDD +0.3
0.4
UNIT
V
V
V
V
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Ambient Temperature
Ambient Temperature
Ambient Temperature
Notes:
*1
*2
VIL
TA
70
°C
°C
°C
TA
-25
-40
85
TA
85
*1: Maximum DC voltage on input and I/O pins are VDD +0.3V. During voltage transitions, inputs may positive overshoot to
VDD +1.0V for periods of up to 5 nS.
*2: Minimum DC voltage on input and I/O pins are -0.3V. During voltage transitions, inputs may negative overshoot to -
1.0V for periods of up to 5 nS.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the datasheet. Users considering application outside the listed conditions are advised to contact their
Winbond representative beforehand.
Publication Release Date: March 31, 2003
- 7 -
Revision A1
W964B6BBN
Capacitance
Test conditions: TA = 25°C, f = 1.0 MHz
SYMBOL
CIN1
DESCRIPTION
TEST SETUP
TYP.
MAX.
UNIT
pF
VIN
Address Input Capacitance
Control Input Capacitance
Data Input/Output Capacitance
-
-
-
5
5
8
= 0V
VIN
CIN2
pF
= 0V
VIO
CIO
pF
= 0V
DC Characteristics
(Under Recommended Operating Conditions unless otherwise noted)
notes*1, *2, *3
PARAMETER
SYM.
ILI
TEST CONDITIONS
VIN = VSS to VDD
VSS to VDD,
MIN. MAX. UNIT
Input Leakage Current
Output Leakage Current
-1.0
-1.0
+1.0
+1.0
µA
µA
ILO
VOUT =
Output Disable
Output High Voltage
Level
Output Low Voltage Level
VDD VDD
=
VOH
VOL
1.8
-
-
V
V
, IOH = -0.5 mA
IOL = 1 mA
0.4
VDD VDD Max.,
=
VIN
= VIH or VIL
CE1
(TTL)
IDDS
-
-
3
mA
Standby
Current
= CE2 = VIH
VDD = VDD Max.,
VIN VDD
-0.2V,
VDD
-0.2V
VIN ≤ 0.2V or
≥
(CMOS)
IDDS1
70
µA
CE1
= CE2 ≥
tRC / tWC =
VDD = VDD Max.,
IDDA1
IDDA2
-
-
20
3
mA
mA
Minimum
VIN = VIH or VIL,
Active Current
tRC / tWC =
CE1
= VIL and CE2 =
1 µS
VIH IOUT = 0 mA
,
Notes:
*1: All voltages are reference to VSS.
*2: DC Characteristics are measured after following POWER-UP timing.
*3: IOUT depends on the output load conditions.
- 8 -
W964B6BBN
AC Characteristics
(Under Recommended Operating Conditions unless otherwise noted)
Read Operation
-70
-80
PARAMETER
SYM.
UNIT
NOTES
Min.
70
-
-
-
Max.
-
65
40
65
-
Min.
80
-
-
-
Max.
-
75
45
75
-
Read Cycle Time
tRC
tCE
tOE
tAA
tOH
nS
nS
nS
nS
nS
Chip Enable Access Time
Output Enable Access Time
Address Access Time
*1, *3
*1
*1
Output Data Hold Time
5
5
*1
tCLZ
tOLZ
tCHZ
tOHZ
tASC
5
0
-
-
-
5
0
-
-
-
nS
nS
nS
nS
nS
*2
*2
*2
*2
*4
CE1 Low to Output Low-Z
OE Low to Output Low-Z
CE1 High to Output High-Z
OE High to Output High-Z
Address Setup Time to CE1 Low
20
20
-
25
25
-
-
-
-5
-5
tASO
tASO[ABS]
30
10
-
-
35
10
-
-
nS
nS
*3, *5
*6
Address Setup Time to OE Low
LB / UB Setup Time to CE1 Low
tBSC
-5
-
-5
-
nS
tBSO
tAX
10
-
-
5
-
10
-
-
5
-
nS
nS
nS
LB / UB Setup Time to OE Low
Address Invalid Time
tCLAH
70
80
Address Hold Time from CE1 Low
Address Hold Time from OE Low
Address Hold Time from CE1 High
Address Hold Time from OE High
LB / UB Hold Time from CE1 High
LB / UB Hold Time from OE High
CE1 Low to OE Low Delay Time
OE Low to CE1 High Delay Time
CE1 High Pulse Width
tOLAH
tCHAH
tOHAH
tCHBH
tOHBH
tCLOL
tOLCH
tCP
40
-5
-
45
-5
-
nS
nS
nS
nS
nS
*9
-
-
-5
-
-5
-
-5
-
-5
-
-5
-
-5
-
25
35
12
1000
30
40
15
1000
nS *3, *5, *7, *8
-
-
-
-
nS
nS
*7
tOP
tOP[ABS]
25
12
1000
-
30
15
1000
-
nS
ns
*5, *7, *8
*6
OE High Pulse Width
Publication Release Date: March 31, 2003
Revision A1
- 9 -
W964B6BBN
Read Operation, Continued
Notes:
*1: The output load is 30 pF.
*2: The output load is 5 pF.
*3: The tCE is applicable if OE is brought to Low before CE1 goes Low and is also applicable if actual value of both or
either tASO or tCLOL is shorter than specified value.
*4: Applicable if OE is brought to Low before CE1 goes Low.
*5: The tASO, tCLOL(min.) and tOP(min.) are reference values when the access time is determined by tOE. If actual value of
each parameter is shorter than specified minimum value, tOE become longer by the amount of subtracting actual
value from specified minimum value.
For example, if actual tASO, tASO(actual), is shorter than specified minimum value, tASO(min), during OE control
access (ie., CE1 stays Low), the tOE become tOE(max.) + tASO(min.) - tASO(actual).
*6: The tASO[ABS] and tOP[ABS] is the absolute minimum value during OE control access.
*7: If actual value of either tCLOL or tOP is shorter than specified minimum value, both tOLAH and tOLCH become tRC(min.) -
tCLOL(actual) or tRC(min.) - tOP(actual).
*8: Maximum value is applicable if CE1 is kept at low.
- 10 -
W964B6BBN
AC Characteristics, Continued
Write Operation
-70
-80
PARAMETER
SYM.
UNIT
NOTES
Min.
70
0
Max.
-
Min.
80
0
Max.
-
Write Cycle Time
tWC
tAS
tAH
tCS
nS
nS
nS
nS
*1
*2
*2
Address Setup Time
Address Hold Time
-
-
-
-
35
0
40
0
1000
1000
CE1 Write Setup Time
tCH
tWS
tWH
tBS
0
0
1000
0
0
1000
nS
nS
nS
nS
CE1 Write Hold Time
WE Setup Time
-
-
-
-
-
-
0
0
WE Hold Time
-5
-5
LB and UB Setup Time
tBH
-5
-
-5
-
nS
LB and UB Hold Time
OE Setup Time
tOES
tOEH
0
1000
0
1000
nS
nS
nS
nS
*3
*3, *4
*5
30
12
-5
1000
35
15
-5
1000
OE Hold Time
tOEH[ABS]
tOHCL
-
-
-
-
*6
OE High to CE1 Low Setup Time
OE High to Address Hold Time
CE1 Write Pulse Width
tOHAH
-5
-
-5
-
nS
*7
tCW
TWP
tWRC
tWR
tDS
45
45
10
10
15
0
-
50
50
15
15
20
0
-
nS
nS
nS
nS
nS
nS
nS
*1, *8
-
-
*1, *8
WE Write Pulse Width
-
-
*1, *9
CE1 Write Recovery Time
1000
1000
*1, *3, *9
WE Write Recovery Time
Data Setup Time
-
-
-
-
-
-
Data Hold Time
tDH
tCP
12
15
*9
CE1 High Pulse Width
Publication Release Date: March 31, 2003
Revision A1
- 11 -
W964B6BBN
Write Operation, Continued
Notes:
*1: Minimum value must be equal or greater than the sum of actual tCW (or tWP) and tWRC (or tWR).
*2: New write address is valid from either CE1 or WE is brought to High.
*3: The tOEH is specified from end of tWC(min.). The tOEH(min.) is a reference value when the access time is determined
by tOE.
If actual value, tOEH(actual) is shorter than specified minimum value, tOE become longer by the amount of subtracting
actual value from specified minimum value.
*4: The tOEH(max.) is applicable if CE1 is kept at Low and both WE and OE are kept at High.
*5: The tOEH[ABS] is the absolute minimum value if write cycle is terminated by WE and CE1 stays Low.
*6: tOHCL(min.) must be satisfied if read operation is not performed prior to write operation.
In case OE is disabled after tOHCL(min.), WE Low must be asserted after tRC(min.) from CE1 Low. In other words,
read operation is initiated if tOHCL(min.) is not satisfied.
*7: Applicable if CE1 stays Low after read operation.
*8: tCW and tWP is applicable if write operation is initiated by CE1 and WE , respectively.
*9: tWRC and tWR is applicable if write operation is terminated by CE1 and WE , respectively.
The tWR(min.) can be ignored if CE1 is brought to High together or after WE is brought to High. In such case, the
tCP(min.) must be satisfied.
- 12 -
W964B6BBN
AC Characteristics, Continued
Power Down and Power Down Program Parameters
-70
-80
PARAMETER
SYM.
UNIT NOTES
Min. Max. Min. Max.
CE2 Low Setup Time for Power Down Entry
CE2 Low Hold Time after Power Down Entry
tCSP
10
70
-
-
10
80
-
-
nS
nS
tC2LP
CE1 High Setup Time following CE2 High after
Power Down Exit
tCHS
10
-
10
-
nS
Other Timing Parameters
PARAMETER
-70
-80
SYM.
UNIT NOTES
Min. Max. Min. Max.
tCHOX
tCHWX
10
10
-
-
10
10
-
-
nS
CE1 High to OE Invalid Time for Standby Entry
nS
*1
CE1 High to WE Invalid Time for Standby Entry
CE2 Low Hold Time after Power-up
tC2LH
tC2HL
50
50
-
-
50
50
-
-
*2
*3
µS
µS
CE2 High Hold Time after Power-up
CE1 High Hold Time following CE2 High after
Power-up
Input Transition Time
tCHH
350
1
-
350
1
-
*2
*4
µS
tT
25
25
nS
Notes:
*1: Some data might be written into any address location if tCHWX(min.) is not satisfied.
*2: Must satisfy tCHH(min.) after tC2LH(min.).
*3: Requires Power Down mode entry and exit after tC2HL.
*4: The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5 nS, it may violate AC
specified of some timing parameters.
AC Test Conditions
SYMBOL
VIH
DESCRIPTION
Input High Level
Input Low Level
Input Timing Measurement Level
Input Transition Time
TEST SETUP
VALUE
2.0
0.4
1.1
5
UNIT
V
V
V
nS
NOTE
VDD = 2.3V to 2.7V
VDD = 2.3V to 2.7V
VDD = 2.3V to 2.7V
Between VIL and VIH
VIL
VREF
TT
Publication Release Date: March 31, 2003
Revision A1
- 13 -
W964B6BBN
9. TIMING WAVEFORMS
Read Timing #1 (OE Control Access)
tRC
tRC
ADDRESS
CE1
ADDRESS VALID
ADDRESS VALID
tCE
tOHAH
tASO
tOHAH
tOLCH
tCLOL
tOE
tOP
tOE
OE
tASO
tBSO
tOHBH
tBSO
tOHBH
LB / UB
tOHZ
tOHZ
tOH
tOLZ
tOH
tOLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
- 14 -
W964B6BBN
Timing Waveforms, Continued
Read Timing #2 (CE1 Control Access)
tRC
tRC
ADDRESS
CE1
ADDRESS VALID
ADDRESS VALID
tASC
tCE
tCHAH
tASC
tCHAH
tCE
tCP
OE
tBSC
tCHBH
tBSC
tCHBH
LB / UB
tCHZ
tOH
tCHZ
tOH
tOLZ
tCLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
Publication Release Date: March 31, 2003
Revision A1
- 15 -
W964B6BBN
Timing Waveforms, Continued
Read Timing #2 (CE1 Control Access)
tRC
tRC
ADDRESS
CE1
ADDRESS VALID
ADDRESS VALID
tASC
tCE
tCHAH
tASC
tCHAH
tCE
tCP
OE
tBSC
tCHBH
tBSC
tCHBH
LB / UB
tCHZ
tOH
tCHZ
tOH
tOLZ
tCLZ
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
- 16 -
W964B6BBN
Timing Waveforms, Continued
Read Timing #3 (Address Access after OE Control Access)
tRC
tRC
ADDRESS
ADDRESS VALID
ADDRESS VALID
tOHAH
tASO
tOLAH
tAX
tAA
CE1
OE
tOE
tOHZ
tOHBH
tBSO
LB / UB
tOLZ
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
Publication Release Date: March 31, 2003
Revision A1
- 17 -
W964B6BBN
Timing Waveforms, Continued
Read Timing #4 (Address Access after CE1 Control Access)
tRC
tRC
ADDRESS
CE1
ADDRESS VALID
ADDRESS VALID
tCHAH
tASC
tCLAH
tAX
tAA
tCE
tCHZ
OE
tCHBH
tBSC
LB / UB
tCLZ
tOH
tOH
DQ
(Output)
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2, PE and WE must be High for entire read cycle.
Either or both LB and UB must be Low when both CE1 and OE are Low.
- 18 -
W964B6BBN
Timing Waveforms, Continued
Write Timing #1 (CE1 Control)
tWC
ADDRESS
CE1
ADDRESS VALID
tAS
tAS
tAH
tWS
tWC
tWRC
tWS
tWH
tBH
WE
tBS
tBS
LB / UB
tOHCL
OE
tDS
tDH
DQ
(Intput)
VALID DATA INTPUT
Note: CE2 and PE must be High for entire write cycle.
Publication Release Date: March 31, 2003
Revision A1
- 19 -
W964B6BBN
Timing Waveforms, Continued
Write Timing #2-1 ( WE Control, Single Write Operation)
tWC
ADDRESS
CE1
ADDRESS VALID
t
OHAH
tAS
tCS
tAH
tAS
tCH
tCP
tOHCL
tWP
tWR
WE
tBH
tBS
tBH
LB / UB
tOES
tOHZ
OE
tDS
tDH
DQ
(Intput)
VALID DATA INTPUT
Note: CE2 and PE must be High for entire write cycle.
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W964B6BBN
Timing Waveforms, Continued
Write Timing #2 ( WE Control, Continuous Write Operation)
tWC
ADDRESS
CE1
ADDRESS VALID
t
OHAH
tAS
tCS
tAH
tAS
tOHCL
tWP
tWR
WE
tOHBH
tBS
tBH
tBS
LB / UB
tOES
tOHZ
OE
tDS
tDH
DQ
(Intput)
VALID DATA INTPUT
Note: CE2 and PE must be High for entire write cycle.
Publication Release Date: March 31, 2003
Revision A1
- 21 -
W964B6BBN
Timing Waveforms, Continued
Read/Write Timing #1-1 (CE1 Control)
tWC
ADDRESS
CE1
ADDRESS VALID
tCHAH
tAS
tAH
tAS
tCP
tCW
tWRC
tWH
tWS
tWH
tWS
tCLOL
tBSO
WE
tCHBH
tBS
tBH
LB / UB
tOHCL
OE
tCHZ
tOLZ
tOH
tDS
tDH
DQ
(Intput)
VALID DATA INTPUT
VALID DATA INTPUT
Note: Write address is valid from either CE1 or WE of last falling edge.
- 22 -
W964B6BBN
Timing Waveforms, Continued
Read/Write Timing #1-2 (CE1 Control)
tRC
ADDRESS
CE1
ADDRESS VALID
WRITE ADDRESS
tWRC tASC
tCHAH
tAS
t
WRC(min)
tCP
tWH
tWS
tWH
t
WS
WE
tBH
tBSC
tOE
tBS
tCHBH
LB / UB
tOEH
tOHCL
OE
DQ
tCHZ
tDH
tCLZ
tOH
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: The tOEH is specified from the time satisfied both tWRC and tWR(min).
Publication Release Date: March 31, 2003
Revision A1
- 23 -
W964B6BBN
Timing Waveforms, Continued
Read (OE Control) / Write ( WE Control) Timing #2-1
tWC
ADDRESS
CE1
WRITE ADDRESS
READ ADDRESS
tASO
t
t
OHAH
tAS
tAH
Low
tWP
tWR
tOEH
tOEH
WE
OHBH
tBS
tBH
LB / UB
tOES
OE
tOHZ
tOLZ
tOH
tDS
tDH
DQ
(Intput)
VALID DATA INTPUT
VALID DATA INTPUT
Note: CE1 can be tied to Low for WE and OE controlled operation.
When CE1 is tied to Low, output is exclusively controlled by OE .
- 24 -
W964B6BBN
Timing Waveforms, Continued
Read (OE Control) / Write ( WE Control) Timing #2-2
tRC
ADDRESS
CE1
ADDRESS VALID
WRITE ADDRESS
tOHAH
tAS
tASO
tOEH
Low
tWR
WE
LB / UB
OE
tOHBH
tBH
tBSO
tBS
tOE
t
OES
tOHZ
tDH
tOLZ
tOH
DQ
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE1 can be tied to Low for WE and OE controlled operation.
When CE1 is tied to Low, output is exclusively controlled by OE .
Publication Release Date: March 31, 2003
Revision A1
- 25 -
W964B6BBN
Timing Waveforms, Continued
Power Down Program Timing
CE1
tEPS
tEP
tEPH
PE
tEAS
tEAH
ADDRESS
(A20-16)
KEY
Note: CE2 must be High for Power Down Program operation.
Any other inputs not specified above can be either High or Low.
Power Down Entry and Exit Timing
CE1
tCHS
CE2
tCSP
tC2LP
tCHH (tCHHN)
High-Z
DQ
Power Down Entry
Power Down Mode
Power Down Exit
Note: This Power Down mode can be also used for Power-up #2 below except that tCHHN can not be used at Power-up timing.
Power-up Timing #1
CE1
tCHS
tC2LH
tCHH
CE2
VDD
VDD min
0V
Note: The tC2LH specifies after VDD reaches specified minimum level.
Timing Waveforms, Continued
- 26 -
W964B6BBN
Power-up Timing #2
CE1
CE2
tCHS
tC2HL
tCSP
tC2LP
tCHH
tC2HL
VDD
VDD min
0V
Note: The tC2HL specifies from CE2 low to High transition after VDD reaches specified minimum level.
CE1 must be brought to High prior to or together with CE2 Low to High transition.
Standby Entry Timing after Read or Write
CE1
tCHOX
tCHWX
OE
WE
Active (Read)
Standby
Active (Write)
Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC(min)
period from either last address transition of A0, A1 and A2, or CE1 Low to High transition.
Publication Release Date: March 31, 2003
- 27 -
Revision A1
W964B6BBN
10. PACKAGE DIMENSION
TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)
- 28 -
W964B6BBN
11. ORDERING INFORMATION
OPERATING
PART NO.
SPEED
PACKAGE
TEMPERATURE
W964B6BBN70
W964B6BBN70E
W964B6BBN70I
W964B6BBN80
W964B6BBN80E
W964B6BBN80I
Notes:
70 nS
70 nS
70 nS
80 nS
80 nS
80 nS
0 to 70
-25 to 85
-40 to 85
0 to 70
-25 to 85
-40 to 85
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
TFBGA 48, 6 mm x 8 mm, BALL PITCH 0.75 mm
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in
applications where personal injury might occur as a consequence of product failure.
Publication Release Date: March 31, 2003
- 29 -
Revision A1
W964B6BBN
12. VERSION HISTORY
VERSION
DATE
March 31, 2003
PAGE
DESCRIPTION
Create new document
A1
-
Headquarters
Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
2727 North First Street, San Jose,
CA 95134, U.S.A.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 886-3-5770066
FAX: 1-408-5441798
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
TEL: 81-45-4781881
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 30 -
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