W9751G8JB-18 [WINBOND]
DDR DRAM, 64MX8, 0.35ns, CMOS, PBGA60, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60;
| 型号： | W9751G8JB-18 |
| 厂家： | 
WINBOND |
| 描述： | DDR DRAM, 64MX8, 0.35ns, CMOS, PBGA60, 8 X 12.50 MM, ROHS COMPLIANT, WBGA-60 动态存储器 双倍数据速率 |
| 文件： | 总86页 (文件大小：1458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W9751G8JB
16M 4 BANKS 8 BIT DDR2 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ...................................................................................................................4
FEATURES...........................................................................................................................................4
KEY PARAMETERS .............................................................................................................................5
BALL CONFIGURATION ......................................................................................................................6
BALL DESCRIPTION............................................................................................................................7
BLOCK DIAGRAM ................................................................................................................................8
FUNCTIONAL DESCRIPTION..............................................................................................................9
Power-up and Initialization Sequence...................................................................................................9
Mode Register and Extended Mode Registers Operation ...................................................................10
7.1
7.2
7.2.1
Mode Register Set Command (MRS)...............................................................................10
Extend Mode Register Set Commands (EMRS) ..............................................................11
Extend Mode Register Set Command (1), EMR (1)................................................11
DLL Enable/Disable................................................................................................12
Extend Mode Register Set Command (2), EMR (2)................................................13
Extend Mode Register Set Command (3), EMR (3)................................................14
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
Extended Mode Register for OCD Impedance Adjustment ....................................16
OCD Impedance Adjust..........................................................................................16
Drive Mode .............................................................................................................17
On-Die Termination (ODT)...............................................................................................18
ODT related timings .........................................................................................................18
MRS command to ODT update delay.....................................................................18
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.4
7.2.5
7.2.5.1
7.3
Command Function.............................................................................................................................20
7.3.1
Bank Activate Command..................................................................................................20
Read Command...............................................................................................................20
Write Command...............................................................................................................21
Burst Read with Auto-precharge Command.....................................................................21
Burst Write with Auto-precharge Command.....................................................................21
Precharge All Command..................................................................................................21
Self Refresh Entry Command ..........................................................................................21
Self Refresh Exit Command.............................................................................................22
Refresh Command...........................................................................................................22
No-Operation Command..................................................................................................23
Device Deselect Command..............................................................................................23
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.4
Read and Write access modes ...........................................................................................................23
7.4.1
7.4.1.1
Posted CAS ....................................................................................................................23
Examples of posted CAS operation......................................................................23
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7.4.2
7.4.3
7.4.4
7.4.5
Burst mode operation.......................................................................................................24
Burst read mode operation...............................................................................................25
Burst write mode operation ..............................................................................................25
Write data mask...............................................................................................................26
7.5
7.6
Burst Interrupt .....................................................................................................................................26
Precharge operation............................................................................................................................27
7.6.1
7.6.2
Burst read operation followed by precharge.....................................................................27
Burst write operation followed by precharge ....................................................................27
7.7
Auto-precharge operation ...................................................................................................................27
7.7.1
7.7.2
Burst read with Auto-precharge .......................................................................................28
Burst write with Auto-precharge.......................................................................................28
7.8
7.9
Refresh Operation...............................................................................................................................29
Power Down Mode..............................................................................................................................29
7.9.1
7.9.2
Power Down Entry ...........................................................................................................30
Power Down Exit..............................................................................................................30
7.10 Input clock frequency change during precharge power down .............................................................30
OPERATION MODE ...........................................................................................................................31
8.
9.
8.1
8.2
8.3
8.4
8.5
Command Truth Table ........................................................................................................................31
Clock Enable (CKE) Truth Table for Synchronous Transitions ...........................................................32
Data Mask (DM) Truth Table...............................................................................................................32
Function Truth Table...........................................................................................................................33
Simplified Stated Diagram...................................................................................................................36
ELECTRICAL CHARACTERISTICS ...................................................................................................37
Absolute Maximum Ratings ................................................................................................................37
Operating Temperature Condition.......................................................................................................37
Recommended DC Operating Conditions...........................................................................................37
ODT DC Electrical Characteristics ......................................................................................................38
Input DC Logic Level...........................................................................................................................38
Input AC Logic Level...........................................................................................................................38
Capacitance........................................................................................................................................39
Leakage and Output Buffer Characteristics ........................................................................................39
DC Characteristics ..............................................................................................................................40
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10 IDD Measurement Test Parameters....................................................................................................42
9.11 AC Characteristics ..............................................................................................................................43
9.11.1
9.11.2
AC Characteristics and Operating Condition for -18 speed grade ...................................43
AC Characteristics and Operating Condition for -25/25I/-3 speed grades........................45
9.12 AC Input Test Conditions ....................................................................................................................65
9.13 Differential Input/Output AC Logic Levels ...........................................................................................65
9.14 AC Overshoot / Undershoot Specification...........................................................................................66
9.14.1
9.14.2
AC Overshoot / Undershoot Specification for Address and Control Pins: ........................66
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins:..........66
10.
TIMING WAVEFORMS .......................................................................................................................67
10.1 Command Input Timing.......................................................................................................................67
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10.2 Timing of the CLK Signals...................................................................................................................67
10.3 ODT Timing for Active/Standby Mode.................................................................................................68
10.4 ODT Timing for Power Down Mode ....................................................................................................68
10.5 ODT Timing mode switch at entering power down mode....................................................................69
10.6 ODT Timing mode switch at exiting power down mode ......................................................................70
10.7 Data output (read) timing ....................................................................................................................71
10.8 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................71
10.9 Data input (write) timing ......................................................................................................................72
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
10.20
10.21
10.22
10.23
10.24
10.25
Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)...........................................................72
Seamless burst read operation: RL = 5 (AL = 2, and CL = 3, BL = 4) .......................................73
Seamless burst write operation: RL = 5 (WL = 4, BL = 4)..........................................................73
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8).............................................................74
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8)..................................................74
Write operation with Data Mask: WL=3, AL=0, BL=4) ...............................................................75
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............76
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............76
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............77
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............77
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............78
Burst write operation followed by precharge: WL = (RL-1) = 3..................................................78
Burst write operation followed by precharge: WL = (RL-1) = 4..................................................79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ...............79
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ...............80
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................80
10.26 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks).......................................................................................81
10.27
10.28
10.29
10.30
10.31
10.32
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3.................................81
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3.......................82
Self Refresh Timing...................................................................................................................82
Active Power Down Mode Entry and Exit Timing.......................................................................83
Precharged Power Down Mode Entry and Exit Timing..............................................................83
Clock frequency change in precharge Power Down mode ........................................................84
11.
12.
PACKAGE SPECIFICATION ..............................................................................................................85
Package Outline WBGA60 (8x12.5 mm2)........................................................................................................85
REVISION HISTORY..........................................................................................................................86
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1. GENERAL DESCRIPTION
The W9751G8JB is a 512M bits DDR2 SDRAM, organized as 16,777,216 words 4 banks 8 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9751G8JB is sorted into the following speed grades: -18, -25, 25I and -3. The -18 is
compliant to the DDR2-1066 (7-7-7) specification. The -25/25I are compliant to the DDR2-800 (5-5-5)
or DDR2-800 (6-6-6) specification (the 25I industrial grade which is guaranteed to support -40°C ≤
TCASE ≤ 95°C). The -3 is compliant to the DDR2-667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and CLK falling). All
I/Os are synchronized with a single ended DQS or differential DQS- DQS pair in a source
synchronous fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.8 V 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK
Data masks (DM) for write data.
)
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 60 Ball (8X12.5 mm2), using Lead free materials with RoHS compliant
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3. KEY PARAMETERS
SPEED GRADE
DDR2-1066
7-7-7
DDR2-800
DDR2-667
5-5-5
-3
SYM.
Bin(CL-tRCD-tRP)
5-5-5/6-6-6
-25/25I
Part Number Extension
-18
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
@CL = 7
2.5 nS
8 nS
@CL = 6
@CL = 5
@CL = 4
@CL = 3
2.5 nS
8 nS
3 nS
tCK(avg)
Average clock period
7.5 nS
3.75 nS
7.5 nS
8 nS
3.75 nS
8 nS
3.75 nS
8 nS
5 nS
5 nS
8 nS
8 nS
tRCD
tRP
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating current
13.125 nS
13.125 nS
53.125 nS
40 nS
12.5 nS
12.5 nS
52.5 nS
40 nS
55 mA
62 mA
85 mA
110 mA
80 mA
6 mA
15 nS
15 nS
55 nS
40 nS
55 mA
60 mA
80 mA
105 mA
80 mA
6 mA
110 mA
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
65 mA
70 mA
120 mA
125 mA
85 mA
6 mA
Operation current (Single bank)
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (TCASE ≤ 85°C)
Operating bank interleave read current
135 mA
120 mA
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W9751G8JB
4. BALL CONFIGURATION
1
2
3
4
5
6
7
8
9
NU/RDQS
VSSQ
DQ1
VDD
DQ6
VSS
DM/RDQS
VDDQ
DQ3
VSS
WE
A
B
C
D
E
F
G
H
J
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
DQS
VSSQ
DQ0
VSSQ
CLK
CLK
CS
VDDQ
DQ7
VDDQ
DQ4
VDDQ
DQ5
VSSQ
VDDL VREF
CKE
VDD
ODT
NC
BA0
A10/AP
A3
BA1
A1
A0
VDD
VSS
VSS
VDD
A5
A6
A4
A7
A9
K
L
A11
A8
A12
NC
NC
A13
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5. BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
Provide the row address for active commands, and the column
address and Auto-precharge bit for Read/Write commands to select
one location out of the memory array in the respective bank.
H8,H3,H7,J2,J8,J3,
J7,K2,K8,K3,H2,K7,
L2,L8
A0−A13
Address
Row address: A0−A13.
Column address: A0−A9. (A10 is used for Auto-precharge)
BA0−BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. Bank address also determines if the
mode register or one of the extended mode registers is to be
accessed during a MRS or EMRS command cycle.
G2,G3
BA0−BA1
Bank Select
Data Input
/ Output
C8,C2,D7,D3,D1,D9,
B1,B9
DQ0−DQ7
Bi-directional data bus.
On Die Termination ODT (registered HIGH) enables termination resistance internal to the
F9
ODT
Control
DDR2 SDRAM.
Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write
Data Strobe /
Differential Read
Data Strobe
B7,A8
DQS,
DQS
data.
is only used when differential data strobe mode is
DQS
enabled via the control bit at EMR (1) [A10] = 0.
All commands are masked when
is registered
CS
G8
Chip Select
HIGH. provides for external Rank selection on systems with
CS
CS
multiple Ranks.
is considered part of the command code.
CS
,
,
,
and
(along with
) define the command being
CS
RAS CAS
RAS CAS
WE
F7,G7,F3
Command Inputs
entered.
WE
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM is input
only, the DM loading matches the DQ and DQS loading. When
RDQS is enabled, RDQS is output with read data only and is ignored
during write data. RDQS is enabled by EMR (1) [A11] = 1. If RDQS is
enabled, the DM function is disabled.
Input Data Mask/
Read Data Strobe
DM/RDQS
B3
A2
is only used when RDQS is enabled and differential data
RDQS
Not Use/Differential
Read Data Strobe
strobe mode is enabled. If differential data strobe mode is disabled
via the control bit at EMR (1) [A10] = 1, then ball A2 and A8 are not
used.
NU/
RDQS
CLK and
are differential clock inputs. All address and control
CLK
input signals are sampled on the crossing of the positive edge of CLK
Differential Clock
Inputs
E8,F8
F2
CLK,
CLK
and negative edge of
crossings of CLK and
. Output (read) data is referenced to the
(both directions of crossing).
CLK
CLK
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
CKE
Clock Enable
E2
A1,E9,H9,L1
A3,E3,J1,K9
A9,C1,C3,C7,C9
A7,B2,B8,D2,D8
G1,L3,L7
VREF
VDD
VSS
Reference Voltage VREF is reference voltage for inputs.
Power Supply
Power Supply: 1.8V ±0.1V.
Ground
Ground.
VDDQ
VSSQ
NC
DQ Power Supply
DQ Ground
DQ Power Supply: 1.8V ±0.1V.
DQ Ground. Isolated on the device for improved noise immunity.
No connection.
No Connection
DLL Power Supply
DLL Ground
E1
VDDL
DLL Power Supply: 1.8V ±0.1V.
DLL Ground.
E7
VSSDL
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6. BLOCK DIAGRAM
CLK
CLK
DLL
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
GENERATOR
RAS
CAS
WE
COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #1
CELL ARRAY
BANK #0
A10
A0
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9
ADDRESS
BUFFER
A11
A12
A13
BA1
BA0
ODT
DQ0
|
DQ7
PREFETCH REGISTER
DQ
DATA CONTROL
CIRCUIT
BUFFER
ODT
DQS
DQS
CONTROL
RDQS
RDQS
COLUMN
COUNTER
REFRESH
COUNTER
DM
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 16384 * 1024 * 8
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7. FUNCTIONAL DESCRIPTION
7.1 Power-up and Initialization Sequence
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined operation. The following sequence is required for
Power-up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT*1 at a LOW state (all other
inputs may be undefined.) Either one of the following sequence is required for Power-up.
A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300
mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| ≤ 0.3 volts.
VDD, VDDL and VDDQ are driven from a single power converter output
VTT is limited to 0.95V max
VREF*2 tracks VDDQ/2
VDDQ ≥ VREF must be met at all times
B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid
DRAM latch-up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be
maintained and is applicable to both AC and DC levels until the ramping of the supply voltages
is complete.
Apply VDD/VDDL*3 before or at the same time as VDDQ
Apply VDDQ*4 before or at the same time as VTT
VREF*2 tracks VDDQ/2
VDDQ ≥ VREF must be met at all times.
2. Start Clock and maintain stable condition for 200 µS (min.).
3. After stable power and clock (CLK, CLK ), apply NOP or Deselect and take CKE HIGH.
4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400
nS period.
5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to
BA0, HIGH to BA1.)
6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to
BA0 and BA1.)
7. Issue an EMRS command to EMR (1) to enable DLL. (To issue DLL Enable command, provide
LOW to A0, HIGH to BA0 and LOW to BA1 and A13. And A9=A8=A7=LOW must be used when
issuing this command.)
8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH
to A8 and LOW to BA0-BA1 and A13.)
9. Issue a precharge all command.
10. Issue 2 or more Auto Refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default
(A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.
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Notes:
1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
2. VREF must be within ±300 mV with respect to VDDQ/2 during supply ramp time.
3. VDD/VDDL voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min.
4. The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be
no greater than 500 mS.
tCH tCL
CLK
CLK
tIS
tIS
CKE
ODT
PRE
ALL
PRE
ALL
ANY
CMD
Command
NOP
EMRS
MRS
REF
MRS
EMRS
EMRS
OCD
REF
tMRD
tRP
tRFC
Follow OCD
Flow chart
400nS
tRP
tMRD
tRFC
tMRD
tOIT
DLL
Enable
DLL
Reset
OCD
Default
min 200 Cycle
CAL. Mode
Exit
Figure 1 – Initialization sequence after power-up
7.2 Mode Register and Extended Mode Registers Operation
For application flexibility, burst length, burst type, CAS Latency, DLL reset function, write recovery
time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS)
command. Additionally, DLL disable function, driver impedance, additive CAS Latency, ODT (On Die
Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user
defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.
Contents of the Mode Register (MR) or Extended Mode Registers EMR (1), EMR (2) and EMR (3) can
be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a
subset of the MR or EMR (1), EMR (2) and EMR (3) variables, all variables within the addressed
register must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which mean re-initialization including those
can be executed at any time after power-up without affecting array contents.
7.2.1 Mode Register Set Command (MRS)
(
CS = "L", RAS = "L", CAS = "L",
= "L", BA0 = "L", BA1 = "L", A0 to A13 = Register Data)
WE
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It
programs CAS Latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and
various vendor specific options to make DDR2 SDRAM useful for various applications. The default
value in the Mode Register after power-up is not defined, therefore the Mode Register must be
programmed during initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into
the mode register. The mode register set command cycle time (tMRD) is required to complete the write
operation to the mode register. The mode register contents can be changed using the same command
and clock cycle requirements during normal operation as long as all banks are in the precharge state.
The mode register is divided into various fields depending on functionality. Burst length is defined by
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
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SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA1 BA0 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Field
Mode Register
Burst Length
0*1
PD
WR
DLL
TM
CAS Latency
Burst Length
0
0
A8
DLL Reset
No
A3
0
Burst Type
Sequential
Interleave
A7
0
Mode
0
1
A2
0
A1
1
A0
0
BL
4
Normal
Test
Yes
1
1
0
1
1
8
BA1 BA0
MRS mode
Write recovery for Auto-precharge
CAS Latency
0
0
1
1
0
1
0
1
MR
EMR (1)
EMR (2)
EMR (3)
A11 A10
A9
0
WR *2
A6
0
A5
0
A4
0
Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Reserved
Reserved
1
2
3
4
5
6
7
8
0
0
1
Reserved
0
0
1
0
Reserved
A12
0
Active power down exit time
Fast exit (use tXARD)
1
0
1
1
3
4
5
6
7
0
1
0
0
1
Slow exit (use tXARDS)
1
1
0
1
0
1
1
0
1
1
1
1
Note:
1. A13 reserved for future use and must be set to "0" when programming the MR.
2. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL
Figure 2 – Mode Register Set (MRS)
7.2.2 Extend Mode Register Set Commands (EMRS)
7.2.2.1 Extend Mode Register Set Command (1), EMR (1)
(
CS = "L", RAS = "L", CAS = "L",
= "L", BA0 = "H", BA1 = "L, A0 to A13 = Register data)
WE
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable and A11 is used for
RDQS enable. A2 and A6 are used for ODT setting.
Publication Release Date: Oct. 12, 2010
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7.2.2.2 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA1
0
BA0
1
A13
0*1
A12
Qoff
A11
A10
A9
A8
A7
A6
Rtt
A5
A4
A3
A2
Rtt
A1
A0
Address Field
Extended Mode Register (1)
OCD program
AdditiveLatency
D.I.C
DLL
RDQS
DQS
A6
0
A2
0
Rtt (nominal)
ODT disabled
75 ohm
DLL Enable
Enable
A0
0
MRS mode
BA1
BA0
0
1
0
0
1
1
0
1
0
1
MRS
1
0
150 ohm
1
Disable
EMR (1)
EMR (2)
EMR (3)
1
1
50 ohm*2
Driver strength control
Output driver
impedance control
A1
Driver size
Driver impedance adjustment
Normal
100%
60%
0
1
OCD Calibration Program
A9
A8
0
A7
0
Reduced
0
0
0
1
1
OCD calibration mode exit; matain setting
Drive (1)
Additive Latency
0
1
A5
0
A4
A3
0
Latency
1
0
Drive (0)
0
0
Adjust mode*3
0
0
0
1
1
0
0
1
1
1
1
OCD Calibration default*4
1
0
1
2
0
0
3
0
1
A12
0
Qoff
4
1
0
Output buffer enabled
Output buffer disabled
5
6
1
1
1
1
0
Resesved
1
1
A10
0
DQS
Enable
1
Disable
A10
A11
Strobe Function Matrix
RDQS Enable*5
Disable
A11
0
(RDQS Enable)
(DQS Enable)
RDQS/DM
DM
DQS
DQS
DQS
Hi-z
RDQS
0 (Disable)
0 (Disable)
1 (Enable)
1 (Enable)
0 (Enable)
1 (Disable)
0 (Enable)
1 (Disable)
Hi-z
Hi-z
DQS
DQS
DQS
DQS
1
Enable
DM
RDQS
RDQS
RDQS
Hi-z
DQS
Hi-z
Notes:
1. A13 reserved for future use and must be set to "0" when programming the EMR (1).
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 7.2.3 for
detailed information.
5. If RDQS is enabled, the DM function is disabled. RDQS is active for reads and don‟t care for writes.
Figure 3 – EMR (1)
Publication Release Date: Oct. 12, 2010
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Revision A01
W9751G8JB
7.2.2.3 Extend Mode Register Set Command (2), EMR (2)
CS = "L", RAS = "L", CAS = "L",
= "L", BA0 = "L", BA1 = "H", A0 to A13 = Register data)
(
WE
The extended mode register (2) controls refresh related features. The default value of the extended
mode register (2) is not defined, therefore the extended mode register (2) must be programmed during
initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into
the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to
complete the write operation to the extended mode register (2). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as
all banks are in the precharge state.
A13
BA1 BA0
A12 A11 A10 A9 A8
A7
A6
A5
A4
A3
0*1
A2
A1
A0
Address Field
0*1
Extended Mode Register (2)
1
0
SELF
BA1 BA0
MRS mode
A7 High Temperature Self Refresh Rate Enable
0
0
1
1
0
1
0
1
MRS
0
1
Disable
EMR (1)
EMR (2)
EMR (3)
Enable*2
Notes:
1. A0-A6, A8-A13 are reserved for future use and must be set to "0" when programming the EMR (2).
2. When DRAM is operated at 85 °C < TCASE ≤ 95 °C the extended Self Refresh rate must be enabled by setting bit A7 to "1"
before the Self Refresh mode can be entered.
Figure 4 – EMR (2)
Publication Release Date: Oct. 12, 2010
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7.2.2.4 Extend Mode Register Set Command (3), EMR (3)
CS = "L", RAS = "L", CAS = "L",
= "L", BA0 = "H", BA1 = "H", A0 to A13 = Register data)
(
WE
No function is defined in extended mode register (3). The default value of the EMR (3) is not defined,
therefore the EMR (3) must be programmed during initialization for proper operation.
BA1 BA0
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A13
Address Field
0*1
1
1
Extended Mode Register (3)
Note:
1. All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to "0" when programming the EMR(3).
Figure 5 – EMR (3)
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7.2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart in Figure 6 is an example of the
sequence. Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command being issued. MRS should be set before entering OCD impedance
adjustment and On Die Termination (ODT) should be carefully controlled depending on system
environment.
All MR shoud be programmed before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
Start
EMRS: OCD calibration mode exit
EMRS: Drive(1)
EMRS: Drive(0)
DQ &DQS High; DQS Low
DQ &DQS Low; DQS High
ALL OK
Need Calibration
ALL OK
Test
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS:
EMRS:
Enter Adjust Mode
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec or NOP
BL=4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Figure 6 – OCD Impedance Adjustment Flow Chart
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7.2.3.1 Extended Mode Register for OCD Impedance Adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs
are driven out by DDR2 SDRAM and drive of RDQS is dependent on EMR bit enabling RDQS
operation. In Drive (1) mode, all DQ, DQS (and RDQS) signals are driven HIGH and all DQS signals
are driven LOW. In Drive (0) mode, all DQ, DQS (and RDQS) signals are driven LOW and all DQS
signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a nominal impedance value of 18 Ω during
nominal temperature and voltage conditions. OCD applies only to normal full strength output drive
setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristics are not
applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or driver strength is set to default, subsequent
EMRS commands not intended to adjust OCD characteristics must specify A[9:7] as ‟000‟ in order to
maintain the default or calibrated value.
Table 1 – OCD Drive Mode Program
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
0
1
1
0
Drive (1) DQ, DQS, (RDQS) HIGH and DQS LOW
Drive (0) DQ, DQS, (RDQS) LOW and DQS HIGH
Adjust mode
1
1
0
1
0
1
OCD calibration default
7.2.3.2 OCD Impedance Adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a
4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL =
4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the
same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver
output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs and DQS‟s of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The
maximum step count for adjustment is 16 and when the limit is reached, further increment or
decrement code has no effect. The default setting may be any step within the 16 step range. When
Adjust mode command is issued, AL from previously set value must be applied.
Table 2 – OCD Adjust Mode Program
4 bit burst code inputs to all DQs
Operation
Pull-up driver strength
DT0
0
DT1
0
DT2
0
DT3
0
Pull-down driver strength
NOP (No operation)
NOP
NOP (No operation)
Increase by 1 step
Decrease by 1 step
NOP
0
0
0
1
0
0
1
0
NOP
0
1
0
0
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Increase by 1 step
Decrease by 1 step
Decrease by 1 step
1
0
0
0
NOP
0
1
0
1
Increase by 1 step
Decrease by 1 step
Increase by 1 step
Decrease by 1 step
0
1
1
0
1
0
0
1
1
0
1
0
Other Combinations
Reserved
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as
shown in Figure 7. For input data pattern for adjustment, DT0 - DT3 is a fixed order and is not affected
by burst type (i.e., sequential or interleave).
CLK
CLK
CMD
NOP
NOP
EMRS
NOP
NOP
NOP
NOP
EMRS
NOP
WL
DQS
WR
DQS_in
tDS tDH
DQ_in
DM
DT0
DT1 DT2 DT3
OCD adjust mode
OCD calibration mode exit
Figure 7 – OCD Adjust Mode
7.2.3.3 Drive Mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration mode exit” command as shown in Figure 8.
CLK
CLK
EMRS
tOIT
NOP
NOP
NOP
NOP
EMRS
tOIT
NOP
NOP
NOP
CMD
HI-Z
DQS
DQS
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
DQs high for Drive (1)
DQs low for Drive (0)
DQ
Enter Drive mode
OCD calibration mode exit
Figure 8 – OCD Drive Mode
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Revision A01
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7.2.4 On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off
termination resistance for each DQ, DQS/DQS , RDQS/RDQS, and DM signal via the ODT control pin.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM
controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function can be used for all active and standby modes. ODT is turned off and not supported
in Self Refresh mode. (Example timing waveforms refer to 10.3, 10.4 ODT Timing for
Active/Standby/Power Down Mode and 10.5, 10.6 ODT timing mode switch at entering/exiting power
down mode diagram in Chapter 10)
VDDQ
VDDQ
VDDQ
sw1
sw2
sw3
Rval1
Rval2
Rval3
DRAM
Input
Buffer
Input
Pin
Rval1
sw1
Rval2
sw2
Rval3
sw3
VSSQ
VSSQ
VSSQ
Switch (sw1, sw2, sw3) is enabled by ODT pin.
Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR (1).
Termination included on all DQs, DM, DQS, DQS , RDQS, and RDQS pins.
Figure 9 – Functional Representation of ODT
7.2.5 ODT related timings
7.2.5.1 MRS command to ODT update delay
During normal operation the value of the effective termination resistance can be changed with an
EMRS command. The update of the Rtt setting is done between tMOD,min and tMOD,max, and CKE
must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown
in the following timing diagram.
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CMD
CLK
EMRS
NOP
NOP
NOP
NOP
NOP
CLK
ODT
tIS
tMOD,max
tAOFD
tMOD,min
Rtt
Old setting
Updating
New setting
1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
2) "setting" in this diagram is the Register and I/O setting, not what is measured from outside.
Figure 10 – ODT update delay timing - tMOD
However, to prevent any impedance glitch on the channel, the following conditions must be met.
tAOFD must be met before issuing the EMRS command.
ODT must remain LOW for the entire duration of tMOD window, until tMOD,max is met.
Now the ODT is ready for normal operation with the new setting, and the ODT signal may be raised
again to turned on the ODT. Following timing diagram shows the proper Rtt update procedure.
CLK
CLK
EMRS
NOP
NOP
NOP
NOP
NOP
CMD
ODT
tIS
tAOND
tAOFD
tMOD,max
Old setting
New setting
Rtt
1) EMRS command directed to EMR(1), which updates the information in EMR(1)[A6,A2], i.e. Rtt (Nominal).
2) "setting" in this diagram is what is measured from outside.
Figure 11 – ODT update delay timing - tMOD, as measured from outside
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Revision A01
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7.3 Command Function
7.3.1 Bank Activate Command
(
CS = "L", RAS = "L", CAS = "H",
= "H", BA0, BA1 = Bank, A0 to A13 be row address)
WE
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
tRCDmin specification, then additive latency must be programmed into the device to delay when the
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (tRC). The minimum time interval between Bank Activate
commands is tRRD.
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
CLK
Internal RAS - RAS delay (≥ tRCDmin)
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
Bank A
Row Addr.
Bank B
Addr.
Address
CAS - CAS delay time(tCCD)
Additive Latency delay(AL)
tRCD = 1
Read Begins
RAS - RAS delay time(≥ tRRD)
Bank A
Post CAS
Read
Bank B
Post CAS
Read
Bank A
Activate
Bank B
Activate
Bank A
Precharge
Bank B
Precharge
Bank A
Activate
Command
Bank Active (≥ tRAS)
Bank Precharge time (≥ tRP)
RAS Cycle time (≥ tRC)
Figure 12 – Bank activate command cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
7.3.2 Read Command
(
CS = "L", RAS = "H", CAS = "L",
= "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
WE
Address)
The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
Publication Release Date: Oct. 12, 2010
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7.3.3 Write Command
CS = "L", RAS = "H", CAS = "L",
(
= "L", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
WE
Address)
The WRITE command is used to initiate a burst write access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the WRITE burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
7.3.4 Burst Read with Auto-precharge Command
(
CS = "L", RAS = "H", CAS ="L",
= "H", BA0, BA1 = Bank, A10 = "H", A0 to A9 = Column
WE
Address)
If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged.
The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles
later than the read with AP command if tRAS(min) and tRTP(min) are satisfied.
7.3.5 Burst Write with Auto-precharge Command
(
CS = "L", RAS = "H", CAS = "L",
= "L", BA0, BA1 = Bank, A10 = "H", A0 to A9 = Column
WE
Address)
If A10 is HIGH when a Write Command is issued, the Write with Auto-precharge function is engaged.
The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write
plus write recovery time (WR) programmed in the mode register.
7.3.6 Precharge All Command
(
CS = "L", RAS = "L", CAS = "H",
= "L", BA0, BA1 = Don‟t Care, A10 = "H", A0 to A9 and
WE
A11 = Don‟t Care)
The Precharge All command precharge all banks simultaneously. Then all banks are switched to the
idle state.
7.3.7 Self Refresh Entry Command
(
CS = "L", RAS = "L", CAS = "L",
= "H", CKE = "L", BA0, BA1, A0 to A13 = Don‟t Care)
WE
The Self Refresh command can be used to retain data, even if the rest of the system is powered
down. When in the Self Refresh mode, the DDR2 SDRAM retains data without external clocking. The
DDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. ODT must be
turned off before issuing Self Refresh command, by either driving ODT pin LOW or using an EMRS
command. Once the command is registered, CKE must be held LOW to keep the device in Self
Refresh mode. The DLL is automatically disabled upon entering Self Refresh and is automatically
enabled upon exiting Self Refresh. When the DDR2 SDRAM has entered Self Refresh mode, all of the
external signals except CKE, are ”Don‟t Care”.
The clock is internally disabled during self refresh operation to save power. The user may change the
external clock frequency or halt the external clock one clock after Self Refresh entry is registered;
however, the clock must be restarted and stable before the device can exit self refresh operation.
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7.3.8 Self Refresh Exit Command
(CKE = "H", CS = "H" or CKE = "H", CS = "L", RAS = "H", CAS = "H",
= "H", BA0, BA1,
WE
A0 to A13 = Don‟t Care)
The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be
stable prior to CKE going back HIGH. Once Self Refresh Exit is registered, a delay of at least tXSNR
must be satisfied before a valid command can be issued to the device to allow for any internal refresh
in progress. CKE must remain HIGH for the entire Self Refresh exit period tXSRD for proper operation
except for self refresh re-entry.
Upon exit from Self Refresh, the DDR2 SDRAM can be put back into Self Refresh mode after waiting
at least tXSNR period and issuing one refresh command (refresh period of tRFC). NOP or Deselect
commands must be registered on each positive clock edge during the Self Refresh exit interval tXSNR.
ODT should be turned off during tXSRD.
The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be
missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh, the DDR2
SDRAM requires a minimum of one extra auto refresh command before it is put back into Self Refresh
mode.
7.3.9 Refresh Command
(
CS = "L", RAS = "L", CAS = "L",
= "H", CKE = "H", BA0, BA1, A0 to A13 = Don‟t Care)
WE
Refresh is used during normal operation of the DDR2 SDRAM. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don‟t Care” during an Auto Refresh command. The DDR2 SDRAM requires Auto Refresh cycles
at an average periodic interval of tREFI (max.).
When the refresh cycle has completed, all banks of the DDR2 SDRAM will be in the precharged (idle)
state. A delay between the auto refresh command (REF) and the next activate command or
subsequent auto refresh command must be greater than or equal to the auto refresh cycle time (tRFC).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight Refresh commands can be posted to any
given DDR2 SDRAM, meaning that the maximum absolute interval between any Refresh command
and the next Refresh command is 9 x tREFI.
T0
T1
T2
T3
Tm
Tn
Tn + 1
CLK/CLK
CKE
"HIGH"
≥ tRFC
≥ tRFC
≥ tRP
REF
REF
NOP
NOP
ANY
CMD
Precharge
NOP
Figure 13 – Refresh command
Publication Release Date: Oct. 12, 2010
Revision A01
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7.3.10 No-Operation Command
CS = "L", RAS = "H", CAS = "H",
(
= "H", CKE, BA0, BA1, A0 to A13 = Don‟t Care)
WE
The No-Operation command simply performs no operation (same command as Device Deselect).
7.3.11 Device Deselect Command
(
CS = "H", RAS
,
CAS
,
, CKE, BA0, BA1, A0 to A13 = Don‟t Care)
WE
The Device Deselect command disables the command decoder so that the RAS
Address inputs are ignored. This command is similar to the No-Operation command.
,
CAS
,
and
WE
7.4 Read and Write access modes
The DDR2 SDRAM provides a fast column access operation. A single Read or Write Command will
initiate a serial read or write operation on successive clock cycles. The boundary of the burst cycle is
strictly restricted to specific segments of the page length.
The 16 Mbit x 8 I/O x 4 Bank chip has a page length of 1024 bits (defined by CA0 to CA9)*. The page
length of 1024 is divided into 256 or 128 uniquely addressable boundary segments depending on
burst length, 256 for 4 bit burst, 128 for 8 bit burst respectively. A 4-bit or 8-bit burst operation will
occur entirely within one of the 256 or 128 groups beginning with the column address supplied to the
device during the Read or Write Command (CA0 to CA9). The second, third and fourth access will
also occur within this group segment. However, the burst order is a function of the starting address,
and the burst sequence.
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting.
However, in case of BL = 8 setting, two cases of interrupt by a new burst access are allowed, one
reads interrupted by a read, the other writes interrupted by a write with 4 bit burst boundary
respectively. The minimum CAS to CAS delay is defined by tCCD, and is a minimum of 2 clocks for
read or write cycles.
Note: Page length is a function of I/O organization and column addressing
16M bits × 8 organization (CA0 to CA9); Page Length = 1024 bits
7.4.1 Posted CAS
Posted CAS operation is supported to make command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. In this operation, the DDR2 SDRAM allows a CAS read or write
command to be issued immediately after the RAS bank activate command (or any time during the
RAS CAS -delay time, tRCD, period). The command is held for the time of the Additive Latency (AL)
-
before it is issued inside the device. The Read Latency (RL) is controlled by the sum of AL and the
CAS Latency (CL). Therefore if a user chooses to issue a Read/Write command before the tRCDmin,
then AL (greater than 0) must be written into the EMR (1). The Write Latency (WL) is always defined
as RL -1 (Read Latency -1) where Read Latency is defined as the sum of Additive Latency plus CAS
Latency (RL = AL + CL). Read or Write operations using AL allow seamless bursts. (Example timing
waveforms refer to 10.11 and 10.12 seamless burst read/write operation diagram in Chapter 10)
7.4.1.1 Examples of posted CAS operation
Examples of a read followed by a write to the same bank where AL = 2 and where AL = 0 are shown
in Figures 14 and 15, respectively.
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6
-1
0
4
5
7
8
9
10
11
12
1
2
3
CLK /CLK
CMD
Active
A-Bank
Read
A-Bank
Write
A-Bank
WL=RL-1=4
CL=3
AL=2
DQS/DQS
DQ
≥ tRCD
RL=AL+CL=5
Din1 Din2
Din3
Dout0
Din0
Dout1 Dout2 Dout3
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Figure 14 – Example 1: Read followed by a write to the same bank,
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK/CLK
CMD
AL=0
Active
A-Bank
Read
A-Bank
Write
A-Bank
WL=RL-1=2
CL=3
DQS/DQS
DQ
≥ tRCD
RL=AL+CL=3
Din0
Din1 Din2 Din3
Dout0 Dout1 Dout2 Dout3
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
Figure 15 – Example 2: Read followed by a write to the same bank,
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
7.4.2 Burst mode operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
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Unlike DDR1 devices, interruption of a burst read or writes cycle during BL = 4 mode operation is
prohibited. However in case of BL = 8 mode, interruption of a burst read or write operation is limited to
two cases, reads interrupted by a read, or writes interrupted by a write. (Example timing waveforms
refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in Chapter 10)
Therefore the Burst Stop command is not supported on DDR2 SDRAM devices.
Table 3 – Burst Length and Sequence
Starting Address
Sequential Addressing
(decimal)
Interleave Addressing
(decimal)
Burst Length
(A2 A1 A0)
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
4
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
8
7.4.3 Burst read mode operation
Burst Read is initiated with a READ command. The address inputs determine the starting column
address for the burst. The delay from the start of the command to when the data from the first cell
appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is
driven LOW one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst
is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on
the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an
additive latency (AL) plus CAS Latency (CL). The CL is defined by the Mode Register Set (MRS). The
AL is defined by the Extended Mode Register EMR (1). (Example timing waveforms refer to 10.7 and
10.8 Data output (read) timing and Burst read operation diagram in Chapter 10)
7.4.4 Burst write mode operation
Burst Write is initiated with a WRITE command. The address inputs determine the starting column
address for the burst. Write Latency (WL) is defined by a Read Latency (RL) minus one and is equal
to (AL + CL -1); and is the number of clocks of delay that are required from the time the write
command is registered to the clock edge associated to the first DQS strobe. A data strobe signal
(DQS) should be driven LOW (preamble) nominally half clock prior to the WL. The first data bit of the
burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble.
The tDQSS specification must be satisfied for each positive DQS transition to its associated clock edge
during write cycles. The subsequent burst bit data are issued on successive edges of the DQS until
the burst length is completed, which is 4 or 8 bit burst. When the burst has finished, any additional
data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is
complete. The time from the completion of the burst write to bank precharge is the write recovery time
(WR). (Example timing waveforms refer to 10.9 and 10.10 Data input (write) timing and Burst write
operation diagram in Chapter 10)
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7.4.5 Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR2 SDRAM,
consistent with the implementation on DDR1 SDRAM. It has identical timings on write operations as
the data bits, and though used in a unidirectional manner, is internally loaded identically to data bits to
insure matched system timing. DM function is disabled, when RDQS / RDQS are enabled by
EMRS(1). (Example timing waveform refer to 10.15 Write operation with Data Mask diagram in
Chapter 10)
7.5 Burst Interrupt
Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8
under the following conditions:
1. Read burst of 8 can only be interrupted by another Read command. Read burst interruption by
Write or Precharge Command is prohibited.
2. Write burst of 8 can only be interrupted by another Write command. Write burst interruption by
Read or Precharge Command is prohibited.
3. Read burst interrupt must occur exactly two clocks after the previous Read command. Any other
Read burst interrupt timings are prohibited.
4. Write burst interrupt must occur exactly two clocks after the previous Write command. Any other
Write burst interrupt timings are prohibited.
5. Read or Write burst interruption is allowed to any bank inside the DDR2 SDRAM.
6. Read or Write burst with Auto-precharge enabled is not allowed to interrupt.
7. Read burst interruption is allowed by a Read with Auto-precharge command.
8. Write burst interruption is allowed by a Write with Auto-precharge command.
9. All command timings are referenced to burst length set in the mode register. They are not
referenced to the actual burst. For example below:
Minimum Read to Precharge timing is AL + BL/2 where BL is the burst length set in the
mode register and not the actual burst (which is shorter because of interrupt).
Minimum Write to Precharge timing is WL + BL/ 2 + tWR, where tWR starts with the rising
clock after the un-interrupted burst end and not from the end of the actual burst end.
(Example timing waveforms refer to 10.13 and 10.14 Burst read and write interrupt timing diagram in
Chapter 10)
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7.6 Precharge operation
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command can be used to precharge each bank independently or all banks simultaneously.
Three address bits A10, BA0 and BA1 are used to define which bank to precharge when the
command is issued.
Table 4 – Bank selection for precharge by address bits
A10
LOW
LOW
LOW
LOW
HIGH
BA1
LOW
BA0
LOW
Precharge Bank(s)
Bank 0 only
Bank 1 only
Bank 2 only
Bank 3 only
All Banks
LOW
HIGH
HIGH
LOW
HIGH
HIGH
Don‟t Care
Don‟t Care
7.6.1 Burst read operation followed by precharge
Minimum Read to Precharge command spacing to the same bank = AL + BL/2 + max(RTP, 2) - 2 clks
For the earliest possible precharge, the precharge command may be issued on the rising edge which
is “Additive Latency (AL) + BL/2 + max(RTP, 2) - 2 clocks” after a Read command. A new bank active
(command) may be issued to the same bank after the RAS precharge time (tRP). A precharge
command cannot be issued until tRAS is satisfied.
The minimum Read to Precharge spacing has also to satisfy a minimum analog time from the rising
clock edge that initiates the last 4-bit prefetch of a Read to Precharge command. This time is called
tRTP (Read to Precharge). For BL = 4 this is the time from the actual read (AL after the Read
command) to Precharge command. For BL = 8 this is the time from AL + 2 clocks after the Read to the
Precharge command. (Example timing waveforms refer to 10.16 to 10.20 Burst read operation
followed by precharge diagram in Chapter 10)
7.6.2 Burst write operation followed by precharge
Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR
For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the
Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced
from the completion of the burst write to the precharge command. No Precharge command should be
issued prior to the tWR delay. (Example timing waveforms refer to 10.21 to 10.22 Burst write operation
followed by precharge diagram in Chapter 10)
7.7 Auto-precharge operation
Before a new row in an active bank can be opened, the active bank must be precharged using either
the Precharge command or the Auto-precharge function. When a Read or a Write command is given
to the DDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the
active bank to automatically begin precharge at the earliest possible moment during the burst read or
write cycle. If A10 is LOW when the READ or WRITE command is issued, then normal Read or Write
burst operation is executed and the bank remains active at the completion of the burst sequence. If
A10 is HIGH when the Read or Write command is issued, then the Auto-precharge function is
engaged. During Auto-precharge, a Read command will execute as normal with the exception that the
active bank will begin to precharge on the rising edge which is CAS Latency (CL) clock cycles before
the end of the read burst.
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Auto-precharge is also implemented during Write commands. The precharge operation engaged by
the Auto-precharge command will not begin until the last data of the burst write sequence is properly
stored in the memory array.
This feature allows the precharge operation to be partially or completely hidden during burst read
cycles (dependent upon CAS Latency) thus improving system performance for random data access.
The RAS lockout circuit internally delays the Precharge operation until the array restore operation
has been completed (tRAS satisfied) so that the Auto-precharge command may be issued with any
read or write command.
7.7.1 Burst read with Auto-precharge
If A10 is HIGH when a Read Command is issued, the Read with Auto-precharge function is engaged.
The DDR2 SDRAM starts an Auto-precharge operation on the rising edge which is (AL + BL/2) cycles
later from the Read with AP command if tRAS(min) and tRTP(min) are satisfied. (Example timing
waveform refer to 10.23 Burst read operation with Auto-precharge diagram in Chapter 10)
If tRAS(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
tRAS(min) is satisfied.
If tRTP(min) is not satisfied at the edge, the start point of Auto-precharge operation will be delayed until
tRTP(min) is satisfied.
In case the internal precharge is pushed out by tRTP, tRP starts at the point where tRTP ends (not at the
next rising clock edge after this event). So for BL = 4 the minimum time from Read with Auto-
precharge to the next Activate command becomes AL + RU{ (tRTP + tRP) / tCK } (Example timing
waveform refer to 10.24 Burst read operation with Auto-precharge diagram in Chapter 10.), for BL = 8
the time from Read with Auto-precharge to the next Activate command is AL + 2 + RU{ (tRTP + tRP) /
tCK }, where RU stands for “rounded up to the next integer”. In any event internal precharge does not
start earlier than two clocks after the last 4-bit prefetch.
A new bank active command may be issued to the same bank if the following two conditions are
satisfied simultaneously.
The RAS precharge time (tRP) has been satisfied from the clock at which the Auto-precharge
begins.
The RAS cycle time (tRC) from the previous bank activation has been satisfied.
(Example timing waveforms refer to 10.25 to 10.26 Burst read with Auto-precharge followed by an
activation to the same bank (tRC Limit) and (tRP Limit) diagram in Chapter 10)
7.7.2 Burst write with Auto-precharge
If A10 is HIGH when a Write Command is issued, the Write with Auto-Precharge function is engaged.
The DDR2 SDRAM automatically begins precharge operation after the completion of the burst write
plus write recovery time (WR) programmed in the mode register. The bank undergoing Auto-
precharge from the completion of the write burst may be reactivated if the following two conditions are
satisfied.
The data-in to bank activate delay time (WR + tRP) has been satisfied.
The RAS cycle time (tRC) from the previous bank activation has been satisfied.
(Example timing waveforms refer to 10.27 to 10.28 Burst write with Auto-precharge (tRC Limit) and
(WR + tRP Limit) diagram in Chapter 10)
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Table 5 – Precharge & Auto-precharge clarifications
From
To Command
Minimum Delay between “From Unit Notes
Command
Command” to “To Command”
Read
Precharge (to same Bank as Read)
Precharge All
AL + BL/2 + max(RTP, 2) - 2
clks
clks
clks
clks
clks
clks
clks
clks
clks
clks
clks
clks
1, 2
1, 2
1, 2
1, 2
2
AL + BL/2 + max(RTP, 2) - 2
Read w/AP
Write
Precharge (to same Bank as Read w/AP)
Precharge All
AL + BL/2 + max(RTP, 2) - 2
AL + BL/2 + max(RTP, 2) - 2
Precharge (to same Bank as Write)
Precharge All
WL + BL/2 + tWR
WL + BL/2 + tWR
2
Write w/AP
Precharge
Precharge (to same Bank as Write w/AP)
Precharge All
WL + BL/2 + WR
2
WL + BL/2 + WR
2
Precharge (to same Bank as Precharge)
Precharge All
1
1
1
1
2
2
Precharge
All
Precharge
2
Precharge All
2
Notes:
1. RTP[cycles] = RU{ tRTP[nS] / tCK(avg)[nS] }, where RU stands for round up.
2. For a given bank, the precharge period should be counted from the latest precharge command, either one bank precharge or
precharge all, issued to that bank. The precharge period is satisfied after tRP depending on the latest precharge command
issued to that bank.
7.8 Refresh Operation
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command
and the next command is specified by tRFC.
Self Refresh mode enters issuing the Self Refresh command (CKE asserted "LOW") while all banks
are in the idle state. The device is in Self Refresh mode for as long as CKE held "LOW". In the case of
8192 burst Auto Refresh commands, 8192 burst Auto Refresh commands must be performed within
7.8 µS before entering and after exiting the Self Refresh mode. In the case of distributed Auto Refresh
commands, distributed auto refresh commands must be issued every 7.8 µS and the last distributed
Auto Refresh commands must be performed within 7.8 µS before entering the self refresh mode. After
exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self
Refresh mode, all input/output buffers are disable, resulting in lower power dissipation (except CKE
buffer). (Example timing waveform refer to 10.29 Self Refresh diagram in Chapter 10)
7.9 Power Down Mode
Power-down is synchronously entered when CKE is registered LOW, along with NOP or Deselect
command. CKE is not allowed to go LOW while mode register or extended mode register command
time, or read or write operation is in progress. CKE is allowed to go LOW while any other operation
such as row activation, Precharge or Auto-precharge or Auto Refresh is in progress, but power down
IDD specification will not be applied until finishing those operations.
The DLL should be in a locked state when power-down is entered. Otherwise DLL should be reset
after exiting power-down mode for proper read operation.
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7.9.1 Power Down Entry
Two types of Power Down Mode can be performed on the device: Precharge Power Down Mode and
Active Power Down Mode.
If power down occurs when all banks are idle, this mode is referred to as Precharge Power Down; if
power down occurs when there is a row active in any bank, this mode is referred to as Active Power
Down. Entering power down deactivates the input and output buffers, excluding CLK, CLK , ODT and
CKE. Also the DLL is disabled upon entering Precharge Power Down or slow exit Active Power Down,
but the DLL is kept enabled during fast exit Active Power Down.
In power down mode, CKE LOW and a stable clock signal must be maintained at the inputs of the
DDR2 SDRAM, and ODT should be in a valid state but all other input signals are “Don‟t Care”. CKE
LOW must be maintained until tCKE has been satisfied. Maximum power down duration is limited by
the refresh requirements of the device, which allows a maximum of 9 x tREFI if maximum posting of
REF is utilized immediately before entering power down. (Example timing waveforms refer to 10.30 to
10.31 Active and Precharged Power Down Mode Entry and Exit diagram in Chapter 10)
7.9.2 Power Down Exit
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or
Deselect command). CKE high must be maintained until tCKE has been satisfied. A valid, executable
command can be applied with power-down exit latency, tXP, tXARD, or tXARDS, after CKE goes HIGH.
Power-down exit latency is defined at AC Characteristics table of this data sheet.
7.10 Input clock frequency change during precharge power down
DDR2 SDRAM input clock frequency can be changed under following condition:
DDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic
LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may
change. SDRAM input clock frequency is allowed to change only within minimum and maximum
operating frequency specified for the particular speed grade. During input clock frequency change,
ODT and CKE must be held at stable LOW levels.
Once input clock frequency is changed, stable new clocks must be provided to DRAM before
precharge power down may be exited and DLL must be RESET via MRS command after precharge
power down exit. Depending on new clock frequency an additional MRS or EMRS command may
need to be issued to appropriately set the WR, CL etc…
During DLL re-lock period, ODT must remain off. After the DLL lock time, the DRAM is ready to
operate with new clock frequency. (Example timing waveform refer to 10.32 Clock frequency change
in precharge Power Down mode diagram in Chapter 10)
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8. OPERATION MODE
8.1 Command Truth Table
CKE
A13
A12
A11
BA1
BA0
COMMAND
A10
A9-A0
NOTES
Previous
Cycle
Current
Cycle
RAS
CAS
WE
CS
Bank Activate
H
H
BA
BA
Row Address
L
L
L
L
L
H
H
H
L
1,2
1,2
Single Bank
Precharge
H
H
X
X
X
Precharge All
Banks
H
H
H
H
H
H
H
H
H
H
X
H
X
L
L
L
L
L
L
H
L
L
L
L
L
L
1
Write
BA
BA
BA
BA
Column
Column
Column
Column
L
H
L
Column
Column
Column
Column
H
H
H
H
1,2,3
1,2,3
1,2,3
1,2,3
Write with Auto-
precharge
L
Read
H
H
Read with Auto-
precharge
H
(Extended)
Mode Register
Set
H
H
H
X
BA
X
OP Code
X
L
L
L
L
L
1,2
1
No Operation
X
X
H
H
H
Device Deselect
Refresh
H
H
X
H
X
X
X
X
X
X
X
X
H
L
X
L
X
L
X
H
1
1
Self Refresh
Entry
H
L
L
X
X
X
X
X
X
X
X
L
L
L
H
1,4
H
L
X
H
X
H
X
H
X
H
X
H
X
H
Self Refresh Exit
H
1,4,5
H
L
Power Down
Mode Entry
H
L
L
X
X
X
X
X
X
X
X
1,6
1,6
H
L
X
H
X
H
X
H
Power Down
Mode Exit
H
Notes:
1. All DDR2 SDRAM commands are defined by states of
,
,
,
and CKE at the rising edge of the clock.
CS RAS CAS WE
2. Bank addresses BA [1:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details.
4. V
must be maintained during Self Refresh operation.
REF
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
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8.2 Clock Enable (CKE) Truth Table for Synchronous Transitions
COMMAND (N) 3
CKE
CURRENT
STATE2
ACTION (N) 3
NOTES
Previous Cycle 1
Current Cycle 1
(N)
RAS CAS CS
,
,
WE
,
(N-1)
L
L
H
L
X
Maintain Power Down
Power Down Exit
11, 13, 15
4, 8, 11, 13
11, 15, 16
4, 5, 9, 16
Power Down
L
L
DESELECT or NOP
X
Maintain Power Down
Self Refresh Exit
Self Refresh
Bank(s) Active
All Banks Idle
L
H
L
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
REFRESH
Active Power Down
Entry
4, 8, 10, 11,
13
H
H
H
H
Precharge Power Down
Entry
4, 8, 10, 11,
13
L
L
Self Refresh Entry
6, 9, 11, 13
7
H
Refer to the Command Truth Table
Notes:
1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
3. COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period.
Read commands may be issued only after tXSRD (200 clocks) is satisfied.
6. Self Refresh mode can only be entered from the All Banks Idle state.
7. Must be a legal command as defined in the Command Truth Table.
8. Valid commands for Power Down Entry and Exit are NOP and DESELECT only.
9. Valid commands for Self Refresh Exit are NOP and DESELECT only.
10. Power Down and Self Refresh can not be entered while Read or Write operations, (Extended) Mode Register Set
operations or Precharge operations are in progress. See section 7.9 "Power Down Mode" and section 7.3.7/7.3.8 "Self
Refresh Entry/Exit Command" for a detailed list of restrictions.
11. tCKEmin of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
12. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
See section 7.2.4.
13. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
refresh requirements outlined in section 7.9.
14. CKE must be maintained HIGH while the SDRAM is in OCD calibration mode.
15. ”X” means “don‟t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
high or low in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMR (1)).
16. VREF must be maintained during Self Refresh operation.
8.3 Data Mask (DM) Truth Table
FUNCTION
Write enable
Write inhibit
DM
L
DQS
Valid
X
NOTE
1
1
H
Note:
1. Used to mask write data, provided coincident with the corresponding data.
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
8.4 Function Truth Table
CURRENT
STATE
CS
RAS CAS WE
ADDRESS
COMMAND
ACTION
NOTES
H
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
X
DSL
NOP
NOP or Power down
NOP or Power down
ILLEGAL
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1
L
ILLEGAL
Idle
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Row activating
L
PRE/PREA
AREF/SELF
Precharge/ Precharge all banks
Auto Refresh or Self Refresh
L
H
2
2
Mode/Extended register
accessing
L
L
L
L
Op-Code
MRS/EMRS
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
X
DSL
NOP
NOP
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
Begin read
L
Begin write
Banks
Active
H
H
L
H
L
BA, RA
ACT
ILLEGAL
1
L
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
Precharge/ Precharge all banks
ILLEGAL
L
H
L
X
L
L
Op-Code
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
X
Continue burst to end
Continue burst to end
Burst interrupt
ILLEGAL
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1,3
1
L
Read
H
H
L
H
L
BA, RA
ACT
ILLEGAL
1
L
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
ILLEGAL
1
L
H
L
X
ILLEGAL
L
L
Op-Code
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
X
Continue burst to end
Continue burst to end
ILLEGAL
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1,3
1
L
Burst interrupt
ILLEGAL
Write
H
H
L
H
L
BA, RA
BA, A10
X
ACT
L
PRE/PREA
AREF/SELF
MRS/EMRS
ILLEGAL
1
L
H
L
ILLEGAL
L
L
Op-Code
ILLEGAL
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
Function Truth Table, continued
CURRENT
STATE
CS
RAS CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
X
DSL
NOP
Continue burst to end
Continue burst to end
ILLEGAL
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1
1
1
Read with
Auto-
precharge
L
ILLEGAL
BA, RA
ACT
H
H
L
H
L
ILLEGAL
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
L
ILLEGAL
X
L
H
L
ILLEGAL
Op-Code
L
L
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
X
Continue burst to end
Continue burst to end
ILLEGAL
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1
1
1
Write with
Auto-
precharge
L
ILLEGAL
BA, RA
ACT
H
H
L
H
L
ILLEGAL
L
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
ILLEGAL
L
H
L
X
ILLEGAL
L
L
Op-Code
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
X
NOP-> Idle after tRP
NOP-> Idle after tRP
ILLEGAL
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1
1
1
L
ILLEGAL
Precharge
BA, RA
ACT
H
H
L
H
L
ILLEGAL
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
L
NOP-> Idle after tRP
ILLEGAL
X
L
H
L
Op-Code
L
L
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
X
NOP-> Row active after tRCD
NOP-> Row active after tRCD
ILLEGAL
NOP
BA, CA, A10 READ/READA
BA, CA, A10 WRIT/WRITA
1
1
1
1
L
ILLEGAL
Row
Activating
BA, RA
BA, A10
X
ACT
H
H
L
H
L
ILLEGAL
PRE/PREA
AREF/SELF
MRS/EMRS
L
ILLEGAL
L
H
L
ILLEGAL
L
L
Op-Code
ILLEGAL
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
Function Truth Table, continued
CURRENT
STATE
CS
RAS CAS
WE
ADDRESS
COMMAND
DSL
ACTION
NOTES
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
NOP-> Bank active after tWR
NOP-> Bank active after tWR
ILLEGAL
X
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READA
WRIT/WRITA
ACT
1
L
New write
Write
Recovering
H
H
L
H
L
ILLEGAL
1
1
BA, A10
L
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
ILLEGAL
L
H
L
X
ILLEGAL
Op-Code
L
L
ILLEGAL
X
H
H
H
L
X
H
L
X
H
H
L
X
NOP-> Precharge after tWR
NOP-> Precharge after tWR
ILLEGAL
X
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READA
WRIT/WRITA
ACT
1
1
1
1
Write
L
ILLEGAL
Recovering
with Auto-
precharge
H
H
L
H
L
ILLEGAL
BA, A10
L
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
ILLEGAL
L
H
L
X
ILLEGAL
Op-Code
L
L
ILLEGAL
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
NOP-> Idle after tRC
NOP-> Idle after tRC
ILLEGAL
X
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READA
WRIT/WRITA
ACT
L
ILLEGAL
Refreshing
H
H
L
H
L
ILLEGAL
L
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
DSL
ILLEGAL
L
H
L
X
ILLEGAL
L
L
Op-Code
ILLEGAL
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
H
H
L
X
NOP-> Idle after tMRD
NOP-> Idle after tMRD
ILLEGAL
X
NOP
BA, CA, A10
BA, CA, A10
BA, RA
READ/READA
WRIT/WRITA
ACT
Mode
Register
Accessing
L
ILLEGAL
H
H
L
H
L
ILLEGAL
L
BA, A10
PRE/PREA
AREF/SELF
MRS/EMRS
ILLEGAL
L
H
L
X
ILLEGAL
L
L
Op-Code
ILLEGAL
Notes:
1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. Read or Write burst interruption is prohibited for burst length of 4 and only allowed for burst length of 8. Burst read/write can
only be interrupted by another read/write with 4 bit burst boundary. Any other case of read/write interrupt is not allowed.
Remark: H = High level, L = Low level, X = High or Low level (Don‟t Care), V = Valid data.
Publication Release Date: Oct. 12, 2010
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Revision A01
W9751G8JB
8.5 Simplified Stated Diagram
Initialization
Sequence
CKEL
OCD
calibration
Self Refreshing
SELF
PRE
CKEH
Setting
MR,EMR (1)
EMR (2)
Idle
All banks
Precharged
(E)MRS
REF
Refreshing
EMR (3)
CKEL
CKEL
ACT
CKEH
Precharge
Power
Down
CKEL
Autoomatic Sequence
Command Sequence
Activating
CKEL
CKEL
Active
Power
Down
CKEH
CKEL
Bank
Active
Read
Write
Write
Read
WRITA
Write
READA
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down
CKEH = CKE HIGH, exit Self Refresh
ACT = Activate
WRITA = Write with Auto-precharge
READA = Read (with Auto-precharge
PREA = Precharge All
Read
Writing
Reading
(E)MRS = (Extended) Mode Register Set
SELF = Enter Self Refresh
WRITA
READA
REF = Refresh
READA
WRITA
Writing
with
Reading
with
Auto-precharge
Auto-precharge
PRE, PREA
PRE, PREA
PRE, PREA
Precharging
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
Voltage on VDD pin relative to VSS
Voltage on VDDQ pin relative to VSS
Voltage on VDDL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
SYMBOL
RATING
-1.0 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-0.5 ~ 2.3
-55 ~ 100
UNIT NOTES
VDD
VDDQ
V
V
1, 2
1, 2
VDDL
V
1, 2
VIN, VOUT
TSTG
V
1, 2
°C
1, 2, 3
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. When VDD and VDDQ and VDDL are less than 500mV; VREF may be equal to or less than 300mV.
3. Storage temperature is the case surface temperature on the center/top side of the DRAM.
9.2 Operating Temperature Condition
PARAMETER
Operating Temperature (for -18/-25/-3)
Operating Temperature (for 25I)
Notes:
SYMBOL
TOPR
RATING
0 ~ 85
UNIT NOTES
°C
°C
1, 2, 3
TOPR
-40 ~ 95
1, 2, 3, 4
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.
2. Supporting 0 ~ 85°C with full JEDEC AC and DC specifications.
3. Supporting 0 ~ 85 °C and being able to extend to 95 °C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 "1" on EMR (2).
4. During operation, the DRAM case temperature must be maintained between -40 to 95°C for Industrial parts under all
specification parameters.
9.3 Recommended DC Operating Conditions
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
SYM.
PARAMETER
Supply Voltage
MIN.
1.7
TYP.
1.8
MAX.
1.9
UNIT NOTES
VDD
V
V
V
V
V
1
5
VDDL Supply Voltage for DLL
VDDQ Supply Voltage for Output
VREF Input Reference Voltage
1.7
1.8
1.9
1.7
1.8
1.9
1, 5
2, 3
4
0.49 x VDDQ
VREF - 0.04
0.5 x VDDQ
VREF
0.51 x VDDQ
VREF + 0.04
VTT
Termination Voltage (System)
Notes:
1. There is no specific device VDD supply voltage requirement for SSTL_18 compliance. However under all conditions VDDQ
must than or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
3. Peak to peak AC noise on VREF may not exceed ±2 % VREF(dc).
4. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
Publication Release Date: Oct. 12, 2010
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Revision A01
W9751G8JB
9.4 ODT DC Electrical Characteristics
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
PARAMETER/CONDITION
SYM.
Rtt1(eff)
Rtt2(eff)
Rtt3(eff)
ΔVM
MIN.
60
NOM. MAX.
UNIT NOTES
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 Ω
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 Ω
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 Ω
Deviation of VM with respect to VDDQ/2
75
150
50
90
180
60
Ω
Ω
Ω
%
1
1
120
40
1, 2
1
-6
+6
Notes:
1. Test condition for Rtt measurements.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
Measurement Definition for Rtt(eff):
Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH (ac)) and I(VIL (ac))
respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18.
Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac))
Measurement Definition for ΔVM:
Measure voltage (VM) at test pin (midpoint) with no load.
ΔVM = ((2 x Vm / VDDQ) – 1) x 100%
9.5 Input DC Logic Level
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
PARAMETER
DC input logic HIGH
DC input logic LOW
SYM.
VIH(dc)
VIL(dc)
MIN.
VREF + 0.125
-0.3
MAX.
UNIT
VDDQ + 0.3
VREF - 0.125
V
V
9.6 Input AC Logic Level
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
-18
-25/25I/-3
PARAMETER
SYM.
UNIT
MIN.
MAX.
MIN.
MAX.
VDDQ + VPEAK1
VIH (ac)
VIL (ac)
VREF + 0.200
VREF + 0.200
VSSQ - VPEAK1
V
V
AC input logic HIGH
AC input logic LOW
VREF - 0.200
VREF - 0.200
Note:
1. Refer to the page 66 sections 9.14.1 and 9.14.2 AC Overshoot/Undershoot specification table for VPEAK value: maximum
peak amplitude allowed for Overshoot/Undershoot.
Publication Release Date: Oct. 12, 2010
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Revision A01
W9751G8JB
9.7 Capacitance
SYM.
PARAMETER
MIN.
MAX.
UNIT
CCK
1.0
2.0
pF
Input Capacitance , CLK andCLK
CDCK
0.25
2.0
pF
pF
pF
1.0
Input Capacitance delta , CLK andCLK
CI
input Capacitance, all other input-only pins
Input Capacitance delta, all other input-only pins
CDI
0.25
Input/output Capacitance, DQ, DM,
DQS,DQS ,RDQS,RDQS
CIO
2.5
3.5
0.5
pF
pF
Input/output Capacitance delta, DQ, DM,
DQS,DQS ,RDQS,RDQS
CDIO
9.8 Leakage and Output Buffer Characteristics
SYM.
PARAMETER
Input Leakage Current
MIN.
MAX.
UNIT
NOTES
IIL
-2
2
5
µA
µA
1
(0V ≤ VIN ≤ VDD)
Output Leakage Current
IOL
-5
2
(Output disabled, 0V ≤ VOUT ≤ VDDQ)
Minimum Required Output Pull-up
Maximum Required Output Pull-down
VOH
VOL
VTT + 0.603
V
V
VTT - 0.603
IOH(dc) Output Minimum Source DC Current
IOL(dc) Output Minimum Sink DC Current
-13.4
mA
3, 5
4, 5
13.4
mA
Notes:
1. All other pins not under test = 0 V.
2. DQ, DQS, , RDQS,
are disabled and ODT is turned off.
RDQS
DQS
3. VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT - VDDQ)/IOH must be less than 21 Ω for values of VOUT between VDDQ and VDDQ -
0.28V.
4. VDDQ = 1.7 V; VOUT = 0.28V. VOUT/IOL must be less than 21 Ω for values of VOUT between 0 V and 0.28V.
5. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 3 and 4. They are used to test drive current
capability to ensure VIHmin plus a noise margin and VILmax minus a noise margin are delivered to an SSTL_18 receiver.
Publication Release Date: Oct. 12, 2010
- 39 -
Revision A01
W9751G8JB
9.9 DC Characteristics
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
-18
-25/25I
-3
SYM.
IDD0
CONDITIONS
UNIT
NOTES
MAX. MAX. MAX.
Operating Current - One Bank Active-Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD);
1,2,3,4,5,
6
65
70
55
62
55
60
mA
CKE is HIGH,
is HIGH between valid commands;
CS
Address and control inputs are SWITCHING;
Databus inputs are SWITCHING.
Operating Current - One Bank Active-Read-
Precharge
IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD), tRCD
= tRCD(IDD);
1,2,3,4,5,
6
mA
IDD1
CKE is HIGH,
is HIGH between valid commands;
CS
Address and control inputs are SWITCHING;
Data bus inputs are SWITCHING.
Precharge Power-Down Current
All banks idle;
tCK = tCK(IDD);
CKE is LOW;
Other control and address inputs are STABLE;
1,2,3,4,5,
6,7
6
6
6
mA
mA
mA
IDD2P
IDD2N
IDD2Q
Data Bus inputs are FLOATING. (TCASE ≤ 85°C)
Precharge Standby Current
All banks idle;
tCK = tCK(IDD);
1,2,3,4,5,
6
40
35
35
30
35
30
CKE is HIGH,
is HIGH;
CS
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
All banks idle;
tCK = tCK(IDD);
1,2,3,4,5,
6
CKE is HIGH,
is HIGH;
CS
Other control and address inputs are STABLE;
Data bus inputs are FLOATING.
Active Power-Down Current
All banks open;
tCK = tCK(IDD);
CKE is LOW;
Other control and address inputs are
STABLE;
Data bus inputs are FLOATING.
Fast PDN Exit
MRS(12) = 0
1,2,3,4,5,
6
10
10
10
10
10
10
mA
mA
IDD3PF
IDD3PS
Slow PDN Exit
MRS(12) = 1
1,2,3,4,5,
6,7
(TCASE ≤ 85°C)
Active Standby Current
All banks open;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
1,2,3,4,5,
6
55
45
45
mA
IDD3N
CKE is HIGH, CS is HIGH between valid commands;
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
Operating Burst Read Current
All banks open, Continuous burst reads, IOUT = 0 mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
1,2,3,4,5,
120
125
85
80
mA
6
IDD4R
IDD4W
CKE is HIGH,
is HIGH between valid commands;
CS
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Operating Burst Write Current
All banks open, Continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD); tRAS = tRASmax(IDD), tRP = tRP(IDD);
1,2,3,4,5,
110
105
mA
6
CKE is HIGH,
is HIGH between valid commands;
CS
Address inputs are SWITCHING;
Data Bus inputs are SWITCHING.
Burst Refresh Current
tCK = tCK(IDD);
Refresh command every tRFC(IDD) interval;
1,2,3,4,5,
6
85
6
80
6
80
6
mA
mA
IDD5B
IDD6
CKE is HIGH,
is HIGH between valid commands;
CS
Other control and address inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self Refresh Current
CKE ≤ 0.2 V, external clock off, CLK and
at 0 V;
CLK
1,2,3,4,5,
6,7
Other control and address inputs are FLOATING;
Data bus inputs are FLOATING. (TCASE ≤ 85°C)
Operating Bank Interleave Read Current
All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD) - 1 x tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD =
tRCD(IDD);
1,2,3,4,5,
6
135
120
110
mA
IDD7
CKE is HIGH,
is HIGH between valid commands;
CS
Address bus inputs are STABLE during deselects;
Data Bus inputs are SWITCHING.
Notes:
1. VDD = 1.8 V 0.1V; VDDQ = 1.8 V 0.1V.
2. IDD specifications are tested after the device is properly initialized.
3. Input slew rate is specified by AC Parametric Test Condition.
4. IDD parameters are specified with ODT disabled.
5. Data Bus consists of DQ, DM, DQS,
6. Definitions for IDD
, RDQS,
.
RDQS
DQS
LOW = Vin ≤ VIL (ac) (max)
HIGH = Vin ≥ VIH (ac) (min)
STABLE = inputs stable at a HIGH or LOW level
FLOATING = inputs at VREF = VDDQ/2
SWITCHING = inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and
control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)
for DQ signals not including masks or strobes.
7. The following IDD values must be derated (IDD limits increase), when TCASE ≥ 85°C IDD2P must be derated by 20 %;
IDD3P(slow) must be derated by 30 % and IDD6 must be derated by 80 %. (IDD6 will increase by this amount if TCASE < 85°C
and the 2X refresh option is still enabled)
Publication Release Date: Oct. 12, 2010
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Revision A01
W9751G8JB
9.10 IDD Measurement Test Parameters
DDR2-1066
DDR2-800
(-25/25I)
DDR2-667
SPEED GRADE
(-18)
(-3)
UNIT
Bin(CL-tRCD-tRP)
7-7-7
5-5-5/6-6-6
5-5-5
CL(IDD)
7
5/6
5
3
tCK
nS
nS
nS
nS
nS
nS
nS
nS
nS
tCK(IDD)
1.875
13.125
13.125
53.125
40
2.5
12.5
12.5
52.5
40
tRCD(IDD)
15
tRP(IDD)
15
tRC(IDD)
55
tRASmin(IDD)
tRASmax(IDD)
tRRD(IDD)-1KB
tFAW(IDD)-1KB
tRFC(IDD)
40
70000
7.5
70000
7.5
70000
7.5
37.5
105
35
35
105
105
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
9.11 AC Characteristics
9.11.1 AC Characteristics and Operating Condition for -18 speed grade
SPEED GRADE
Bin(CL-tRCD-tRP)
DDR2-1066 (-18)
7-7-7
SYM.
UNIT25
NOTES
PARAMETER
MIN.
MAX.
tRCD
tRP
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Auto Refresh to Active/Auto Refresh command period
13.125
13.125
53.125
40
nS
nS
nS
nS
nS
μS
23
23
23
4,23
5
tRC
tRAS
tRFC
70000
105
7.8
5
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
Average periodic
refresh Interval
tREFI
tCCD
3.9
μS
5,6
2
nCK
to
command delay
CAS
CAS
tCK(avg) @ CL=4
tCK(avg) @ CL=5
tCK(avg) @ CL=6
tCK(avg) @ CL=7
3.75
3
7.5
nS
nS
30,31
30,31
30,31
30,31
30,31
30,31
7.5
tCK(avg)
Average clock period
2.5
7.5
nS
1.875
0.48
0.48
7.5
nS
tCH(avg)
tCL(avg)
Average clock high pulse width
Average clock low pulse width
0.52
0.52
tCK(avg)
tCK(avg)
tAC
-350
-325
350
325
pS
pS
35
35
DQ output access time from CLK/
CLK
tDQSCK
DQS output access time from CLK /
CLK
tDQSQ
tCKE
tRRD
tFAW
tWR
DQS-DQ skew for DQS & associated DQ signals
CKE minimum high and low pulse width
Active to active command period for 1KB page size
Four Activate Window for 1KB page size
Write recovery time
175
pS
nCK
nS
13
7
3
7.5
8,23
23
35
nS
15
nS
23
tDAL
tWTR
tRTP
Auto-precharge write recovery + precharge time
Internal Write to Read command delay
Internal Read to Precharge command delay
WR + tnRP
7.5
nCK
nS
24
9,23
4,23
7.5
nS
10, 26,
40,42,43
tIS (base)
tIH (base)
tIS (ref)
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
125
200
325
325
pS
pS
pS
pS
11, 26,
40,42,43
10,26,
40,42,43
11,26,
40,42,43
tIH (ref)
tIPW
tDQSS
tDSS
Address and control input pulse width for each input
DQS latching rising transitions to associated clock edges
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
DQS input high pulse width
0.6
-0.25
0.2
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
0.25
28
28
28
tDSH
0.2
tDQSH
tDQSL
0.35
0.35
DQS input low pulse width
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
AC Characteristics and Operating Condition for -18 speed grade, continued
SPEED GRADE
DDR2-1066 (-18)
7-7-7
SYM.
Bin(CL-tRCD-tRP)
PARAMETER
UNITS25 NOTES
MIN.
MAX.
tWPRE
tWPST
tRPRE
tRPST
Write preamble
Write postamble
Read preamble
Read postamble
0.35
0.4
0.9
0.4
tCK(avg)
0.6
1.1
0.6
tCK(avg)
tCK(avg)
tCK(avg)
12
14,36
14,37
16,27,29,
41,42,44
tDS(base)
tDH(base)
tDS(ref)
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input setup time
0
pS
pS
pS
pS
17,27,29,
41,42,44
75
16,27,29,
41,42,44
200
200
17,27,29,
41,42,44
tDH(ref)
DQ and DM input hold time
tDIPW
tHZ
DQ and DM input pulse width for each input
0.35
tCK(avg)
pS
tAC,max
15,35
15,35
15,35
Data-out high-impedance time from CLK/
CLK
tLZ(DQS)
tLZ(DQ)
tAC,min
tAC,max
tAC,max
pS
pS
DQS/
-low-impedance time from CLK/
DQS
CLK
2 x tAC,min
DQ low-impedance time from CLK/
Clock half pulse width
CLK
Min. (tCH(abs),
tCL(abs))
tHP
pS
32
tQHS
tQH
Data hold skew factor
250
pS
pS
33
34
23
DQ/DQS output hold time from DQS
tHP - tQHS
tXSNR
tXSRD
tXP
Exit Self Refresh to a non-Read command
Exit Self Refresh to a Read command
tRFC + 10
nS
200
3
nCK
nCK
nCK
Exit precharge power down to any command
Exit active power down to Read command
Exit active power down to Read command
(slow exit, lower power)
tXARD
3
18
tXARDS
10 - AL
nCK
18,19
tAOND
tAON
ODT turn-on delay
2
2
nCK
nS
20
ODT turn-on
tAC,min
tAC,max + 2.575
20,35
3 x tCK(avg) +
tAC,max+1
tAONPD
ODT turn-on (Power Down mode)
tAC,min + 2
nS
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
nCK
nS
21,39
tAC,min
tAC,max + 0.6
21,38,39
2.5 x tCK(avg) +
tAC,max + 1
tAOFPD
ODT turn-off (Power Down mode)
tAC,min + 2
nS
tANPD
tAXPD
tMRD
tMOD
tOIT
ODT to power down Entry Latency
ODT Power Down Exit Latency
4
11
2
nCK
nCK
nCK
nS
Mode Register Set command cycle time
MRS command to ODT update delay
OCD Drive mode output delay
0
12
12
23
23
0
nS
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS+tCK(avg)+tIH
nS
22
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
9.11.2 AC Characteristics and Operating Condition for -25/25I/-3 speed grades
DDR2-800
(-25/25I)
DDR2-667
SPEED GRADE
(-3)
SYM.
UNITS25 NOTES
Bin(CL-tRCD-tRP)
PARAMETER
5-5-5/6-6-6
5-5-5
MIN.
MAX.
MIN.
15
MAX.
tRCD
tRP
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
12.5
12.5
52.5
40
nS
nS
nS
nS
23
23
15
tRC
55
23
tRAS
70000
40
70000
4,23
Auto Refresh to Active/Auto Refresh command
period
tRFC
105
105
nS
5
7.8
3.9
7.8
3.9
μS
μS
5
2
2
0°C ≤ TCASE ≤ 85°C
85°C < TCASE ≤ 95°C
Average periodic
refresh Interval
tREFI
tCCD
5,6
nCK
to
command delay
CAS
CAS
tCK(avg) @ CL=3
tCK(avg) @ CL=4
tCK(avg) @ CL=5
tCK(avg) @ CL=6
5
8
8
5
3.75
3
8
8
nS
nS
30,31
30,31
30,31
30,31
30,31
30,31
3.75
2.5
tCK(avg) Average clock period
8
8
nS
2.5
8
nS
tCH(avg) Average clock high pulse width
tCL(avg) Average clock low pulse width
0.48
0.48
0.52
0.52
0.48
0.48
0.52
0.52
tCK(avg)
tCK(avg)
tAC
-400
-350
400
350
-450
-400
450
400
pS
pS
35
35
DQ output access time from CLK/
CLK
tDQSCK
DQS output access time from CLK /
CLK
tDQSQ
tCKE
DQS-DQ skew for DQS & associated DQ signals
CKE minimum high and low pulse width
200
240
pS
13
7
3
3
nCK
Active to active command period for 1KB page
size
tRRD
7.5
7.5
nS
8,23
tFAW
tWR
Four Activate Window for 1KB page size
Write recovery time
35
15
37.5
15
nS
nS
23
23
tDAL
tWTR
tRTP
Auto-precharge write recovery + precharge time WR + tnRP
WR + tnRP
7.5
nCK
nS
24
Internal Write to Read command delay
7.5
7.5
9,23
4,23
Internal Read to Precharge command delay
7.5
nS
10, 26,
40,42,43
tIS (base) Address and control input setup time
tIH (base) Address and control input hold time
175
250
375
375
0.6
200
275
400
400
0.6
pS
pS
11, 26,
40,42,43
10,26,
40,42,43
tIS (ref)
tIH (ref)
tIPW
Address and control input setup time
Address and control input hold time
pS
11,26,
40,42,43
pS
Address and control input pulse width for each
input
tCK(avg)
tCK(avg)
DQS latching rising transitions to associated
clock edges
tDQSS
-0.25
0.25
-0.25
0.25
28
tDSS
tDSH
DQS falling edge to CLK setup time
DQS falling edge hold time from CLK
DQS input high pulse width
0.2
0.2
0.2
0.2
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
28
28
tDQSH
tDQSL
0.35
0.35
0.35
0.35
DQS input low pulse width
Publication Release Date: Oct. 12, 2010
Revision A01
- 45 -
W9751G8JB
AC Characteristics and Operating Condition for -25/25I/-3 speed grades, continued
DDR2-800
DDR2-667
(-3)
SPEED GRADE
(-25/25I)
SYM.
UNITS25 NOTES
Bin(CL-tRCD-tRP)
PARAMETER
5-5-5/6-6-6
5-5-5
MIN.
MAX.
MIN.
0.35
0.4
MAX.
tWPRE Write preamble
0.35
0.4
0.9
0.4
tCK(avg)
tCK(avg)
tWPST
tRPRE
tRPST
Write postamble
0.6
1.1
0.6
0.6
1.1
0.6
12
Read preamble
Read postamble
0.9
tCK(avg) 14,36
tCK(avg) 14,37
0.4
16,27,29,
pS
tDS(base) DQ and DM input setup time
tDH(base) DQ and DM input hold time
tDS(ref) DQ and DM input setup time
tDH(ref) DQ and DM input hold time
50
100
175
300
300
0.35
41,42,44
17,27,29,
pS
125
250
250
0.35
41,42,44
16,27,29,
pS
41,42,44
17,27,29,
pS
41,42,44
DQ and DM input pulse width for each
tDIPW
tHZ
tCK(avg)
input
Data-out high-impedance time from
tAC,max
tAC,max
pS
15,35
CLK/
CLK
DQS/
CLK/
-low-impedance time from
DQS
tLZ(DQS)
tLZ(DQ)
tHP
tAC,min
tAC,max
tAC,max
tAC,min
tAC,max
tAC,max
pS
pS
pS
15,35
15,35
32
CLK
2 x tAC,min
2 x tAC,min
DQ low-impedance time from CLK/
Clock half pulse width
CLK
Min.
(tCH(abs),
tCL(abs))
Min.
(tCH(abs),
tCL(abs))
tQHS
tQH
Data hold skew factor
300
340
pS
pS
33
34
23
DQ/DQS output hold time from DQS
tHP - tQHS
tHP - tQHS
tRFC + 10
200
tXSNR
tXSRD
Exit Self Refresh to a non-Read command tRFC + 10
nS
Exit Self Refresh to a Read command
200
nCK
Exit precharge power down to any
command
tXP
2
2
2
nCK
nCK
tXARD
Exit active power down to Read command
Exit active power down to Read command
(slow exit, lower power)
2
18
tXARDS
8 - AL
7 - AL
nCK
18,19
tAOND
tAON
ODT turn-on delay
2
2
2
2
nCK
nS
20
ODT turn-on
tAC,min
tAC,max + 0.7
tAC,min
tAC,max + 0.7
20,35
2 x tCK(avg) +
tAC,max + 1
2 x tCK(avg) +
tAC,max + 1
tAONPD ODT turn-on (Power Down mode)
tAC,min + 2
tAC,min + 2
nS
tAOFD
tAOF
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
nCK
nS
21,39
tAC,min
tAC,max + 0.6
tAC,min
tAC,max + 0.6
21,38,39
2.5 x tCK(avg)
+ tAC,max + 1
2.5 x tCK(avg)
+ tAC,max + 1
tAOFPD ODT turn-off (Power Down mode)
tAC,min + 2
tAC,min + 2
nS
tANPD
tAXPD
tMRD
tMOD
tOIT
ODT to power down Entry Latency
ODT Power Down Exit Latency
3
8
2
0
0
3
8
2
0
0
nCK
nCK
nCK
nS
Mode Register Set command cycle time
MRS command to ODT update delay
OCD Drive mode output delay
12
12
12
12
23
23
nS
Minimum time clocks remain ON after
CKE asynchronously drops LOW
tIS+tCK(avg)+
tIH
tIS+tCK(avg)+
tIH
tDELAY
nS
22
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
Notes:
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified. ODT is
disabled for all measurements that are not ODT-specific.
3. AC timing reference load:
VDDQ
DQ
Output
DUT
VTT = VDDQ/2
DQS
Timing
reference
point
25Ω
DQS
Figure 16 – AC timing reference load
4. This is a minimum requirement. Minimum read to precharge timing is AL + BL / 2 provided that the tRTP and tRAS(min)
have been satisfied.
5. If refresh timing is violated, data corruption may occur and the data must be re-written with valid data before a valid READ
can be executed.
6. This is an optional feature. For detailed information, please refer to “operating temperature condition” section 9.2 in this data
sheet.
7. tCKE min of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the
valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
8. A minimum of two clocks (2 *nCK) is required irrespective of operating frequency.
9. tWTR is at least two clocks (2 * nCK) independent of operation frequency.
10. There are two sets of values listed for Command/Address input setup time: tIS(base) and tIS(ref). The tIS(ref) value (for
reference only) is equivalent to the baseline value of tIS(base) at VREF when the slew rate is 1.0 V/nS. The baseline value
tIS(base) is the JEDEC defined value, referenced from the input signal crossing at the VIH(ac) level for a rising signal and
VIL(ac) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to
1.0 V/nS, then the baseline values must be derated by adding the values from table of tIS/tIH derating values for DDR2-667,
DDR2-800 and DDR2-1066 (page 55).
CLK
CLK
tIH(base)
tIS(base) tIH(base)
tIS(base)
Logic levels
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
VREF levels
tIS(ref)
tIH(ref)
tIS(ref)
tIH(ref)
Figure 17 – Differential input waveform timing – tIS and tIH
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
11. There are two sets of values listed for Command/Address input hold time: tIH(base) and tIH(ref). The tIH(ref) value (for
reference only) is equivalent to the baseline value of tIH(base) at VREF when the slew rate is 1.0 V/nS. The baseline value
tIH(base) is the JEDEC defined value, referenced from the input signal crossing at the VIL(dc) level for a rising signal and
VIH(dc) for a falling signal applied to the device under test. See Figure 17. If the Command/Address slew rate is not equal to
1.0 V/nS, then the baseline values must be derated by adding the values from table tIS/tIH derating values for DDR2-667,
DDR2-800 and DDR2-1066 (page 55).
12. The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this
parameter, but system performance (bus turnaround) will degrades accordingly.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as
well as output Slew Rate mismatch between DQS /
and associated DQ in any given cycle.
DQS
14. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is
no longer driving (tRPST), or begins driving (tRPRE). Figure 18 shows a method to calculate these points when the device
is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent.
15. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a
specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ). Figure 18
shows a method to calculate the point when device is no longer driving (tHZ), or begins driving (tLZ) by measuring the
signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is
consistent. tLZ(DQ) refers to tLZ of the DQ‟s and tLZ(DQS) refers to tLZ of the (DQS,
, RDQS,
) each treated
RDQS
DQS
as single-ended signal.
VOH - x mV
VTT + 2x mV
VTT + x mV
VOH - 2x mV
tHZ
tLZ
tRPRE begin point
tRPST end point
VOL + 2x mV
VOL + x mV
VTT - x mV
VTT - 2x mV
T1 T2
T1 T2
tHZ,tRPST end point = 2 x T1 - T2
tLZ,tRPRE begin point = 2 x T1 - T2
Figure 18 – Method for calculating transitions and endpoints
16. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and
DM input setup time: tDS(base) and tDS(ref). The tDS(ref) value (for reference only) is equivalent to the baseline value
tDS(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDS(base) is the JEDEC defined value,
referenced from the input signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and
from the input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied to the
device under test. DQS,
signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the
DQS
differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from
table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60).
17. Input waveform timing tDH with differential data strobe enabled MR[bit10]=0. There are two sets of values listed for DQ and
DM input hold time: tDH(base) and tDH(ref). The tDH(ref) value (for reference only) is equivalent to the baseline value
tDH(base) at VREF when the slew rate is 2.0 V/nS, differentially. The baseline value tDH(base) is the JEDEC defined value,
referenced from the differential data strobe crosspoint to the input signal crossing at the VIH(dc) level for a falling signal and
from the differential data strobe crosspoint to the input signal crossing at the VIL(dc) level for a rising signal applied to the
device under test. DQS,
signals must be monotonic between VIL(dc)max and VIH(dc)min. See Figure 19. If the
DQS
differential DQS slew rate is not equal to 2.0 V/nS, then the baseline values must be derated by adding the values from
table of DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe (page 60).
Publication Release Date: Oct. 12, 2010
- 48 -
Revision A01
W9751G8JB
DQS
DQS
tDS(base)
tDH(base)
tDS(base) tDH(base)
Logic levels
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
VREF levels
tDS(ref)
tDH(ref)
tDS(ref)
tDH(ref)
Figure 19 – Differential input waveform timing – tDS and tDH
18. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active
power down exit timing. tXARDS is expected to be used for slow active power down exit timing.
19. AL = Additive Latency.
20. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND, which is interpreted differently per speed bin.
For DDR2-667/800/1066, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual
input clock edges.
21. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
For DDR2-667/800: This is interpreted differently per speed bin. If tCK(avg) = 3 nS is assumed, tAOFD is 1.5 nS (=
0.5 x 3 nS) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by
counting the actual input clock edges.
For DDR2-1066: This is interpreted as 0.5 x tCK(avg) [nS] after the second trailing clock edge counting from the
clock edge that registered a first ODT LOW and by counting the actual input clock edges. tAOFD is 0.9375 [nS] (=
0.5 x 1.875 [nS]) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW
and by counting the actual input clock edges.
22. The clock frequency is allowed to change during Self Refresh mode or precharge power-down mode. In case of clock
frequency change during precharge power-down, a specific procedure is required as described in section 7.10.
23. For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM /
tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
Examples:
The device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are
met. This means: For DDR2-667 5-5-5, of which tRP = 15nS, the device will support tnRP = RU{tRP / tCK(avg)} = 5,
i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm+5
is valid even if (Tm+5 - Tm) is less than 15nS due to input clock jitter. For DDR2-1066 7-7-7, of which tRP = 13.125
nS, the device will support tnRP = RU{tRP / tCK(avg)} = 7, i.e. as long as the input clock jitter specifications are met,
Precharge command at Tm and Active command at Tm+7 is valid even if (Tm+7 - Tm) is less than 13.125 nS due to
input clock jitter.
24. tDAL [nCK] = WR [nCK] + tnRP [nCK] = WR + RU {tRP [pS] / tCK(avg) [pS] }, where WR is the value programmed in the
mode register set and RU stands for round up.
Example:
For DDR2-1066 7-7-7 at tCK(avg) = 1.875 nS with WR programmed to 8 nCK, tDAL = 8 + RU{13.125 nS / 1.875
nS} [nCK] = 8 + 7 [nCK] = 15 [nCK].
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25. New units, „tCK(avg)‟ and „nCK‟, are introduced in DDR2-667, DDR2-800 and DDR2-1066.
Unit „tCK(avg)‟ represents the actual tCK(avg) of the input clock under operation.
Unit „nCK‟ represents one clock cycle of the input clock, counting the actual clock edges.
Examples:
For DDR2-667/800: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+2, even if (Tm+2 - Tm) is 2 x tCK(avg) + tERR(2per),min.
For DDR2-1066: tXP = 3 [nCK] means; if Power Down exit is registered at Tm, an Active command may be
registered at Tm+3, even if (Tm+3 - Tm) is 3 x tCK(avg) + tERR(3per),min.
26. These parameters are measured from a command/address signal (CKE,
,
,
,
, ODT, BA0, A0, A1, etc.)
WE
CS RAS CAS
transition edge to its respective clock signal (CLK/
) crossing. The spec values are not affected by the amount of clock
CLK
jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the
command/address. That is, these parameters should be met whether clock jitter is present or not.
27. If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can
be executed.
28. These parameters are measured from a data strobe signal (DQS,
, RDQS,
) crossing to its respective clock
RDQS
DQS
signal (CLK/
) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc),
CLK
etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is
present or not.
29. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe
signal (DQS,
, RDQS,
) crossing.
RDQS
DQS
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30. Input clock jitter spec parameter. These parameters and the ones in the table below are referred to as 'input clock jitter spec
parameters'. The jitter specified is a random jitter meeting a Gaussian distribution.
Input clock-Jitter specifications parameters for DDR2-667, DDR2-800 and DDR2-1066
DDR2-667
MIN. MAX.
DDR2-800
MIN. MAX.
DDR2-1066
PARAMETER
SYMBOL
UNIT
MIN.
-90
MAX.
90
Clock period jitter
tJIT(per)
tJIT(per,lck)
tJIT(cc)
-125
-100
-250
-200
125
100
250
200
-100
-80
100
80
pS
pS
pS
pS
Clock period jitter during DLL locking period
Cycle to cycle clock period
-80
80
-200
-160
200
160
-180
-160
180
160
Cycle to cycle clock period jitter during DLL
locking period
tJIT(cc,lck)
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6-10per)
-175
-225
-250
-250
-350
175
225
250
250
350
-150
-175
-200
-200
-300
150
175
200
200
300
-132
-157
-175
-188
-250
132
157
175
188
250
pS
pS
pS
pS
pS
Cumulative error across n cycles,
n = 6 ... 10, inclusive
Cumulative error across n cycles,
n = 11 ... 50, inclusive
tERR(11-50per)
tJIT(duty)
-450
-125
450
125
-450
-100
450
100
-425
-75
425
75
pS
pS
Duty cycle jitter
Definitions:
-
tCK(avg)
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window.
N
tCK(avg) =
tCK / N
j
j1
where
N = 200
-
tCH(avg) and tCL(avg)
tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses.
N
tCH(avg) =
tCH / (N × tCK(avg))
j
j1
where
N = 200
tCL(avg) is defined as the average LOW pulse width, as calculated across any consecutive 200 LOW pulses.
N
tCL(avg) =
tCL / (N × tCK(avg))
j
j1
where
N = 200
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tJIT(duty)
tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from
tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).
tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)}
where,
tJIT(CH) = {tCHi- tCH(avg) where i=1 to 200}
tJIT(CL) = {tCLi- tCL(avg) where i=1 to 200}
-
tJIT(per), tJIT(per,lck)
tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi- tCK(avg) where i=1 to 200}
tJIT(per) defines the single period jitter when the DLL is already locked.
tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.
tJIT(per) and tJIT(per,lck) are not guaranteed through final production testing.
-
tJIT(cc), tJIT(cc,lck)
tJIT(cc) is defined as the difference in clock period between two consecutive clock cycles:
tJIT(cc) = Max of |tCKi+1 – tCKi|
tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked.
tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.
tJIT(cc) and tJIT(cc,lck) are not guaranteed through final production testing.
-
tERR(2per), tERR (3per), tERR (4per), tERR (5per), tERR (6-10per) and tERR (11-50per)
tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).
in1
tERR(nper) =
tCK –n × tCK(avg)
j
j1
n = 2
n = 3
n = 4
n = 5
for tERR(2per)
for tERR(3per)
for tERR(4per)
for tERR(5per)
Where
6 n 10 for tERR(6 –10per)
11 n 50 for tERR(11– 50per)
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31. These parameters are specified per their average values, however it is understood that the following relationship between
the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used
for calculations in the table below.)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Absolute clock period
tCK(abs)
tCK(avg),min + tJIT(per),min
tCK(avg),max + tJIT(per),max
pS
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
tCH(abs)
tCL(abs)
tCH(avg),min x tCK(avg),min +
tJIT(duty),min
tCH(avg),max x tCK(avg),max +
tJIT(duty),max
pS
pS
tCL(avg),min x tCK(avg),min +
tJIT(duty),min
tCL(avg),max x tCK(avg),max +
tJIT(duty),max
Examples: 1) For DDR2-667, tCH(abs),min = ( 0.48 x 3000 pS ) - 125 pS = 1315 pS
2) For DDR2-1066, tCH(abs),min = ( 0.48 x 1875 pS ) - 75 pS = 825 pS
32. tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input
specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for
tQH calculation is determined by the following equation;
tHP = Min ( tCH(abs), tCL(abs) ),
where,
tCH(abs) is the minimum of the actual instantaneous clock HIGH time;
tCL(abs) is the minimum of the actual instantaneous clock LOW time;
33. tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,
both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-
channel variation of the output drivers
34. tQH = tHP – tQHS, where:
tHP is the minimum of the absolute half period of the actual input clock; and
tQHS is the specification value under the max column.
{The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples:
1) If the system provides tHP of 1315 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 975 pS minimum.
2) If the system provides tHP of 1420 pS into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 pS minimum.
3) If the system provides tHP of 825 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 575 pS minimum.
4) If the system provides tHP of 900 pS into a DDR2-1066 SDRAM, the DRAM provides tQH of 650 pS minimum.
35. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the
input clock. (output deratings are relative to the SDRAM input clock.)
Examples:
1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS and tERR(6-10per),max = +
293 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 400 pS - 293 pS = - 693 pS and
tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 400 pS + 272 pS = + 672 pS.
Similarly, tLZ(DQ) for DDR2-667 derates to tLZ(DQ),min(derated) = - 900 pS - 293 pS = - 1193 pS and
tLZ(DQ),max(derated) = 450 pS + 272 pS = + 722 pS. (Caution on the min/max usage!)
2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS and tERR(6-10per),max = +
223 pS, then tDQSCK,min(derated) = tDQSCK,min - tERR(6-10per),max = - 300 pS - 223 pS = - 523 pS and
tDQSCK,max(derated) = tDQSCK,max - tERR(6-10per),min = 300 pS + 202 pS = + 502 pS.
Similarly, tLZ(DQ) for DDR2-1066 derates to tLZ(DQ),min(derated) = - 700 pS - 223 pS = - 923 pS and
tLZ(DQ),max(derated) = 350 pS + 202 pS = + 552 pS. (Caution on the min/max usage!)
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36. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per) of the input
clock. (output deratings are relative to the SDRAM input clock.)
Examples:
1) If the measured jitter into a DDR2-667 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 93 pS, then
tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 2178 pS and tRPRE,max(derated) =
tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 93 pS = + 2843 pS. (Caution on the min/max usage!)
2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(per),min = - 72 pS and tJIT(per),max = + 63 pS, then
tRPRE,min(derated) = tRPRE,min + tJIT(per),min = 0.9 x tCK(avg) - 72 pS = + 1615.5 pS and tRPRE,max(derated)
= tRPRE,max + tJIT(per),max = 1.1 x tCK(avg) + 63 pS = + 2125.5 pS. (Caution on the min/max usage!)
37. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(duty) of the input
clock. (output deratings are relative to the SDRAM input clock.)
Examples:
1) If the measured jitter into a DDR2-667 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 93 pS, then
tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 928 pS and tRPST,max(derated) =
tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 93 pS = + 1592 pS. (Caution on the min/max usage!)
2) If the measured jitter into a DDR2-1066 SDRAM has tJIT(duty),min = - 72 pS and tJIT(duty),max = + 63 pS, then
tRPST,min(derated) = tRPST,min + tJIT(duty),min = 0.4 x tCK(avg) - 72 pS = + 678 pS and tRPST,max(derated) =
tRPST,max + tJIT(duty),max = 0.6 x tCK(avg) + 63 pS = + 1188 pS. (Caution on the min/max usage!)
38. When the device is operated with input clock jitter, this parameter needs to be derated by { -tJIT(duty),max - tERR(6-
10per),max } and { - tJIT(duty),min - tERR(6-10per),min } of the actual input clock. (output deratings are relative to the
SDRAM input clock.)
Examples:
1) If the measured jitter into a DDR2-667 SDRAM has tERR(6-10per),min = - 272 pS, tERR(6-10per),max = + 293
pS, tJIT(duty),min = - 106 pS and tJIT(duty),max = + 94 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max
- tERR(6-10per),max } = - 450 pS + { - 94 pS - 293 pS} = - 837 pS and tAOF,max(derated) = tAOF,max + { -
tJIT(duty),min - tERR(6-10per),min } = 1050 pS + { 106 pS + 272 pS } = + 1428 pS. (Caution on the min/max
usage!)
2) If the measured jitter into a DDR2-1066 SDRAM has tERR(6-10per),min = - 202 pS, tERR(6-10per),max = + 223
pS, tJIT(duty),min = - 66 pS and tJIT(duty),max = + 74 pS, then tAOF,min(derated) = tAOF,min + { - tJIT(duty),max -
tERR(6-10per),max } = - 350 pS + { - 74 pS - 223 pS} = - 647 pS and tAOF,max(derated) = tAOF,max + { -
tJIT(duty),min - tERR(6-10per),min } = 950 pS + { 66 pS + 202 pS } = + 1218 pS. (Caution on the min/max usage!)
39. For tAOFD of DDR2-667/800/1066, the 1/2 clock of nCK in the 2.5 x nCK assumes a tCH(avg), average input clock HIGH
pulse width of 0.5 relative to tCK(avg). tAOF,min and tAOF,max should each be derated by the same amount as the actual
amount of tCH(avg) offset present at the DRAM input with respect to 0.5.
Example:
If an input clock has a worst case tCH(avg) of 0.48, the tAOF,min should be derated by subtracting 0.02 x tCK(avg)
from it, whereas if an input clock has a worst case tCH(avg) of 0.52, the tAOF,max should be derated by adding
0.02 x tCK(avg) to it. Therefore, we have;
tAOF,min(derated) = tAC,min - [0.5 - Min(0.5, tCH(avg),min)] x tCK(avg)
tAOF,max(derated) = tAC,max + 0.6 + [Max(0.5, tCH(avg),max) - 0.5] x tCK(avg)
or
tAOF,min(derated) = Min(tAC,min, tAC,min - [0.5 - tCH(avg),min] x tCK(avg))
tAOF,max(derated) = 0.6 + Max(tAC,max, tAC,max + [tCH(avg),max - 0.5] x tCK(avg))
where tCH(avg),min and tCH(avg),max are the minimum and maximum of tCH(avg) actually measured at the DRAM
input balls.
Note that these deratings are in addition to the tAOF derating per input clock jitter, i.e. tJIT(duty) and tERR(6-10per). However
tAC values used in the equations shown above are from the timing parameter table and are not derated.
Thus the final derated values for tAOF are;
tAOF,min(derated_final) = tAOF,min(derated) + { - tJIT(duty),max - tERR(6-10per),max }
tAOF,max(derated_final) = tAOF,max(derated) + { - tJIT(duty),min - tERR(6-10per),min }
40. Timings are specified with command/address input slew rate of 1.0 V/nS.
41. Timings are specified with DQs and DM input slew rate of 1.0V/nS.
42. Timings are specified with CLK/ CLK differential slew rate of 2.0 V/nS. Timings are guaranteed for DQS signals with a
differential slew rate of 2.0 V/nS in differential strobe mode.
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43. tIS and tIH (input setup and hold) derating.
tIS/tIH Derating values for DDR2-667, DDR2-800 and DDR2-1066
ΔtIS and ΔtIH Derating Values for DDR2-667, DDR2-800 and DDR2-1066
Command/
Address
Slew Rate
(V/nS)
CLK/ CLK Differential Slew Rate
2.0 V/nS
1.5 V/nS
1.0 V/nS
Unit
ΔtIS
+150
+143
+133
+120
+100
+67
0
ΔtIH
+94
+89
+83
+75
+45
+21
0
ΔtIS
+180
+173
+163
+150
+130
+97
+30
+25
+17
+8
ΔtIH
+124
+119
+113
+105
+75
ΔtIS
+210
+203
+193
+180
+160
+127
+60
ΔtIH
+154
+149
+143
+135
+105
+81
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
pS
+51
+30
+60
-5
-14
+16
+55
+46
-13
-31
-1
+47
+29
-22
-54
-24
+38
+6
-34
-83
-4
-53
+26
-23
-60
-125
-188
-292
-375
-500
-708
-1125
-30
-95
0
-65
-100
-168
-200
-325
-517
-1000
-70
-158
-262
-345
-470
-678
-1095
-40
-128
-232
-315
-440
-648
-1065
-138
-170
-295
-487
-970
-108
-140
-265
-457
-940
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and
tIH(base) value to the ΔtIS and ΔtIH derating value respectively. Example: tIS (total setup time) = tIS(base) + ΔtIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 20 Illustration of nominal slew rate for tIS.
If the actual signal is later than the nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 21 Illustration of tangent line
for tIS.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded „DC to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 22 Illustration of nominal slew rate for tIH.
If the actual signal is earlier than the nominal slew rate line anywhere between shaded „DC to VREF(dc) region‟, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 23 Illustration of
tangent line for tIH.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above tIS/tIH derating values for DDR2-667, DDR2-800 and DDR2-1066 table, the
derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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CLK
CLK
tIS
tIH
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
VREF to AC
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to AC
region
VIL(ac)max
VSS
ΔTF
ΔTR
VIH(ac)min - VREF(dc)
VREF(dc) - VIL(ac)max
Setup Slew Rate
Rising Signal
Setup Slew Rate
Falling Signal
=
=
ΔTR
ΔTF
Figure 20 – Illustration of nominal slew rate for tIS
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CLK
CLK
tIS
tIH
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
line
VREF to AC
region
tangent
line
VREF(dc)
tangent
line
VIL(dc)max
VREF to AC
region
VIL(ac)max
nominal
line
ΔTR
VSS
tangent line[VIH(ac)min - VREF(dc)
]
Setup Slew Rate
Rising Signal
=
ΔTF
ΔTR
tangent line[VREF(dc) - VIL(ac)max
]
Setup Slew Rate
Falling Signal
=
ΔTF
Figure 21 – Illustration of tangent line for tIS
Publication Release Date: Oct. 12, 2010
Revision A01
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W9751G8JB
CLK
CLK
tIH
tIS
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
DC to VREF
region
nominal
slew rate
VREF(dc)
nominal
slew rate
DC to VREF
region
VIL(dc)max
VIL(ac)max
VSS
ΔTR
ΔTF
VIH(dc)min - VREF(dc)
VREF(dc) - VIL(dc)max
Hold Slew Rate
Falling Signal
Hold Slew Rate
Rising Signal
=
=
ΔTF
ΔTR
Figure 22 – Illustration of nominal slew rate for tIH
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CLK
CLK
tIS
tIH
tIS
tIH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
line
DC to VREF
region
tangent
line
VREF(dc)
tangent
line
DC to VREF
region
nominal
line
VIL(dc)max
VIL(ac)max
VSS
ΔTR
ΔTF
tangent line[VREF(dc) - VIL(ac)max
]
Hold Slew Rate
Rising Signal
=
ΔTR
tangent line[VIH(dc)min - VREF(dc)
]
Hold Slew Rate
Falling Signal
=
ΔTF
Figure 23 – Illustration of tangent line for tIH
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44. Data setup and hold time derating.
DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential data strobe
ΔtDS, ΔtDH derating values for DDR2-667, DDR2-800 and DDR2-1066 (All units in „pS‟; the note applies to
the entire table)
DQ
Slew
Rate
(V/nS)
DQS/DQS Differential Slew Rate
4.0 V/nS
3.0 V/nS
2.0 V/nS
1.8 V/nS
1.6 V/nS
1.4 V/nS
1.2 V/nS
1.0 V/nS
0.8 V/nS
ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH ΔtDS ΔtDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
45 100
45 100
45
21
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
67
0
-
21
0
-
67
0
-5
-
21
67
0
79
12
7
33
12
-2
-
-
0
24
19
11
2
24
10
-7
-30
-
-
-
-
-
-
-
-
-
-14
-5
-14
31
23
14
2
22
5
-
-
-
-
-
-
-
-
-
-
-
-
-13 -31
-1
-19
35
26
14
17
-6
-35
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-10 -42
-18
-47
38
26
0
6
-
-
-
-
-
-
-
-
-
-
-
-10 -59
-23
-65
38
12
-11
-53
-
-
-
-
-
-
-
-24 -89 -12 -77
-
-
-
-
-
-52 -140 -40 -128 -28 -116
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and
tDH(base) value to the ΔtDS and ΔtDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first
crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line between
shaded „VREF(dc) to AC region‟, use nominal slew rate for derating value. See Figure 24 Illustration of nominal slew rate for
tDS (differential DQS,
).
DQS
If the actual signal is later than the nominal slew rate line anywhere between shaded „VREF(dc) to AC region‟, the slew rate of a
tangent line to the actual signal from the AC level to DC level is used for derating value. See Figure 25 Illustration of tangent line
for tDS (differential DQS,
).
DQS
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VIH(dc)min and the first crossing of VREF(dc). If the actual signal is always later than the nominal slew rate line between
shaded „DC level to VREF(dc) region‟, use nominal slew rate for derating value. See Figure 26 Illustration of nominal slew rate
for tDH (differential DQS,
).
DQS
If the actual signal is earlier than the nominal slew rate line anywhere between shaded „DC to VREF(dc) region‟, the slew rate of
a tangent line to the actual signal from the DC level to VREF(dc) level is used for derating value. See Figure 27 Illustration of
tangent line for tDH (differential DQS,
).
DQS
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at
the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in above DDR2-667, DDR2-800 and DDR2-1066 tDS/tDH derating with differential
data strobe table, the derating values may be obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
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DQS
DQS
tDH
tDS
tDS
tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF to AC
region
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to AC
region
VIL(ac)max
VSS
ΔTF
ΔTR
VREF(dc) - VIL(ac)max
VIH(ac)min - VREF(dc)
Setup Slew Rate
Falling Signal
Setup Slew Rate
Rising Signal
=
=
ΔTF
ΔTR
Figure 24 – Illustration of nominal slew rate for tDS (differential DQS,
)
DQS
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DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
VREF(dc)
VREF to AC
region
tangent
line
tangent
line
VIL(dc)max
VIL(ac)max
VREF to AC
region
nominal
line
ΔTR
VSS
Setup Slew Rate
Rising Signal
tangent line[VIH(ac)min - VREF(dc)
]
=
ΔTR
ΔTF
tangent line[VREF(dc) - VIL(ac)max
]
Setup Slew Rate
Falling Signal
=
ΔTF
Figure 25 – Illustration of tangent line for tDS (differential DQS,DQS
)
Publication Release Date: Oct. 12, 2010
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DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
DC to VREF
region
nominal
slew rate
nominal
slew rate
DC to VREF
region
VIL(dc)max
VIL(ac)max
VSS
ΔTR
ΔTF
VREF(dc) - VIL(dc)max
VIH(dc)min - VREF(dc)
Hold Slew Rate
Rising Signal
Hold Slew Rate
Falling Signal
=
=
ΔTR
ΔTF
Figure 26 – Illustration of nominal slew rate for tDH (differential DQS,
)
DQS
Publication Release Date: Oct. 12, 2010
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DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
line
DC to VREF
region
tangent
line
VREF(dc)
tangent
line
DC to VREF
nominal
line
region
VIL(dc)max
VIL(ac)max
VSS
ΔTR
ΔTF
tangent line[VREF(dc) - VIL(ac)max
]
Hold Slew Rate
Rising Signal
=
ΔTR
tangent line [VIH(dc)min - VREF(dc)
]
Hold Slew Rate
Falling Signal
=
ΔTF
Figure 27 – Illustration tangent line for tDH (differential DQS,
)
DQS
Publication Release Date: Oct. 12, 2010
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9.12 AC Input Test Conditions
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
CONDITION
Input reference voltage
SYMBOL
VREF
VALUE
0.5 x VDDQ
1.0
UNIT
V
NOTES
1
1
Input signal maximum peak to peak swing
Input signal minimum slew rate
Notes:
VSWING(MAX)
SLEW
V
1.0
V/nS
2, 3
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(ac) level applied to the device under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the
range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
9.13 Differential Input/Output AC Logic Levels
(0°C ≤ TCASE ≤ 85°C for -18/-25/-3, -40°C ≤ TCASE ≤ 95°C for 25I, VDD, VDDQ = 1.8V ± 0.1V)
PARAMETER
AC differential input voltage
AC differential cross point input voltage
AC differential cross point output voltage
Notes:
SYM.
VID (ac)
VIX (ac)
VOX (ac)
MIN.
0.5
MAX.
UNIT NOTES
VDDQ + 0.6
V
V
V
1
2
3
0.5 x VDDQ - 0.175
0.5 x VDDQ - 0.125
0.5 x VDDQ + 0.175
0.5 x VDDQ + 0.125
1. VID (ac) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such
as CLK, DQS) and VCP is the complementary input signal (such as
VIL (ac).
,
). The minimum value is equal to VIH (ac) -
DQS
CLK
2. The typical value of VIX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (ac) is expected to track
variations in VDDQ. VIX (ac) indicates the voltage at which differential input signals must cross.
3. The typical value of VOX (ac) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (ac) is expected to
track variations in VDDQ. VOX (ac) indicates the voltage at which differential output signals must cross.
VDDQ
VIH(ac) min
VIH(dc) min
VSWING(MAX)
VREF
VDDQ
VID
VIL(dc) max
VTR
VCP
Crossing point
VIX or VOX
VIL(ac) max
VSS
ΔTF
ΔTR
VSSQ
VREF - VIL(ac) max
VIH(ac) min - VREF
Falling Slew =
Rising Slew =
ΔTF
ΔTR
Figure 28 – AC input test signal and Differential signal levels waveform
Publication Release Date: Oct. 12, 2010
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9.14 AC Overshoot / Undershoot Specification
9.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins:
Applies to A0-A13, BA0-BA1, /CS, /RAS, /CAS, /WE, CKE, ODT
PARAMETER
DDR2-1066
DDR2-800
0.9
DDR2-667
0.9
UNIT
V
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDD
0.9
0.9
0.5
0.5
0.9
0.9
V
0.66
0.8
V-nS
V-nS
Maximum undershoot area below VSS
0.66
0.8
9.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins:
Applies to DQ, DQS, /DQS, RDQS, /RDQS, DM, CLK, /CL K
PARAMETER
DDR2-1066
0.9
DDR2-800
0.9
DDR2-667
0.9
UNIT
V
Maximum peak amplitude allowed for overshoot area
Maximum peak amplitude allowed for undershoot area
Maximum overshoot area above VDDQ
0.9
0.9
0.9
V
0.19
0.23
0.23
V-nS
V-nS
Maximum undershoot area below VSSQ
0.19
0.23
0.23
Maximum Amplitude
Overshoot Area
VDD/VDDQ
VSS/VSSQ
Volts (V)
Undershoot Area
Maximum Amplitude
Time (nS)
Figure 29 – AC overshoot and undershoot definition
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10. TIMING WAVEFORMS
10.1 Command Input Timing
tCK
tCK
tCH
tCL
CLK
CLK
tIS
tIS
tIS
tIS
tIS
tIH
CS
tIH
RAS
tIH
tIH
tIH
CAS
WE
A0~A13
BA0,1
Refer to the Command Truth Table
10.2 Timing of the CLK Signals
tCL
tCH
VIH
CLK
CLK
VIH(AC)
VIL(AC)
VIL
tT
tT
tCK
CLK
VIH
VIL
CLK
VX
VX
VX
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10.3 ODT Timing for Active/Standby Mode
T0
T4
T5
T6
T8
T1
T2
T3
T7
CLK
CLK
tIS
CKE
ODT
tIS
tIS
VIH(ac)
VIL(ac)
tAOFD
tAOND
Internal
Term Res.
RTT
tAON(min)
tAOF(min)
tAOF(max)
tAON(max)
10.4 ODT Timing for Power Down Mode
T0
T4
T5
T6
T7
T8
T1
T2
T3
CLK
CLK
CKE
tIS
tIS
VIH(ac)
ODT
VIL(ac)
tAOFPD(max)
tAOFPD(min)
Internal
Term Res.
RTT
tAONPD(min)
tAONPD(max)
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10.5 ODT Timing mode switch at entering power down mode
T-2
T-1
T0
T1
T2
T-5
T-4
T-3
CLK
CLK
tANPD
CKE
tIS
Entering Slow Exit Active Power Down
Mode or Precharge Power Down Mode
tIS
ODT
VIL(ac)
Active & Standby
mode timings to be
applied
Internal
Term Res.
RTT
tAOFD
tIS
ODT
VIL(ac)
Power Down mode
timings to be applied
Internal
Term Res.
RTT
tAOFPD(max)
tIS
Active & Standby
mode timings to be
applied
VIH(ac)
tAOND
ODT
Internal
RTT
Term Res.
tIS
VIH(ac)
Power Down mode
timings to be applied
tAONPD(max)
ODT
Internal
Term Res.
RTT
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10.6 ODT Timing mode switch at exiting power down mode
T0
T1
T5
T6
T7
T8
T9
T10
CLK
CLK
tIS
tAXPD
VIH(ac)
CKE
Exiting from Slow Active Power Down Mode
or Precharge Power Down Mode
tIS
ODT
Active & Standby mode
timings to be applied
VIL(ac)
Internal
Term Res.
RTT
tAOFD
tIS
ODT
Power Down mode
VIL(ac)
timings to be applied
Internal
Term Res.
RTT
tAOFPD(max)
tIS
VIH(ac)
ODT
Internal
Active & Standby mode
timings to be applied
RTT
Term Res.
tAOND
tIS
VIH(ac)
ODT
Internal
Term Res.
Power Down mode
timings to be applied
RTT
tAONPD(max)
Publication Release Date: Oct. 12, 2010
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10.7 Data output (read) timing
tCH
tCL
CLK
CLK
DQS
DQS
DQS
DQS
tRPST
tRPRE
Q
Q
Q
Q
DQ
tDQSmax
tDQSmax
tQH
tQH
10.8 Burst read operation: RL=5 (AL=2, CL=3, BL=4)
T4
T0
T1
T2
T3
T5
T6
T7
T8
CLK/CLK
CMD
Posted CAS
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
≤ tDQSCK
DQS,
DQS
CL = 3
AL = 2
RL = 5
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
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Revision A01
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10.9 Data input (write) timing
tDQSH
tDQSL
DQS
DQS
DQS
DQS
tWPRE
tWPST
VIH(ac)
D
VIH(dc)
D
VIL(dc)
D
D
DQ
VIL(ac)
tDH
tDH
tDS
tDS
VIH(ac)
DMin
VIH(dc)
DMin
VIL(dc)
DMin
DMin
DM
VIL(ac)
10.10 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
CLK
CLK
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
CMD
tDQSS
tDQSS
tDSS
Completion of
The Burst Write
Case 1: with tDQSS(max)
tDSS
DQS
DQS
WL = RL – 1= 4
≥ tWR
DIN
A0
tDQSS
DIN
A1
DIN
A2
tDQSS
DIN
A3
DQs
Case 2: with tDQSS(min)
tDSH
tDSH
DQS
DQS
WL = RL – 1= 4
≥ tWR
DIN
A0
DIN
A1
DIN
A2
DIN
A3
DQs
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Revision A01
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10.11 Seamless burst read operation: RL = 5 (AL = 2, and CL = 3, BL = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CLK
Post CAS
READ A
Post CAS
READ B
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
CL = 3
AL = 2
RL = 5
DOUT
B2
DOUT
A1
DOUT
A2
DOUT
A3
DOUT
B0
DOUT
B1
DOUT
A0
DQ's
Note:
The seamless burst read operation is supported by enabling a read command at every other clock for BL = 4 operation, and
every 4 clock for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are
activated.
10.12 Seamless burst write operation: RL = 5 (WL = 4, BL = 4)
T0
T1
T2
T3
T8
T4
T5
T6
T7
CLK
CLK
Post CAS
Write B
Post CAS
Write A
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQS
WL = RL - 1 = 4
DIN
A3
DIN
B0
DIN
A1
DIN
A2
DIN
B1
DIN
B2
DIN
B3
DIN
A0
DQ's
Note:
The seamless burst write operation is supported by enabling a write command every other clock for BL = 4 operation, every four
clocks for BL = 8 operation. This operation is allowed regardless of same or different banks as long as the banks are activated.
Publication Release Date: Oct. 12, 2010
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10.13 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
NOP
NOP
NOP
NOP
NOP
NOP
NOP
READ A
READ B
DQS,
DQS
Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout
A0 A1 A2 A3 B0 B1 B2 B3 B4 B5 B6 B7
DQ's
10.14 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
NOP
Write A
NOP
Write B
NOP
NOP
NOP
NOP
NOP
DQS,
DQS
Din
A0
Din
A1
Din
A2
Din
A3
Din
B0
Din
B1
Din
B2
Din
B3
Din
B4
Din
B5
Din
B6
Din
B7
DQ's
Publication Release Date: Oct. 12, 2010
Revision A01
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10.15 Write operation with Data Mask: WL=3, AL=0, BL=4)
Data Mask Timing
DQS/
DQS
DQ
VIH(ac)
VIL(ac)
VIH(ac)
VIL(ac)
VIH(dc)
VIL(dc)
VIH(dc)
VIL(dc)
DM
tDS tDH
tDS tDH
CLK
CLK
CMDMAND
Write
tWR
WL + tDQSS (min)
Case 1: min tDQSS
DQS/DQS
DQ
DM
WL + tDQSS (max)
Case 2: max tDQSS
DQS/DQS
DQ
DM
Publication Release Date: Oct. 12, 2010
Revision A01
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10.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP
≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Post CAS
READ A
Bank A
Activate
NOP
NOP
AL+BL/2 clks
Precharge
NOP
NOP
≥ tRP
NOP
NOP
DQS,
DQS
AL = 1
CL = 3
RL = 4
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
≥ tRAS
≥ tRTP
10.17 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP
≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Post CAS
READ A
NOP
NOP
AL + BL/2 clks
NOP
NOP
Precharge
NOP
NOP
NOP
DQS,
DQS
AL = 1
CL = 3
RL = 4
Dout
A0
Dout
A1
Dout
A2
Dout
A3
Dout
A4
Dout
A5
Dout
A6
Dout
A7
DQ's
≥ tRTP
first 4-bit prefetch
second 4-bit prefetch
Publication Release Date: Oct. 12, 2010
Revision A01
- 76 -
W9751G8JB
10.18 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP
≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READ A
Precharge
NOP
NOP
NOP
NOP
NOP
NOP
AL + BL/2 clks
≥ tRP
DQS,
DQS
AL = 2
CL = 3
RL = 5
Dout
A3
Dout
A0
Dout
A1
Dout
A2
DQ's
≥ tRAS
CL = 3
≥ tRTP
10.19 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP
≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READA
NOP
NOP
AL + BL/2 clks
NOP
NOP
NOP
Precharge
NOP
≥ tRP
DQS,
DQS
AL = 2
CL = 4
RL = 6
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
≥ tRAS
CL = 4
≥ tRTP
Publication Release Date: Oct. 12, 2010
Revision A01
- 77 -
W9751G8JB
10.20 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP
> 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READ A
Precharge
NOP
NOP
AL + BL/2 + max(RTP, 2) - 2 clks
NOP
NOP
NOP
NOP
DQS,
DQS
AL = 0
CL = 4
RL = 4
≥ tRP
Dout
A0
Dout
A1
Dout
A2
Dout
A3
Dout
A4
Dout
A5
Dout
A6
Dout
A7
DQ's
≥ tRAS
≥ tRTP
second 4-bit prefetch
first 4-bit prefetch
10.21 Burst write operation followed by precharge: WL = (RL-1) = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Post CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Precharge
Completion of the Burst Write
≥ tWR
DQS,
DQS
WL = 3
DIN
A0
DIN
A1
DIN
A2
DIN
A3
DQ's
Publication Release Date: Oct. 12, 2010
Revision A01
- 78 -
W9751G8JB
10.22 Burst write operation followed by precharge: WL = (RL-1) = 4
T0
T1
T2
T3
T4
T5
T6
T7
T9
CLK/CLK
CMD
Posted CAS
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
Precharge A
NOP
Completion of the Burst Write
≥ tWR
DQS,
DQS
WL = 4
DIN A0 DIN A1 DIN A2 DIN A3
DQ's
10.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤
2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
AL + BL/2 clks
≥ tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
Dout
A0
Dout
A1
Dout
A2
Dout
A3
Dout
A4
Dout
A5
Dout
A6
Dout
A7
DQ's
≥ tRTP
first 4-bit prefetch
second 4-bit prefetch
tRTP
Precharge begins here
Publication Release Date: Oct. 12, 2010
Revision A01
- 79 -
W9751G8JB
10.24 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP >
2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
≥ AL + tRTP + tRP
DQS,
DQS
AL = 1
CL = 3
RL = 4
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
4-bit prefetch
tRTP
tRP
Precharge begins here
10.25 Burst read with Auto-precharge followed by an activation to the same bank
(tRC Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
Auto-precharge begins
≥ tRAS min. (AL + BL/2)
DQS,
DQS
≥ tRP
AL = 2
CL = 3
RL = 5
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
tRC min.
Publication Release Date: Oct. 12, 2010
Revision A01
- 80 -
W9751G8JB
10.26 Burst read with Auto-precharge followed by an activation to the same bank
(tRP Limit): RL=5 (AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK/CLK
CMD
Bank A
Activate
Post CAS
READA
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
Auto-precharge begins
≥ tRAS min.
DQS,
DQS
tRP min.
AL = 2
CL = 3
RL = 5
Dout
A0
Dout
A1
Dout
A2
Dout
A3
DQ's
≥ tRC
10.27 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3
Tm
T0
T1
T2
T3
T4
T5
T6
T7
CLK/CLK
CMD
Bank A
Activate
Post CAS
WRA Bank A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
Completion of the Burst Write
Auto-precharge Begins
≥ WR ≥ tRP
DQS,
DQS
WL= RL- 1 = 2
DIN
A0
DIN
A1
DIN
A2
DIN
A3
DQ's
tRC min.
Publication Release Date: Oct. 12, 2010
Revision A01
- 81 -
W9751G8JB
10.28 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3
T6
T11
T0
T3
T4
T5
T7
T8
T9
CLK/CLK
CMD
Post CAS
WRA Bank A
Bank A
Activate
NOP
NOP
NOP
NOP
NOP
NOP
NOP
A10 = 1
Completion of the Burst Write
Auto-precharge Begins
DQS,
DQS
tRP min.
≥ WR
WL = RL - 1 = 4
DIN
A0
DIN
A1
DIN
A2
DIN
A3
DQ's
≥ tRC
10.29 Self Refresh Timing
T0
T1
T2
T3
T4
Tm
Tn
T5
T6
tCK
tCH tCL
CLK
CLK
≥ tXSNR
tRP
≥ tXSRD
CKE
ODT
VIH(ac)
VIL(ac)
tAOFD
tIS
tIH
VIL(ac)
tIS
tIH
tIS
tIH
tIS tIH
VIH(ac)
VIL(ac)
VIH(dc)
VIL(dc)
Read
Command
Self
Refresh
Non-Read
Command
CMD
NOP
NOP
Publication Release Date: Oct. 12, 2010
Revision A01
- 82 -
W9751G8JB
10.30 Active Power Down Mode Entry and Exit Timing
Tn+2
T0
T1
T2
Tn
Tn+1
CLK
CLK
Valid
Command
CMD
CKE
Activate
NOP
tIS
NOP
NOP
tIS
NOP
tXARD or
tXARDS
Active
Power Down
Exit
Active
Power Down
Entry
10.31 Precharged Power Down Mode Entry and Exit Timing
T0
T1
T2
T3
Tn
Tn+1
Tn+2
CLK
CLK
Valid
NOP
Precharge
NOP
NOP
NOP
NOP
NOP
CMD
CKE
Command
tIS
tIS
tRP
tXP
Precharge
Power Down
Entry
Precharge
Power Down
Exit
Publication Release Date: Oct. 12, 2010
Revision A01
- 83 -
W9751G8JB
10.32 Clock frequency change in precharge Power Down mode
T0
T1
T2
T4
TX
TX+1
TY
TY+1
TY+2
TY+3
TY+4
Tz
CLK
CLK
DLL
RESET
CMD
CKE
NOP
NOP
NOP
NOP
NOP
Valid
200 Clocks
tIS
tIS
Frequency change
Occurs here
ODT
tRP
tAOFD
tIH
tXP
ODT is off during
DLL RESET
Minimum 2 clocks
required before
changing frequency
Stable new clock
before power down exit
Publication Release Date: Oct. 12, 2010
Revision A01
- 84 -
W9751G8JB
11. PACKAGE SPECIFICATION
Package Outline WBGA60 (8x12.5 mm2)
bbb C
E1
aaa
A
A1
E
eE
Pin A1 index
Pin A1 index
9
8
7
3
2
1
B
A
B
C
D
E
F
G
H
J
A
K
L
THE WINDOW-SIDE
ENCAPSULANT
60xψb
ccc
C
SOLDER BALL DIAMETER REFERS.
TO POST REFLOW CONDITION.
C
SEATING PLANE
DIMENSION (MM)
SYMBOL
Ball Land
MIN.
---
NOM.
---
MAX.
1.20
0.40
0.50
12.60
8.10
A
0.25
0.40
A1
b
---
0.45
12.40
7.90
12.50
8.00
D
E
D1
8.00 BSC.
6.40 BSC.
0.80 BSC.
0.80 BSC.
---
E1
eE
Ball Opening
eD
aaa
bbb
ccc
Note: 1. Ball land : 0.5mm
---
---
---
2. Ball opening : 0.4mm
3. PCB Ball land suggested ≤ 0.4mm
0.15
0.20
0.10
---
---
Publication Release Date: Oct. 12, 2010
Revision A01
- 85 -
W9751G8JB
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
Initial formally data sheet
A01
Oct. 12, 2010
All
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date: Oct. 12, 2010
- 86 -
Revision A01
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