W9812G21B-6I [WINBOND]
Synchronous DRAM, 4MX32, 5ns, CMOS, PBGA90, 8 X 13 MM, ROHS COMPLIANT, TFBGA-90;
| 型号： | W9812G21B-6I |
| 厂家： | 
WINBOND |
| 描述： | Synchronous DRAM, 4MX32, 5ns, CMOS, PBGA90, 8 X 13 MM, ROHS COMPLIANT, TFBGA-90 动态存储器 内存集成电路 |
| 文件： | 总43页 (文件大小：1468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W9812G2IB
1M × 4 BANKS × 32BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION.............................................................................................................. 3
2. FEATURES...................................................................................................................................... 3
3. AVAILABLE PART NUMBER .......................................................................................................... 3
4. BALL CONFIGURATION................................................................................................................. 4
5. BALL DESCRIPTION ...................................................................................................................... 5
6. BLOCK DIAGRAM........................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION........................................................................................................ 7
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
Power Up and Initialization ................................................................................................. 7
Programming Mode Register.............................................................................................. 7
Bank Activate Command .................................................................................................... 7
Read and Write Access Modes .......................................................................................... 7
Burst Read Command ........................................................................................................ 8
Burst Write Command......................................................................................................... 8
Read Interrupted by a Read ............................................................................................... 8
Read Interrupted by a Write................................................................................................ 8
Write Interrupted by a Write................................................................................................ 8
7.10. Write Interrupted by a Read................................................................................................ 8
7.11. Burst Stop Command.......................................................................................................... 9
7.12. Addressing Sequence of Sequential Mode......................................................................... 9
7.13. Addressing Sequence of Interleave Mode.......................................................................... 9
7.14. Auto-precharge Command................................................................................................ 10
7.15. Precharge Command........................................................................................................ 10
7.16. Self Refresh Command..................................................................................................... 10
7.17. Power Down Mode............................................................................................................ 11
7.18. No Operation Command................................................................................................... 11
7.19. Deselect Command .......................................................................................................... 11
7.20. Clock Suspend Mode........................................................................................................ 11
8. OPERATION MODE...................................................................................................................... 12
8.1.
Simplified Stated Diagram ................................................................................................ 13
9. ELECTRICAL CHARACTERISTICS ............................................................................................. 14
9.1.
9.2.
9.3.
Absolute Maximum Ratings.............................................................................................. 14
Recommended DC Operating Conditions ........................................................................ 14
Capacitance...................................................................................................................... 15
Publication Release Date: Nov. 06, 2008
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Revision A01
W9812G2IB
9.4.
9.5.
DC Characteristics............................................................................................................ 15
AC Characteristics and Operating Condition.................................................................... 16
10. TIMING WAVEFORMS.................................................................................................................. 18
10.1. Command Input Timing..................................................................................................... 18
10.2. Read Timing...................................................................................................................... 19
10.3. Control Timing of Input/Output Data................................................................................. 20
10.4. Mode Register Set Cycle .................................................................................................. 21
11. OPERATING TIMING EXAMPLE.................................................................................................. 22
11.1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3).......................................... 22
11.2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)............... 23
11.3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3).......................................... 24
11.4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)............... 25
11.5. Interleaved Bank Write (Burst Length = 8) ....................................................................... 26
11.6. Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 27
11.7. Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................... 28
11.8. Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 29
11.9. Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 30
11.10. Auto-precharge Write (Burst Length = 4).......................................................................... 31
11.11. Auto Refresh Cycle........................................................................................................... 32
11.12. Self Refresh Cycle ............................................................................................................ 33
11.13. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)................................. 34
11.14. Power Down Mode............................................................................................................ 35
11.15. Auto-precharge Timing (Read Cycle) ............................................................................... 36
11.16. Auto-precharge Timing (Write Cycle) ............................................................................... 37
11.17. Timing Chart of Read to Write Cycle ................................................................................ 38
11.18. Timing Chart of Write to Read Cycle ................................................................................ 38
11.19. Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 39
11.20. Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 39
11.21. CKE/DQM Input Timing (Write Cycle) .............................................................................. 40
11.22. CKE/DQM Input Timing (Read Cycle) .............................................................................. 41
12. PACKAGE SPECIFICATION......................................................................................................... 42
12.1. TFBGA 90 Balls (8X13 mm2, Ball pitch: 0.8mm, Ø=0.45mm) .......................................... 42
13. REVISION HISTORY..................................................................................................................... 43
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W9812G2IB
1. GENERAL DESCRIPTION
W9812G2IB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1,048,576 words × 4 banks × 32 bits. W9812G2IB delivers a data bandwidth of up to 166M words per
second (-6). For different application, W9812G2IB is sorted into following speed grades:-6/-6I and -75.
The -6/-6I is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support
-40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9812G2IB is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
3.3V ± 0.3V Power Supply
Up to 166 MHz Clock Frequency
1,048,576 Words × 4 banks × 32 bits organization
Self Refresh Mode
CAS Latency: 2, 3 and 4
Burst Length: 1, 2, 4, 8 and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM0-3
Auto-precharge and Controlled Precharge
4K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TFBGA 90 Ball (8X13 mm2), using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
PART NUMBER
SPEED
W9812G2IB-6
W9812G2IB-6I
W9812G2IB-75
166MHz/CL3
166MHz/CL3
133MHz/CL3
2mA
2mA
2mA
0°C ~ 70°C
-40°C ~ 85°C
0°C ~ 70°C
Publication Release Date:Nov. 06, 2008
Revision A01
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W9812G2IB
4. BALL CONFIGURATION
Top View
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26
DQ24
VSS
VDD
DQ23
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
VDDQ VSSQ
DQ28 VDDQ VSSQ
DQ22
DQ17
NC
DQ20
DQ18
DQ16
DQM2
A0
VSSQ
VSSQ
VDDQ
DQ27
DQ29
DQ25
DQ30
DQ31 NC
A2
VSS DQM3 A3
G
H
J
A10
A1
A4
A7
A5
A8
A6
NC
BS1 A11
NC
BS0
CAS#
VDD
DQ6
DQ1
CS#
WE#
DQ7
DQ5
DQ3
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
CLK
CKE
NC
A9
K
L
DQM1
VDDQ
VSSQ
VSSQ
NC
DQ8
DQ10
DQ12
VSS
DQ9
DQ14
M
N
P
R
VDDQ VSSQ
DQ11 VDDQ VSSQ
DQ13
DQ15
VSS
VDD
DQ0
DQ2
Publication Release Date: Nov. 06, 2008
Revision A01
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W9812G2IB
5. BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9
Address
A0−A11
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
J7,H8
BS0, BS1
Bank Select
R8,N7,R9,N8,P9,M8,
M7,L8,L2,M3,M2,P1,
N2,R1,N3,R2,E8,D7,
D8,B9,C8,A9,C7,A8,
A2,C3,A1,C2,B1,D2,
D3,E2
Data Input/
Output
Multiplexed pins for data output and input.
DQ0−DQ31
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
J8
J9
Chip Select
CS
Command input. When sampled at the rising edge of the
Row Address
Strobe
RAS CAS
WE
define the operation to be
RAS
clock
,
and
executed.
Column Address
Strobe
K7
K8
RAS
RAS
CAS
WE
Referred to
Write Enable
Referred to
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
K9,K1,F8,F2
DQM0~3
Input/output mask
System clock used to sample inputs on the rising edge of
clock.
J1
J2
CLK
CKE
Clock Inputs
Clock Enable
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
A7,F9,L7,R7
A3,F1,L3,R3
VDD
VSS
Power (+3.3V)
Ground
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
Power (+3.3V) for Separated power from VDD, to improve DQ noise
VDDQ
VSSQ
I/O buffer
immunity.
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8
Ground for I/O
buffer
Separated ground from VSS, to improve DQ noise
immunity.
E3,E7,H3,H7,K2,K3 NC
No Connection
No connection
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W9812G2IB
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
GENERATOR
RAS
COMMAND
CAS
DECODER
COLUMN DECODER
COLUMN DECODER
WE
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
MODE
REGISTER
AND
EMRS
SENSE AMPLIFIER
A0
SENSE AMPLIFIER
ADDRESS
BUFFER
A9
DMn
A11
BS0
BS1
DQ0
DATA
CONTROL
CIRCUIT
DQ
BUFFER
DQ31
REFRESH
COUNTER
COLUMN
COUNTER
.
DQMn
COLUMN DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE: The cell array configuration is 4096 * 256 * 32
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Revision A01
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W9812G2IB
7. FUNCTIONAL DESCRIPTION
7.1. Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs.
During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage
when the input signals are held in the “NOP” state. The power up voltage must not exceed VDD +0.3V
on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed
by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power up, it is required that the DQM and CKE pins be held high during the initial pause period.
Once all banks have been precharged, the Mode Register Set Command must be issued to initialize
the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after
programming the Mode Register to ensure proper subsequent operation.
7.2. Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3. Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS (max).
7.4. Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address.
Reading or writing to a different row within an activated bank requires the bank be precharged and a
new Bank Activate command be issued. When more than one bank is activated, interleaved bank
Read or Write operations are possible. By using the programmed burst length and alternating the
access and precharge operations between multiple banks, seamless data access operation among
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W9812G2IB
many different pages can be realized. Read or Write Commands can also be issued to the same bank
or between active banks on every clock cycle.
7.5. Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequential mode.
7.6. Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7. Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8. Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9. Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10. Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
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W9812G2IB
7.11. Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open
for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency
in a burst read cycle interrupted by Burst Stop.
7.12. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
ACCESS ADDRESS
BURST LENGTH
n
BL = 2 (disturb address is A0)
No address carry from A0 to A1
BL = 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
BL = 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
7.13. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
ACCESS ADDRESS
BURST LENGTH
A8 A7 A6 A5 A4 A3 A2 A1 A0
BL = 2
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
BL = 4
BL = 8
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W9812G2IB
7.14. Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a
read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation
two clocks delay from the last burst write cycle. This delay is referred to as Write tWR. The bank
undergoing auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS (min).
7.15. Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16. Self Refresh Command
The Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high
at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode. The period between the Auto Refresh command and the next
command is specified by tRC.
Publication Release Date: Nov. 06, 2008
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W9812G2IB
7.17. Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations,
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS (min) + tCK (min).
7.18. No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS, CAS , and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing, such
as a burst read or write cycle.
7.19. Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS, CAS , and WE signals become don’t cares.
7.20. Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
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W9812G2IB
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
Table 1 Truth Table (Note (1), (2))
COMMAND
DEVICE
STATE
A0−A9
A11
WE
RAS CAS
CS
CKEn-1 CKEn DQM BS0, 1 A10
Bank Active
Idle
Any
H
H
H
H
H
H
H
H
H
H
H
H
H
L
x
x
x
x
x
x
x
x
x
x
x
H
L
H
x
x
x
x
x
x
x
x
x
x
x
x
x
x
v
v
x
v
v
v
v
v
x
x
x
x
x
x
v
L
H
L
H
L
H
v
v
x
x
v
v
v
v
v
x
x
x
x
x
x
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
L
H
H
H
L
L
L
L
L
H
H
x
H
L
Bank Precharge
Precharge All
Any
L
L
Write
Active (3)
Active (3)
Active (3)
Active (3)
Idle
H
H
H
H
L
L
Write with Auto-precharge
Read
L
H
H
L
Read with Auto-precharge
Mode Register Set
No – Operation
Burst Stop
Any
x
H
H
x
H
L
Active (4)
x
Device Deselect
Auto - Refresh
Self - Refresh Entry
Any
x
x
Idle
x
L
L
L
x
H
H
x
Idle
x
L
idle
x
x
Self Refresh Exit
(S.R.)
Active
Idle Active (5)
L
H
L
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Clock suspend Mode Entry
Power Down Mode Entry
Clock Suspend Mode Exit
H
H
L
x
x
x
x
H
x
x
x
H
L
L
x
x
x
x
x
x
x
x
L
x
H
x
H
x
x
x
Active
Any
H
L
L
H
H
x
x
x
x
x
x
x
x
H
L
x
x
x
x
Power Down Mode Exit
(power down)
H
H
Data write/Output Enable
Data Write/Output Disable
Active
Active
H
H
x
x
L
x
x
x
x
x
x
x
x
x
x
x
x
x
x
H
Notes:
(1) v = valid
x = Don’t care
L = Low Level H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BS0, BS1 signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
Publication Release Date: Nov. 06, 2008
Revision A01
- 12 -
W9812G2IB
8.1. Simplified Stated Diagram
Self
Refresh
Mode
Register
Set
MRS
REF
CBR
Refresh
IDLE
Power
Down
CKE
Active
Power
Down
ROW
ACTIVE
CKE
B
T
S
S
R
T
e
a
B
e
t
i
d
r
W
Write
Read
CKE
CKE
CKE
CKE
Read
WRITE
READ
WRITE
READ
SUSPEND
SUSPEND
Write
CKE
CKE
CKE
CKE
WRITEA
SUSPEND
READA
SUSPEND
READA
WRITEA
POWER
ON
Precharge
Precharge
Automatic sequence
Manual input
MRS = Mode Register Set
REF = Refresh
ACT = Active
PRE = Precharge
WRITEA = Write with Auto-precharge
READA = Read with Auto-precharge
Publication Release Date:Nov. 06, 2008
Revision A01
- 13 -
W9812G2IB
9. ELECTRICAL CHARACTERISTICS
9.1. Absolute Maximum Ratings
PARAMETER
Input/Output Voltage
SYMBOL
RATING
-0.3~VDD+ 0.3V
-0.3 ~ 4.6
0 ~ 70
UNIT
V
NOTES
VIN, VOUT
VDD, VDDQ
TOPR
1
1
1
1
1
1
1
1
Power Supply Voltage
V
Operating Temperature(-6/-75)
Operating Temperature(-6I)
Storage Temperature
°C
°C
°C
°C
W
TOPR
-40 ~ 85
-55 ~ 150
260
TSTG
TSOLDER
PD
Soldering Temperature (10s)
Power Dissipation
1
Short Circuit Output Current
IOUT
50
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2. Recommended DC Operating Conditions
(TA = 0 to 70°C for -6/-75, TA = -40 to 85°C for -6I)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Power Supply Voltage
I/O Buffer Supply Voltage
Input High Voltage
VDD
VDDQ
VIH
3.0
3.0
2.0
-0.3
2.4
-
3.3
3.6
V
V
3.3
3.6
-
-
-
-
-
-
VDD + 0.3
V
1
Input Low Voltage
VIL
0.8
-
V
2
Output logic high voltage
Output logic low voltage
Input leakage current
IOH= -2mA
VOH
VOL
II(L)
V
IOL= 2mA
0.4
5
V
-5
µA
µA
3
4
Output leakage current
IO(L)
-5
5
Note:
1. VIH (max.) = VDD/VDDQ+1.5V for pulse width < 5 nS.
2. VIL (min.) = VSS/VSSQ-1.5V for pulse width < 5 nS.
3. Any input 0V<VIN<VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Output disabled, 0V ≤ VOUT ≤ VDDQ.
Publication Release Date: Nov. 06, 2008
Revision A01
- 14 -
W9812G2IB
9.3. Capacitance
(VDD = 3.3V, f = 1 MHz, TA = 25°C)
PARAMETER
SYM.
MIN.
MAX.
UNIT
Input Capacitance
CI
-
3.8
pf
(A0 to A11, BS0, BS1, CS, RAS , CAS , WE , DQM, CKE)
Input Capacitance (CLK)
CCLK
CIO
-
-
3.5
6.5
pf
pf
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested
9.4. DC Characteristics
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -6/-75, TA = -40 to 85°C for -6I)
MAX.
PARAMETER
SYM.
UNIT
NOTES
-6/-6I
-75
Operating Current
tCK = min., tRC = min.
1 Bank operation
CKE = VIH
IDD1
130
110
3
Active precharge command cycling
without burst operation
Standby Current
IDD2
45
2
35
2
3
3
tCK = min, CS = VIH
VIH/L = VIH(min)/VIL(max.)
Bank: Inactive state
CKE = VIL
IDD2P
(Power Down mode)
Standby Current
CKE = VIH
IDD2S
15
15
CLK = VIL, CS = VIH
VIH/L = VIH(min)/VIL(max)
Bank: Inactive state
CKE = VIL
IDD2PS
IDD3
2
2
mA
(Power Down mode)
No Operating Current
CKE = VIH
70
15
65
15
tCK = min., CS = VIH(min)
CKE = VIL
Bank: Active state
(4 banks)
IDD3P
(Power Down mode)
Burst Operating Current
IDD4
200
230
2
180
210
2
3, 4
3
tCK = min.
Read/ Write command cycling
Auto Refresh Current
IDD5
IDD6
tCK = min.
Auto refresh command cycling
Self Refresh Current
Self Refresh Mode
CKE = 0.2V
Publication Release Date:Nov. 06, 2008
Revision A01
- 15 -
W9812G2IB
9.5. AC Characteristics and Operating Condition
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C for -6/-75, TA = -40 to 85°C for -6I) (Notes: 5, 6)
-6/-6I
-75
PARAMETER
SYM.
UNIT NOTES
MAX.
MIN.
60
MAX.
MIN.
65
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
tRC
tRAS
tRCD
42
100000
45
100000
nS
18
20
Read/Write(a) to Read/Write(b) Command
Period
1
1
tCK
nS
tCCD
Precharge to Active Command Period
Active(a) to Active(b) Command Period
18
12
2
20
15
2
tRP
tRRD
CL* = 2
Write Recovery Time
CLK Cycle Time
tCK
tWR
tCK
CL* = 3
CL* = 2
CL* = 3
2
2
10
6
1000
1000
10
7.5
2.5
2.5
1000
1000
8
8
CLK High Level width
CLK Low Level width
2
tCH
tCL
2
CL* = 2
CL* = 3
CL* = 2
CL* = 3
CL* = 2
CL* = 3
6
5
6
Access Time from CLK
9
9
tAC
tOH
tHZ
5.4
3
2
3
2
Output Data Hold Time
6
5
6
Output Data High Impedance Time
7
9
5.4
Output Data Low Impedance Time
Power Down Mode Entry Time
0
0
0
0
tLZ
nS
6
1
7.5
1
tSB
Transition Time of CLK
(Rise and Fall)
tT
Data-in Set-up Time
Data-in Hold Time
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
8
8
8
8
8
8
8
8
tDS
tDH
Address Set-up Time
Address Hold Time
tAS
tAH
CKE Set-up Time
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
tXSR
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
64
64
mS
tCK
Mode register Set Cycle Time
Exit self refresh to ACTIVE command
*CL = CAS Latency
2
2
72
75
nS
Publication Release Date: Nov. 06, 2008
Revision A01
- 16 -
W9812G2IB
Notes:
1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.
2. All voltages are referenced to VSS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence is further described in the “Functional Description” section.
6. AC Test Load diagram.
1.4 V
50 ohms
output
Z = 50 ohms
30pF
ACTEST LOAD
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to
output level.
8. Assumed input transition Time (tT) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
(The tT maximum can’t be more than 10nS for low frequency application.)
9. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter.
Publication Release Date:Nov. 06, 2008
- 17 -
Revision A01
W9812G2IB
10. TIMING WAVEFORMS
10.1. Command Input Timing
t
CL
tCH
t
CK
V
IH
IL
CLK
CS
V
t
T
tT
t
CMS
tCMH
t
CMH
tCMS
t
CMS
t
CMH
RAS
t
t
CMS
t
t
CMH
CAS
WE
CMS
CMH
t
AS
tAH
A0-A11
BS0, 1
t
CKS
t
CKH
tCKH
tCKS
t
CKS
t
CKH
CKE
Publication Release Date: Nov. 06, 2008
Revision A01
- 18 -
W9812G2IB
10.2. Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
A0-A11
BS0, 1
t
AC
t
AC
t
HZ
t
OH
t
OH
t
LZ
Valid
Data-Out
Valid
Data-Out
DQ
Read Command
Burst Length
Publication Release Date:Nov. 06, 2008
Revision A01
- 19 -
W9812G2IB
10.3. Control Timing of Input/Output Data
Control Timing of Input Data
(Word Mask)
CLK
t
CMS
tCMH
t
CMH
tCMS
DQM
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
DS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -31
(Clock Mask)
CLK
t
CKH
t
CKS
t
CKH
tCKS
CKE
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
tDS
tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
DQ0 -31
Control Timing of Output Data
(Output Enable)
CLK
t
CMH
t
CMS
tCMS
t
CMH
DQM
t
AC
t
HZ
tAC
t
AC
t
AC
t
LZ
t
OH
t
OH
t
OH
t
OH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
OPEN
DQ0 -31
(Clock Mask)
CLK
t
CKH
t
CKS
t
CKH
tCKS
CKE
t
AC
t
AC
tAC
t
AC
t
OH
tOH
t
OH
tOH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
DQ0 -31
Publication Release Date: Nov. 06, 2008
Revision A01
- 20 -
W9812G2IB
10.4. Mode Register Set Cycle
t
RSC
CLK
t
CMS
tCMH
CS
t
CMS
tCMH
RAS
CAS
WE
t
t
CMS
CMS
t
t
CMH
CMH
t
AS
tAH
A0-A11
BS0,1
Register
set data
next
command
A2 A1A0
BurstLength
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
4
8
2
4
8
Addressing Mode
CAS Latency
Reserved
FullPage
Reserved
A3
0
1
Addressing Mode
Sequential
Interleave
"0" (Test Mode)
"0"
Reserved
A6 A5A4
CAS Latency
Reserved
Reserved
2
3
Reserved
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
WriteMode
"0"
"0"
BS0 "0"
"0"
Reserved
A9
0
1
Single Write Mode
Burst read andBurst write
Burst read andsingle write
BS1
Publication Release Date:Nov. 06, 2008
Revision A01
- 21 -
W9812G2IB
11. OPERATING TIMING EXAMPLE
11.1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
t
RC
tRC
RAS
CAS
t
RAS
t
RP
t
RAS
RP
tRP
t
RAS
t
tRAS
WE
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAa
RAa
RBb
RAc
RAc
RBd
RBd
A10
RAe
RAe
A0-A9,
A11
CBx
RBb
CAy
CAw
CBz
DQM
CKE
DQ
tAC
t
AC
t
AC
t
AC
bx3
bx1
aw0
aw2 aw3
bx0
bx2
cy0 cy1
cy2 cy3
aw1
t
RRD
tRRD
tRRD
t
RRD
Precharge
Read
Active
Read
Precharge
Active
Bank #0
Bank #1
Bank #2
Bank #3
Read
Active
Precharge
Read
Active
Active
Idle
Publication Release Date: Nov. 06, 2008
Revision A01
- 22 -
W9812G2IB
11.2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
t
RAS
t
RP
t
RAS
t
RP
t
RAS
t
RP
tRAS
WE
BS0
BS1
A10
t
RCD
t
RCD
t
RCD
tRCD
RAe
RBd
RAa
RBb
RAc
A0-A9,
A11
CBz
RAa
CAw
CAy
RAe
CBx
RBb
RAc
RBd
DQM
CKE
t
AC
t
AC
t
AC
tAC
aw0 aw1 aw2
aw3
bx0 bx1
bx2 bx3
cy0
cy1 cy2
cy3
dz0
DQ
t
RRD
tRRD
tRRD
tRRD
Read
AP*
Active
AP*
Read
Active
Active
Active
AP*
Bank #0
Bank #1
Bank #2
Bank #3
Read
Read
Active
Idle
* AP is the internal precharge start timing
Publication Release Date:Nov. 06, 2008
Revision A01
- 23 -
W9812G2IB
11.3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
RAS
t
RAS
t
RP
tRAS
t
RP
t
RAS
tRP
CAS
WE
BS0
BS1
t
RCD
t
RCD
tRCD
RAa
RAa
RAc
RAc
A10
RBb
RBb
A0-A9,
A11
CAx
CBy
CAz
DQM
CKE
tAC
t
AC
tAC
ax0 ax1
ax2
ax3
ax4
ax5 ax6
by0
by1
by4 by5
by6
by7
DQ
CZ0
t
RRD
t
RRD
Read
Active
Idle
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Bank #2
Bank #3
Active
Precharge
Read
Publication Release Date: Nov. 06, 2008
Revision A01
- 24 -
W9812G2IB
11.4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
21 22 23
0
CLK
CS
t
RC
RAS
t
RAS
t
RAS
t
RP
t
RAS
t
RP
CAS
WE
BS0
BS1
t
RCD
tRCD
t
RCD
A10
RBb
RBb
RAc
RAa
RAa
CAz
CAx
RAc
CBy
A0-A9,
A11
DQM
CKE
DQ
t
CAC
t
CAC
t
CAC
ax3
ax4
ax0
ax2
ax5 ax6
ax7
by0
by1
by4
by5
by6
ax1
CZ0
t
RRD
t
RRD
AP*
Read
Active
Bank #0 Active
Bank #1
Read
Active
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date:Nov. 06, 2008
Revision A01
- 25 -
W9812G2IB
11.5. Interleaved Bank Write (Burst Length = 8)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
t
RC
RAS
CAS
t
RAS
t
RAS
t
RP
tRP
t
RAS
tRCD
t
RCD
t
RCD
WE
BS0
BS1
RBb
RAc
RAc
RAa
RAa
A10
A0-A9,
A11
CAx
RBb
CBy
CAz
DQM
CKE
DQ
ax0 ax1
ax4
ax5
ax6 ax7 by0
by1 by2
by3
by4
by5
by6
by7
CZ0
CZ1
CZ2
t
RRD
tRRD
Active
Write
Precharge
Active
Write
Bank #0
Active
Write
Precharge
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: Nov. 06, 2008
Revision A01
- 26 -
W9812G2IB
11.6. Interleaved Bank Write (Burst Length = 8, Auto-precharge)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RC
RAS
CAS
t
RP
t
RAS
t
RAS
WE
BS0
BS1
t
RCD
tRCD
t
RCD
RAa
RAa
RBb
RBb
RAb
RAc
A10
A0-A9
A11
CAx
CBy
CAz
DQM
CKE
DQ
ax4
by2
by5
ax0 ax1
ax5
ax6 ax7
by0 by1
by3
by4
by6
by7 CZ0
CZ1
CZ2
tRRD
t
RRD
Write
Active
AP*
Active
Write
Bank #0
Bank #1
Bank #2
Bank #3
AP*
Write
Active
Idle
* AP is the internal precharge start timing
Publication Release Date:Nov. 06, 2008
Revision A01
- 27 -
W9812G2IB
11.7. Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
CCD
t
CCD
tCCD
t
RAS
tRP
t
RAS
tRP
RAS
CAS
WE
BS0
BS1
t
RCD
tRCD
RAa
RAa
RBb
RBb
A10
A0-A9,
A11
CBx
CAy
CAm
CBz
CAI
DQM
CKE
t
AC
t
AC
t
AC
t
AC
tAC
am1
am2 bz0
bz1
bz2
bz3
a0
a1
a3
bx0
Ay0
Ay1 Ay2 am0
a2
bx1
DQ
t
RRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
AP*
Active
Read
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Nov. 06, 2008
Revision A01
- 28 -
W9812G2IB
11.8. Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
6
7
8
11
12
13
16
17
18
1
2
3
5
9
10
14
15
19
21
0
4
20
22
23
CLK
CS
tRP
tRAS
RAS
CAS
WE
BS0
BS1
tRCD
RAa
RAa
A10
CAx
A0-A9,
A11
CAy
DQM
CKE
tAC
tWR
ay1
ax0
ay0
ay2
ay4
ax1
ax3
ax5
ax2
ax4
ay3
DQ
Q
Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Write
Precharge
Publication Release Date:Nov. 06, 2008
Revision A01
- 29 -
W9812G2IB
11.9. Auto-precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
tRC
RAS
t
RAS
t
RP
t
RAS
tRP
CAS
WE
BS0
BS1
A10
t
RCD
tRCD
RAa
RAb
A0-A9,
A11
CAx
RAa
CAw
RAb
DQM
CKE
DQ
t
AC
t
AC
aw0 aw1 aw2 aw3
bx0
bx1
bx2 bx3
Bank #0
AP*
Active
Idle
Read
Active
Read
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date: Nov. 06, 2008
Revision A01
- 30 -
W9812G2IB
11.10. Auto-precharge Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
t
RC
t
RC
RAS
CAS
t
RAS
t
RP
t
RAS
tRP
WE
BS0
BS1
t
RCD
t
RCD
RAc
RAa
RAa
RAb
A10
A0-A9,
A11
CAw
RAb
CAx
RAc
DQM
CKE
DQ
bx0
aw1 aw2
bx1
bx3
bx2
aw0
aw3
Active
Idle
AP*
Bank #0
Write
Active
Write
Active
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date:Nov. 06, 2008
Revision A01
- 31 -
W9812G2IB
11.11. Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
t
RP
t
RC
tRC
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Publication Release Date: Nov. 06, 2008
Revision A01
- 32 -
W9812G2IB
11.12. Self Refresh Cycle
(CLK = 100 MHz)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
RAS
CAS
WE
BS0,1
A10
A0-A9,
A11
DQM
tCKS
tCKS
tSB
CKE
DQ
tCKS
tXSR
Self Refresh Cycle
No Operation / Command Inhibit
Self Refresh
Exit
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
Publication Release Date:Nov. 06, 2008
Revision A01
- 33 -
W9812G2IB
11.13. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
t
RCD
WE
BS0
BS1
A10
RBa
A0-A9,
A11
CBz
RBa
CBv
CBw
CBx CBy
DQM
CKE
t
AC
tAC
DQ
av0
av1
av3
aw0
ax0
ay0
az1
az2
az3
az0
av2
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Active
Single Write
Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date: Nov. 06, 2008
Revision A01
- 34 -
W9812G2IB
11.14. Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BS
RAa
RAa
RAa
RAa
A10
A0-A9
A11
CAa
CAx
DQM
tSB
tSB
CKE
DQ
tCKS
tCKS
tCKS
tCKS
ax0
ax2
ax3
ax1
Active
NOP Read
Precharge
NOP Active
Precharge Standby
Power Down mode
Active Standby
Power Down mode
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
Publication Release Date:Nov. 06, 2008
Revision A01
- 35 -
W9812G2IB
11.15. Auto-precharge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Read
AP
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
Read
Read
Read
AP
Q0
Act
t
RP
DQ
Q1
( c ) burst length = 4
Command
AP
Q2
Act
Q4
t
RP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
AP
Q6
Act
t
RP
DQ
Q2
Act
Q3
Q5
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
Read
Read
Read
AP
tRP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
Command
AP
Act
tRP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Act
Q4
tRP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
AP
Q5
Act
tRP
DQ
Q1
Q6
Q7
Note:
Read
AP
Act
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS (min).
Publication Release Date: Nov. 06, 2008
Revision A01
- 36 -
W9812G2IB
11.16. Auto-precharge Timing (Write Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK
(1) CAS Latency = 2
(a) burst length = 1
Command
Write
D0
AP
Act
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
AP
tWR
tRP
DQ
D1
D1
(c) burst length = 4
Command
Act
D7
Write
D0
tRP
tWR
DQ
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D2
AP
D4
D5
D6
(2) CAS Latency = 3
(a) burst length = 1
Command
Write
D0
Act
tWR
tRP
DQ
(b) burst length = 2
Command
Write
D0
AP
Act
tWR
tRP
DQ
D1
D1
D1
(c) burst length = 4
Command
Write
D0
AP
D5
Act
tWR
tRP
DQ
D2
D2
D3
D3
(d) burst length = 8
Command
Write
D0
AP
Act
tWR
tRP
DQ
D4
D6
D7
Note )
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
Act
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Publication Release Date:Nov. 06, 2008
Revision A01
- 37 -
W9812G2IB
11.17. Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
( a ) Command
Read Write
DQM
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
Read
Write
DQM
DQ
D0
D3
(2) CAS Latency=3
( a ) Command
DQM
Read Write
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
Read
Write
DQM
DQ
D0
D3
Note: The Output data must be masked by DQM to avoid I/O conflict
11.18. Timing Chart of Write to Read Cycle
In the case of Burst Length=4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency=2
Write Read
( a ) Command
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
DQ
D0
D1
Q3
(2) CAS Latency=3
( a ) Command
DQM
Write Read
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Write
Read
DQ
D0
D1
Q3
Publication Release Date: Nov. 06, 2008
Revision A01
- 38 -
W9812G2IB
11.19. Timing Chart of Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
Command Read
BST
Q3
DQ
Q4
Q3
Q0
Q1
Q0
Q2
Q1
( b )CAS latency = 3
Command
Read
BST
Q2
DQ
Q4
(2) Write cycle
Command
Write
Q0
BST
DQ
Q1
Q2
Q3
Q4
Note: BST
represents the Burst stop command
11.20. Timing Chart of Burst Stop Cycle (Precharge Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) R ead cycle
(a) C A S latency = 2
C om m and
R ead
R ead
P R C G
Q 3
D Q
Q 0
Q 1
Q 0
Q 2
Q 1
Q 4
Q 3
(b) C A S latency = 3
P R C G
Q 2
C om m and
D Q
Q 4
(2) W rite cycle
W rite
Q 0
P R C G
C om m and
tW R
D Q M
D Q
Q 1
Q 2
Q 3
Q 4
Publication Release Date:Nov. 06, 2008
Revision A01
- 39 -
W9812G2IB
11.21. CKE/DQM Input Timing (Write Cycle)
1
CLK cycle No.
2
3
4
5
7
6
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
CKE MASK
( 1 )
CLK cycle No.
External
2
3
4
5
7
1
6
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D5
D6
DQM MASK
( 2 )
CKE MASK
1
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
Publication Release Date: Nov. 06, 2008
Revision A01
- 40 -
W9812G2IB
11.22. CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q1
Q2
Q3
Q4
Open
Open
( 1 )
1
2
3
4
5
7
CLK cycle No.
External
6
CLK
Internal
CKE
DQM
DQ
Q3
Q4
Q6
Q1
Q2
Open
( 2 )
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q3
Q1
Q5
Q4
Q2
( 3 )
Publication Release Date:Nov. 06, 2008
Revision A01
- 41 -
W9812G2IB
12. PACKAGE SPECIFICATION
12.1. TFBGA 90 Balls (8X13 mm2, Ball pitch: 0.8mm, Ø=0.45mm)
e
D2
D
Publication Release Date: Nov. 06, 2008
Revision A01
- 42 -
W9812G2IB
13. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
Initial formal data sheet
A01
Nov. 06, 2008
All
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Publication Release Date:Nov. 06, 2008
- 43 -
Revision A01
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