W987D2HBJX6E [WINBOND]
128Mb Mobile LPSDR;
| 型号： | W987D2HBJX6E |
| 厂家： | 
WINBOND |
| 描述： | 128Mb Mobile LPSDR |
| 文件： | 总66页 (文件大小：1067K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W987D6HB / W987D2HB
128Mb Mobile LPSDR
1. GENERAL DESCRIPTION
The Winbond 128Mb Low Power SDRAM is a low power synchronous memory containing
134,217,728 memory cells fabricated with Winbond high performance process technology.
It is designed to consume less power than the ordinary SDRAM with low power features essential
for applications which use batteries. It is available in two organizations: 1,048,576 words × 4 banks
× 32 bits or 2,097,152 words × 4 banks × 16 bits. The device operates in a fully synchronous
mode, and the output data are synchronized to positive edges of the system clock and is capable
of delivering data at clock rate up to 166MHz. The device supports special low power functions
such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh
(ATCSR).
The Low Power SDRAM is suitable for 2.5G / 3G cellular phone, PDA, digital still camera, mobile
game consoles and other handheld applications where large memory density and low power
consumption are required. The device operates from 1.8V power supply, and supports the 1.8V
LVCMOS bus interface.
2. FEATURES
Power supply VDD = 1.7V~1.95V
CAS Latency: 2 and 3
VDDQ = 1.7V~1.95V
Burst Length: 1, 2, 4, 8, and full page
Refresh: refresh cycle 64ms
Interface: LVCMOS
Frequency : 166MHz (-6) ,133MHz(-75)
Programmable Partial Array Self Refresh
Power Down Mode
Support package :
Deep Power Down Mode (DPD)
Programmable output buffer driver strength
Automatic Temperature Compensated Self Refresh
54 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended (-25°C ~ +85°C)
Industrial (-40°C ~ +85°C)
Publication Release Date : September 25, 2013
Revision : A01-004
- 1 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
3. ORDERING INFORMATION
Mobile LPDDR/LPSDR SDRAM Package Part Numbering
W 9 8
7
D
6
H
B
G
X
6
I
Product Line
98:mobile LPSDR SDRAM
94:mobile LPDDR SDRAM
Temperature
with standard Idd6
G:-25C~85C
Density
7:27=128M 8:28=256M
9:29=512M
with low power Idd6
E:-25C~85C
I:-40C~85C
Power Supply
D:1.8/1.8 VDD / VDDQ
Clock rate
5:5ns200MHz
6:6ns166MHz
7:7.5ns133MHz
I/O Ports width
6:16bit
2:32bit
Package Material
Generation
X: Lead-free + Halogen-free
Design revision.
Package configuration code
G: 54VFBGA, 8mmx9mm
H: 60VFBGA, 8mmx9mm
J: 90VFBGA, 8mmx13mm
Package or KGD
K: KGD
B: BGA
Part Number
W987D6HBGX6I
W987D6HBGX6E
W987D6HBGX7I
W987D6HBGX7E
W987D6HBGX7G
W987D2HBJX6I
W987D2HBJX6E
W987D2HBJX7I
W987D2HBJX7E
W987D2HBJX7G
VDD/VDDQ I/O Width Package
Others
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
16
16
16
16
16
32
32
32
32
32
54VFBGA 166MHz, -40°C ~85°C, Low Power
54VFBGA 166MHz, -25°C ~85°C, Low Power
54VFBGA 133MHz, -40°C ~85°C, Low Power
54VFBGA 133MHz, -25°C ~85°C, Low Power
54VFBGA 133MHz, -25°C ~85°C
90VFBGA 166MHz, -40°C ~85°C, Low Power
90VFBGA 166MHz, -25°C ~85°C, Low Power
90VFBGA 133MHz, -40°C ~85°C, Low Power
90VFBGA 133MHz, -25°C ~85°C, Low Power
90VFBGA 133MHz, -25°C ~85°C
Publication Release Date : September 25, 2013
- 2 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION............................................................................................................. 1
2. FEATURES..................................................................................................................................... 1
3. ORDERING INFORMATION .......................................................................................................... 2
4. PIN CONFIGURATION................................................................................................................... 6
4.1 Ball Assignment: LPSDR X 16...............................................................................................................6
4.2 Ball Assignment: LPSDR X 32...............................................................................................................6
5. PIN DESCRIPTION......................................................................................................................... 7
5.1 Signal Description ..................................................................................................................................7
5.2 Addressing Table ...................................................................................................................................7
6. BLOCK DIAGRAM ......................................................................................................................... 8
7. ELECTRICAL CHARACTERISTICS .............................................................................................. 9
7.1 Absolute Maximum Ratings ...................................................................................................................9
7.2 Operating Conditions .............................................................................................................................9
7.3 Capacitance ...........................................................................................................................................9
7.4 DC Characteristics ...............................................................................................................................10
7.5 Automatic Temperature Compensated Self Refresh Current Feature.................................................12
7.6 AC Characteristics And AC Operating Conditions ...............................................................................13
7.6.1 AC Characteristics....................................................................................................................................... 13
7.6.2 AC Test Condition ....................................................................................................................................... 14
7.6.3 AC Latency Characteristics......................................................................................................................... 15
8. FUNCTION DESCRIPTION.......................................................................................................... 16
8.1 Command Function..............................................................................................................................16
8.1.1Table 1. Truth Table..................................................................................................................................... 16
8.1.2 Functional Truth Table (See Note 1)........................................................................................................... 17
8.1.3 Function Truth Table for CKE ..................................................................................................................... 20
8.1.4 Bank Activate Command............................................................................................................................. 21
8.1.5 Bank Precharge Command......................................................................................................................... 21
8.1.6 Precharge All Command............................................................................................................................. 21
8.1.7 Write Command .......................................................................................................................................... 21
8.1.8 Write with Auto Precharge Command......................................................................................................... 21
8.1.9 Read Command .......................................................................................................................................... 21
8.1.10 Read with Auto Precharge Command....................................................................................................... 21
8.1.11 Extended Mode Register Set Command .................................................................................................. 21
8.1.12 Mode Register Set Command................................................................................................................... 22
8.1.13 No-Operation Command........................................................................................................................... 22
8.1.14 Burst Stop Command................................................................................................................................ 22
8.1.15 Device Deselect Command....................................................................................................................... 22
8.1.16 Auto Refresh Command............................................................................................................................ 22
8.1.17 Self Refresh Entry Command ................................................................................................................... 22
8.1.18 Self Refresh Exit Command...................................................................................................................... 22
8.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command............................................................ 22
8.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command................................................................. 22
Publication Release Date : September 25, 2013
- 3 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.21 Data Write/Output Enable, Data Mask/Output Disable Command ........................................................... 23
9. OPERATION................................................................................................................................. 23
9.1 Read Operation....................................................................................................................................23
9.2 Write Operation....................................................................................................................................23
9.3 Precharge ............................................................................................................................................24
9.3.1 Auto Precharge ........................................................................................................................................... 24
9.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge) ................................ 24
9.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge)............................... 25
9.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge)............................... 25
9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ............................. 26
9.4 Burst Termination.................................................................................................................................26
9.5 Mode Register Operation.....................................................................................................................27
9.5.1 Burst Length field (A2~A0).......................................................................................................................... 27
9.5.2 Addressing Mode Select (A3) ..................................................................................................................... 27
9.5.3 Addressing Sequence for Sequential Mode................................................................................................ 28
9.5.4 Addressing Sequence for Interleave Mode................................................................................................. 28
9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13)............................................. 29
9.5.6 Read Cycle CAS Latency = 3 .................................................................................................................. 29
9.5.7 CAS Latency field (A6~A4) ...................................................................................................................... 30
9.5.8 Mode Register Definition............................................................................................................................. 30
9.6 Extended Mode Register Description...................................................................................................31
9.7 Simplified State Diagram......................................................................................................................32
10. CONTROL TIMING WAVEFORMS ............................................................................................ 33
10.1 Command Input Timing......................................................................................................................33
10.2 Read Timing.......................................................................................................................................34
10.3 Control Timing of Input Data (x16).....................................................................................................35
10.4 Control Timing of Output Data (x16) ..................................................................................................36
10.5 Control Timing of Input Data (x32).....................................................................................................37
10.6 Control Timing of Output Data (x32) ..................................................................................................38
10.7 Mode register Set (MRS) Cycle .........................................................................................................39
10.8 Extended Mode register Set (EMRS) Cycle.......................................................................................40
11. OPERATING TIMING EXAMPLE............................................................................................... 41
CAS
11.1 Interleaved Bank Read (Burst Length = 4,
Latency = 3).........................................................41
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge) ..............................42
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .........................................................43
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge) ..............................44
11.5 Interleaved Bank Write (Burst Length = 8).........................................................................................45
11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge)..............................................................46
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)..................................................................47
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3).......................................................48
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ...........................................................49
Publication Release Date : September 25, 2013
- 4 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.10 Auto Precharge Write (Burst Length = 4).........................................................................................50
11.11 Auto Refresh Cycle ..........................................................................................................................51
11.12 Self Refresh Cycle ...........................................................................................................................52
11.13 Power Down Mode...........................................................................................................................53
11.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ..............................................54
11.15 Deep Power Down Mode Entry........................................................................................................55
11.16 Deep Power Down Mode Exit ..........................................................................................................56
11.17 Auto Precharge Timing (Read Cycle) ..............................................................................................57
11.18 Auto Precharge Timing (Write Cycle)...............................................................................................58
11.19 Timing Chart of Read to Write Cycle................................................................................................59
11.20 Timing Chart for Write to Read Cycle ..............................................................................................59
11.21 Timing Chart for Burst Stop Cycle (Burst Stop Command)..............................................................60
11.22 Timing Chart for Burst Stop Cycle (Precharge Command)..............................................................60
11.23 CKE/DQM Input Timing (Write Cycle)..............................................................................................61
11.24 CKE/DQM Input Timing (Read Cycle)..............................................................................................62
12. PACKAGE DIMENSION............................................................................................................. 63
12.1 : LPSDR X 16.....................................................................................................................................63
12.2 : LPSDR X 32.....................................................................................................................................64
13. REVISION HISTORY.................................................................................................................. 65
Publication Release Date : September 25, 2013
- 5 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
4. PIN CONFIGURATION
4.1 Ball Assignment: LPSDR X 16
54Ball FBGA
4 5 6
1
2
3
7
8
9
A
B
C
D
E
F
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
DQ15
DQ13
DQ11
DQ9
NC
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CAS
BA0
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
VDD
DQ1
DQ3
DQ5
DQ7
WE
CLK
A11
A7
G
H
J
CS
A8
A6
A0
A10
VDD
VSS
A5
A4
A3
A2
(Top View)
4.2 Ball Assignment: LPSDR X 32
90Ball FBGA
1
2
3
4 5 6
7
8
9
A
B
C
D
E
F
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
VSS
VSSQ
DQ25
DQ30
NC
VDD
VDDQ
DQ22
DQ17
NC
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A3
A2
G
H
J
A4
A6
A10
A1
A7
A8
NC
NC
BA1
A11
CLK
CKE
A9
BA0
CAS
VDD
DQ6
DQ1
VDDQ
VDD
CS
RAS
K
L
DQM1
VDDQ
VSSQ
VSSQ
DQ11
DQ13
NC
NC
WE
DQM0
VSSQ
VDDQ
VDDQ
DQ4
DQ8
VSS
DQ9
DQ14
VSSQ
VSS
DQ7
DQ5
DQ3
VSSQ
DQ0
M
N
P
R
DQ10
DQ12
VDDQ
DQ15
DQ2
(Top View)
Publication Release Date : September 25, 2013
Revision : A01-004
- 6 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
5. PIN DESCRIPTION
5.1 Signal Description
Ball Name
Function
Description
Multiplexed pins for row and column address.
A10 is Auto Precharge Select
A [n : 0]
Address
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
BA0, BA1
Bank Select
DQ0~DQ15 (×16)
DQ0~DQ31 (×32)
Data Input/ Output Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder
Chip Select
is disabled, new command is ignored and previous operation
continues.
CS
Command input. When sampled at the rising edge of the clock,
Row
Address Strobe
RAS
RAS
,
CAS and WE define the operation to be executed.
Column
Address Strobe
CAS
WE
Referred toRAS
Referred to WE
Write Enable
The output buffer is placed at Hi-Z (with latency of 2 in CL=2, 3;)
when DQM is sampled high in read cycle. In write cycle, sampling
DQM high will block the write operation with zero latency
UDQM / LDQM(x16)
DQM0 ~ DQM3 (x32)
I/O Mask
CLK
CKE
Clock Inputs
Clock Enable
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode or Self Refresh mode is
entered.
VDD
VSS
Power
Ground
Power for I/O
Buffer
Power supply for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Power supply separated from VDD, used for output buffers to
improve noise.
VDDQ
Ground for
I/O Buffer
No Connection No connection
Separated ground from VSS, used for output buffers to improve
noise.
VSSQ
NC
5.2 Addressing Table
Item
128 Mb
4
Number of banks
Bank address pins
Auto precharge pin
BA0,BA1
A10/AP
A0-A11
A0-A8
A0-A11
A0-A7
Row addresses
X16
x32
Column addresses
Row addresses
Column addresses
Publication Release Date : September 25, 2013
Revision : A01-004
- 7 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
6. BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
GENERATOR
COMMAND
DECODER
CAS
COLUMN DECODER
COLUMN DECODER
WE
R
O
W
R
O
W
D
E
C
O
R
D
E
R
D
E
C
O
R
D
E
R
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A10
MODE
REGISTER
A0
SENSE AMPLIFIER
SENSE AMPLIFIER
An
ADDRESS
BUFFER
BA0
BA1
DMn
DQ
DATA CONTROL
CIRCUIT
DQ0 – DQn
BUFFER
DQM
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
COLUMN DECODER
R
O
W
R
O
W
D
E
C
O
R
D
E
R
D
E
C
O
R
D
E
R
CELL ARRAY
BANK #3
CELL ARRAY
BANK #2
SENSE AMPLIFIER
SENSE AMPLIFIER
Publication Release Date : September 25, 2013
Revision : A01-004
- 8 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Values
Units
Parameter
Symbol
Min
−0.5
−0.5
−0.5
−55
Max
Voltage on VDD relative to VSS
Voltage on VDDQ relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VDD
VDDQ
VIN, VOUT
TSTG
2.3
V
V
2.3
2.3
V
150
±50
1.0
°C
mA
W
Short Circuit Output Current
Power Dissipation
IOUT
PD
Notes: stresses greater than those listed in “absolute maximum ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
7.2 Operating Conditions
Parameter
Symbol
VDD
Min.
1.7
Typ
Max.
1.95
Unit
Supply Voltage
V
V
V
V
V
V
1.8
Supply Voltage (for I/O Buffer)
Input High level Voltage
Input Low level Voltage
VDDQ
VIH
1.7
1.8
1.95
0.8*VDDQ
-0.3
-
-
-
-
VDDQ + 0.3
+0.3
VIL
LVCOMS Output H Level Voltage (IOUT = -0.1 mA )
LVCMOS Output L Level Voltage (IOUT = +0.1 mA )
-
VOH
VOL
0.9*VDDQ
-
0.2
Input Leakage Current
II(L)
A
A
-1
-5
-
-
1
5
(0V VIN VDD, all other pins not under test = 0V)
Output Leakage Current (Output disable , 0V VOUT
VDDQ)
IO(L)
Note: VIH(max) = VDD/ VDDQ+1.2V for pulse width < 5 ns , VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 ns
7.3 Capacitance
Parameter
Input Capacitance : All other input-only
Input Capacitance (CLK)
Symbol
CI
Min.
1.5
Max.
3.0
Unit
pf
pf
pf
CCLK
CIO
1.5
3.5
Input/Output capacitance
3.0
5.0
Note: These parameters are periodically sampled and not 100% tested.
Publication Release Date : September 25, 2013
Revision : A01-004
- 9 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
7.4 DC Characteristics
(X16)
-6
-75
Parameter / Condition
Sym.
Unit
Notes
Max. Max.
Operating current:
Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA,
Active Precharge command cycling without burst operation.
IDD1
38
35
mA
2, 3, 4
Low
power
0.23
0.28
10
0.23
0.28
10
Standby current:
Power-down mode, All banks idle, CKE = LOW.
Idd2P
mA
5
Normal
power
Standby current:
Nonpower-down mode, All banks idle, CKE = HIGH.
Standby current:
Active mode; CKE = LOW, CS# = HIGH, All banks active,
No accesses in progress.
Idd2N
Idd3P
mA
mA
3
3
3, 4, 6
3, 4, 6
2, 3, 4
Standby current:
Active mode, CKE = HIGH, CS# = HIGH, All banks active after
tRCD met,
No accesses in progress.
Operating current:
Burst mode, All banks active, Iout=0mA,
READ/WRITE command cycling,
Auto refresh current:
Idd3N
Idd4
20
75
15
70
mA
mA
Idd5
Izz
50
10
50
10
mA 2, 3, 4, 6
μA 5,8
tRFC=tRFC (MIN), Auto refresh command cycling
Deep Power Down Mode
Publication Release Date : September 25, 2013
Revision : A01-004
- 10 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
(X32)
-6
-75
Parameter / Condition
Sym.
Unit
Notes
Max. Max.
Operating current:
Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA,
Active Precharge command cycling without burst operation.
IDD1
38
35
mA
2, 3, 4
Low
power
0.23
0.28
10
0.23
0.28
10
Standby current:
Power-down mode, All banks idle, CKE = LOW.
Idd2P
mA
5
Normal
power
Standby current:
Nonpower-down mode, All banks idle, CKE = HIGH.
Idd2N
mA
mA
Standby current:
Active mode; CKE = LOW, CS# = HIGH, All banks active,
No accesses in progress.
Standby current:
Active mode, CKE = HIGH, CS# = HIGH, All banks active after
tRCD met,
No accesses in progress.
Operating current:
Burst mode, All banks active, Iout=0mA,
READ/WRITE command cycling,
Operating current:
Idd3P
Idd3N
Idd4
3
3
3, 4, 6
3, 4, 6
2, 3, 4
20
75
15
70
mA
mA
Active mode, 1 bank, BL = 1, tRC = tRC (min), Iout=0mA,
Active Precharge command cycling without burst operation.
Idd5
Izz
50
10
50
10
mA 2, 3, 4, 6
Standby current:
Power-down mode, All banks idle, CKE = LOW.
μA
5,8
Publication Release Date : September 25, 2013
Revision : A01-004
- 11 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
7.5 Automatic Temperature Compensated Self Refresh Current Feature
IDD6
Low Power
Normal Power
Units
ATCSR Range
Full Array
45°C
180
85°C
230
45°C
85°C
280
220
190
170
uA
1/2 Array
160
200
250
1/4 Array
150
180
230
Notes:
1. A full initialization sequence is required before proper device operation is ensured.
2. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and
the outputs open.
3. The Idd current will increase or decrease proportionally according to the amount of frequency alteration for the test
condition.
4. Address transitions average one transition every 2 clocks.
5. Measurement is taken 500ms after entering into this operating mode to provide tester measuring unit settling time.
6. Other input signals can transition only one time for every 2 clocks and are otherwise at valid Vih or Vil levels.
7. CKE is HIGH during the REFRESH command period tRFC (MIN) else CKE is LOW.
8. Typical values at 25°C (not a maximum value).
9. Enables on-die refresh and address counters.
10. Values for Idd6 85°C full array and partial array are guaranteed for the entire temperature range. All other Idd6
values are estimated.
Publication Release Date : September 25, 2013
- 12 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
7.6 AC Characteristics And AC Operating Conditions
7.6.1 AC Characteristics
*CL=CAS Latency; (Notes: 5,6,7)
-6
-75
Parameter
Sym
Unit
Note
Min.
Max.
Min.
Max.
Ref/Active to Ref/Active
Command Period
tRC
tRAS
tRCD
60
72.5
-
ns
ns
ns
8
8
8
Active to precharge
Command Period
42
18
100000
50
18
100000
-
Active to Read/Write
Command Delay Time
Read/Write(a) to
Read/Write(b)Command
Period
tCCD
tRP
1
1
-
-
CLK
ns
8
Precharge to Active
Command Period
18
18
8
8
Active(a) to Active(b)
Command Period
tRRD
tWR
12
15
1
15
15
1
-
-
ns
ns
Write Recovery Time
Write-Recovery Time
(Last data to Read)
tLDR
CLK
CL * = 3
CL * = 2
6
12
2
1000
1000
7.5
12
2.5
2.5
-
1000
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK Cycle Time
tCK
1000
CLK High Level width
CLK Low Level width
tCH
tCL
-
-
2
CL * = 3
CL * = 2
5.4
6
5.4
8
Access Time from CLK
Output Data Hold Time
tAC
-
tOH
tHZ
2.5
2.5
-
-
CL * = 3
CL * = 2
5.4
6
5.4
6
7
7
Output Data High
Impedance Time
-
Output Data Low
Impedance Time
tLZ
tSB
tT
1
0
1
0
-
ns
ns
ns
Power Down Mode
Entry Time
6
1
7.5
1.2
Transition Time of CLK
(Rise and Fall)
0.3
0.3
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
tDS
tDH
1.5
1
1.5
1
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
tAS
1.5
1
1.5
1
tAH
tCKS
tCKH
tCMS
1.5
1
1.5
1
Command Set-up Time
1.5
1.5
Publication Release Date : September 25, 2013
Revision : A01-004
- 13 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
-6
-75
Parameter
Sym
Unit
Note
Min.
Max.
Min.
Max.
Command Hold Time
Refresh Time
tCMH
tREF
1
1
-
ns
64
64
ms
Mode register Set Cycle
Time
tMRD
tRFC
12
72
15
72
-
-
ns
ns
8
Ref to Ref/Active
Command period
Self Refresh exit to next
valid command delay
tXSR
115
115
-
ns
7.6.2 AC Test Condition
SYMBOL
VIH(min)
VIL(max)
VOTR
PARAMETER
VALUE
UNIT
Input High Voltage Level (AC)
Input Low Voltage Level (AC)
Output Signal Reference Level
0.8 x VDDQ
0.2 x VDDQ
0.5 x VDDQ
V
V
V
I/O
Time Reference Load
Z0 = 50 Ohms
20pF
Input signal transition time between VIH and VIL is assumed as 1 volts/ns.
Publication Release Date : September 25, 2013
Revision : A01-004
- 14 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
Note :
1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect deice reliability.
2. All voltages are referenced to VSS and VSSQ.
3. These parameters depend on the cycle rate. These values are measured at a cycle rate with the minimum values of tCK and
tRC . Input signals transition once per tCK period.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 9.
6. AC TEST CONDITIONS : (refer to 7.6.2)
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage
levels.
8. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as
follows: The number of clock cycles = specified value of timing / clock period (count fractions as a whole number)
9. Power up Sequence : The SDRAM should be powered up by the following sequence of operations.
a. Power must be applied to VDD before or at the seme time as VDDQ while all input signals are held in the “NOP” state.
The CLK signal will be applied at power up with power.
b. After power-up a pause of at least 200 uA is required. It is required that DQM and CKE signals must be held “High” (VDD
levels ) to ensure that the DQ output is in High-impedance state.
c. All banks must be precharged.
d. The Mode Register Set command must be issued to initialize the Mode Register.
e. The Extended Mode Register Set command must be issued to initialize the Extended Mode Register.
f. Issue two or more Auto Refresh dummy cycles to stabilize the internal circuitry of the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
7.6.3 AC Latency Characteristics
CKE to clock disable (CKE Latency)
1
DQM to output in High-Z (Read DQM Latency)
DQM to input data delay (Write DQM Latency)
Write command to input data (Write Data Latency)
CS to Command input ( CS Latency)
2
0
0
0
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
2
Precharge to DQ Hi-Z Lead time
3
Cycle
1
Precharge to Last Valid data out
2
2
Burst Stop Command to DQ Hi-Z Lead time
Burst Stop Command to Last Valid data out
Read with Auto Precharge Command to Active/Ref Command
Write with Auto Precharge Command to Active/Ref Command
3
1
2
BL+ tRP
BL+ tRP
Cycle + ns
CL = 2 BL+1 + tRP
CL = 3 BL+1 + tRP
Publication Release Date : September 25, 2013
Revision : A01-004
- 15 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8. FUNCTION DESCRIPTION
8.1 Command Function
8.1.1Table 1. Truth Table
BS0,
BS1
Symbol
Command
Device State
CKEn
DQM(5)
A10
An~A0
CKEn-1
WE
CS
RAS
CAS
ACT
PRE
Bank Activate
Idle (3)
Any
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
V
V
L
V
X
X
V
V
V
V
V
L
L
L
L
L
L
L
L
L
L
H
H
H
L
H
L
Bank Precharge
Precharge All
PREA
WRIT
WRITA
READ
READA
MRS
Any
H
L
L
L
Write
Active (3)
Active (3)
Active (3)
Active (3)
Idle
H
H
H
H
L
L
Write with Auto Precharge
Read
H
L
L
L
L
H
H
L
Read with Auto Precharge
Mode Register Set
H
V
L
L
Extended Mode Register
Set
EMRS
Idle
H
X
X
V
V
V
L
L
L
L
NOP
BST
No-Operation
Burst stop
Any
Active (4)
Any
H
H
H
H
H
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
L
H
H
X
L
H
L
DSL
Device Deselect
Auto-Refresh
Self-Refresh Entry
H
L
X
H
H
X
H
AREF
SELF
Idle
Idle
L
L
L
H
L
X
H
X
H
Idle
SELEX
CSE
Self-Refresh Exit
L
H
L
X
X
X
X
X
X
X
X
(Self Refresh)
Clock Suspend Mode
Entry
Active
H
X
X
X
X
H
L
X
H
X
X
H
X
X
X
H
X
X
H
X
X
X
H
X
X
X
X
X
PD
Power Down Mode Entry
Clock Suspend Mode Exit
Power Down Mode Exit
Idle/Active (6)
Active
H
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CSEX
PDEX
X
H
L
Any
(Power Down)
DE
DD
Data Write/Output Enable
Data Write/Output Disable
Active
Active
H
H
X
X
L
X
X
X
X
X
X
X
X
H
Deep Power Down Mode
Entry
DPD
Idle
H
L
L
X
X
X
X
X
X
X
X
L
H
X
H
X
L
Deep Power Down Mode
Exit
DPDE
Idle (DPD)
H
X
X
Note
1.
V = Valid, × = Don’t Care, L = Low level, H = High level
2.
CKEn signal is input level when commands are issued.
CKEn-1 signal is input level one clock cycle before the commands are issued.
These are state designated by the BS0, BS1 signals.
Device state is Full Page Burst operation.
3.
4.
5.
6.
x32: DQM0-3, x16 : LDQM / UDQM
Power Down Mode cannot entry in the burst cycle.
When this command assert in the burst cycle, device state is clock suspend mode.
Publication Release Date : September 25, 2013
Revision : A01-004
- 16 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.2 Functional Truth Table (See Note 1)
Current State
Address
Command
Action
Notes
CS
H
L
CAS
X
RAS
X
WE
X
X
X
DSL
Nop
Nop
H
H
L
X
NOP/BST
L
H
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL
3
3
L
H
L
ILLEGAL
Idle
L
L
H
H
L
H
L
Row activating
Nop
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
L
L
H
L
Refresh or Self refresh
Mode register accessing
2
2
L
L
L
Op-Code
H
L
L
L
L
L
L
L
X
H
H
H
L
X
H
L
X
X
H
L
X
X
DSL
Nop
Nop
NOP/BST
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA Begin read: Determine AP
4
4
3
5
L
WRIT/WRITA
ACT
Begin write: Determine AP
ILLEGAL
Row active
H
H
L
H
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
Precharge
L
H
L
ILLEGAL
L
L
Op-Code
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DSL
NOP
BST
Continue burst to end
Continue burst to end
Burst stop
Term burst, new read: Determine
AP
L
L
H
H
L
L
H
L
BS, CA, A10
BS, CA, A10
READ/READA
WRIT/WRITA
6
Read
Term burst, begin write:
Determine AP
6,7
3
L
L
L
L
L
L
L
L
H
H
L
H
L
BS, RA
BS, A10
X
ACT
ILLEGAL
PRE/PREA
AREF/SELF
MRS/EMRS
Term burst, precharging
ILLEGAL
H
L
L
Op-Code
ILLEGAL
H
L
L
X
H
H
X
H
H
X
H
L
X
X
X
DSL
NOP
BST
Continue burst to end.
Continue burst to end
Burst stop, row active
Term burst, start read: Determine
AP
L
L
H
H
L
L
H
L
BS, CA, A10
BS, CA, A10
READ/READA
WRIT/WRITA
6, 7
6
Write
Term burst, new write: Determine
AP
L
L
L
L
L
L
L
L
H
H
L
H
L
BS, RA
BS, A10
X
ACT
ILLEGAL
3
8
PRE/PREA
AREF/SELF
MRS/EMRS
Term burst. precharging
ILLEGAL
H
L
L
Op-Code
ILLEGAL
Publication Release Date : September 25, 2013
Revision : A01-004
- 17 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
Current State
Address
Command
Action
Notes
CS
H
L
CAS
X
RAS
X
WE
X
H
L
X
X
DSL
NOP
Continue burst to end
Continue burst to end
ILLEGAL
H
H
H
L
L
H
X
BST
L
H
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL
3
3
3
3
Read with
auto
precharge
L
H
L
ILLEGAL
L
L
H
H
L
H
L
ILLEGAL
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
Op-Code
ILLEGAL
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
DSL
NOP
Continue burst to end
Continue burst to end
ILLEGAL
X
BST
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL
3
3
3
3
Write with
auto
precharge
L
ILLEGAL
H
H
L
H
L
ILLEGAL
L
PRE/PREA
AREF/SELF
MRS/EMRS
ILLEGAL
L
H
L
ILLEGAL
L
L
Op-Code
ILLEGAL
Nop
Nop
→
→
Idle after t
Idle after t
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
DSL
NOP
RP
RP
X
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
3
3
3
Precharging
L
H
H
L
H
L
Nop
→ Idle after t
RP
L
PRE/PREA
AREF/SELF
MRS/EMRS
L
H
L
ILLEGAL
ILLEGAL
L
L
Op-Code
Nop
Nop
→
→
Row active after t
Row active after t
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
DSL
NOP
RCD
RCD
X
BST
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
3
3
3
3
Row
activating
L
H
H
L
H
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
L
H
L
L
L
Op-Code
Publication Release Date : September 25, 2013
Revision : A01-004
- 18 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
Current State
Address
Command
Action
Notes
CS
H
L
CAS
X
RAS
X
WE
X
H
L
Nop
Nop
Nop
→
→
→
Maintain Row active after t
Maintain Row active after t
Maintain Row active after t
X
X
DSL
NOP
WR
WR
WR
H
H
H
L
L
H
X
BST
L
H
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
Begin Read
Begin new Write
ILLEGAL
7
Write
recovering
L
H
L
L
L
H
H
L
H
L
3
3
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
ILLEGAL
L
L
H
L
ILLEGAL
L
L
L
Op-Code
ILLEGAL
Nop
Nop
Nop
→
→
→
Enter precharge after t
Enter precharge after t
Enter precharge after t
H
L
L
L
L
L
L
L
L
X
H
H
H
H
L
X
H
H
L
X
H
L
X
X
DSL
NOP
WR
WR
WR
X
BST
Write
H
L
BS, CA, A10
BS, CA, A10
BS, RA
BS, A10
X
READ/READA
WRIT/WRITA
ACT
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
3
3
3
3
recovering
with auto
precharge
L
H
H
L
H
L
L
PRE/PREA
AREF/SELF
MRS/EMRS
L
H
L
L
L
Op-Code
Nop
Nop
Nop
→
→
→
Idle after t
Idle after t
Idle after t
H
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
X
X
X
X
DSL
NOP
RFC
RFC
RFC
BST
Refreshing
X
X
READ/WRIT
ACT/PRE/PREA
ILLEGAL
ILLEGAL
H
AREF/SELF/MRS/
EMRS
L
L
L
X
X
ILLEGAL
Nop
Nop
→
→
Idle after t
Idle after t
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
X
X
X
DSL
NOP
MRD
MRD
BST
ILLEGAL
ILLEGAL
Mode register
accessing
X
READ/WRIT
ACT/PRE/PREA/
AREF/SELF/MRS/
EMRS
L
L
X
X
X
ILLEGAL
Note:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle (CKEn-1 = CKEn = ”1”)
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR.
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data
Publication Release Date : September 25, 2013
- 19 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.3 Function Truth Table for CKE
CKE
Current State
Address
Action
Notes
CS
CAS
RAS
WE
n-1
n
H
L
L
L
L
L
X
H
H
H
H
L
X
H
L
X
X
H
H
L
X
X
H
L
X
X
H
X
X
X
X
X
X
X
X
X
N/A
Exit Self Refresh → Idle after tRFC
Exit Self Refresh → Idle after tRFC
ILLEGAL
Self refresh
L
L
X
X
ILLEGAL
X
X
Maintain Self Refresh
H
L
L
X
H
L
X
H
L
X
X
H
X
X
X
H
X
X
X
H
X
X
X
X
X
N/A
Power-Down
Exit Power Down → Idle after 1 clock cycle
X
Maintain Power-Down
H
L
L
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
N/A
Deep Power-Down
Exit Deep Power-Down → Exit Sequence
Maintain Deep Power-Down
H
H
H
H
H
H
H
L
H
L
L
L
L
L
L
X
X
H
L
L
L
L
L
X
X
X
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
Refer to Function Truth Table
Enter Power-down
Enter Power-Down
Enter Deep Power-Down
Self Refresh
2
2
3
1
All banks idle
H
X
X
X
H
L
L
ILLEGAL
X
X
ILLEGAL
X
Power-Down
2
H
H
H
H
H
H
L
H
L
L
L
L
L
X
X
H
L
X
X
H
L
X
X
H
L
X
X
H
H
X
X
X
X
X
X
X
X
X
X
Refer to Function Truth Table
Enter Power down
Enter Power down
ILLEGAL
2
2
Row Active
L
L
H
L
L
ILLEGAL
L
X
X
ILLEGAL
X
X
Power-Down → Row Active or Maintain PD
Any state other than
listed above
H
H
X
X
X
X
X
Refer to Function Truth Table
Note:
1. Self refresh can enter only from the all banks idle state.
2. Power-down can enter only from the all banks idle or row active state.
3. Deep power-down can enter only from the all banks idle state.
Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data
Publication Release Date : September 25, 2013
Revision : A01-004
- 20 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.4 Bank Activate Command
RAS = L, CAS = H, WE = H, BA0, BA1 = Bank, A0~An = Row Address)
(
The Bank Activate command activates the bank designated by the BS (Bank Select) signal.
Row addresses are latched on A0~An when this command is issued and the cell data is read out to the sense amplifiers. The
maximum time that each bank can be held in the active state is specified as tRAS (max).
8.1.5 Bank Precharge Command
(
RAS = L, RAS = H, WE = L, BA0, BA1 = Bank, A10 =L )
The Bank Precharge command is used to close (or precharge) the bank that is activated. Using this command, systems can
designated the bank to be closed by specifying the BS address bit setting in the command set. A Precharge command can be
used to precharge each bank separately (Bank Precharge) or all four banks simultaneously (Precharge All). After the Bank
Precharge command is issued, any one bank can close, and the closed bank transitions from the active state to the idle state.
To re-activate the closed bank, a system has to wait the minimum tRP delay after issuing the Precharge command before
issuing the Active Command for the device to complete the Precharge operation.
8.1.6 Precharge All Command
(
RAS = L, CAS = H, WE = L, BA0, BA1 = Don’t care, A10 =H )
The Precharge All command is used to precharge all banks simultaneously. After this command is issued, all four banks close
and transition from the active state to the idle state.
8.1.7 Write Command
(
RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = L )
The Write command initiates a Write operation to the bank selected by BA0 and BA1 address inputs. The write data is latched at
the positive edge of CLK. Users should preprogram the length of the write data (Burst Length) and the column access sequence
(Addressing Mode) by setting the Mode Resister at power-up prior to using the Write command.
8.1.8 Write with Auto Precharge Command
(
RAS = H, CAS = L, WE = L, BA0, BA1 = Bank, A10 = H )
The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. The internal
precharge starts in the cycles immediately following the cycle in which the last data is written independent of CAS Latency.
8.1.9 Read Command
(
RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 = L )
The Read command performs a Read operation to the bank designated by BA0-1. The read data is issued sequentially
synchronized to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode and CAS Latency
(access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Write
operation.
8.1.10 Read with Auto Precharge Command
(
RAS = H, CAS = L, WE = H, BA0, BA1 = Bank, A10 =H )
The Read with Auto Precharge command automatically performs the Precharge operation after the Read operation.
When the CAS Latency = 3, the internal precharge starts two cycles before the last data is output. When the
CAS Latency = 2, the internal precharge starts one cycle before the last data is output.
8.1.11 Extended Mode Register Set Command
(
RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data)
The Extended Mode Register Set command is designed to support Partial Array Self Refresh, Temperature Compensated Self
Refresh, and Output Driver Strength/Size by allowing users to program each value by setting predefined address bits. The
default values in the Extended Mode Register after power-up are undefined; therefore this command must be issued during the
power-up sequence. Also, this command can be issued while all banks are in the idle state.
Publication Release Date : September 25, 2013
- 21 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.12 Mode Register Set Command
RAS = L, CAS = L, WE = L, BA0, BA1, A0~An = Register Data)
(
The Mode Register Set command is used to program the values of CAS latency, Addressing Mode and Burst Length in the
Mode Register. The default values in the Mode Register after power-up are undefined; therefore this command must be issued
during the power-up sequence and re-issued after the Deep Power Down Exit Command. Also, this command can be issued
while all banks are in the idle state.
8.1.13 No-Operation Command
(
RAS = H, CAS = H, WE = H)
The No-Operation command is used in cases such as preventing the device from registering unintended commands. The device
performs no operation when this command is registered. This command is functionally equivalent to the Device Deselect
command.
8.1.14 Burst Stop Command
(
RAS = H, CAS = H, WE = L)
The Burst stop command is used to stop the already activated burst operation. The activated page is left unclosed and future
commands can be issued to access the same page of the active bank. If this command is issued during a burst read operation,
the read data will go to a Hi-Z state after a delay equal to the CAS latency. If a burst stop command is issued during a burst
write operation, then the burst data is terminated and data bus goes to Hi-Z at the same clock that the burst command is
activated. Any remaining data from the burst write cycle is ignored.
8.1.15 Device Deselect Command
(
CS = H)
The Device Deselect command disables the command decoder so that the RAS
ignored. This command is similar to the No-Operation command.
CAS WE and Address inputs are
, ,
8.1.16 Auto Refresh Command
(
RAS = L, CAS = L, WE = H, CKE = H, BA0, BA1, A0~An = Don’t care)
The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation
must be performed 8192 times within 64 ms. The next command can be issued after tRC from the end of the Auto Refresh
command. When the Auto Refresh command is issued, All banks must be in the idle state. The Auto Refresh operation is
equivalent to the CAS -before-RAS operation in a conventional DRAM.
8.1.17 Self Refresh Entry Command
(
RAS = L, CAS = L, WE = H, CKE = L, BA0, BA1, A0~An = Don’t care)
When the Self Refresh Entry command is issued, the device enters the Self Refresh mode. While the device is in Self Refresh
mode, the device automatically refreshes memory cells, and all input and I/O buffers (except the CKE buffer) are disabled. By
asserting the CKE signal “high” (and by issuing the Self Refresh Exit command), the device exits the Self Refresh mode.
8.1.18 Self Refresh Exit Command
(CKE = H, CS = H or CKE = H, RAS = H, CAS = H)
This command is issued to exit out of the Self Refresh mode. One tRC delay is required prior to issuing any subsequent
command from the end of the Self Refresh Exit command.
8.1.19 Clock Suspend Mode Entry/Power Down Mode Entry Command
(CKE = L)
The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted “low”). The device state is
held intact while the CLK is suspended. On the other hand, when the device is not operating the Burst cycle, this command
performs entry into Power Down mode. All input and output buffers (except the CKE buffer) are turned off in Power Down
mode.
8.1.20 Clock Suspend Mode Exit/Power Down Mode Exit Command
(CKE = H)
When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command (asserting
CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled buffers are turned on to the
active state. Any subsequent commands can be issued after one clock cycle from the end of this command.
Publication Release Date : September 25, 2013
- 22 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
8.1.21 Data Write/Output Enable, Data Mask/Output Disable Command
(DQM = L/H or LDQM, UDQM = L/H or DQM0-3=L/H)
During a Write cycle, the DQM or LDQM, UDQM or DQM0-3 signals mask write data. Each of these signals control the input
buffers per byte. During a Read cycle, the DQM or LDQM, UDQM or DQM0-3 signals control of the output buffers per byte.
I/O Org.
MASK PIN
LDQM
MASKED DQs
DQ0~DQ7
×16
UDQM:
DQM0:
DQM1:
DQM2:
DQM3:
DQ8~DQ15
DQ0~DQ7
DQ8~DQ15
DQ16~DQ23
DQ24~DQ31
×32
9. OPERATION
9.1 Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from
the Bank Activate command, the data is read out sequentially, synchronized to the positive edges of CLK (a Burst Read operation).
The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS latency must be
set in the Mode Register at power-up. In addition, the burst length of read data and Addressing Mode must be set. Each bank is
held in the active state unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle,
then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Also, when the Burst
Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tRAS
(min). In this case, tRAS (min) must be satisfied by extending tRCD
.
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is terminated.
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or Precharge command is
issued.
9.2 Write Operation
Issuing the Write command after tRCD from the Bank Activate command, the input data is latched sequentially, synchronizing with
the positive edges of CLK after the Write command (Burst Write operation). The burst length of the Write data (Burst Length) and
Addressing Mode must be set in the Mode Register at power-up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle,
then the bank is switched to the idle state. This command cannot be interrupted by any other command for the entire burst data
duration. Also, when the Burst Length is 1 and tRCD (min), the timing from the RAS command to the start of the Auto Precharge
operation is shorter than tRAS (min). In this case, tRAS (min) must be satisfied by extending tRCD
.
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated.
When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the Precharge command is
issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst length.
Publication Release Date : September 25, 2013
Revision : A01-004
- 23 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.3 Precharge
There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the Bank Precharge
command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command
can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time
each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS (max)
from the Bank Activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the
Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the
precharged bank is then switched to the idle state.
9.3.1 Auto Precharge
Auto precharge is a feature that performs the same individual-bank PRECHARGE function described previously, without requiring
an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon
completion of the READ or WRITE burst.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. Another command cannot be issued
to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time.
Winbond SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and WRITEs are defined
below.
9.3.2 READ with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to bank n
begins when the READ to bank m is registered.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ-AP
Bank n
READ-AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Command
Bank n
Page active
READ with burst of 4
Interrupt burst, precharge
Idle
tRP-bank n
tRP-bank m
Internal
states
Page active
READ with burst of 4
Precharge
Bank m
Bank n,
Col a
Bank m,
Col d
Address
DQ
Dout
a
Dout
a+1
Dout
d
Dout
d+1
CL=3 (bank n)
CL=3 (bank m)
Don’t Care
Note: 1. DQM is LOW.
Publication Release Date : September 25, 2013
Revision : A01-004
- 24 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.3.3 READ with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the
WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is
registered.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ-AP
Bank n
WRITE-AP
Bank m
NOP
NOP
NOP
NOP
NOP
Command
Bank n
NOP
Page
active
READ with burst of 4
Page active
Interrupt burst, precharge
tRP-bank n
Idle
Internal
states
tWR-bank m
WRITE with burst of 4
Write-back
Bank m
Address
Bank n,
Col a
Bank m,
Col d
1
DQM
Din
d+2
DOUT
a
Din
d+3
Din
d
Din
d+1
DQ
CL=3 (bank n)
Don’t Care
Note: 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.
9.3.4 WRITE with auto precharge interrupted by a READ (with or without auto precharge)
A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank
n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be
data in registered one clock prior to the READ to bank m.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
WRITE-AP
Bank n
READ-AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Interrupt burst, write-back
tWR-bank n
Page active
WRITE with burst of 4
precharge
tRP-bank n
Internal
states
tRP-bank m
READ with burst of 4
Page active
Bank m
Bank n,
Col a
Bank m,
Col d
Address
DQ
Din
a+1
Dout
d
Dout
d+1
Din
a
CL=3 (bank m)
Don’t Care
Note: 1. DQM is LOW.
Publication Release Date : September 25, 2013
Revision : A01-004
- 25 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.3.5 WRITE with auto precharge interrupted by a WRITE (with or without auto precharge)
A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where
tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to
a WRITE to bank m.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Bank n
WRITE-AP
Bank n
WRITE-AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
WRITE with burst of 4
Interrupt burst, write-back
tWR-bank n
precharge
tRP-bank n
Page active
Internal
states
tWR-bank m
Write-back
WRITE with burst of 4
Page active
Bank m
Bank m,
Col d
Bank n,
Col a
Address
DQ
Din
a
Din
a+1
Din
a+2
Din
d
Din
d+1
Din
d+2
Din
d+3
Don’t Care
Note: 1. DQM is LOW.
9.4 Burst Termination
The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted by a Write
command, the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a
Read command, only the input data before the Read command is enable and the input data after the Read command is disabled.
- Read Interrupted by a Precharge
A Precharge command can be issued to terminate a Burst cycle early. When a Burst Read cycle is interrupted by a Precharge
command, the read operation is terminated after ( CAS latency-1) clock cycles from the Precharge command.
- Write Interrupted by a Precharge
A burst Write cycle can be interrupted by a Precharge command, the input circuit is reset at the same clock cycle at which the
Precharge command is issued. In this case, the DQM signal must be asserted high to prevent writing the invalid data to the
cell array.
- Read Interrupted by a Burst Stop
When the Burst Stop command is issued for the bank in a Burst cycle, the Burst operation is terminated. When the Burst Stop
command is issued during a Burst Read cycle, the read operation is terminated after clock cycle of ( CAS latency-1) from the
Burst Stop command.
- Write Interrupted by a Burst Stop
When the Burst Stop command is issued during a Burst Write cycle, the write operation is terminated at the same clock cycle
that the Burst Stop command is issued.
- Write Interrupted by a Read
A burst of write operation can be interrupted by a read command. The read command interrupts the write operation on the
same clock that the read command is issued. All the burst writes that are presented on the data bus before the read command
is issued will be written to the memory. Any remaining burst writes will be ignored once the read command is activated. There
must be at least one clock bubble (Hi-Z state) on the data bus to avoid bus contention.
- Read Interrupted by a Write
A burst of read operation can be interrupted by a write command by driving output drivers in a Hi-Z state using DQM before
write to avoid data conflict. DQM should be utilized if there is data from a Read command on the first and second cycles of the
subsequent write cycles to ensure the read data are tri-stated. From the third clock cycle, the write command will control the
data bus and DQM is not needed.
Publication Release Date : September 25, 2013
- 26 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.5 Mode Register Operation
The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Burst
Length field to set the length of burst data, an Addressing Mode selected bits to designate the column access sequence in a Burst
cycle, and a CAS Latency field to set the access time in clock cycle.
The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The data to be set in
the Mode Register is transferred using the A0~An, BA0, BA1 address inputs. The initial value of the Mode Register after power-up
is undefined; therefore the Mode Register Set command must be issued before proper operation.
9.5.1 Burst Length field (A2~A0)
This field specifies the data length for column access using the A2~A0 pins and sets the Burst Length to be 1, 2, 4, 8, words, or
full-page.
BUST
LENGTH
A2
A1
A0
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
1 word
2 words
4 words
8 words
Full-Page
9.5.2 Addressing Mode Select (A3)
The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is 0, Sequential mode is
selected. When the A3 bit is 1, Interleave mode is selected. Both Addressing modes support burst length of 1, 2, 4 and 8 words.
Additionally, Sequential mode supports the full-page burst.
A3
ADDRESSING MODE
0
1
Sequential
Interleave
Addressing sequence of Sequential mode
A column access is performed by incrementing the column address input to the device. The address is varied by the Burst
Length shown as below table.
Publication Release Date : September 25, 2013
- 27 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.5.3 Addressing Sequence for Sequential Mode
DATA
Access Address
Burst Length
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
n
2 words (Address bits is A0)
not carried from A0 to A1
n + 1
n + 2
n + 3
n + 4
n + 5
n + 6
n + 7
4 words (Address bits is A1, A0)
not carried from A1 to A2
8 words (Address bits is A2, A1, A0)
not carried from A2 to A3
Addressing sequence of Interleave mode
A column access is started from the input column address and is performed by inverting the address bits in the sequence
shown as below table.
9.5.4 Addressing Sequence for Interleave Mode
DATA
Access Address
Burst Length
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
2 words
4 words
8 words
Publication Release Date : September 25, 2013
Revision : A01-004
- 28 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.5.5 Addressing Sequence Example (Burst Length = 8 and Input Address is 13)
INTERLEAVE MODE
SEQUENTIAL MODE
DATA
A8 A7 A6 A5 A4 A3 A2 A1 A0
ADD
13
12
15
14
9
ADD
13
Data0
Data1
Data2
Data3
Data4
Data5
Data6
Data7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
13
13 + 1
13 + 2
13 + 3
13 + 4
13 + 5
13 + 6
13 + 7
14
calculated using
15
8
A2, A1 and A0 bits
not carry from
A2 to A3 bit.
9
8
10
11
12
11
10
9.5.6 Read Cycle CAS Latency = 3
0
1
2
3
4
5
6
7
8
9
10
11
Command
Address
Read
13
DQ0~DQ7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
13
13
12
14
15
15
14
8
9
9
8
11
11
10
12
Interleave mode
Sequential mode
Data Address {
10
Publication Release Date : September 25, 2013
Revision : A01-004
- 29 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.5.7 CAS Latency field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values
of CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this
field.
A6
A5
A4
CASLatency
0
0
1
1
0
1
2 clock
3 clock
Reserved bits (A7, A8, A10, A11, An, BA0, BA1)
These bits are reserved for future operations. They must be set to 0 for normal operation.
Single Write mode (A9)
This bit is used to select the write mode. When the A9 bit is 0, Burst Read and Burst Write mode are selected. When the A9
bit is 1, Burst Read and Single Write mode are selected.
A9
0
Write Mode
Burst Read and Burst Write
Burst Read and Single Write
1
9.5.8 Mode Register Definition
BurstLength
A0
A2 A1 A0
Sequential
1
Interleave
A1
A2
Burst Length
Addressing Mode
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
2
4
8
A3
Reserved
Full Page
A4
Reserved
A5
A6
A3
0
1
Addressing Mode
Sequential
Interleave
A7
"0"
"0"
Reserved
Reserved
A8
A6 A5 A4
CAS Latency
Reserved
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
A9
WriteMode
Reserved
2
A10
A11
"0"
"0"
3
Reserved
Reserved
"0"
"0"
"0"
A90
0
1
Single Write Mode
An
Burst read andBurst write
Burst read andsingle write
BA0
BA1
Publication Release Date : September 25, 2013
Revision : A01-004
- 30 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.6 Extended Mode Register Description
The Extended Mode Register designates the operation condition while SDRAM is in Self Refresh Mode and selects
the output driver strength as full, 1/2, 1/4, or 1/8 strength. The register is divided into two fields; (1) Partial Array Self
Refresh field selects how much banks or which part of a bank need to be refreshed during Self Refresh. (2) Driver
Strength selected bit to control the size of output buffer. The initial value of the Extended Mode Register after power-
up is Full Driver Strength, and all banks are refreshed during Self Refresh Mode.
A2 A1 A0
Self-Refresh coverage
All banks
A0
A1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Partial Array
Self Refresh
Banks 0 and 1 (BA1=0)
Bank 0 (BA1=BA0=0)
Reserved
A2
A3
"0"
"0"
Reserved
Reserved
Reserved
A4
A5
Reserved
Reserved
Output Driver
A6
A7
A8
A9
"0"
"0"
"0"
Reserved
A10 "0"
A6
A5
Driver Strength
Full strength
1/2 strength
1/4 strength
1/8 strength
"0"
"0"
"0"
"1"
A11
0
0
1
1
0
1
0
1
An
Extended
Mode
Register Set
BA0
BA1
Publication Release Date : September 25, 2013
Revision : A01-004
- 31 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
9.7 Simplified State Diagram
Publication Release Date : September 25, 2013
Revision : A01-004
- 32 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10. CONTROL TIMING WAVEFORMS
10.1 Command Input Timing
tCL
tCH
tCK
VIH
CLK
VIL
tT
tT
tCMS
tCMH
tCMH
tCMS
CS
tCMS
tCMH
RAS
tCMS
tCMH
tCMH
CAS
tCMS
WE
tAS
tAH
Address
BA0, BA1
tCKS
tCKH
tCKH
tCKS
tCKS
tCKH
CKE
Publication Release Date : September 25, 2013
Revision : A01-004
- 33 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.2 Read Timing
Read CAS Latency
CLK
CS
RAS
CAS
WE
Address
BA0, BA1
tAC
tAC
tHZ
tOH
tOH
tLZ
Output
Output
Data Valid
Data Valid
DQ
Read Command
Burst Length
Publication Release Date : September 25, 2013
Revision : A01-004
- 34 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.3 Control Timing of Input Data (x16)
(Word Mask)
CLK
tCMS
tCMH
tCMH
tCMS
LDQM
UDQM
tCMS
tCMH
tCMS
tCMH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ0~DQ7
tDS
tDH
tDS
tDH
tDH
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ8~DQ15
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ0~DQ7
tDS
tDH
tDH
tDS
tDH
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ8~DQ15
Publication Release Date : September 25, 2013
Revision : A01-004
- 35 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.4 Control Timing of Output Data (x16)
(Output Enable)
CLK
tCMH
tCMH
tCMS
tCMS
tCMS
tCMH
LDQM
tCMS
tCMH
UDQM
tAC
tHZ
tAC
tAC
tAC
tAC
tLZ
tOH
tOH
tOH
tOH
Output
Data Valid
Output
Output
DQ0~DQ7
Data Valid
Data Valid
OPEN
tAC
tHZ
tAC
tAC
tLZ
tOH
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
Output
Data Valid
DQ8~DQ15
OPEN
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tAC
tOH
tAC
tOH
tAC
tOH
tOH
Output
Data Valid
Output
Data Valid
Output Data Valid
DQ0~DQ7
tAC
tAC
tAC
tOH
tAC
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
DQ8~DQ15
Output Data Valid
Publication Release Date : September 25, 2013
Revision : A01-004
- 36 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.5 Control Timing of Input Data (x32)
CLK
(Word Mask)
tCMS
tCMH
tCMH
tCMS
DQM0
DQM1
tCMH
tCMS
tCMS
tCMH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ0~DQ7
tDS
tDS
tDH
tDS
tDH
tDS
tDH
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ8~DQ15
tDS
tDS
tDS
tDS
tDS
tDS
tDH
tDS
tDH
tDH
tDH
tDH
Input
Data Valid
Input
Data Valid
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ16~DQ23
DQ24~DQ31
tDS
tDS
tDH
tDS
tDH
tDH
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
*DQM2, 3 = “L”
(Clock Mask)
CLK
tCKH
tCKS
tCKH
tCKS
RAS
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ0~DQ7
tDS
tDH
tDH
tDS
tDH
tDS
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ8~DQ15
tDS
tDH
tDS
tDH
tDS
tDH
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ16~DQ23
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
Input
Data Valid
Input
Data Valid
Input
Data Valid
Input
Data Valid
DQ24~DQ31
*DQM2, 3 = “L”
Publication Release Date : September 25, 2013
Revision : A01-004
- 37 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.6 Control Timing of Output Data (x32)
(Output Enable)
CLK
tCMH
tCMH
tCMH
tCMS
tCMS
tCMS
DQM0
tCMS
tCMH
DQM1
tAC
tHZ
tAC
tAC
tAC
tOH
tLZ
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
Output
Data Valid
DQ0~DQ7
OPEN
tAC
tAC
tAC
tHZ
tAC
tAC
tLZ
tOH
tOH
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
Output
Data Valid
DQ8~DQ15
OPEN
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tLZ
Output
Data Valid
Output
Data Valid
Output
Data Valid
Output
Data Valid
DQ16~DQ23
tAC
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
Output
Data Valid
Output
Data Valid
DQ24~DQ31
(Clock Mask)
CLK
DQM2, 3 = “L”
tCKH
tCKS
tCKH
tCKS
CKE
tAC
tAC
tOH
tAC
tAC
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
DQ0~DQ7
Output Data Valid
tAC
tAC
tAC
tAC
tAC
tAC
tAC
tOH
tAC
tOH
tOH
tOH
tOH
tOH
tOH
tOH
Output
Data Valid
Output
Data Valid
DQ8~DQ15
Output Data Valid
Output Data Valid
Output Data Valid
tAC
tOH
tAC
tOH
Output
Data Valid
Output
Data Valid
DQ16~DQ23
DQ24~DQ31
tAC
tOH
tAC
tOH
Output
Data Valid
Output
Data Valid
DQM2, 3 = “L”
Publication Release Date : September 25, 2013
Revision : A01-004
- 38 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.7 Mode register Set (MRS) Cycle
tMRD
CLK
tCMS
tCMS
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tCMH
tCMS
tAS
tCMH
tAH
Address
BA0,BA1
Register
set data
next command
BurstLength
A2 A1 A0
A0
A1
A2
Sequential
Interleave
Burst Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
4
8
2
4
8
A3 Addressing Mode
A4
Reserved
FullPage
Reserved
A5
A6
CAS Latency
A3
0
1
Addressing Mode
Sequential
Interleave
0
0
Reserved
Reserved
A7
A8
CAS Latency
Reserved
Reserved
2
3
Reserved
A6 A5 A4
A9
WriteMode
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
A10
A11
An
Reserved
A9
0
1
Single Write Mode
Burst read and Burst write
Burst read and single write
BA0
BA1
Mode
Register Set
“Reserved” pins should be set to “0” during MRS cycle.
Publication Release Date : September 25, 2013
Revision : A01-004
- 39 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
10.8 Extended Mode register Set (EMRS) Cycle
tMRD
CLK
tCMS
tCMS
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tCMH
tCMS
tAS
tCMH
tAH
Address
BA0,BA1
Register
set data
next command
A2 A1 A0
Partial Self Refresh
Allbanks
Bank0,1(BA1=0)
Bank0(BA0=BA1=0)
A0
A1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
PASR
0
1
A2
1
0
0
0
A3
Reserved
0
Reserved
A4
1
1
A5
Output Driver
A6
0
0
0
A7
A8
A9
Reserved
Output Driver Strength
A6 A5
00
01
10
11
A10
A11
An
BA0
BA1
0
0
0
Full Strength
1/2 Strength
1/4 Strength
1/8 Strength
Extended
Mode
Register Set
0
1
"Reserved" pins should be set to "0" during EMRS cycle
Publication Release Date : September 25, 2013
Revision : A01-004
- 40 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
WE
BA0
BA1
tRCD
tRCD
tRCD
tRCD
RAa
RAa
RBb
RBb
RAc
RBd
RBd
A10
RAe
RAe
CBx
RAc
CAy
CAw
CBz
Address
DQM
CKE
DQ
tAC
tAC
tAC
tAC
bx3
bx1
aw0
aw2
aw3
bx0
bx2
cy0
cy1
cy2
cy3
aw1
tRRD
tRRD
tRRD
tRRD
Active
Read
Active
Bank #0
Bank #1
Read
Active
Precharge
Read
Precharge
Read
Precharge
Active
Active
Bank #2
Bank #3
Idle
Publication Release Date : September 25, 2013
Revision : A01-004
- 41 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRAS
tRP
tRP
tRAS
WE
BA0
BA1
A10
tRCD
tRCD
tRCD
tRCD
RBd
RAa
RAa
RBb
RBb
RAc
RAe
Address
DQM
CBz
CAw
CAy
RAe
CBx
RAc
RBd
CKE
tAC
tAC
tAC
tAC
aw0 aw1 aw2 aw3
cy0
cy1
cy2
bx0
bx1
bx3
cy3
dz0
bx2
DQ
tRRD
tRRD
tRRD
Read
tRRD
Active
AP*
AP*
Read
Active
Active
AP*
Bank #0
Bank #1
Bank #2
Bank #3
Read
Active
Read
Active
Idle
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 42 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
tRC
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
tRCD
tRCD
A10
RAa
RAa
RAc
RAc
RBb
RBb
CAx
CBy
CAz
Address
DQM
CKE
DQ
tAC
tAC
tAC
ax0
ax1
ax2
ax3
ax4
ax5
ax6
by0
by1
by4
by5
by6
by7
CZ0
tRRD
tRRD
Read
Active
Idle
Precharge
Active
Read
Precharge
Bank #0
Bank #1
Bank #2
Bank #3
Active
Precharge
Read
Publication Release Date : September 25, 2013
Revision : A01-004
- 43 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
1
2
3
4
5
21 22 23
0
CLK
CS
tRC
tRC
RAS
tRAS
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
tRCD
tRCD
A10
RBb
RAc
RAc
RAa
RAa
CAz
CAx
RBb
CBy
Address
DQM
CKE
DQ
tAC
tAC
tAC
ax3
ax0
ax1
ax2
ax4
ax5
ax6
ax7
by0
by1
by4
by5
by6
cz0
tRRD
tRRD
AP*
Read
Active
Bank #0 Active
Bank #1
Read
Active
Read
AP*
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 44 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.5 Interleaved Bank Write (Burst Length = 8)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
tRC
RAS
CAS
tRAS
tRP
tRP
tRAS
tRCD
tRCD
tRCD
WE
BA0
BA1
RBb
RAc
RAc
RAa
RAa
A10
CAx
CBy
CAz
RBb
Address
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
cz0
cz1
cz2
tRRD
tRRD
Active
Write
Precharge
Active
Write
Bank #0
Active
Write
Precharge
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date : September 25, 2013
Revision : A01-004
- 45 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.6 Interleaved Bank Write (Burst Length = 8, Auto Precharge)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
1
2
3
4
5
0
CLK
CS
tRC
RAS
CAS
tRAS
tRAS
tRP
tRAS
tRP
WE
BA0
BA1
A10
tRCD
tRCD
tRCD
RAc
RAc
RBb
RAa
RAa
CAx
RBb
CBy
CAz
Address
DQM
CKE
DQ
ax0
ax1
ax4
ax5
ax6
ax7
by0
by1
by2
by3
by4
by5
by6
by7
cz0
cz1
cz2
tRRD
tRRD
Active
Write
|
AP*
Active
Write
Bank #0
AP*
|
Write
Active
Bank #1
Bank #2
Bank #3
Idle
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 46 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tCCD
tCCD
tCCD
tRAS
tRP
tRAS
tRP
RAS
CAS
WE
BA0
BA1
tRCD
tRCD
RAa
RAa
RBb
RBb
A10
CBx
CAy
CAm
CBz
CAI
Address
DQM
CKE
tAC
tAC
tAC
tAC
tAC
bz0
bz1
bz2
bz3
am2
al0
al1
al3
bx0
Ay0
Ay1
Ay2
bx1
am0 am1
al2
DQ
tRRD
Read
Bank #0 Active
Bank #1
Read
Read
Precharge
AP*
Active
Read
Read
Bank #2
Idle
Bank #3
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 47 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
tRAS
tRP
RAS
CAS
WE
BA0
BA1
tRCD
RAa
RAa
A10
CAx
CAy
Address
DQM
CKE
tAC
tWR
ay1
ax0
ax1
ax3
ay0
ax5
ay2
ay4
ax2
ax4
ay3
DQ
Q Q
Q
Q
Q
Q
D
D
D
D
D
Bank #0
Bank #1
Bank #2
Bank #3
Active
Idle
Read
Write
Precharge
Publication Release Date : September 25, 2013
Revision : A01-004
- 48 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
tRAS
tRP
tRAS
tRP
CAS
WE
BA0
BA1
tRCD
tRCD
RAa
RAa
RAb
A10
CAx
CAw
RAb
Address
DQM
CKE
DQ
tAC
tAC
aw0
aw1 aw2 aw3
bx0
bx1
bx2 bx3
Bank #0
AP*
Active
Idle
Read
Active
Read
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 49 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.10 Auto Precharge Write (Burst Length = 4)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRC
tRC
RAS
CAS
tRAS
tRP
tRAS
tRP
WE
BA0
BA1
tRCD
tRCD
RAc
RAa
RAa
RAb
A10
Address
DQM
CKE
CAw
RAb
CAx
RAc
bx0
aw2 aw3
bx1
bx3
aw0 aw1
bx2
DQ
Active
Idle
AP*
Bank #0
Write
Active
Write
Active
AP*
Bank #1
Bank #2
Bank #3
* AP is the internal precharge start timing
Publication Release Date : September 25, 2013
Revision : A01-004
- 50 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.11 Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
tRFC
tRFC
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
CKE
DQ
All Banks
Prechage
Auto
Refresh
Auto Refresh (Arbitrary Cycle)
Publication Release Date : September 25, 2013
- 51 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.12 Self Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
tRP
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
tCKS
tCKS
tSB
CKE
DQ
tCKS
tRFC
Device Deselect (DSL) Cycle
All Bank Precharge
Self Refresh
Entry
Self Refresh
Exit
Arbitrary Cycle
Note: The device exit the Self Refresh mode asynchronously at the rising edge of the CKE signal.
After CKE goes high, the Device Deselect or No-operation command must be registered at the immediately following
CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exit the Self Refresh Mode.
A bust of 8K auto refeesh cycle within 7.8us before entering and exiting is necessary if the system does not use the
auto refresh function.
Publication Release Date : September 25, 2013
Revision : A01-004
- 52 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.13 Power Down Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
RAS
CAS
WE
BA
RAa
RAa
RAa
RAa
A10
CAa
CAx
Address
DQM
tSB
tSB
CKE
DQ
tCKS
tCKS
tCKS
tCKS
ax3
ax2
ax0
ax1
Active
Active
DSL
Precharge
&
Power Down Mode Entry
Power Down MPoodweer Down Mode
Entry Exit
Device Deselect
Power Down Mode Exit
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
Publication Release Date : September 25, 2013
Revision : A01-004
- 53 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.14 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
tRCD
WE
BA0
BA1
A10
RBa
RBa
CBz
Address
CBv
CBw
CBx CBy
DQM
CKE
tAC
tAC
DQ
av0
av1
av3
aw0
ax0
ay0
az1
az2
az3
az0
av2
Q
Q
Q
Q
D
D
D
Q
Q
Q
Q
Read
Active
Single Write
Read
Bank #0
Bank #1
Bank #2
Bank #3
Idle
Publication Release Date : September 25, 2013
Revision : A01-004
- 54 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.15 Deep Power Down Mode Entry
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CLK
CS
tRP
RAS
CAS
WE
BA0,BA1
A10
Address
DQM
tSB
CKE
DQ
tCKS
Active Banks Precharge
Deep Power Down Entry
Publication Release Date : September 25, 2013
Revision : A01-004
- 55 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.16 Deep Power Down Mode Exit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
22
CLK
CS
tRP
tMRD
tMRD
RAS
CAS
WE
A10
OP-Code
OP-Code
Address
DQM
CKE
DQ
tCKS
200μs
tRFC
tRFC
Extended Mode
Register Set
All Banks Precharge
Auto Refresh
Arbitrary Cycle
Mode Register Set
Auto Refresh
DSL
Deep Power Down Exit
Issue Auto Refresh cycle two or more
Note:
The device exits the Deep Power Down Mode asynchronously at the rising edge of the CKE signal.
After CKE goes high, the Device Deselect or No-operation command must be register at the immediately
following CLK rising edge, and CKE must remain high at least for tCKS delay immediately after exiting
the Deep Power Down Mode.
Publication Release Date : September 25, 2013
Revision : A01-004
- 56 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.17 Auto Precharge Timing (Read Cycle)
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
( a ) burst length = 1
Command
Read
AP
Act
tRP
DQ
Q0
( b ) burst length = 2
Command
Read
Read
Read
AP
Q0
Act
tRP
DQ
Q1
( c ) burst length = 4
Command
AP
Q2
Act
Q4
tRP
DQ
Q0
Q0
Q1
Q1
Q3
( d ) burst length = 8
Command
AP
Q6
Act
tRP
DQ
Q2
Act
Q3
Act
Q5
Q7
(2) CAS Latency=3
( a ) burst length = 1
Command
Read
Read
Read
Read
AP
tRP
DQ
Q0
Q0
Q0
Q0
( b ) burst length = 2
Command
AP
tRP
DQ
Q1
AP
Q1
( c ) burst length = 4
Command
Act
Q4
tRP
DQ
Q2
Q2
Q3
Q3
( d ) burst length = 8
Command
AP
Q5
Act
tRP
DQ
Q1
Q6
Q7
Note:
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Read
AP
Act
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least tRAS (min).
“Dn” = Write data, and “Qn” = Read data
Publication Release Date : September 25, 2013
Revision : A01-004
- 57 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.18 Auto Precharge Timing (Write Cycle)
0
Write
1
2
PRE
3
4
5
6
7
8
9
10
11
12
(1) burst length = 1
Command
tWR
Write / A
D0
AP
Act
tRP
tWR’
DQ
(2) burst length = 2
PRE
AP
Write
tWR
Command
Act
Write / A
tWR’
tRP
DQ
D0
D1
(3) burst length = 4
PRE
AP
Write
tWR
Act
Command
Write / A
D0
tWR’
tRP
DQ
D1
D1
D2
D2
D3
D3
PRE
AP
(4) burst length = 8
Command
tWR
Write
Act
Write / A
tWR’
tRP
DQ
D0
D4
D5
D6
D7
Note: 1.
represents the write command.
Write
represents the Write with Auto precharge command.
represents the start of internal precharging.
Write / A
AP
represents the Precharge command.
PRE
represents the Bank Activate command.
Act
When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at
2.
least tRAS (min).“Dn” = Write data, and “Qn” = Read data
For WRITE without auto-precharge, tWR= 15ns.
For WRITE with auto-precharge, tWR=2tCK.
3.
4.
Publication Release Date : September 25, 2013
- 58 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.19 Timing Chart of Read to Write Cycle
In the case of Burst Length = 4
1
2
3
4
5
6
7
8
9
10
11
0
(1) CAS Latency = 2
DQM Latency = 2
( a ) Command
Read
Write
DQM
DQ
D0
D1
D2
D1
D3
D2
( b ) Command
DQM
Read
Write
D0
D3
DQ
(2) CAS Latency = 3
DQM Latency = 2
( a ) Command
Read
Read
Write
D0
DQM
D1
D2
D1
D3
D2
DQ
( b ) Command
Write
DQM
DQ
D0
D3
Note: The Output data must be masked by DQM to avoid I/O conflict.
“Dn” = Write data, and “Qn” = Read data
11.20 Timing Chart for Write to Read Cycle
In the case of Burst
Length=4
0
1
2
3
4
5
6
7
8
9
10
11
(1) CAS Latency=2
Write Read
( a ) Command
DQM
tLDR
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
DQM
Read
Write
tLDR
DQ
D0
D1
Q3
(2) CAS Latency=3
( a ) Command
Write Read
tLDR
DQM
DQ
D0
Q0
Q1
Q0
Q2
Q1
Q3
Q2
( b ) Command
Write
Read
tLDR
DQM
DQ
D0
D1
Q3
Note: “Dn” = Write data, and “Qn” = Read data
Publication Release Date : September 25, 2013
Revision : A01-004
- 59 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.21 Timing Chart for Burst Stop Cycle (Burst Stop Command)
0
1
2
3
4
5
6
7
8
9
10
11
(1) Read cycle
( a ) CAS latency =2
Command
Read
BST
Q3
DQ
Q0
Q1
Q0
Q2
Q1
Q4
Q3
( b )CAS latency = 3
Command
DQ
Read
BST
Q2
Q4
(2) Write cycle
Command
Write
Q0
BST
Q1
Q2
Q3
Q4
DQ
BST
“Dn” = Write data, and “Qn” = Read data
Note:
represents the Burst stop command
11.22 Timing Chart for Burst Stop Cycle (Precharge Command)
In the case of urst
0
1
2
3
4
5
6
7
8
9
10
11
Length = 8
(1) Read cycle
(a) CAS latency =2
Read
PRCG
Q3
Command
DQ
Q0
Q1
Q0
Q2
Q1
Q4
(b) CAS latency =3
Command
Read
Write
PRCG
Q2
DQ
Q3
Q4
(2) Write cycle
(a) CAS latency =2
Command
Write DQM Latency = 0
PRCG
tWR
DQM
Q0
Q1
Q2
Q3
Q4
DQ
(b) CAS latency =3
Command
PRCG
Write
tWR
Write DQM Latency = 0
DQM
Q0
Q1
Q2
Q3
Q4
DQ
PRCG
Note:
represents the Precharge command.
“Dn” = Write data, and “Qn” = Read data.
Publication Release Date : September 25, 2013
Revision : A01-004
- 60 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.23 CKE/DQM Input Timing (Write Cycle)
1
2
3
4
5
6
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
5
D6
7
DQM MASK
CKE MASK
( 1 )
4
CLK cycle No.
External
6
CLK
Internal
CKE
DQM
DQ
D1
1
D2
2
D3
3
D5
6
D6
DQM MASK
( 2 )
CKE MASK
4
5
7
CLK cycle No.
External
CLK
Internal
CKE
DQM
DQ
D1
D2
D3
D4
D5
D6
CKE MASK
( 3 )
Note) “Dn” = Write data, and “Qn” = Read data
Publication Release Date : September 25, 2013
Revision : A01-004
- 61 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
11.24 CKE/DQM Input Timing (Read Cycle)
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q1
Q2
Q3
Q4
Open
Open
( 1 )
1
2
3
4
5
7
CLK cycle No.
External
6
CLK
Internal
CKE
DQM
DQ
Q3
Q4
Q6
Q1
Q2
Open
( 2 )
1
CLK cycle No.
2
3
4
5
6
7
External
CLK
Internal
CKE
DQM
DQ
Q6
Q3
Q1
Q5
Q4
Q2
Note) “Dn” = Write data, and “Qn” = Read data
( 3 )
Publication Release Date : September 25, 2013
Revision : A01-004
- 62 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
12. PACKAGE DIMENSION
12.1 : LPSDR X 16
VBGA 54Ball (8X9 MM^2, Ball pitch:0.8mm)
Note:
1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm
2. Dimensions apply to Solder Balls Post-Reflow.The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad
Publication Release Date : September 25, 2013
- 63 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
12.2 : LPSDR X 32
VBGA90Ball (8X13 MM^2, Ball pitch:0.8mm)
Note:
1. Ball land:0.5mm. Ball opening:0.4mm. PCB Ball land suggested ≦0.4mm
2. Dimensions apply to Solder Balls Post-Reflow. The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad.
Publication Release Date : September 25, 2013
- 64 -
Revision : A01-004
W987D6HB / W987D2HB
128Mb Mobile LPSDR
13. REVISION HISTORY
Version
Date
Page
Description
A01-001
04/29/2011
All
Product datasheet for customer.
Update IDD4 value , Add Normal power grade & PASR.
Update ordering info.
9~11
66
A01-002
A01-003
06/09/2011
11/21/2012
2
Update ordering Info. typo.
Add note to section 7.1.
9
14
58
60
Remove section 7.6.2 VREF & SLEW.
Update section 11.16 figure.
Update section 11.18 figure.
9
Update VDD;VDDQ;Vin/Vout value of section 7.1.
14,19,39,40,56 Update tRSC to tMRD
A01-004
09/25/2013
14
26
Update table of 7.6.2.
Update text typo.
Publication Release Date : September 25, 2013
Revision : A01-004
- 65 -
W987D6HB / W987D2HB
128Mb Mobile LPSDR
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
------------------------------------------------------------------------------------------------------------------------------------------------------------
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in the datasheet belong to their respective owners.
Publication Release Date : September 25, 2013
- 66 -
Revision : A01-004
相关型号：
W987D2HBJX6I
128Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D2HBJX7E
128Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D2HBJX7G
128Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D2HBJX7I
128Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBGX5G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBGX6G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBGX7G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBHX5G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBHX6G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBJX5G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CBJX6G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
W987D6CKGX5G
512Mb Mobile LPSDRWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WINBOND
©2020 ICPDF网 联系我们和版权申明