W9960CF_技术文档

W9960CF

VIDEO CODEC

Technical Reference Manual

Version 1.11

June, 1997

Winbond Confidential

1

June 1997

W9960CF

The information in this document has been carefully checked and is believed to be correct as of

the date of publication. Winbond Electronics Corp. reserves the right to make changes in the

product or specification, or both, presented in this publication at any time without notice.

Winbond assumes no responsibility or liability arising from the specification listed herein.

Winbond makes no representations that the use of its products in the manner described in this

publication will not infringe on existing or future patent, trademark, copyright, or rights of third

parties. No license is granted by implication or other under any patent or patent rights of

Winbond Electronics Corp.

IBM is a registered trademark and AT, XT, and OS/2 are trademarks of International Business

Machines Corp.

Intel is a registered trademark of Intel Corporation.

Microsoft is a registered trademark and Windows, Windows 95, and DirectDraw are trademarks

of Microsoft Corp.

Philips is a registered trademark of Philips International B.V.

ALL OTHER TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE HOLDERS.

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1. INTRODUCTION..................................................................................................... 5

1.1 OVERVIEW................................................................................................................. 5

1.2 FEATURES.................................................................................................................. 6

2. PIN DESCRIPTION.................................................................................................. 7

2.1 PIN DEFINITION.......................................................................................................... 7

2.2 PINOUT DIAGRAM.................................................................................................... 11

3. FUNCTIONAL DESCRIPTION ............................................................................ 12

3.1 W9960CF ARCHITECTURE ....................................................................................... 12

3.2 PCI INTERFACE........................................................................................................ 13

3.3 VRISC .................................................................................................................... 14

3.4 FRAME MEMORY DMA CONTROLLER ( FDMA )...................................................... 20

3.4.1 Bus Arbitration ................................................................................................. 21

3.4.2 FDMA Transfer Type ........................................................................................ 21

3.4.3 FDMA Programming ........................................................................................ 22

3.4.4 FDMA Addressing Registers ............................................................................. 24

3.5 EXTERNAL MEMORY DMA CONTROLLER ( XDMA )................................................ 26

3.6 DRAM MEMORY INTERFACE................................................................................... 28

3.7 INTERRUPT/TRIGGER CONTROLLER ................................................................... 30

3.8 X_INTERRUPT CONTROLLER ( XINTC )............................................................... 32

3.9 GPIO ( GENERAL PURPOSE INPUT/OUPUT) PORT..................................................... 33

3.10 TIMER.................................................................................................................. 33

3.11 VIDEO PRE/POST PROCESSING ENGINE ................................................................... 35

3.11.1 Video PreProcessor (VPRE)............................................................................ 35

3.11.2 Video PostProcessor (VPOST)......................................................................... 36

3.12 MOTION ESTIMATION ENGINE ................................................................................ 38

3.13 FILTER ENGINE.................................................................................................... 39

3.14 FIDCT/Q/IQ ENGINE............................................................................................. 42

3.15 PROGRAMMABLE INPUT/OUTPUT ENGINE ............................................................... 44

3.16 VARIABLE LENGTH CODE DECODER ....................................................................... 46

3.17 AUDIO COPROCESSOR INTERFACE .......................................................................... 47

3.18 VARIABLE LENGTH CODE ENCODING (VLE) ENGINE.............................................. 48

3.19 ISA-LIKE INTERFACE.............................................................................................. 49

4. W9960CF REGISTERS.......................................................................................... 51

4.1 PCI CONFIGURATION REGISTERS.............................................................................. 51

5. ELECTRICAL SPECIFICATIONS....................................................................... 57

5.1 ABSOLUTE MAXIMUM RATINGS................................................................................ 57

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5.2 DC SPECIFICATIONS................................................................................................. 57

5.3 AC SPECIFICATIONS................................................................................................. 57

5.3.1 Clock Specification ........................................................................................... 58

5.3.2 Reset Timing ..................................................................................................... 58

5.3.3 PCI Interface AC Timing................................................................................... 59

5.3.4 AUDIO Interface AC Timing............................................................................. 60

5.3.5 DRAM Interface AC Timing.............................................................................. 61

5.3.6 GPIO AC Timing............................................................................................... 62

5.3.7 Video PreProcessor AC Timing......................................................................... 63

5.3.8 ISA-Like Bus AC Timing ................................................................................... 64

6. APPENDIXES ......................................................................................................... 65

6.1 PORTING GUIDE FOR W9960 WIN95 DEVICE DRIVER ............................................... 65

6.2 FIRMWARE LOADING PRECEDURE ............................................................................ 65

6.3 APPLICATION/FIRMWARE COMMAND BLOCK............................................................ 65

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W9960CF

1. INTRODUCTION

1.1 Overview

W9960CF is a single chip multi-protocol high performance video CODEC offered by Winbond

Electronics Corp. for video compression and decompression applications such as video-

conference.

W9960CF is composed of a high performance RISC processor core (VRISC), function blocks for

video encoding/decoding and a downloadable program memory such that the system can be run-

time configured for a variety of video applications. The function blocks in W9960CF are

computing engines for: Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform

(IDCT), Motion Estimation (ME), Motion Compensation (MC), Quantization (Q), Dequantization

(Q^-1) and VLE/VLD (Variable Length Encoding/Decoding) algorithms. Using these function

blocks, the firmware can direct the VRISC processor to perform ITU-T H.261/ H.263

simultaneous video bitstream encoding/decoding.

Although W9960CF is designed for multiple standard video encoding and decoding, it is

particularly optimized for H.261/H.263 video-conference application. W9960CF supports all

video resolutions as specified in the H.261/H.263 standards, including SQCIF, QCIF and CIF

at high video frame rate. For CIF resolution in H.261 and QCIF resolution in H.263,

specifically, W9960CF delivers excellent encoding/decoding performance.

Implementing most the advanced video encoding options, W9960CF enables lowest video

data rate such that maximum frame rate can be achieved through ISDN, PSTN and Internet

networks. The advanced encoding options supported are: Unrestricted Motion Vector Mode, and

PB-frame Mode. With half-pixel search for motion estimation function, W9960CF further

enhances video quality with even lowered video bitstream data rate.

W9960CF is also designed with a most cost-effective PC based video-conference solution in

mind. It has a digital live video interface for glueless support a of major video decoders and

coefficient-programmable filter circuitry for input video enhancement. For video displaying, it

supports PCI master mode capability to access video frame buffer of PCI-based graphics

adapters. W9960CF also provides an interface for audio modules. The audio modules connected

can be a CODEC for G.711/G.722/G.723/G.728 standards, or a PCM CODEC for audio raw

data. W9960CF uses ordinary FPM or EDO DRAM as working storage. Figure shows application

block diagram.

PCI Bus

Video

Decoder

256x16

D R A M

W9960

Video CODEC

Video Camera

Digital Camera

M ic/Spk

(Optional)

Audio

C O D E C

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W9960CF

1.2 Features

· Built-in RISC processor core and 4.5Kx22 bits program memory

· Supports ITU-T H.263 and H.261 simultaneous video encoding and decoding

· Supports SQCIF, QCIF and CIF video resolutions

· Supports H.263 Annex D Unrestricted Motion Vector mode

· Supports H.263 Annex G PB-frames Mode

· Supports both integer search and half-pixel search motion estimation

· Built-in BCH error correction and framing error detection circuitry

· Supports YUV 4:2:2 video input interface for video camera

· Built-in filter circuit with programmable coefficients for input video enhancement

· Selectable video output formats including YUV 4:2:2 and RGB 5:6:5

· Supports PCI master mode to access graphics adapters for video displaying

· Supports panning and zooming over video input

· Provides audio connection to external audio DSP modules

· Uses conventional FPM and EDO DRAM

· No SRAM required

· Optimized for 3.3 volts operation

· 0.5um CMOS technology

· 208-pin PQFP package

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2. PIN DESCRIPTION

2.1 Pin Definition

Pin Name

Pin No.

Type

Function

PCI BUS (50 pins)

AD31-AD0

204-205,4-9,

16-23, 42-49,

57-60, 65-68

IO

Address and Data are multiplexed on the same PCI pins. The

address phase is the clock cycle in which FRAME# is

asserted. During data phase AD7-AD0 contain the least

significant byte (lsb) and AD31-AD24 contain the most

significant byte (msb)

C/BE3-C/BE0 14,28,37,56

IO

Bus Command and Byte Enables are multiplexed on the

same PCI pins. During the address phase of a transaction,

C/BE3#-C/BE0# define the bus command. During the data

phase C/BE3#-C/BE0# are used as Byte Enable

PAR

36

29

31

IO

Parity is even parity across AD31-AD0 and C/BE3#-C/BE0#

FRAME# is asserted to indicate a bus transaction is beginning

FRAME#

TRDY#

Target Ready indicates the ability of target agent to complete

the current data phase of the transaction

IRDY#

30

IO

Initiator Ready indicates the ability of bus master to complete

the current data phase of the transaction.

INTA#

199

33

O

Interrupt A is used to request an interrupt

STOP#

IO

I

Stop indicates the current target is requesting the master to

stop the current transaction.

DEVSEL#

IDSEL

32

15

Device Select, indicates the driving device has decoded its

address as the target of the current access

Initialization Device Select is used as chip select during

configuration read and write transactions.

PERR#

SERR#

34

35

IO

O

Parity Error is for the reporting of data parity errors

System Error is for reporting address parity errors, or any

other system error where the result will be catastrophic.

REQ#

GNT#

203

202

O

I

Request indicates to the arbiter that W9960 desires use of the

bus

Grant indicates that W9960 access to the bus has been

granted

CLK

201

200

I

PCI Clock

PCI Reset

RST#

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GPIO BUS (4 pins)

GPIO3-

GPIO0

153, 160-162 IO

Connect to GPIO bus to video decoder or coprocessor

Pin Name

Pin No.

Type

Function

DRAM BUS (50 pins)

MD31-MD0

141-132,127-

118, 113-108,

101-96

IO

DRAM Data Bus

OE1# -OE0# 74,70

O

DRAM Output Enable

RAS1# -

RAS0#

81,73

80,72

91-82

DRAM Row Address Strobes

CAS1# -

CAS0#

O

DRAM Column Address Strobes

MA9 - MA0

O

DRAM Address Bus

WE1# -WE0# 75,71

DRAM Write Enable; WE1# for MD31-MD16,

and WE0# for MD15-MD0

AUDIO BUS ( 5 pins )

Receiver Frame Signal

Transmission Frame Signal

Transmission Data

RFS

TFS

DT

148

149

150

151

152

IO

O

I

DR

Receiver Data

SCLK

IO

clock of serial port

VIDEO BUS ( 20 pins )

Video Data Bus

VD15-VD0

186-184, 179-

169, 164-163

I

HS/HRESET# 187

VS/VRESET# 188

HREF/ACTive 189

IU

I

Horizontal Sync

Vertical Sync

I

Active region

Dvalid

193

IU

Video Data Valid

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Pin Name

Pin No.

Type

Function

ISA-Like BUS ( 30 pins )

SADATA0 -

SADATA7

196-197, 207,

25-26, 54, 62-

63,

IO

8-bit Parallel Data Bus

SAADDR0 - 77-78, 93-94,

SAADDR15 103, 106, 115-

116, 129-130,

O

16-bit Parallel Address Bus

143-144, 155,

158, 166-167

SAIOR#

SAIOW#

EINT1#

EINT2#

BTEN#

181

182

192

208

190

O

IO Read Control signal

IO Write Control signal

External Interrupt #1

IU

External Interrupt #2

External Boot ROM Enable

When BTEN# low active, firmware down-load by through ISA-

Like Bus automatically after RST# inactive

BTFLAG#

191

O

External Boot ROM Chip Select

CLOCK SOURCE ( 2 pins )

Internal Clock

CLK_MEM

CLK_Video

69

I

194

Video Clock

Note: IU : Input with internal pull-high Pad

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Pin Name

Pin No.

Type

Function

POWER ( 39 pins )

VDD

1,10,24,38,53,

61,76,92,105,

114,128,142,

157,165,180,

3.3V DC Power supply

195

VSS

3,13,27,41,50,

55,64,79,95,

Ground

102,

107,117,131,

145, 154, 159,

168, 183, 198,

206

VDD5V

NC

52,104,156

5.0V DC Power supply

NC ( 8 pins )

2,11,12, 39,

40, 51, 146,

147

No Connection

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2.2 PinOut Diagram

S S

A A

D D

R R

1 1

1 0

S

A

S S

A A

D D

R R

S S

A A

D D

R R

7 6

S

A

D

R

5

V

G

P

I

O

3

D

R

1

D

5

V

S

B

S

C

L

M M M M M M M M M M

D D D D D D D D D D

3 3 2 2 2 2 2 2 2 2

1 0 9 8 7 6 5 4 3 2

M M M M M M M M M M

D D D D D D D D D D

M M M M M M V

D D D D D D S

1 1 9 8 7 6 S

V

D

I

V

S

B

V

D

B

V

S

I

V

D

I

V

S

B

V

D

B

T R

N

C

N

C

D D F F

2

1

2 1 1 1 1 1 1 1

0 9 8 7 6 5 4 3

1

2

V

K R T S S

1 0

I

9

8

2

1

5

1

5

0

1

4

5

1

4

0

1

3

5

1

2

5

1

2

0

1

5

1

0

1

0

5

3

0

VDDI

VDD5V

SAADDR4

VSSB

MD5

SAADDR13

VSSI

160

165

170

175

180

185

190

195

200

205

GPIO2

GPIO1

GPIO0

VD0

100

MD4

MD3

MD2

VD1

MD1

MD0

VDDB

SAADDR14

SAADDR15

VSSB

VD2

95

90

85

80

75

70

65

60

55

VSSB

SAADDR3

SAADDR2

VDDB

MA9

VD3

VD4

MA8

VD5

MA7

VD6

MA6

VD7

MA5

VD8

MA4

VD9

MA3

VD10

VD11

VD12

MA2

MA1

W9960CF

Video CODEC

MA0

RAS1#

CAS1#

VSSI

VDDI

SAIOR#

SAIOW#

VSSI

SAADDR1

SAADDR0

VDDI

VD13

VD14

VD15

WE1#

OE1#

RAS0#

CAS0#

WE0#

OE0#

CLK_MEM

AD0

HRESET#

VRESET#

ACTive

BTEN#

BTFLAG#

EINT1#

Dvalid

CLK_Video

VDDB

AD1

AD2

SADATA0

SADATA1

VSSB

AD3

VSSB

SADATA7

SADATA6

VDDB

AD4

INTA#

RST#

CLK

GNT#

AD5

REQ#

AD6

AD31

AD7

AD30

C/BE0#

VSSI

SADATA2

EINT2#

SADATA5

VDDI

1

0

1

5

2

0

2

5

3

0

3

5

4

0

4

5

0

1

5

I

C

/

B

E

3

#

S S

A A

D D

A A

T T

A A

3 4

C F

V

S

B

V

D

B

V

S

B

V

D

I

V

S

I

D

E

V

S

E

L

A A A A A A

D D D D D D

A

D

1

T

R

D

Y

#

S P

T E

O R

P R

C V

V

S

B

A A A A A A A

D D D D D D D

I

S P

E A

R R

R

N

C

A A A A A A A A

D D D D D D D D

N

C

V N V

S C D

N

C

N N

C C

D

S

E

L

/

R

D

I

/

D

R

D

Y

#

B A

E M

2

9

2 2 2 2 2

8 7 6 5 4

B D

E B

1

2

3

2 2 2 1 1

2 1 0 9 8

1

7

1

5

1 1 1 1 1 9 8

4 3 2 1 0

S

B

D

5

6

2

#

E

#

V

#

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W9960CF

3. FUNCTIONAL DESCRIPTION

3.1 W9960CF Architecture

W9960CF is composed of a high performance RISC processor core (VRISC), function blocks for

video encoding/decoding and a downloadable program memory such that the system can be run-

time configured for a variety of video applications. The figure is a block diagram for W9960CF.

W9960CF

Frame Memory

DMA Controller

DRAM

Controller

DRAM

PCI_BUS

RISC

Video

Decoder

Video Pre/post

Processor

Camera

PCI Memory

DMA Controller

ISDN

Modem

Filter

PCI Bus

Interface

Speaker

DSP

Audio Port

Controller

Mic

Motion

Estimation

Graphics

Adapter

ISA-Like

DCT/IDCT

Q/IQ

Timer/GPIO

Interrupt Controller

VLE/VLD/BCH

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3.2 PCI Interface

W9960CF provides PCI master/slave Interface. In the master mode, it supports fast DMA data

transfer for video/audio bitstream, picture direct draw to graphic display device and VRISC

firmware download. In the slave mode, there are two Base Address Registers for W9960CF

internal registers and external DRAM accessing by the host processor. All data accessing, except

for configuration registers, should be word (2-byte) or double word (4-byte) read/write operations.

PCI Interface

CONF

MASCTL SLACTL

Internal CPU Bus

External PCI Bus

DATAPATH

Internal XDMA Bus

Address \ Bit

00H

31

24

23

16

15

8

7

0

Device ID

Status

Vendor ID

Command

04H

08H

Class Code

Revision ID

Latency Timer

0CH

Reserved

Header Type

10H

Base Address Register 0 (BAR0)

Base Address Register 1 (BAR1)

Reserved

14H

18H - 38H

3CH

Reserved

Interrupt Pin

Interrupt Line

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3.3 VRISC

VRISC contains a 4-staged pipeline: Instruction Fetch (IF), Instruction Decoding (DEC),

Operand Execution (EXE), and Result Write-Back (WB), and a 16-bit ALU with Integer

Multiplication and Division. It uses a built-in 1K-byte Data RAM and a 4.5Kx22 bit Instruction

RAM to which the firmware program can be downloaded from the host processor. This VRISC

contains a tri-port (2-read/1-write) 32x16 bit Register File and 32 interrupt vectors.

RISC Bus

Program

Interrupt

control

Counter

control

int1

int8

Register

File

imm

Instruction

Fetch

mux

src2

IRAM

control

Instruction

RAM

src1

mux

Decoding Inst. Reg.

Decoder

Decoding

Execution

ALU

ALU Result Reg.

mux

Exec. Inst. Reg.

Arbiter

wp

rp

Write

Back

WB Inst. Reg. 1

WB Inst. Reg. 2

Address Spaces

VRISC has two address spaces: the Program Address Space and the Data Memory Address

Space. The following figure illustrates the layout of the booting address, interrupt vector address

space in the main program address space. Program always start from booting address ( 0000H )

after the host enables VRISC. Address 0001H through 001FH stores Interrupt vector for

Interrupt service routines. Figure 2 illustrates the layout of the registers, Data Memory (DM),

external DRAM address space in the main data memory address space. Address 000000H

through 0001FFH is for VRISC Register File referencing, address 000200H through 0003FFH is

for internal DM memory accessing, and address 000400H through 1FFFFFH is for external

DRAM accessing. VRISC cannot access the external DRAM from address 000000H through

0003FFH since this address space are reserved for internal registers and DM memory.

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0000H

11FFH

Booting

0000H

0001H

Program

Address

Space

Interrupt

Vector

Address

Space

22bits

001FH

Program Addressing Space

000000H

Engine

Register

Address

Space

(512)

0001FFH

000200H

0003FFH

000400H

DM

Address

Space

(512)

000000H

Data

Memory

Address

Space

(2M)

1FFFFFH

16bit

DRAM

Address

Space

1FFFFFH

Data Memory Addressing Space

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Addressing Mapping

VRISC has a 5-bit segment register, DMSA. The 21-bit memory address is composed of the 5-

bit content of the DMSA and the content of one of the 32 16-bit general registers as specified in

the Load and Store instruction. The segment register provides a solution to extend the address

space from 64K to 2M bytes. DMSA is a write-only register which can be programmed by the

SEGS imm5 instruction ( see VRISC Instruction Set).

Data Memory Address Mapping

20

16

15

0

DMSA[4:0]

R#[15:0]

General Registers (R0..R31)

VRISC has 32 16-bit general registers to provide the resource for all computation. They are

numbered as R0 through R31. R0 delivers zero when referenced as a source operand. When R0

is used as destination, the result is discarded.

1 6 b its

1 5

0

R 0

R 1

R 2

R 3

R 3 0

R 3 1

Interrupt Handling

Vector

0000h

0001h

0002h

0003h

Name

Engine

Description

main program starting address

ME ready interrupt

MERDY

FRDY

ME

FILTER

DCT/IDCT

FILTER ready interrupt

IDCT ready interrupt

TendINT

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(D)

0004h

RISCINT

DCT/IDCT

(E)

DCT ready interrupt

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

001Ah

001Bh

001Ch

001Dh

001Eh

001Fh

XDMATC

EXTINT

XDMA

XDMA TC interrupt

Ext. Interrupt

VLE

External Interrupt

VLE_INT

DTR_INT

ETR_INT

TOUT0

VLE ready interrupt

TIMER

HOST

DTR time out interrupt

ETR time out interrupt

Timer #0 time out interrupt

Timer #1 time out interrupt

Host interrupt VRISC

TOUT1

PCI_INT

VLRDY_INT

UFRAME_INT

VLDREQ_INT

FDREQ

VLPIO

FILTER

ME

VLD ready interrupt

Unframe or FIFO empty Interrupt

FIFO full or Block error interrupt

DMA TC interrupt for FILTER input

DMA TC interrupt for Search Window

DMA TC interrupt for Current Block

DMA TC interrupt for FILTER output

DMA TC interrupt for DCT input

DREQ_SWIN

DREQ_CBLK

FODREQ

DRQDMAIN

DRQIDCTR_D

DRQDCTR_E

dreqV

ME

FILTER

DCT/IDCT

VPRE

DMA TC int. for IDCT output of Decoding

DMA TC int. for IDCT output of Encoding

DMA TC int. for V block of Capture-in

DMA TC int. for U block of Capture-in

DMA TC int. for Y block of Capture-in

DMA TC int. for Y block of Display-out

DMA TC int. for U block of Display-out

DMA TC int. for V block of Display-out

DMA TC int. for Encoding bitstream

DMA TC int. for Decoding bitstream

DMA TC int. for bitstream from PCI FIFO

dreqU

VPRE

dreqY

VPRE

ydreq

VPOST

VLPIO

udreq

vdreq

DREQ_ENCF

DREQ_DECF

DREQ_IPTF

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W9960CF

VRISC provides 32 vectors on the top of the VRISC program space for jumping to interrupt

service routines. These 32 interrupt jump vectors consist of 15 engine interrupts (0001h~000Fh)

and 16 DMA TC interrupts (0010h~001Fh). The 0000h vector jumps to the main program

starting address. The following example describes the interrupt handling flow:

·

VRISC Start : VRISC Program Counter (PC) always starts from address 0000h after the

host processor enables VRISC. The content of address 0000h should be a JMP

instruction to jump to the entry point of the main program. (path1)

·

Engine Interrupts : When VRISC receives an engine interrupt, Program Counter assumes

the value of the interrupt vector address according to the interrupt happening (path2).

The processor then jumps to the interrupt service routine (path3). When an interrupt is

happening, VRISC disables other interrupt inputs and stores the current fetch address at

IF stage, current instruction at DEC stage, and current status at EXE stage to shadow

registers. They will be restored after VRISC finishes the interrupt service.

·

Interrupt Service Routine : The IVEC (Interrupt Vector) register has to be read out to

generate an acknowledge signal to the interrupting engine. An EI instruction should be

used at the bottom of the service routine to enable other interrupt inputs again. The last

instruction of a service routine is the RET instruction, which restores all status from the

shadow registers and then the VRISC resumes the original program flow (path4).

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RISC start

0000h Jmp main

0001h Jmp Int1

0002h Jmp Int2

path1

path2

001Dh Jmp DMAint13

001Eh Jmp DMAint14

001Fh Jmp DMAint15

main:

path3

Engine

interrupt

N

N+1

Int1:

Int2:

Int1

Service

task

Int2

Service

task

path4

VRISC Shadow Registers

VRISC Shadow Registers are used to store the CPU status when VRISC runs into a Call

instruction or an Interrupt. All registers in this group can only be accessed by VRISC. Host

cannot access registers of this group.

Description

VRISC Address

008H

Name

MPZ0

Read/Write

R/W

R

Execution Status Return Register

Program Counter Return Register

low-order bits of Instruction Return Register

high-order bits of Instruction Return Register

high-order bits of TEMPRES Register

low-order bits of TEMPRES Register

009H

PC0

00AH

IR0_L

00BH

IR0_H

00CH

TEMPRES_H

TEMPRES_L

00DH

R

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3.4 Frame Memory DMA Controller ( FDMA )

There are 16 FDMA channels which are used for direct memory accessing between frame

memory ( DRAM ) and the engines. The transfer type can be either Demand or Block Mode.

Each transfer type can be either Linear or Blocking Addressing. The programmer needs to

specify the picture size with PH/PW register, transfer size with the EH/EW register, the picture

starting point with FMSA register and engine starting address with ESP register.

FDMA generates a TC signal to interrupt VRISC when DMA service is completed. When TC

interrupts VRISC, the DMASK bit is cleared automatically. The FDMA requests are queued

when FDMA is busy. The software FDMA has the highest priority.

FDMA channel assignment is as follows:

Channel DMA request

Engine direction

U

LIN dmd R/W

Description

block in for MC

0

1

FDREQ

Filter

ME

M> E

M > E

E > M

M > E

E > M

M > E

E > M

W

R

DREQ_SWIN

DREQ_CBLK

FODREQ

block in for Search Window of ME

block in for Current Block of ME

block out for BY-pass Filter

block in for DCT

2

ME

3

Filter

4

DRQDMAIN DCT/IDCT

DRQIDCTR_D DCT/IDCT

DRQDCTR_E DCT/IDCT

W

R

5

block out for Decoder Re-Construct

block out for Encoder Re-Construct

Chrom Cr of Video Capture

Chrom Cb of Video Capture

Lum Y of Video Capture

6

R

7

dreqV

dreqU

Video_In

Video_Out

PIO

dmd

R

8

9

dreqY

dmd

R

10

11

12

13

14

15

dreqY

dmd

W

R

Lum Y of Display

dreqU

dmd

Chrom Cb of Display

dreqV

dmd

Chrom Cr of Display

DREQ_ENCF

DREQ_DECF

DREQ_IPTF

LIN dmd

Encoder bitstream out

PIO

Decoder bitstream from FM to VLD

PIO

Incoming decoding bitstream from

PIO input FIFO to FM

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Block Diagram

FW

FH

TCout

Dreq

Queue

DW

DH

DACK

TSR

DMSK

DSR

SDMA

TCMSK

Engine

CPU_Bus

DMA_BUS

3.4.1 BUS ARBITRATION

PCI bridge has the highest priority of bus access, VRISC has second priority and FDMA has the

lowest priority. PCI issues CBR_(CPU Bus Request) to get memory bus when VRISC is working.

Also, VRISC can interrupt FDMA by issuing a MBR_(Memory Bus Request) signal to get access

to memory bus.

C B R _

M B R _ 1

0

R I S C

D M A C

M B G _

C B G _

PCI

P C I _ B u s

3.4.2 FDMA TRANSFER TYPE

The FDMA do Unrestricted Mode when the start point of picture is out of picture boundary.

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BLOCK Addressing

Linear Addressing

ME

Filter

DCT/IDCT

Video_In

Video_Out

PIO

3.4.3 FDMA PROGRAMMING

1. FDMA has two addressing modes: Linear and Block Addressing; and two transfer modes:

Block and Demand Mode transfer.

2. Unrestricted mode is only supported by chanenl0 through channel3. So the PSP (

Picture Start Point ) can be of negative value.

3. Block addressing mode : The following is the relation between DRAM address and Engine

address

DRAM

FMSA = 1000

PICTURE

(0,0)

(9,0)

finit = 1023

1026

ENGINE

ESP(1,1)

PSP(3,2)

1033

1036

EH+1

EW+1

EW=3

1043

1046

(9,9)

PH=9

PW=9

(0,9)

EH=3

1053

1056

DRAM

Picture Engine

DRAM

Picture Engine

Address

Y

X

y

x

Address

1036

1043

1044

1045

1046

1053

1054

Y

X

y x

1023

1024

1025

1026

1033

1034

1035

2

3

4

5

6

3

4

5

1

2

1

3

4

5

6

3

4

5

6

3

4

2

3

4

2

3

2

3

4

1

2

3

1

2

3

4

1

2

1099

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4. Program FDMA control registers.

a. MODE register : LIN=0 ( block addressing ), PP(2:0), Eph(3:0), Epw(3:0), Dmd(0), RW_

b. Transfer size register : EW( EPw(3:0)), EH( Eph(3:0)),

transfer size = ( EW+1) * ( EH + 1 ) = ( 3+1 ) * ( 3+1 ) = 16

c. Picture size register : PW( PP(2:0)), PH( PP(2:0))

d. Frame memory starting address : FMSA = 1000

e. Picture Start Point : PSPy = 2, PSPx = 3,

f. Start to calculate finit=( PSPy * ( PW+1) + PSPx ) + FMSA = ( 2 * ( 9+1 ) + 3 ) + 1000 = 1023

g. Engine start point : ESP = ( 1, 1 )

h. Enable DMASK

5. Linear addressing mode

D R A M

F M S A = 1 0 0 0

E N G IN E

D R A M

a d d r e s s

1 0 1 5

1 0 1 6

1 0 1 7

E n g ine

y

x

0

1

2

3

finit=1015

0

P S P y = 0

P S P x = 1 5

1 0 1 8

.

1 1 1 4

1 1 1 5

0

9 9

0 1 0 0

1 1 1 5

1 0 0

6. Program control registers.

a. MODE register : LIN=1 (linear addressing ), Eph(3:0), Epw(3:0), Dmd(1), RW_

b. Transfer size register : EW( EPw(3:0)), EH( Eph(3:0)),

transfer size = EH x 2**9 + (EW + 1) = 0 x 2* *9 + (100 + 1) = 101

c. Frame memory starting address : FMSA = 1000

d. Picture start point : PSPy = 0, PSPx = 15,

e. Start to calculate finit=(PSPy*( PW+1) + PSPx) + FMSA = ( 0 * ( 9+1 ) + 15 ) + 1000 = 1015

f. Engine start point : ESP = ( 0, 0 )

g. Enable DMASK

7. In demand mode, the DMA service will pause if DMA request becomes inactive, and the

service will continue if DMA request is active again.

8. FDMA still transfers two sets of data after DMA request becomes inactive in demand mode.

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3.4.4 FDMA ADDRESSING REGISTERS

Each channel has 4 addressing registers: Engine Start Point Register, Picture Start Point

Register of X_axis, Picture Start Point Register of Y_axis and Frame Memory Start Address

Register.

PW + 1

DRAM

( 0,0 )

Picture

PH + 1

PSP

FMSA

(PW,PH)

DMA

FMSA+[(PW+1)(PH+1)-1]

Transfer

(0,0)

Engine

ESP

EH+1

EW+1

FDMA Registers List

RISC Address/PCI Offset Address

0040H - 004FH/0100H - 013CH

0050H - 005FH/ 0140H - 017CH

Name

Read/Write

Description

ESP0-15

PSPx0-15

R/W

W

Engine Start Point Register

Picture Start Point of X-axial

Frame initial value-L

R

0060H - 006FH/ 0180H - 01BCH

0070H - 007FH,/ 01C0H - 01FCH

PSPy0-15

FMSA0-15

W

Picture Start Point of Y-axial

Frame initial value-H

R

R/W

Frame Memory Start Address

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RISC Address/PCI Offset Address

0030H/00C0H

Name

DMA_Index

DMSK

Read/Write

R/W

Description

FDMA Index Register

FDMA Mask Register

Software FDMA

0031H/00C4H

R/W

0032H/00C8H

SDMA

R/W

0033H/00CCH

DSTS

R/W

FDMA Status Register

TC Status Register

TC Mask Register

Reserved

0034H/00D0H

DTS

R

0035H/00D4H

TCMSK

R/W

0037H/00DCH

DMA_HW

R/W

Height/Width Register

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3.5 External Memory DMA Controller ( XDMA )

There are 8 channels in XDMA which is used for direct memory accessing between PCI bus and

internal engines. While XDMA has DMA request, PCI interface will enter PCI master mode to

issue master cycles in PCI bus. The DMA transfer type supports both Demand Mode and Block

Mode, each with Linear Addressing or Blocking Addressing. Channel #0 and #1 are used to

transfer the remote and local picture out to system memory or graphic display device directly.

Channel #2 and #3 are used to transfer audio bitstream to external DSP coprocessor. Channel

#4 and #5 are used for video bitstream encoding and decoding. Channel #6 is used for firmware

downloading. Channel #7 is for verifying half-pixel search window memory. Channel #7should

not be activated in normal operation. The programming sequence is like the following:

1. Setting DMA start address : programming XMSA register ( External Memory Start

Address register) with 32-bit access. The address should be double-word (4 bytes)

aligned.

2. Setting DMA transfer mode : each channel has its own transfer mode register. The

register is accessed by two steps: set index value into XDMA Index register and then

write the data value into Height/Width register to set the Mode register (such as

Linear/Block Addressing, Demand/Block Transfer, direction, and size index)

3. Setting DMA transfer size : the transfer size is defined by EH and EW registers. For

Block Addressing Mode, the transfer size is (EW+1)x(EH+1)x4 bytes; for Linear

Addressing Mode, the size is generated by concatenating EH and EW registers, i.e. the

transfer size is ({EH[8:0], EW[10:2]}+1)x4 bytes. XDMA provides 8 sets of EH and EW

registers as indicated by each XDMA channel from the Mode register setting. The

programming method of EH and EW register is the same as in programming Mode

registers.

4. Setting frame size : XDMA , in Block Addressing Mode, refers to frame size of external

memory to generate the block address. XDMA provides 8 sets of PH and PW registers

to define the frame size (PW+1)x(PH+1)x4.

5. Setting XTC Mask register: XTC Mask register indicates XDMA assert TC interrupt or

not.

6. Setting XSDMA or XDMSK register: Host and VRISC can program XSDMA register to

trigger software DMA operation. XDMSK register is for enabling hardware triggered

DMA operations. Hardware engines can issue DMA requests to XDMA to trigger DMA

when the corresponding bits in the XDMASK register are set.

7. Read XDTS register: while DMA operation has been completed and XDMA issues a TC

interrupt to host or VRISC, the interrupt service routine has to read the XDTS register

(TC status of XDMA) to clear the TC flag, so that the XDMA can continue with the next

DMA operation.

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Channel DMA request

Engine

VPOST

Audio

PIO

Direction R/W LIN dmd Description

0

1

2

3

4

5

6

7

XRdrq

E > PCI

PCI > E

E > PCI

PCI > E

E > PCI

R

*

dmd Remote Video out

dmd Local Video out

DRQVPOSTX

XDREQ_RX

XDREQ_TX

XDREQ_OPTF

XDREQ_IPTF

CPU_PM

R

LIN dmd Bit-stream for Audio out

W

R

LIN dmd Bit-stream for Audio in

LIN dmd Video Encoding Bit-stream output

LIN dmd Video Bit-stream for Remote Data in

LIN dmd Firmware download to PM

PIO

W

R

CPU

DACK_HSW

ME

*

Half_pixel Search Window (for Testing)

XDMAC Registers

RISC Address/PCI Offset Address

0090H - 0097H/0240H - 025CH

00A0H - 00A7H/0280H - 029CH

00B0H - 00B7H/ 02C0H - 02DCH

Name

Read/Write

Description

XMIL0-7

XMIH0-7

XMSA0-7

W

External Memory initial value-L

External Memory initial value-H

External Memory Start Address

R/W

RISC Address/PCI Offset Address

0038H/00E0H

Name

Read/Write

R/W

Description

XDMA_Index

XDMSK

XSDMA

XDSTS

XDMA Index Register

XDMA Mask Register

XDMA Software Trigger Register

XDMA Status Register

TC Status of XDMA Register

TC Mask of XDMA Register

(Reserved)

0039H/00E4H

R/W

003AH/00E8H

R/W

003BH/00ECH

R/W

003CH/00F0H

XDTS

R

003DH/00F4H

XTCMSK

R/W

003EH/00F8H

003FH/00FCH

XDMA_HW

R/W

XDMA Height/Width Register

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3.6 DRAM Memory Interface

W9960CF provides a 32-bit DRAM data bus for DMA data transfer and VRISC access. It

supports the control timing for Fast Page Mode or EDO DRAMs. The DRAM address space has

three types of configurations: 1M, 2M, and 4M bytes. For 1M and 2M-byte space, the DRAM

devices must be two or four 256Kx16 DRAM devices. For 4M-byte space, it must be two 1Mx16.

1ST MBYTE

MD[15:0]

2ND MBYTE

MD[15:0]

MD[31:0]

MA[8:0]

MD[31:16]

256Kx16

A[8:0]

RAS#

CAS#

OE#

D[15:0]

A[8:0]

RAS#

CAS#

OE#

D[15:0]

A[8:0]

RAS#

CAS#

OE#

D[15:0]

A[8:0]

RAS#

CAS#

OE#

D[15:0]

W9960CF

WE#

RAS0#

CAS0#

OE0#

WE0#

WE1#

RAS1#

CAS1#

OE1#

4 MBYTE

MD[31:0]

MA[9:0]

MD[15:0]

MD[31:16]

D[15:0]

1Mx16

A[9:0]

RAS#

CAS#

OE#

D[15:0]

A[9:0]

RAS#

CAS#

OE#

W9960CF

WE#

RAS0#

CAS0#

OE0#

WE0#

WE1#

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Timing

Normal Case

CLK

MCS#

RAS#

CAS#

Row Addr.

R

Column Column Column Column

ADD[9:0]

C

C+1

C+2

C+3

Write to DRAM

WE#

MD[31:0]

Data

C

Data

C+1

Data

C+2

Data

C+3

mrdy_

edowr_

Read from DRAM

OE#

mrdy_

(Fast mode)

edowr_

MD[31:0]

Data

C

Data

C+1

Data

C+2

Data

C+3

(EDO mode)

edowr_

MD[31:0]

Data

C

Data

C+1

Data

C+2

Data

C+3

At E6F4 Mode (EDO-60, 40MHz )

CLK

MCS#

RAS#

CAS#

Row Addr.

R

Column Column

Column

C+2

Column

C+3

ADD[9:0]

C

C+1

Write to DRAM

WE#

MD[31:0]

Data

C

Data

C+1

Data

C+2

Data

C+3

mrdy_

edowr_

Read from DRAM

OE#

MD[31:0]

Data

C

Data

C+1

Data

C+2

Data

C+3

mrdy_

edowr_

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3.7 INTERRUPT/TRIGGER Controller

This controller provides 10 different Interrupts to VRISC and 5 triggering signals for VRISC to

trigger engines.

Trigger #0 is used for Video Capture triggering. Trigger #1 is used to start ME motion estimation

search. Trigger #2 is used to start FILTER block operation. Trigger #3 is used to trigger IDCT to

start decoding inverse discrete cosine transform operation. Trigger #4 is used to trigger DCT to

start encoding forward discrete cosine transform.

Interrupt #5 is XDMA Terminal Count Interrupt. Interrupt #6 is the interrupt coming from ISA-like

external interface. Interrupt #7 indicates the VLE FIFO full while T-coeff. encoding. Interrupt #8

and #9 are TIMER TR (Temporal Reference) Interrupts for decoding and encoding. Interrupt #10

and #11 are the TIMER time out interrupts. Interrupt #12 is used for host to interrupt VRISC.

Interrupt #13 indicates VLD operation is completed after VLD command register is triggered.

Interrupt #14 indicates the PIO BCH code is not aligned with frame. Interrupt #15 indicates a

Run-Level Block Error in VLD decoding.

All interrupts can be enabled or disabled as specified by the mask bits of the IMSK register. It will

response which channel is active on ISR register and generate an INT to VRISC. When VRISC

enters an interrupt service routine, it has to read out the IVEC register to have Interrupt

Controller assert INTA to clear interrupt status.

Signal Type

INTG_IN

INTG_OUT

Capture_Trigger

METG

ENGINE

VideoPre

ME

Description

0

TRIG

INTR

Video Capture trigger

Trigger Motion Estimation

Trigger Filter

1

MERDY

FRDY

2

3

F_TRIGGER

TriggerDEC

TriggerENC

FILTER

DCT/IDCT

XDMA

TendINT

RISCINT

int1

Trigger IDCT

4

Trigger DCT

5

XDMA TC Interrupt

ISA External Interrupt

VLE FIFO Full Interrupt

Temp. Ref. Interrupt (Decoder)

Temp. Ref. Interrupt (Encoder)

Timer 0 interrupt

6

extint

ISA-Like

VLETCO

TIMER

HOST

7

VLE_INT

DTR_INT

ETR_INT

TOUT0

TOUT1

PCI_INT

8

9

10

11

12

13

14

15

Timer 1 interrupt

Host interrupt RISC

VLD is over

INTR VLRDY_INT

TG_INTA

PIO

INTR UFRAME_INT UFRAME_INTA

INTR VLDREQ_INT VLDREQ_INTA

PIO

Frame Un-lock Interrupt

VLD Run Level Block Error

VLD

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Block Diagram

Irdy

ISR

IVEC

IMSK

Queue

INT

CPU_Bus

ITrig

TMODE STG

INTG Registers

RISC Address/PCI Offset Address

0019H/0064H

Name

IMSK

ISR

Read/Write

Description

R/W

R

Interrupt Mask Register

Interrupt Status Register

Interrupt Vector Register

Trigger Mode Register

Software Trigger Register

001AH/0068H

001BH/006CH

IVEC

TMOD

STG

R/W

W

001CH/0070H

001DH/0074H

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3.8 X_INTERRUPT Controller ( XINTC )

XINTC provides 16 channels interrupt trigger source and generates INTA# to PCI_BUS.

Channel #0~#7 are used for XDMA requests. Channel #8~#11 are reserved for VRISC to issue

interrupts to host. Channel #12 is for the ISA-like external Interrupt. Channel#13~#14 are the TC

interrupts for XDMA and FDMA. Channel#15 is the interrupt from INTC controller. All channels

are maskable by XMSK register. Host has to read the XSTS register to identify interrupt source

when receiving a W9960CF issued interrupt. Host issues interrupt to VRISC by programming

PCI_INT register, which will generate a interrupt trigger pulse for VRISC to enter interrupt service

routine.

Channel

XINT_IN

xdreq0

xdreq1

xdreq2

xdreq3

xdreq4

xdreq5

xdreq6

xdreq7

1

Description

0

1

dreq of XDMAC

2

3

4

5

6

7

8

(Reserved for VRISC)

ISA External Interrupt

tc of XDMAC

9

1

10

11

12

13

14

15

1

extint

int1

tc_out

int

tc of FDMAC

INT of INTG

XINTC Registers

RISC Address/PCI Offset Address

0006H/0018H

Name

XMSK

Read/Write

Description

R/W

R

X_Interrupt Mask Register

X_Status Register

0007H/001CH

XSTS

PCI_INT

W

PCI_INT Command

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3.9 GPIO ( General Purpose Input/Ouput) Port

W9960CF provides 4 pins as a GPIO port. These four pins are programmable to be input or

output. GPIO0 and GPIO1 are two open drain IO pads and pull-high resistors are necessary in

application circuits. GPIO2 and GPIO3 are tri-state IO pads. GPIO port is used to connect to

external devices such as analog video decoder and/or audio coprocessor.

wr_(CPU Bus)

rd_(CPU Bus)

Hi-Z

GPIO[3:2]

GPIO[1:0]

1

0

1

0

Hi-Z

3.10 TIMER

W9960CF provides a programmable pre-scale counter (PSR register) for different Video Clock

input and three period registers (TP0~TP2) for period setting of the temporal reference, time

counter and DRAM reference. W9960 also provides two TR reference counters for decoding and

encoding (DTR and ETR registers). Here is the programming example:

if the video clock (CLK_Video pin) is 13.5MHz, set:

RC2~RC0 to 010b,

P3~P0 to 0011b

TP0= 6DF8h (29.97016frame/sec), 83D5h (25.00 frame/sec),

TP2=000Dh;

If the Video clock is 27MHz, set:

RC2~RC0= 010b,

P3~P0=0100b,

TP0= 6DF8h (29.97016frame/sec), 83D5h (25.00 frame/sec),

TP2=000Dh.

The frequency calculation statement is as:

Fre. = VCLK / ( (2**⁽^N+1))*(TP+1) )

where VCLK is input frequency of CLK_Video pin, N is the value of RC[2:0], and TP is the

period setting of TP0, TP1, or TP2.

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Block Diagram

TIMER

Video

Clock

Pre-Scaler

Counter

(8 stages)

Counter

(8 stages)

TRV Counter

(8 stages)

16

(/2 ~ /2 )

TP

TER

register

8

register

8

16

Comparetor

TOUT Interrupt

8

Comparetor

TR_INT

TIMER Registers

RISC Address / PCI Offset Address Name Read/Write

010H / 040H

011H / 044H

012H / 048H

013H / 04CH

014H / 050H

015H / 054H

016H / 058H

017H / 05CH

PSR

TR0

TR1

DTR

TP0

TP1

TP2

ETR

R/W

R

Pre-Scale Register

Timer Register #0

Timer Register #1

R

R/W

Temporal Reference of Decode Register

Timer Period Register #0

Timer Period Register #1

Timer Period Register #2

Temporal Reference of Encode Register

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3.11 Video Pre/Post Processing Engine

The functions of Video Preprocessing engine are capturing, cropping, zooming video in 4CIF,

CIF, QCIF, Sub-QCIF resolution. Actually, user can command this engine to capture image of

any size within 704 x 576(PAL) or 704x480(NTSC). Video Preprocessing Engine also provides

two programmable decimation horizontal filters for luminance data and chrominance data to

smooth the captured image.

Video Postprocessing Engine supports both RGB 5:6:5 and YUV 4:2:2 for both local and remote

video output. RGB format is for normal VGA card without color space conversion. YUV format is

for those video cards with color space conversion and scaling support.

3.11.1 VIDEO PREPROCESSOR (VPRE)

The Video PreProcessor (VPRE) transfers the captured video data to frame buffer DRAM

through horizontal filters, horizontal subsampler and FIFO for DMA data transfer. The size of the

Y FIFO is 44x4 bytes. U FIFO and V FIFO is 22x4 bytes each. The block diagram is shown

below:

D_Bus

HA

HD

VA

VD

Video

Interface

FIFO

44x32bits

Y

U

V

HS

VS

22x32bits

Image

Grabber

YUV

422

v

YUV422

signal

from

VD(15:0)

VCLK

1/2H

420

Video Decoder

ScaleH

( 1, 1/2, 1/4 )

FIFO Control

Bt/Ph_

taps filter

Even

/OddScaleV

(1, 1/2, 1/5 )

Full

( 1, 3/4, 2/4, 1/4 )

Cap_trig

Video PreProcess Diagram

The following is the register parameters used to configure for different formats:

NTSC/ HA

PAL

VA

E

O

Scale

H

Scale

1/5

O

Picture Size

( H x V )

Format

Description

V

1

NTSC 704 240

704 240

on

off

on

1

off

on

off

on

off

704

352

176

704

480

288

144

576

4CIF

CIF

1/2

1

4CIF ZO to CIF

CIF ZI fr 4CIF ,P

QCIF ZI fr 4CIF, P

4CIF ZO to QCIF

352 240

1

CIF

352 144

1/2

1/4

1

QCIF

4CIF

704 240

1/2

1

PAL

704 288

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704 288

352 288

352 144

704 288

on

off

on

off

1/2

1

off

352

176

288

144

CIF

1/2

1

1/2

1/4

QCIF

1/2

3.11.2 VIDEO POSTPROCESSOR (VPOST)

VPOST provides an option of 1/2 scaling-down for both local and remote picture. It also supports

color space conversion for either YUV422 or RGB565 video output. VPOST provides FIFO for

DMA data transfer. The size of Y FIFO is 16x4bytes. U FIFO and V FIFO is 8x4 bytes each.

D_Bus

rgb

deci2

X_Bus

16x4bytes

BUFFER

Y

U

V

deci2y

deci2u

deci2v

Colour

Space

8x4bytes

Vout

PACK

Convert

YUV422 -> RGB565

8x4bytes

Trig

Video PostProcessor Diagram

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W9960CF

VIDEO Register

RISC Address/PCI Offset Address

01A0H/0680H

Name

VPRE Mode

HDelay

VDelay

HA

Read/Write

R/W

Description

Video Preprocessing operation mode

Horizontal delay pixel number

Vertical delay line number

01A1H/0684H

R/W

01A2H/0688H

R/W

01A3H/068CH

R/W

Horizontal active pixel number

Vertical active line number

01A4H/0690H

VA

R/W

015AH/0694H

LFP

R/W

Luminance filter parameters, Tap1 and

Tap2

01A6H/0698H

01A7H/069CH

CFP

R/W

Chrominance filter parameters, Tap1

and Tap2.Luminance decimation filter

parameter Tap3.

VPOST Mode

VideoPostprocessor operation mode

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W9960CF

3.12 Motion Estimation Engine

W9960CF motion estimation (ME) engine implements full search matching algorithm (FSA),

which is widely used thanks to its simplicity and regularity. In this algorithm, for each reference

block in the current frame, the previous frame is searched within a neighborhood, i.e. search

window, to find the most matched pixel block.

CPU-bus

DMA-data

DMA-addr

half-pixel

1.5

Search

window

Current

block

Search

Caddr

Saddr

Window

DMA-request

CONTROL

LOGIC

DMA-ack

Mode

SREGION

Half-Pixel

INT-request

Trigger

Half-Pixel

Accelerator

p'

ph

ph'

p

c

MV

MAD,MA,MB,MX

8*PE

Comparator

ME Registers

RISC Address/PCI Offset Address

0190H / 0640H

Name

Read/Write Description

MEMODE

MVR

R/W

Mode Register

0191H / 0644H

Motion Vector Register

0192H / 0648H

MADR

MBR

Mean Absolute Difference Register

Mean Current Macro Block Register

Mean Average Difference Register

Mean First Search Register

Search Region Register

0193H / 064CH

0194H / 0650H

MAR

0195H / 0654H

MXR

0196H / 0658H

SRGION

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W9960CF

3.13 FILTER Engine

Filter Engine implements the loop filter function of H.261. It is a two-dimensional spatial filter as

shown below. The Filter Engine also performs the interpolation function of half pixel prediction

and PB frame prediction in H.263.

H.261 8x8 predicted Block with 1-2-1 Filter

0

1

2

3

4

5

6

7

1 2 1

2 4 2

1 2 1

8

9

10

18

26

34

42

50

58

11

19

27

35

43

51

59

12

20

28

36

44

52

60

13

21

29

37

45

53

61

14

22

30

38

46

54

62

15

23

31

39

47

55

63

(1) 1/16

for pixels inside the block

16

24

32

40

48

56

17

25

33

41

49

57

(2) 1/16 | 4 8 4 | for pixels on the block edge

(3) 1/16 | 16 | for pixels on the block corner positions

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W9960CF

H.261 1-2-1 Filter Table

1

2

1

2

1

2

1

2

1

2

1

2

1

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

2 4 2

1 2 1

1

2

1

2

1

2

1

2

1

2

1

2

1

Block Diagram

The prediction picture is transferred into Filter Engine by DMA operation. Half Pixel

PreProcessor module performs the half pixel interpolation in x-axial direction. HPP module

performs the half pixel interpolation in y-axial direction. OMC module performs PB frame

prediction. The control flow is specified in FCR0 (Filter Control Register #0) and BRR (Bi-

direction Range Register) registers.

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W9960CF

Input from DRAM Controller

MUX

Half Pixel

PreProcessor

8

1

8

2

8

0

8

9

dmablk

MUX

F/F

MUX

F/F

0,1/4, 2/4

F/F

0,1,2/8,4/8

4/8,8/8,4/8,8/8

CSA

0,1,2/8

0,2/4,4/4

F/F

0,1/4

ADDER

F/F

CSA

OMC

ADDER

HPP

F/F

8

dctblk

To DCT/IDCT Engine

or DRAM Controller

Filter Registers

RISC Address / PCI Offset Address

018CH / 0630H

Name Read/Write

FCR0

FCR1

BRR

R/W

Filter Control Register #0

Filter Control Register #1

Bi-direction Range Register

018DH / 0634H

018EH / 0638H

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W9960CF

3.14 FIDCT/Q/IQ Engine

W9960CF contains Forward/Inverse Discrete Cosine Transform Engine (FIDCT) and

Quantization /Inverse Quantization Engine, which are frequently used in video

compression/decompression.

For video encoding, DCT is used to reduce spatial redundancy of images. The quantization logic

further filters most AC values and keeps the DC value.

In video decoding, each 8x8 block is transformed back by Inverse Quantization. This IQ process

induces quantization error in AC values compared with original data, but the DC value is

recovered losslessly. Thereafter, data is sent to Inverse Discrete Cosine Transform stage to do

image recovery process. In the INTRA mode, the result is final reconstructed image. While in

the INTER mode, the result has to be added with the previous block data to reconstruct the

image.

Block Diagram

From Filter

RE-Construct

BUFFER

Current Block

ADD

BUFFER

IDCT

ADD

DCT

Q

Quant

Table

IQ

Zig/Zag

From VLD

BUFFER

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W9960CF

DCT/IDCT Register

RISC address/PCI Offset Address

0180H/0600H

Name

Read/Write Description

Q_Control

R/W

Quantization value selection

CBP threshold value

0182H/0608H

CBP threshold

CheckSum

0183H/060CH

DCT result checksum

0184H/0610H

EQuant value

DQuant value

EBD Quant value

DBD Quant value

CODEC

Encoding loop Quant value

Decoding loop Quant value

Encoding loop BQ/DQ value

Decoding loop BQ/DQ value

Intra/inter mode, coding/decoding

0185H/0614H

0186H/0618H

0187H/061CH

0188H/0620H

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W9960CF

3.15 Programmable Input/Output Engine

Programmable input/output (PIO) engine can control the input bit stream data from X_bus or

CPU_data_bus to the variable length decoder (VLD). PIO plays the role of interface between the

frame memory (FM) and X_bus during bitstream receiving for decoding and bitstream

transmission after encoding.

Block Diagram

X_BUS

CPU

FM-R

FM-T

BUS

DREQ

ENCF

XDREQ_IPTF

DREQ

DECF

1

ENCODE

FIFO

CR1

VLD

CR3

DECODER

FIFO

1

INPUT

DATA

FIFO

1

CT1

BCH

DECODE

1

CR2

FIFO

BCH

DECODER

P>S

S>P

BCH

ENCODER

P<S

1

S<P

CT2

OUTPUT

DATA

FIFO

XDREQ_OPTF

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W9960CF

PIO Registers

RISC Address/PCI Offset Address

01A8H / 06A0H

Name

CDFIFO_H

CDFIFO_L

PIOCTL

XDMAR

FDMAR

FC

Read/Write Description

R/W

Compressed Data FIFO High Word Register

Compressed Data FIFO Low Word Register

01A9H / 06A4H

01AAH / 06A8H

PIO Control Register

01ABH / 06ACH

X_Bus DMA Request Enable Register

Frame Memory DMA Request Enable Register

Frame Code Register

01ACH / 06B0H

01ADH / 06B4H

01AEH / 06B8H

LPD

Lock Position Detect Register

Input/Output FIFO Status Register

01AFH / 06BCH

IOFSR

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W9960CF

3.16 Variable Length Code Decoder

The Variable Length (VL) Engine uses the code books or lookup tables to map the Huffman code

words. Huffman coding is a kind of entropy coding method used in H26X. Image or video data

size can be reduced significantly when proper Huffman tables are used. Not only the variable

length codes but also the fixed length codes can be decoded in this engine. Bit streams coming

from the programmable in/out port (PIO) are fed into VL engine during decoding process.

VLD Register

RISC Address / PCI Offset Address

01B8H / 06E0H

Name

MCR_L

MCR_H

MSR

Read/Write Description

R/W

R

Match Code Low Word Register

01B9H / 06E4H

Match Code High Word Register

Match Size Register

01BAH / 06E8H

01BBH / 06ECH

VLCMD

VLRES

VL Command Register

VL Result Register

01BCH / 06F0H

01BDH / 06F4H

VLRES_LW

R

VL Result Low Word Register

RISC Address / PCI Offset Address

01C0H / 0700H

Name

Read/Write Description

VLDTC0

R/W

.......

R/W

VLD TCoefficient Register 0

................

..................

VLDTC63

...................................................

VLD Tcoefficient Register 63

01FFH / 07FCH

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W9960CF

3.17 Audio Coprocessor Interface

W9960CF provides an ADSP-21xx SPORT compatible serial port to interface to audio

coprocessors. Multi-channel mode in AD SPORT0 is provided for interfacing with other chips

time-division multiplexing (TDM) function. Transmitter FIFO and Receiver FIFO are used since

serial one-bit bit stream is packed into 32-bit word, and no CPU instructions to access Tx or Rx

registers. This T/R FIFO should access with frame memory via 32-bit X_bus. No compounding

function is provided with, since no management for u-law or A-law data format.

Block Diagram

X_BUS

32

Tx

Rx

16

Transmit

Shift Reg

Serial

Control

Receive

Shift Reg

ISCLK

DT

TFS

DR

RFS

SCLK

AUDIO PORT Register

RISC Address / PCI Offset Address

0198H / 0660H

Name

ACTL

Read/Write Description

R/W

Audio Port Control Register

0199H / 0664H

SCLKDIV

RFSDIV

RWE_L

RWE_H

TWE_L

TWE_H

Serial Clock Divisor Register

019AH / 0668H

Receive Frame Sync Divisor Register

Receive Word Enables for Low Word Register

Receive Word Enables for High Word Register

Transmit Word Enables for Low Word Register

019BH / 066CH

019CH / 0670H

019DH / 0674H

019EH / 0678H

Transmit Word Enables for High Word

Register

019FH / 067CH

TRBDR

R

Transmit/Receive Buffer Detect Register

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W9960CF

3.18 Variable Length Code Encoding (VLE) Engine

There are two modules in VLE Engine, one is for Tcoeff (Transform coefficient) encoding and the

other is for variable length encoding. The Tcoeff is based on the run level pair generated from

the result of DCT/Quantization and pushed into the 16x32-bit Tcoeff_FIFO. When DCT/Q is

completed, VRISC shall check some conditions such as checksum register and determine

whether to trigger RLC ( Run Level Code ) to generate transform coefficient. When all blocks is

encoded into Tcoeff_FIFO, VRISC shall read Bit Length Register to check how many bits are

generated (overflow condition if Bit Length Register is over 512, busy condition if Bit Length

Register is Zero). Then VRISC read out the Tcoeff value from Tcoeff Result Register. VLE_INT

will assert when the coding bit length is over the threshold of Tcoff_FIFO. VRISC can also write a

command including data and table-indicator into Command Register to generate variable length

code ( except Tcoeff ).

Block Diagram

H261/H263/MPEG/JPEG

DCT_Trig

VLE Command Register

DCT/QUANT

DCT_rdy

INTRA/

INTER

RLC

RLC_Trig

VLC Table

Tcoeff-VLE

( Tcoeff FIFO overflow )

VLE_INT

16 x 32bit

FIFO

VLE Result Register

Bit Length Register

Tcoeff Result Register

VLE Register

RISC Address/PCI Offset Address

01B4H / 06D0H

Name

BLR

Read/Write Description

R

Bit Length Register

01B5H / 06D4H

TRR

VRR

VCR

Tcoeff Result Register

VLE Result Register

01B6H / 06D8H

R

01B7H / 06DCH

W

VLE Command Register

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W9960CF

3.19 ISA-like Interface

The ISA-like Interface implements a parallel I/O port to connect to co-processors, and a Boot-

ROM mechanism to download VRISC firmware automatically.

This ISA-like parallel I/O port provides an 8-bit data bus and 16-bit address bus to connect to co-

processor easily. The host can access the connected co-processor through W9960CF PCI

interface and this ISA-like interface. In this sense, W9960CF acts as a PCI to ISA bridge. It also

provides two external interrupt requests of level or edge trigger.

This ISA-like Interface provides another path to download VRISC firmware in addition to the PCI-

bus interface. In Boot-ROM mode, the ISA-like interface will issue Boot-ROM access cycle to

download firmware after W9960CF is reset.

W 9960CF

RISC

Co-Processor

P C I

Interface

ISA-Like

Interface

P C I Bus

Internal Bus

R O M

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W9960CF

ISA-Like Interface Resigisters

RISC Address/PCI Offset Address Name

Read/Write Description

Setting ISA control operation register

Setting ISA output address register

020H/080H

021H/084H

022H/088H

023H/08CH

ISACTL

SAADDR

SADATA

ISAINT

R/W

ISA input/output data register

External interrupt control/status register

Programming Sequence

W9960CF assert I/O read/write cycles on ISA-like interface accroding to the following

programming sequence.

IO Write Cycle

IO Read Cycle

Store ISACTL register

(set WE bit enable)

Store ISACTL register

(set RE bit enable)

Store ISAADDR register

(set effective address)

Store ISAADDR register

(set effective address)

Store ISADATA register

(set effective data)

Insert Delay

(7-14 clock cycles)

Load ISADATA register

(read effective data)

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W9960CF

4. W9960CF REGISTERS

4.1 PCI Configuration Registers

Address \ Bit

00H

31

24

Device ID

Status

23

16

15

8

7

0

Vendor ID

Command

04H

08H

Class Code

Revision ID

0CH

Reserved

Header Type

Latency Timer

10H

Base Address Register 0 (BAR0)

Base Address Register 1 (BAR1)

Reserved

14H

18H - 38H

3CH

Reserved

Interrupt Pin

Interrupt Line

Device/Vendor ID Register

Read-only

PCI Configuration Address: 00H

Default: 9960 1050H

31

30

29

28

12

27

11

26

10

25

9

24

8

23

7

22

6

21

5

20

4

19

3

18

2

17

1

16

0

Device ID

15

14

13

Vendor ID

Bits 31-16 Device ID

Device ID allocated for the W9960 is 9960H.

Bits 15-0 Vendor ID

Vendor ID is allocated by the PCI SIG to ensure uniqueness. The value assigned to

Winbond Electronic Corp. is 1050H.

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W9960CF

Status/Command Register

Read/Write

PCI Configuration Address: 04H

Default: 0280 0000H

31

30

29

28

27

26

25

24

23

22

21

20

4

19

3

18

2

17

1

16

DPE SSE RMA RTA STA DEVSEL

MDP FBC Reserved

CLK

15

14

13

12

11

10

9

8

7

6

5

0

Reserved

FBE SEE

-

PEE Reserved

BME MSE -

Bit 31

DPE ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Detected Parity Error

1 = Parity Error

0 = Parity Correct

Bit 30

Bit 29

Bit 28

Bit 27

SSE ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Signaled System Error

1 = System Error

0 = System Correct

RMA ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Received Master Abort

1 = Master Abort On

0 = Off

RTA ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Received Target Abort

1 = Target Abort On

0 = Off

STA ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Signaled Target Abort

1 = Target Abort On

0 = Off

Bits 26-25 DEVSEL Timing ( Read only )

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W9960CF

01 = Medium DEVSEL# timing

Bit 24

Bit 23

MDP ( this bit will be clear to 0 , if the write data in the corresponding bit location is a 1 )

Master Data Parity Error Detected

1 = Detect Parity Error

0 = Parity Correct

FBC

Fast Back-to-Back Capable ( Read only )

1 = Support Fast Back-to-Back Capable

Bits 22-17 Reserved

Bit 16

CLK

PCI CLK Support ( Read only )

0 = 33Mhz

Bits 15-10 Reserved

Bit 9

FBE

Fast Back-to-Back Enable

1 = Enable

0 = Disable

SERR# Enable

1 = Enable

Bit 8

0 = Disable

Reserved

Bit 7

Bit 6

PEE

Parity Error Response Enable

1 = Enable

0 = Disable

Bits 5-3

Bit 2

Reserved

BME : Bus Master Enable

1 = Enable

0 = Disable

MSE

Bit 1

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W9960CF

Memory Space Enable

1 = Enable the device response to memory space accesses

0 = Disable the device response to memory space accesses

Reserved

Bit 0

Class Code/Revision ID Register

Read-only

PCI Configuration Address: 08H

Default: 0400 0000H

31

30

29

28

12

27

11

26

10

25

9

24

8

23

22

21

20

4

19

3

18

2

17

1

16

0

Base Class Code

Sub-Class Code

15

14

13

7

6

5

Programming Interface

Revision ID

Bits 31-24 Base Class Code

Bits 23-16 Sub-Class Code

Bits 15-8 Programming Interface

Bits 7-0

Revision ID

Bits 31-8 are hardwired to 040000H to specify that the W9960 is a multimedia device.

Header Type / Latency Timer Register

Read-Write

PCI Configuration Address: 0CH

Default: 0000 FF00H

31

30

29

13

28

12

27

11

26

10

25

9

24

8

23

22

21

5

20

4

19

3

18

2

17

1

16

0

Reserved

Header Type

15

14

7

6

Latency Timer

Reserved

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W9960CF

Bits 31-24 Reserved

Bits 23-16 Header Type ( Read only )

00H = Type 00H

Bits 15-8 Latency Timer for Master

the low-order 3 bits are read only, high-order 5 bits are read-writable

Reserved

Bits 7-0

Base Address 0 Register

Read/Write

PCI Configuration Address: 10H

Default: 0000 0000H

31

30

29

28

12

27

11

26

10

25

9

24

8

23

7

22

6

21

5

20

4

19

3

18

2

17

1

16

0

Base Address 0

15

14

13

Base Address 0

Bits 31-0 Base Address 0

This field can be used to relocate memory address space to any location that is aligned to

4 Kbytes for mapping W9960 Engine Registers and Data Memory.

The low-order 12bits are read only and hardwired to 000H, the high-order 20bits are read-

writable.

Base Address 1 Register

Read/Write PCI Configuration Address: 14H

Default: 0000 0000H

31 30 29

Base Address 1

28

12

27

11

26

10

25

9

24

8

23

22

6

21

5

20

4

19

3

18

2

17

1

16

0

15

14

13

7

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W9960CF

Base Address 1

Bits 31-0 Base Address 1

This field can be used to relocate memory address space to any location that is aligned to

4 Mbytes for mapping W9960 DRAM Frame Memory. The low-order 22bits are read only

and hardwired to 0_0000H, the high-order 10bits are read-writable.

Interrupt Line Register

Read/Write

PCI Configuration Address: 3CH

Default: 00H

7

6

5

4

3

2

1

0

Interrupt Line

Bits 7-0

Interrupt Line

This 8-bit register is used to communicate interrupt line routing information. POST software

will write the routing information into this register as it initializes and configures the system.

Interrupt Pin Register

Read-only

PCI Configuration Address: 3DH

Default: 01H

7

6

5

4

3

2

1

0

Interrupt Pin

Bits 7-0

Interrupt Line (hardwired to 01H)

This register is hardwired to 1 to specify that INTA# is the interrupt pin used.

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W9960CF

5. ELECTRICAL SPECIFICATIONS

5.1 Absolute Maximum Ratings

Ambient temperature

0^oC to 70^oC

Storage temperature

-40^oC to 125^oC

DC supply voltage

-0.5V to 5V

I/O pin voltage with respect to Vss

-0.5V to VDD+0.5V

5.2 DC Specifications

(V_DD= 3.0V to 3.6V, V_SS= 0V, V_DD5V= 5V, TA=0^oC to 70^oC)

Symbol

V_IL

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

Output Tri-state Current

Input Capacitance

Output Capacitance

Power Supply Current

Min Typ

Max

Unit

V

Conditions

0.8

V_IH

2.0

V

V_OL

V_OH

I_IL

Vss+0.4

V

I_OL=10mA

I_OH=6mA

2.4

V

±10

mA

pF

mA

I_IH

I_OZ

C_IN

10

50

C_OUT

I_CC

400

5.3 AC Specifications

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W9960CF

5.3.1 CLOCK SPECIFICATION

t

cyc

3.3 Volt Clock

t

high

0.6VDD

0.5VDD

0.4VDD

0.3VDD

t

low

0.2VDD

Symbol

t_cyc

Parameter

Min

30

11

1

Max

Units

ns

CLK Cycle Time

CLK High Time

CLK Low Time

CLK Slew Rate

¥

ns

t_high

ns

t_low

4

V/ns

5.3.2 RESET TIMING

t

Lo

w

RST

#

Symbol

Parameter

Min

Max

Unit

ns

System reset active pulse width

t_Low

10 t_cyc

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W9960CF

5.3.3 PCI INTERFACE AC TIMING

0.6VDD

0.2VDD

0.4VDD

CLK

t

val

OUTPUT

DELAY

0.285VDD (rising edge)

0.615VDD (falling edge)

Tri_State

OUTPUT

t

on

t

off

CLK

0.4VDD

t

h

su

0.6VDD

0.2VDD

INPUT

inputs

valid

0.4VDD

Symbol

t_val

Parameter

Min Max Units

Notes

1

CLK to Signal Valid Delay - bused signals

CLK to Signal Valid Delay - point to point

Float to Active Delay

2

11

12

ns

2

t_val(ptp)

t_on

1,4

1,3

2

Active to Float Delay

28

t_off

Input Set Up Time to CLK - bused signals

Input Set Up Time to CLK - point to point

Input Hold Time from CLK

7

10

0

t_su

t_su(ptp)

t_h

1,2,3

Note 1: bused signals : AD31-AD0, C/BE3-C/BE0, PAR, FRAME#, TRDY#, IRDY#, STOP#,

DEVSEL#, PERR#,

Note 2: point to point signals : REQ# is output signal, GNT# is input signal

Note 3: Input Signal : IDSEL

Note 4 : Output Signal : INTA#, SERR#

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5.3.4 AUDIO INTERFACE AC TIMING

t

sck

SCLK

0.4VDD

t

sch

scs

DR

RFS (in)

0.6VDD

inputs

valid

TFS (in)

0.2VDD

0.4VDD

t

fsd

RFS (out)

TFS (out)

0.285VDD (rising edge)

0.615VDD (falling edge)

t

scdv

DT

t

tdv

TFS (in)

Symbol

t_sck

t_scs

Parameter

Min

100

10

Max

Unit

ns

SCLK Period

-

DR/TFS/RFS Setup Time

Ref. to SCLK falling

ns

DR/TFS/RFS Hold Time

Ref. to SCLK falling

10

-

ns

t_sch

TFS/RFS Valid Delay from SCLK rising

DT Valid Delay from SCLK rising

DT Valid Delay from TFS

-

25

20

ns

t_fsd

t_scdv

t_tdv

(Alternate Frame Mode)

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5.3.5 DRAM INTERFACE AC TIMING

CLK_MEM

t

rv1

t

rv2

RAS0#,RAS1#

CAS0#,CAS1#

t

cv2

cv1

t

av

MA7-MA0

Row Addr

Column Addr

t

wv

dv

WE1#,WE0#

MD31-MD0

(output)

Data

t

ov

OE1#,OE0#

t

dsu

Data

dh

MD31-MD0

(input)

Data

Symbol

Parameter

Min

Max

14

12

16

20

14

20

12

Unit

ns

RAS# valid delay ref. to CLK_MEM rising

RAS# valid delay ref. to CLK_MEM falling

CAS# valid delay ref. to CLK_MEM falling

CAS# valid delay ref. to CLK_MEM rising

Memory address valid delay

t_rv1

t_rv2

t_cv1

t_cv2

t_av

Memory WE# valid delay

t_wv

t_dv

Memory Data valid delay

Memory OE# valid delay

t_ov

Memory Data setup time

12

2

t_dsu

t_dh

Memory Data hold time

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W9960CF

5.3.6 GPIO AC TIMING

CLK_MEM

t

AC

GPIO3-GPIO0

(Output)

t

SETUP

t

HOLD

GPIO3-GPIO0

(Input)

Symbol

t_AC

Parameter

Min

Max

Unit

GPIO output access

time

15

ns

GPIO input set up time

GPIO input hold time

10

5

ns

t_SETUP

t_HOLD

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W9960CF

5.3.7 VIDEO PREPROCESSOR AC TIMING

t

LLC

t

LLCL

CLK_Video

t

HOLD

t

LLCH

t

SETUP

HREF, VS, HS, VD[15:0]

Symbol

t_LLC

Parameter

CLK_Video period

CLK_Video Low width

CLK_Video High width

Input Set Up time

Input Hold Time

Min

Typ

Max

Unit

ns

74

37

ns

t_LLCL

ns

t_LLCH

15

5

ns

t_SETUP

t_HOLD

ns

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5.3.8 ISA-LIKE BUS AC TIMING

Waveform of IO Write Operation

SAIOW#

SAADDR15-0

Address

Data

SADATA7-0

50ns

150ns

80ns

Waveform of IO Read Operation

150ns

SAIOR#

SAADDR15-0

Address

Data

20ns

SADATA7-0

50ns

0ns

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W9960CF

6. APPENDIXES

6.1 Porting Guide for W9960 Win95 Device Driver

6.2 Firmware Loading Precedure

6.3 Application/Firmware Command Block

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June 1997


型号：	W9960CF
厂家：	WINBOND
描述：	Consumer Circuit, CMOS, PQFP208, PLASTIC, QFP-208 商用集成电路
文件：	总65页 (文件大小：390K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W9960CF [WINBOND]

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