WMS7101050M [WINBOND]
Digital Potentiometer, 1 Func, 50000ohm, Increment/decrement Control Interface, 256 Positions, PDSO8, 3 MM, MO-187AA, MSOP-8;
| 型号： | WMS7101050M |
| 厂家： | 
WINBOND |
| 描述： | Digital Potentiometer, 1 Func, 50000ohm, Increment/decrement Control Interface, 256 Positions, PDSO8, 3 MM, MO-187AA, MSOP-8 光电二极管 转换器 电阻器 |
| 文件： | 总23页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
WMS7100/1
NONVOLATILE DIGITAL POTENTIOMETERS
WITH UP/DOWN (3-WIRE) INTERFACE,
10KOHM, 50KOHM, 100KOHM RESISTANCE
256 TAPS
WITH OPTIONAL OUTPUT BUFFER
Publication Release Date: April 21, 2005
Revision 1.1
- 1 -
WMS7100/1
1. GENERAL DESCRIPTION
The WMS710x is a 256 non-volatile linear digital potentiometers available in 10KΩ, 50KΩ and 100KΩ
resistance values. The WMS7100/1 can be used as a three-terminal potentiometer or as a two
terminal variable resistor in a wide variety of applications.
The output of each potentiometer is determined by the wiper position, which varies in linearly between
VA and VB terminal according to the content stored in the volatile Tap Register (TR) which is
programmed through Up/Down (Increment/Decrement) interface. The channel has one non-volatile
memory location (NVMEM0) that can be directly written to by users through the Up/Down interface.
Power-on recall is also built in so the content of the NVMEM0 to Tap Register is automatically loaded.
The WMS7100/1 devices pin out the resistor wiper directly. The WMS7101 devices feature an output
buffer with 3mA minimum drive capability.
All the WMS7100/1 devices are single channel devices offered in 8-pin PDIP, SOIC and MSOP
packages. The WMS7100/1 devices operate over a wide operating voltage ranging from 2.7V to
5.5V.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
Drop-in replacements for many popular parts
Available output buffer for WMS7101 devices
Single linear-taper channel
256 taps
10K, 50K and 100K end-to end resistance
VSS to VDD terminal voltages
Non-volatile storage of wiper positions with power-on recall
Data storage and potentiometer control through Up/Down (3-wire) interface
Endurance 100,000 write cycles
Data retention 100 years
Package options:
o
8-pin PDIP, SOIC or MSOP
•
•
Industrial temperature range: -40° ~ 85°C
Single supply operation 2.7V to 5.5V
- 2 -
WMS7100/1
3. BLOCK DIAGRAM
VA
INC
VW
Up/Down
CS
Serial
U/D
VB
Interface
NV Memory
NVMEM0
NV Memory
Control
VSS
VDD
FIGURE 1 – WMS7100 BLOCK DIAGRAM (Rheostat Mode)
VA
INC
Up/Down
Serial
VW
VB
CS
U/D
Interface
NV Memory
NVMEM0
NV Memory
Control
VSS
VDD
FIGURE 2 – WMS7101 BLOCK DIAGRAM (Divider Mode)
Publication Release Date: April 21, 2005
Revision 1.1
- 3 -
WMS7100/1
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 5
6. PIN DESCRIPTION............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
7.1. Potentiometer and Rheostat Modes............................................................................................. 7
7.1.1. Rheostat Configuration .......................................................................................................... 7
7.1.2. Potentiometer Configuration .................................................................................................. 7
7.2. Non-Volatile Memory (NVMEM) ................................................................................................... 7
7.3. Serial Data Interface..................................................................................................................... 8
7.4. Operation Overview...................................................................................................................... 8
8. TIMING DIAGRAMS............................................................................................................................ 9
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 11
10. ELECTRICAL CHARACTERISTICS............................................................................................... 12
10.1 Test Circuits............................................................................................................................... 14
11. TYPICAL APPLICATION CIRCUITS .............................................................................................. 15
11.1. Layout Considerations.............................................................................................................. 17
12. PACKAGE DRAWINGS AND DIMENSIONS.................................................................................. 18
13. ORDERING INFORMATION........................................................................................................... 21
14. VERSION HISTORY ....................................................................................................................... 22
- 4 -
WMS7100/1
5. PIN CONFIGURATION
VDD
CS
VB
1
8
7
INC
1
2
3
4
INC
U/D
8
7
VDD
CS
VB
U/D
VA
2
3
4
6
5
VSS
VW
VA
6
8-MSOP
VSS
5
VW
8-SOIC
1
2
3
4
VDD
INC
8
7
U/D
VA
CS
6
5
VB
VW
VSS
8-PDIP
Publication Release Date: April 21, 2005
Revision 1.1
- 5 -
WMS7100/1
6. PIN DESCRIPTION
TABLE 1 – PIN DESCRIPTION
Pin Name
I/O
Description
INC
Increment Control. A High-Low transition of
when
I
INC
U/D
CS
is low will move the wiper up or down for one
increment based on the U/D input
Up/Down control Input. High state will cause the wiper to
move to the VB terminal, Low state to the VA terminal
I
VA
-
-
-
High terminal of WinPot
Ground pin, logic ground reference
Power Supply
VSS
VDD
CS
Chip Select. When
is HIGH, the part is deselected
CS
I
CS
VB
and the device will be in the standby mode.
LOW
enables the part, placing it in the active power mode
-
Low terminal of WinPot
Wiper terminal of WinPot (can be buffered), its position on
INC
the resistor array is controlled by the inputs on
CS
, U/D,
VW
O
and
- 6 -
WMS7100/1
7. FUNCTIONAL DESCRIPTION
The WMS7100/1, a nonvolatile digitally programmable potentiometers with 256 taps, with or without
output buffer, is designed to operate as both a potentiometer or a variable resistor depending upon
the output configuration selected.
The chip can store up to one 8-bit word in a nonvolatile memory (NVMEM0) in order to set the tap
register value when the device is powered up.
The WMS7100/1 is controlled by a serial Up-Down (3-wire) interface that allows setting the tap
register value as well as storing data in the nonvolatile memory.
7.1. POTENTIOMETER AND RHEOSTAT MODES
The WMS7100/1 can operate as either a rheostat or as a potentiometer (voltage divider). When in the
potentiometer configuration there are two possible modes. One is done using WMS7100 Winpot
device without the output buffer and the other mode is done with WMS7101 WinPot device with the
output buffer.
7.1.1. Rheostat Configuration
The WMS7100/1 acts as a two terminal resistive element in the rheostat configuration where one
terminal can be connected to either the end point pins of the resistor (VA and VB) and the other
terminal is the wiper (VW) pin. This configuration controls the resistance between the two terminals
and the resistance can be adjusted by sending the corresponding tap register setting to the
WMS7100/1 or can also be set by loading a pre-set tap register value from nonvolatile memory
NVMEM0 upon power up.
7.1.2. Potentiometer Configuration
In potentiometer configuration an input voltage is applied to either one of the end point pins (VA or VB).
The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the
wiper setting. The resistance cannot be directly measured in this configuration.
7.2. NON-VOLATILE MEMORY (NVMEM)
The WMS7100/1 has one NVMEM position available for storing the potentiometer setting. The
NVMEM position can be directly written via the Up/Down interface. The potentiometer is loaded with
the value stored in the NVMEM0 on power up.
Publication Release Date: April 21, 2005
- 7 -
Revision 1.1
WMS7100/1
7.3. SERIAL DATA INTERFACE
CS INC
, U/D pins. Only
The Up/Down family has a 3-wire Serial Data Interface consisting of
,
UP/DOWN operations can be performed. The key features of this interface include:
•
•
•
Increment/Decrement operations on the tap register (TR)
Direct refresh of tap register (TR) from internal NVMEM
Nonvolatile storage of the present tap register value into the NVMEM and automatic recall at
power up
•
For WMS7101 devices, output buffer amplifier
7.4. OPERATION OVERVIEW
The wiper position or the Tap Register(TR) setting can only be changed by the UP/DOWN operation
CS
INC
CS
with the combination of
the TR setting can be changed by toggling
down when U/D is Low. The TR setting will be stored into the user NVMEM automatically each time
CS INC INC CS
, U/D, and
signals. When
is low, the part will be activated and
INC
, and TR will move up when U/D is High and move
goes high while
holds high. Otherwise, if
is low when
goes high, the TR setting
will not be stored. The NVMEM content will be automatically loaded into TR at Power On. The user
NVMEM can be tested through the voltage measurement on the wiper pin after saving TR setting into
the NVMEM and reloading into the TR. When the TR setting is already at LOW, further DOWN
operations won’t change the setting. Similarly, when TR setting is at HIGH, further UP operations
won’t change the setting.
CS
When
is held HIGH, the part will be in Standby mode and the TR setting will not be changed.
The operating modes of Up/Down are summarized below.
Operation
Wiper toward VA
U/D
INC
CS
Low
High
High to Low
Low
Low to High
Low to High
High
Low
High to Low
Wiper toward VB
x
x
x
High
Low
x
Store Wiper Position
No Store, Return to Standby
Standby
Note: x means don’t care
- 8 -
WMS7100/1
8. TIMING DIAGRAMS
Conditions: VDD = +2.7V to 5.5V, VA = VDD, VB = 0V, T = 25°C
CS
(store)
tCPH
tCYC
tIC
tCI
tIL
tIH
90% 90%
INC
U/D
10%
tF
tR
tDI tID
tIW
[1]
MI
VW
FIGURE 3 –WMS7100/1 TIMING DIAGRAM
Note:
[1] MI in the AC Timing diagram (Figure 3) refers to the minimum incremental change in the wiper output due to a change in the
wiper position.
Publication Release Date: April 21, 2005
- 9 -
Revision 1.1
WMS7100/1
TABLE 10 – TIMING PARAMETERS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
tCI
100
50
ns
CS
INC
INC
INC
to
Setup
Setup
Hold
tDI
tID
ns
ns
ns
ns
U/D to
U/D to
100
tIL
250
INC
INC
INC
CS
LOW Period
HIGH Period
tIH
250
tIC
1
μs
ns
CS
Inactive to
Inactive
tCPH
100
Deselect Time (NO STORE)
Deselect Time (STORE)
15 (2.7V)
ms
tCPH
CS
tIW
5
μs
μs
μs
INC
INC
INC
to VW Change
tCYC
1
Cycle Time
500
1
tR, tF
tPU
Input Rise and Fall Time
ms
Power-Up to Wiper Stable
0.2
50
V/ms
(13ms
0-2.7V)
VCC Power-Up rate
tR VCC
(54μs
0-2.7V)
- 10 -
WMS7100/1
9. ABSOLUTE MAXIMUM RATINGS
TABLE 11 – ABSOLUTE MAXIMUM RATINGS (PACKAGED PARTS)[1]
Conditions
Junction temperature
Storage temperature
Values
150ºC
-65º to +150ºC
Voltage applied to any pad
VDD – VSS
(Vss – 0.3V) to (VDD + 0.3V)
-0.3 to 7.0V
TABLE 12 – OPERATING CONDITIONS (PACKAGED PARTS)
Conditions
Commercial operating temperature range
Extended operating temperature
Industrial operating temperature
Supply voltage (VDD)
Values
0ºC to +70ºC
-20ºC to +70ºC
-40ºC to +85ºC
+2.7V to +5.5V
0V
Ground voltage (VSS)
[1] Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum
ratings may affect device reliability. Functional operation is not implied at these conditions
Publication Release Date: April 21, 2005
- 11 -
Revision 1.1
WMS7100/1
10. ELECTRICAL CHARACTERISTICS
TABLE 12 – ELECTRICAL CHARACTERISTICS (Packaged parts)
PARAMETERS
Rheostat Mode
SYMBOL
MIN.
TYP.
MAX.
UNITS
CONDITIONDS
Nominal Resistance
Different Non Linearity [2]
Integral Non Linearity [2]
Tempo1
R
DNL
INL
-20
-1
+20
+1
%
LSB
LSB
ppm/°C
Ω
T=25ºC, VW open
-1
+1
300
50
ΔRAB/ΔT
RW
Wiper Resistance [2]
VDD=5V, I=VDD/RTotal
VDD=2.7V, I=VDD/RTotal
80
Ω
Wiper Current
IW
-1
1
mA
Divider Mode
Resolution
N
8
Bits
LSB
LSB
Different Non Linearity [2]
Integral Non Linearity [2]
Temperature Coefficient [1]
Full Scale Error
DNL
INL
-1
-1
+1
+1
±0.4
±0.2
+20
Code = 80h
ΔVw/ΔT
VFSE
ppm/°C
LSB
-1
0
0
1
Code = Full Scale
Code = Zero Scale
Zero Scale Error
VZSE
LSB
Resistor Terminal
Voltage Range
VA,VB,VW
CA, CB
VSS
VDD
V
Terminal Capacitance [1]
30
30
pF
pF
Wiper Capacitance [1]
Dynamic Characteristics [1]
BW10K
BW50K
BW100K
TS
1.5
300
200
80
MHz
KHz
KHz
uS
VDD=5V, VB=VSS
Code = 80h
Bandwidth –3dB
Settling Time to 1 LSB
100
Analog Output (Buffer enables)
Amp Output Current
IOUT
3
mA
VO=1/2 scale
IL = 100uA
Amp Output Resistance
Rout
1
10
Ω
VA=2.5V, VDD=5V, f=1kHz,
VIN=1VRMS
Total Harmonic Distortion [1]
THD
0.08
%
Digital Inputs/Outputs
Input High Voltage
Input Low Voltage
VIH
VIL
0.7VDD
V
V
0.3VDD
- 12 -
WMS7100/1
PARAMETERS
Output Low Voltage
Input Leakage Current
SYMBOL
MIN.
TYP.
MAX.
0.4
UNITS
V
CONDITIONDS
VOL
ILI
IOL=2mA
-1
-1
+1
uA
CS
CS
=VDD,Vin=Vss ~ VDD
=VDD,Vin=VSS ~ VDD
Output Leakage Current
ILo
+1
uA
Input Capacitance [1]
Output Capacitance [1]
CIN
25
25
pF
pF
VDD=5V, fc = 1Mhz
VDD=5V, fc = 1Mhz
COUT
Power Requirements
Operating Voltage
VDD
IDDR
2.7
5.5
1
V
All ops except NVMEM
program
Operating Current
Operating Current
0.5
1
mA
During
Non-volatile
IDDW
2
1
1
1
mA
mA
memory program
Buffer is active, NOP, no
load
[3]
ISA
0.5
0.1
Standby Current
Buffer is inactive, Power
Down, No load
[4]
ISB
uA
Power Supply Rejection
Ratio
PSRR
LSB/V
VDD=5V±10%, Code=80H
Notes:
[1] Not subject to production test.
[2] LSB = (VA - VB) / (T- 1); DNL = (Vi+1 - Vi) / LSB; INL = (Vi - i*LSB) / LSB;
where i = [0, (T -1)] and T = # of taps of the device.
[3] WMS71x1 only.
[4] WMS71x0 only.
Publication Release Date: April 21, 2005
Revision 1.1
- 13 -
WMS7100/1
10.1 TEST CIRCUITS
±
V+ = V 10%
DD
PSRR(dB) = 20LOG(
Δ
VMS
)
VA
V+ = VDD
1LSB= V+/256
Δ
VDD
VA
VB
Δ
VMS
PSS(%/%) =
VW
Δ
VDD
VW
V+
V+
VB
VMS*
VMS*
WMS71xx
WMS71xx
*Assume infinite input impedance
*Assume infinite input impedance
Potentiometer divider nonlinearity error
test circuit (INL, DNL)
Power supply sensitivity test circuit (PSS, PSRR)
WMS71xx
No Connection
WMS71xx
VA
VB
+5V
VW
IW
VA
W
VW
VOUT
VB
VMS*
~
VIN
2.5V DC
Offset
*Assume infinite input impedance
Resistor position nonlinearity error test
Capacitance test circuit
circuit (Rheostat Operation: R-INL, R-DNL)
V*
WMS71xx
+5V
VA
VW
IW = V /RTotal
DD
VA
VB
IW
~
VIN
VOUT
VW
VB
OFFSET
GND
RW = V /IW
MS
WMS71xx
2.5V DC
*Assume infinite input impedance
Gain vs. frequency test circuit
Wiper resistance test circuit
FIGURE 4 – TEST CIRCUITS
- 14 -
WMS7100/1
11. TYPICAL APPLICATION CIRCUITS
RA
RB
Vin
WMS71XX
_
+
VOUT
OP
AMP
R
B
VOUT = - VIN
RA
RAB(256 −D)
RABD
256
RA =
,
RB =
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS71XX
FIGURE 5 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7100/1
VIN
+
_
VOUT
OP
AMP
RA
RB
WMS71XX
R
B
VOUT = VIN (1+
)
RA
RAB(256 −D)
RABD
RA =
, RB =
256
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS71XX
FIGURE 6 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7100/1
Publication Release Date: April 21, 2005
- 15 -
Revision 1.1
WMS7100/1
V+
I = 32mA
VREFH
VREF = 5.0v
WMS71xx
GND
FIGURE 7 – WMS7100/1 TRIMMING VOLTAGE REFERENCE
VDD
L1
CHOKE
C1
0.1uF
CS\
CS\
U/D\
INC\
VSS
VDD
VA
VW
RF OUT
U/D\
Q1
INC\
FILTER
VB
RF POWER AMP
WMS71xx WINPOT
C2
RF Input
FIGURE 8 – WMS7100/1 RF AMP CONTROL
- 16 -
WMS7100/1
11.1. LAYOUT CONSIDERATIONS
Use a 0.1μF bypass capacitor as close as possible to the VDD pin. This is recommended for best
performance. Often this can be done by placing the surface mount capacitor on the bottom side of the
PC board, directly between the VDD and VSS pins. Care should be taken to separate the analog and
digital traces. Sensitive traces should not run under the device or close to the bypass capacitors.
A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
INC
U/D
VA
VDD
CS
VB
DIGITAL
CONTROL LINES
DIGITAL
CONTROL LINE
CAP
ANALOG
SIGNAL LINE
ANALOG
SIGNAL LINES
VSS
VW
FIGURE 9 – WMS7100/1 LAYOUT
Publication Release Date: April 21, 2005
Revision 1.1
- 17 -
WMS7100/1
12. PACKAGE DRAWINGS AND DIMENSIONS
8
c
5
E
H
E
L
1
4
O
0.25
D
A
Y
e
SEATING PLANE
GAUGE PLANE
A1
b
Control demensions are in milmeters .
DIMENSION IN MM
DIMENSION IN INCH
SYMBOL
MIN.
1.35
MAX.
MIN.
MAX.
0.053
0.069
0.010
0.020
A
A1
b
1.75
0.10
0.33
0.19
0.004
0.013
0.25
0.51
c
0.25
0.008
0.150
0.010
0.157
3.80
4.80
E
D
4.00
5.00
0.188
0.196
e
0.050 BSC
1.27 BSC
6.20
0.10
1.27
10
H
5.80
0.228
0.244
0.004
E
Y
0.40
0
0.016
0
0.050
10
L
θ
FIGURE 10: 8L 150MIL SOIC
- 18 -
WMS7100/1
D
8
5
E 1
4
1
B
B
1
E
S
c
2
B ase P lane
A1
A
A
L
S eating P lane
e 1
e A
α
D im en sio n in in ch
D im en sio n in m m
S ym b o l
A
M in N o m
M ax
M in N o m
M ax
4.45
0.175
0.010
0.25
A
1
0.130
0.125
0.135
0.022
0.064
0.014
0.380
A 2
3.18
0.41
1.47
0.20
3.30
0.46
1.52
0.25
9.14
7.62
6.35
2.54
3.30
3.43
0.56
1.63
0.36
9.65
7.87
6.48
2.79
0.016 0.018
B
0.060
0.058
B
c
1
0.008 0.010
0.360
D
0.310
0.255
0.110
0.290
0.300
7.37
6.22
2.29
3.05
E
E
e
1
1
0.245 0.250
0.090 0.100
L
α
e
0.120 0.130
0
0.140
15
3.56
15
0
A
0.335
0.375
0.045
8.51
9.53
1.14
0.355
9.02
S
FIGURE 11: 8L 300MIL PDIP
Publication Release Date: April 21, 2005
Revision 1.1
- 19 -
WMS7100/1
FIGURE 12: 8L 3MM MSOP
- 20 -
WMS7100/1
13. ORDERING INFORMATION
Winbond’s WinPot Part Number Description:
Winbond WinPot Products w/ Up-Down Interface
WMS71 T
B
RRR P
Number Of Taps:
0 = 256
For Up/Down interface:
0 : No buffer
1 : With buffer
End-to-end Resistance:
010: 10Kohm
050: 50Kohm
100: 100Kohm
Package:
S: SOIC
P: PDIP
M: MSOP
Output
Buffer
End-to-End
Resistance
SOIC
PDIP
MSOP
NO
10K
50K
WMS7100010S
WMS7100050S
WMS7100100S
WMS7101010S
WMS7101050S
WMS7101100S
WMS7100010P
WMS7100050P
WMS7100100P
WMS7101010P
WMS7101050P
WMS7101100P
WMS7100010M
WMS7100050M
WMS7100100M
WMS7101010M
WMS7101050M
WMS7101100M
100K
10K
YES
50K
100K
Notes:
Part number with white background: Available for sampling and mass production.
Part numbers with shaded background: Call factory for availability.
For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com
Publication Release Date: April 21, 2005
Revision 1.1
- 21 -
WMS7100/1
14. VERSION HISTORY
VERSION
1.0
DATE
DESCRIPTION
June 2003
April 2005
Initial issue
1.1
Revise disclaim section
- 22 -
WMS7100/1
Winbond products are not designed, intended, authorized or warranted for use as components in systems or
equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments,
transportation instruments, traffic signal instruments, combustion control instruments, or for other applications
intended to support or sustain life. Furthermore, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or severe property or
environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their own risk and agree to
fully indemnify Winbond for any damages resulting from such improper use or sales.
The contents of this document are provided only as a guide for the applications of Winbond products. Winbond
makes no representation or warranties with respect to the accuracy or completeness of the contents of this
publication and reserves the right to discontinue or make changes to specifications and product descriptions at any
time without notice. No license, whether express or implied, to any intellectual property or other right of Winbond or
others is granted by this publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale,
Winbond assumes no liability whatsoever and disclaims any express or implied warranty of merchantability, fitness
for a particular purpose or infringement of any Intellectual property.
The contents of this document are provided “AS IS”, and Winbond assumes no liability whatsoever and disclaims
any express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual
property. In no event, shall Winbond be liable for any damages whatsoever (including, without limitation, damages
for loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of
this documents, even if Winbond has been advised of the possibility of such damages.
Application examples and alternative uses of any integrated circuit contained in this publication are for illustration
only and Winbond makes no representation or warranty that such applications shall be suitable for the use specified.
The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published
in the Winbond Reliability Report, and are neither warranted nor guaranteed by Winbond. This product incorporates
SuperFlash®.
This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD® ChipCorder®
product specifications. In the event any inconsistencies exist between the information in this and other product
documentation, or in the event that other product documentation contains information in addition to the information in
this, the information contained herein supersedes and governs such other information in its entirety. This datasheet
is subject to change without notice.
Copyright© 2005, Winbond Electronics Corporation. All rights reserved. ChipCorder® and ISD® are trademarks of
Winbond Electronics Corporation. SuperFlash® is the trademark of Silicon Storage Technology, Inc. All other
trademarks are properties of their respective owners.
Publication Release Date: April 21, 2005
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Revision 1.1
相关型号：
WMS7101100S
Digital Potentiometer, 1 Func, 100000ohm, Increment/decrement Control Interface, 256 Positions, PDSO8, 0.150 INCH, SOIC-8
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