WMS7204010SY [WINBOND]
Digital Potentiometer, 4 Func, 10000ohm, 3-wire Serial Control Interface, 256 Positions, PDSO20, 0.150 INCH, LEAD FREE, SOIC-20;
| 型号： | WMS7204010SY |
| 厂家： | 
WINBOND |
| 描述： | Digital Potentiometer, 4 Func, 10000ohm, 3-wire Serial Control Interface, 256 Positions, PDSO20, 0.150 INCH, LEAD FREE, SOIC-20 数字电位计 |
| 文件： | 总29页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
WMS7201
256-TAP NON-VOLATILE DIGITAL POTENTIOMETER
Publication Release Date: January 2003
- 1 -
Revision 1.1
WMS7201
1. GENERAL DESCRIPTION
The WMS7201 is a 256-tap, single-channel non-volatile digital potentiometer available in 10KΩ, 50KΩ
and 100KΩ end-to-end resistances. These devices can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of applications.
The output of the potentiometer is determined by the wiper position, which varies linearly between VA
and VB terminal according to the content stored in the volatile Tap Register (TR). The settings of the
TR can be provided either directly by the user through the industry standard SPI interface, or by the
non-volatile memory (NVMEM0~3) where the previous settings are stored. When changes are made
to the TR to establish a new wiper position, the value of the setting can be saved into any non-volatile
memory location (NVMEM0~3) by executing a NVMEM save operation. Upon powerup the content of
the NVMEM0 is automatically loaded to the Tap Register.
The WMS7201 contains a single potentiometer in 8-pin PDIP, SOIC, MSOP or 10 pin TSSOP
packages and can operate over a wide operating voltage range from 2.7V to 5.5V. A selectable output
buffer is built-in for those applications where an output buffer is required.
2. FEATURES
• 256 taps for the potentiometer
• End-to-end resistance available in 10KΩ, 50KΩ and 100KΩ
• Selectable output buffer for each channel
• SPI Serial Interface for data transfer and potentiometer control
• Daisy-chain operation for multiple devices (10-pin TSSOP package only)
• Nonvolatile storage of four wiper positions per channel with power-on recall from NVMEM0
• Low standby current (1µA Max. with output buffer inactive)
• Endurance 100K typical stores per bit
• Register Data Retention 100 years
• Industrial temperature range: -40 ~ 85°C
• Wide operating voltage range: 2.7V ~ 5.5V
• Package option:
ꢀ
8-pin MSOP, 8-pin SOIC, 8-pin PDIP, 10-pin TSSOP
- 2 -
WMS7201
3. BLOCK DIAGRAM
VA1
CLK
VW1
Serial
CS
Interface
SDI
VB1
1
SDO
NV Memory
9th
Power on/Preset Mem Tap
bit
1
9th
bit
NV Memory
Control
WP
VDD
VSS
3 Addressable Preset Tap values
FIGURE 1 – WMS7201 BLOCK DIAGRAM
Note 1: Available in 10-pin TSSOP packages only.
Publication Release Date: January 2003
Revision 1.1
- 3 -
WMS7201
4. TABLE OF CONTENTS
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. BLOCK DIAGRAM .............................................................................................................................. 3
4. TABLE OF CONTENTS ...................................................................................................................... 4
5. PIN CONFIGURATION ....................................................................................................................... 5
6. PIN DESCRIPTION............................................................................................................................. 5
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
7.1. Potentiometer and Rheostat Modes............................................................................................. 7
7.1.1. Rheostat Configuration .......................................................................................................... 7
7.1.2. Potentiometer Configuration .................................................................................................. 7
7.2. Programming Modes .................................................................................................................... 7
7.3. Non-Volatile Memory (NVMEM) ................................................................................................... 8
7.3.1 Write Protect of NVMEM......................................................................................................... 8
7.4 Flow Control................................................................................................................................... 8
7.5. Daisy Chain .................................................................................................................................. 9
7.6. Serial Data Iterface..................................................................................................................... 10
7.7. Instruction Set............................................................................................................................. 12
7.8. Basic Operation .......................................................................................................................... 12
7.8.1 Sending a Command ............................................................................................................ 12
7.8.2 Wake Up/Sleep/Power Commands ...................................................................................... 13
7.8.3 Write to Tap Register (TR).................................................................................................... 13
7.8.4 Programming Non-Volatile Memory (NVMEM)..................................................................... 14
7.8.5 Reading Tap Register and NVMEM Location (10-pin TSSOP package only)...................... 15
8. TIMING DIAGRAMS.......................................................................................................................... 16
9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 18
10. ELECTRICAL CHARACTERISTICS............................................................................................... 19
10.1 Test Circuits............................................................................................................................... 21
11. TYPICAL APPLICATION CIRCUIT................................................................................................. 22
11.1. Layout Considerations.............................................................................................................. 24
12. PACKAGE DRAWINGS AND DEMINSIONS.................................................................................. 25
13. ORDERING INFORMATION........................................................................................................... 28
14. VERSION HISTORY ....................................................................................................................... 29
- 4 -
WMS7201
5. PIN CONFIGURATION
FIGURE 2 – PACKAGE TYPES
Publication Release Date: January 2003
Revision 1.1
- 5 -
WMS7201
6. PIN DESCRIPTION
TABLE 1 – PIN DESCRIPTION
DESCRIPTION
PIN NAME PIN NO I/O
2
Serial Clock pin. Data Shifts in one bit at a time on positive clock
CLK
CS
I
(CLK) edges
Chip Select pin. When CS is HIGH, WMS7201 is deselected and
the SDO pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby state. CS LOW
enables WMS7201, placing it in the active power mode. It should
be noted that after a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
I
1
3
Serial Data Input pin. All opcodes, byte addresses and data to be
written to the registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Data Output pin with open-drain output. During a read cycle,
data is shifted out on this pin. Data is clocked out by the falling
edge of the serial clock except for the 1st bit, which is clocked out
by the falling edge of CS. Also can be used to daisy-chain several
parts. (Only 10-pin TSSOP package)
SDI
I
O
I
NC
SDO1
Hardware Write Protect pin. When active LOW WP prevents any
changes to the present contents except retrieving NVMEM
contents. (Only 10-pin TSSOP package)
1
NC
WP
VDD
VSS
8
4
-
-
Power Supply
Ground pin, logic ground reference
7
5
6
A terminal of potentiometer ‘1’, equivalent to the HI terminal
connection on a mechanical potentiometer
B terminal of potentiometer ‘1’, equivalent to the LO terminal
connection on a mechanical potentiometer
Wiper terminal of potentiometer ‘1’, equivalent to the wiper terminal
of a mechanical potentiometer
VA1
VB1
VW1
-
-
O
- 6 -
WMS7201
7. FUNCTIONAL DESCRIPTION
The WMS7201 series, a family of 256-tap, nonvolatile digitally programmable potentiometers is
designed to operate as both a potentiometer or a variable resistor depending upon the output
configuration selected.
The chip can store four 9-bit words in nonvolatile memory (NVMEM0 ~ NVMEM3) and the word stored
in the NVMEM0 will be used to set the tap register values when the device is powered up.
The WMS7201 is controlled by a serial SPI interface that allows setting tap register value as well as
storing data in the nonvolatile memory.
7.1. POTENTIOMETER AND RHEOSTAT MODES
The WMS7201 can operate as either a rheostat or as a potentiometer (voltage divider). When in the
potentiometer configuration there are two possible modes. One is without the output buffer and the
other mode is with the output buffer. Selecting the mode is done by controlling bit D8 of the data
register. D8 = 0 sets the output buffer off and D8 = 1 sets it on.
Note that this bit can only be set by loading the value to the NVMEM with instructions #5 and
then loading the TAP register with instruction #6 from NVMEM. This bit cannot be controlled by
directly writing the value to the chip when the tap register is set.
7.1.1. Rheostat Configuration
The WMS7201 acts as a two terminal resistive element in the rheostat configuration where one
terminal is either one of the end point pins of the resistor (VA and VB) and the other terminal is the
wiper (VW) pin. This configuration controls the resistance between the two terminals and the
resistance can be adjusted by sending the corresponding tap register setting commands to the
WMS7201 or loading a pre-set tap register value from nonvolatile memory NVMEM0 ~ MVMEM3.
7.1.2. Potentiometer Configuration
In potentiometer configuration an input voltage is connected to one of the end point pins (VA or VB).
The voltage on the wiper pin will be proportional to the voltage difference between VA and VB and the
wiper setting. The resistance cannot be directly measured in this configuration.
7.2. PROGRAMMING MODES
Two program modes are available for the WMS7201:
•
Direct program mode. The tap register setting can be changed either by loading a
predetermined value from an external microcontroller or by using the UP/DOWN command.
The UP and DOWN commands change the tap register setting incrementally i.e., 1 LSB at a
time. The UP and DOWN commands will not wrap around at the ends of the scale.
•
NVMEM restore mode. One of the previously stored settings can be loaded into the TR
register from the non-volatile memory. Four 9-bit non-volatile memories, are available for to
store the tap register settings. The first register, NVMEM0, stores the favorite or default tap
register setting that will be loaded into the tap register at system power up or software power
on reset operation.
Publication Release Date: January 2003
- 7 -
Revision 1.1
WMS7201
7.3. NON-VOLATILE MEMORY (NVMEM)
The WMS7201 has four NVMEM positions available for storing the output buffer operating mode and
the potentiometer setting. These NVMEM positions can be directly written through the SPI using a
write command (#5) with address and data bytes. Another command (#7) is available that stores the
current output buffer operating mode and potentiometer settings into the selected NVMEM position.
Bit A3 and A2 in the instruction byte decide which NVMEM position is used. (See Table 5)
The potentiometer is loaded with the value stored in the NVMEM position 0 on power up.
7.3.1 Write Protect of NVMEM
Write-Protect ( WP ) disables any changes of current content in the NVMEM regardless of the
commands, except that NVMEM setting can be retrieved using commands 4, 6 of Table 5. Therefore,
Write-Protect ( WP ) pin provides hardware NVMEM protection feature with WP tied to Vss. WP ,
which is active at logic LOW, should be tied directly to VDD if it is not being used. This function is only
available on the 10-pin package.
7.4 FLOW CONTROL
Reading and writing to NVMEM requires an internal access cycle to complete before the next
command can be sent.
Read Tap Register (#2)
Read NVMEM (#4)
Program NVMEM (#5)
Load Tap Register(#6)
Program NVMEM with Tap Register (#7)
- 8 -
WMS7201
7.5. DAISY CHAIN
Multiple devices can be controlled by the same bus without the need for extra CS lines from the
microcontroller by daisy chaining the devices with the SDO of the first device connected to SDI of the
next device as shown in figure 3 when using the 10-pin package.
VDD
CS
Micro
controller
SDO
CS
CS
CS
SDI SDO
SDI SDO
SDI SDO
Device
Device
Device
FIGURE 3 – DAISY CHAIN CONFIGURATION [10-PIN TSSOP PACKAGE ONLY]
A complete command is 24 bits including the instruction and the two data bytes. When shifting 24 bits
in to the first device in the chain, the 24 bits of the previous command will be shifted out. So to set up
two devices in a daisy chain, a total of 48 bits must be sent where the first 24 bits will be shifted out to
the second device and the 24 bits shifted in last will remain in the first device.
1. Command and data for device 2 is shifted into device 1, this will propagate to Device 2 when
the next 24 bits are shifted in.
Device
Command 1
Data
Device
xx
2
Data
2
xx
xx
2. Command and data for device 1 is shifted into device 1. Now Device 1 and 2 are correctly set
up. 10-pin TSSOP package only.
Device
Command 2
Data
1
Data
1
Device
Command 1
Data
2
Data
2
FIGURE 4 – DAISY CHAIN COMMAND EXAMPLE
Publication Release Date: January 2003
Revision 1.1
- 9 -
WMS7201
7.6. SERIAL DATA ITERFACE
The WMS7201 contains a four-wire SPI interface:
•
SDO (Serial Data Output) Used for reading out the internal register contents and for daisy
chaining multiple devices on the 10-pin package.
•
•
SDI (Serial Data Input) Used for clocking in commands and potentiometer settings.
CS (Chip Select) This pin must be pulled LOW before starting to send a command and pulled
HIGH to signal the end of the command; this pin can be used to control multiple devices on
the bus.
•
CLK (Clock) The SDI bits are shifted in on the rising edge of the clock and SDO data is
shifted out on the falling edge of the clock.
The key features of this interface include:
•
•
•
•
Independently programmable Read & Write to all registers
Direct parallel refresh of Tap register from corresponding internal NVMEM registers
Increment and decrement instruction for Tap register
Nonvolatile storage of the present Tap register values into one of the four NVMEM registers
available.
•
•
Configurable output buffer amplifier to allow both the functions of a potentiometer and a
variable resistor
Four 9-bit non-volatile registers store four preset wiper positions and the first one will be
recalled to set the wiper position during power up.
The serial interface uses an SPI compatible uniform 24-bit word format as shown below. This format is
used for all members of the WMS720x family. The data is sent MSB first.
TABLE 2 – 24-BIT DATA WORD FORMAT
MSB
C3
LSB
D0
C2
C1
C0
A3
A2
A1
A0
X
X
X
X
X
X
X
D8
D7
D6
D5
D4
D3
D2
D1
C3-C0 are the command bits that control the operation of the digital potentiometer according to the
command instructions shown in the Instruction Set in Table 5 in Section 7.7.
A1 and A0 are the address bits that determine which channel is activated in the WMS720x family as
shown in the table below. For the WMS7201 A0 and A1 are always set to 0.
- 10 -
WMS7201
TABLE 3 – A1 AND A0 ADDRESS BIT DECODE TABLE
[A1 A0]
Channel
[0 0]
0
[0 1]
1
[1 0]
2
[1 1]
3
A3 and A2 are the address bits that decide which NVMEM memory to be accessed, as shown in the
table below.
TABLE 4 – A3 AND A2 ADDRESS BIT DECODE TABLE
[A3 A2]
NVMEM
[0 0]
0
[0 1]
1
[1 0]
2
[1 1]
3
D7-D0 are the data values to be loaded into the Tap Register to set the wiper position, while D8 is
used to set the output mode. D8 has to be loaded into the NVMEM0~3 first and then the “Load Tap
Register” command (#6) has be executed to load D8 into the output-selection MUX to set the output
mode. D8=0 sets the output to Buffer Off mode while D8=1 sets to Buffer On mode.
CS is taken LOW
before command
starts
CS is taken HIGH
after command is
sent
CS
1
2
3
4 5
6
7
8
9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
CLK
SDI
C3C2 C1 C0 A3 A2 A1 A0 x
`
x
x
x
x
x
x D8 D7 D6 D5 D4 D3 D2 D1 D0
Note:
•
A multiple of 24 bits must always be sent or the
command will not be valid
•
Bits marked ‘x’ are don’t care bits.
FIGURE 5 – SPI COMMAND WAVEFORMS
Publication Release Date: January 2003
Revision 1.1
- 11 -
WMS7201
7.7. INSTRUCTION SET
TABLE 5 – INSTRUCTION SET
Inst
No.
Instruction Byte
Data Byte 1
Data Byte 2
Operation
C3 C2 C1 C0 A3 A2 A1
A0
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
1
0
1
0
1
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
No Operation (NOP). Do nothing
2
x A1 A0
Read Tap Register and output
selection MUX register
3
4
5
0
1
0
1
0
0
0
1
1
0
x
x A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D7 D6 D5 D4 D3 D2 D1 D0
Write to Tap Register with D7-D0
Read NVMEM pointed to by A3-A0
0 A3 A2 A1 A0
0 A3 A2 A1 A0
x x x x x x x x
x
D7 D6 D5 D4 D3 D2 D1 D0
Program NVMEM pointed to by
D8
A3-A0 with D8-D0
6
1
0
1
1 A3 A2 A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Load Tap Register and output
selection MUX register with the
contents of NVMEM pointed to by
A3-A0
7
0
0
1
1 A3 A2 A1 A0
x
x
x
x
x
x
x
Program NVMEM pointed to by
A3-A0 with the contents of Tap
Register and output selection MUX
register
8
0
1
1
0
1
1
1
1
0
0
1
0
1
1
0
0
0
0
1
1
0
1
x
x
x
x
x A1 A0
x A1 A0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Up: Increment setting of TR by one
tap
9
Down: Decrement setting of TR by
one tap
10
11
12
13
x
x
x
x
x
x
Sleep: Discontinue clock supply to
the logic and memories
Wake Up: Clock supply to the logic
and memories
1 A3 A2 A1 A0
Byte-erase NVMEM pointed to by
A3-A0
1
x x x x
Power On Reset: Software reset
the part to the power up state
Note: C3-C0 are the command op-code; A3, A2 are the NVMEM address; A1, A0 are the channel address.
7.8. BASIC OPERATION
This chapter describes the sequences of commands to send to the WMS7201 and how to use the
different features.
7.8.1 Sending a Command
1. Take the chip out of SLEEP mode.
2. Check that the write protect is set correctly if writing to NVMEM (10-pin TSSOP package
only).
3. Pull the CS pin LOW before sending data to the device.
- 12 -
WMS7201
4. 24 clock pulses are sent for each command. SDI must be valid on the rising edge of the clock,
SDO is valid on the falling edge of the clock or CS.
5. Take CS HIGH after the command has completed
6. If command 2, 4, 5, 6 or 7 is sent, wait TSV time before sending the next command.
7.8.2 Wake Up/Sleep/Power Commands
The chip is in SLEEP mode after:
•
•
•
VDD is applied
A Power on Reset command is sent
A SLEEP command is sent
Before any operations can be performed the WAKE UP command must be sent.
When a SLEEP command is sent, the chip retains its resistor settings as long as the chip is powered
up but cannot accept any other commands than a WAKE UP command.
TABLE 6 – POWER RELATED COMMANDS
Inst. Command
Command Byte Data Byte 1
Data Byte 2
Comment
No.
11
Name:
Wake Up
Sleep
0 0 0 1 x x x x
1 0 0 0 x x x x
x x x x x x x x x x x x x x x x Wake Up entire chip
x x x x x x x x x x x x x x x x Send chip into power
save mode
10
13
1
Power on Reset
NOP
1 0 0 1 x x x x
0 0 0 0 x x x x
x x x x x x x x x x x x x x x x Reset Chip
x x x x x x x x x x x x x x x x Dummy instruction
The commands above control the entire chip.
7.8.3 Write to Tap Register (TR)
The microcontroller can write a value directly into the tap register or send an increment or decrement
command to control the tap register. Alternatively, the contents of an NVMEM location can be written
to the tap register. The only way to change the output buffer mode is to write the desired value of bit
D8 into an NVMEM location and then load the corresponding NVMEM location into the tap register.
Publication Release Date: January 2003
- 13 -
Revision 1.1
WMS7201
TABLE 7 – WRITING TO THE TAP REGISTERS
Command Byte Data Byte 1 Data Byte 2
Inst. Comman
Comment
No.
d Name:
3
Write to
0 1 0 0
x
x 0 0
x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 Writes a value to the
tap register.
Tap
Register
8
9
6
Up
0 1 1 1
1 1 1 1
x
x
x 0 0
x 0 0
x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x
x x x x x x x x x x x x x x x x
Increment tap
register value by one
Down
Decrement tap
register value by one
Load Tap
Register
1 0 1 1 A3 A2 0 0
Load the selected
NVMEM location into
the tap register
7.8.4 Programming Non-Volatile Memory (NVMEM)
The value stored in the NVMEM location is 9 bits, the 8 bits (D7-D0) of the tap register plus 1 bit (D8)
of the output buffer mode. The NVMEM position must be erased before writing to it. There are two
ways to program a value into NVMEM.
Write a value directly from the microcontroller.
Load the current potentiometer setting into NVMEM.
TABLE 8 – PROGRAMMING NVMEM
Inst. Command Command Byte
Data Byte 1
Data Byte 2
Comment
No
Name
12
Erase
1 1 0 1 A3 A2 0 0
x x x x x x x x
x
x
x
x
x
x
x
x
Erases the 9 bit word
pointed to by A3, A2, A1
and A0.
NVMEM
5
7
Program
NVMEM
Program
NVMEM
with Tap
Register
0 0 1 0 A3 A2 0 0
0 0 1 1 A3 A2 0 0
x x x x x x x D8
x x x x x x x x
D7 D6 D5 D4 D3 D2 D1 D0 Writes a value to the
NVMEM register.
x
x
x
x
x
x
x
x
Takes the current
potentiometer settings and
saves in the selected
NVMEM location.
For programming NVMEM, the following sequence must be followed:
1. Erase word at NVMEM location
2. Program word at NVMEM location
- 14 -
WMS7201
7.8.5 Reading Tap Register and NVMEM Location (10-pin TSSOP package only)
The contents of the tap register or any NVMEM location can be read back through the SDO pin. When
a command is sent, the data is clocked out on the falling edge of the clock. Since daisy-chain
operation requires data from one command to be clocked out when the next command arrives, any
read command must be followed by another command to get the correct data on the SDO pin.
TABLE 9 – READING THE TAP REGISTER
Inst. Command Command Byte
Data Byte 1
Data Byte 2
Comment
No.
Name:
4
Read
1 0 1 0 A3 A2 0 0
x x x x x x x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Read the value of the
selected NVMEM
location
Read the value of the
selected tap register
NVMEM
2
1
Read Tap
Register
1 1 0 0
0 0 0 0
x
x
x 0 0
x x x
x x x x x x x x
NOP to
Read
x x x x x x x D8 D7 D6 D5 D4 D3 D2 D1 D0 Output data to SDO
pin
Register
To read the contents of either the tap register or a NVMEM location, the following sequence must be
followed.
1. Send the desired read command (#2 or #4)
2. Send another command such as NOP and read the SDO pin on the falling edge of the clock.
The other command could be any command, but to make sure that the chip does not change
anything, send either another Read command or a NOP command (#1).
Publication Release Date: January 2003
- 15 -
Revision 1.1
WMS7201
8. TIMING DIAGRAMS
CLK
tCYC
tWL
tWH
tLEAD
tLAG
CS
tCS
tDSU
tDH
SDI
tPD
tLAC
tLRL
MSB
LSB
SDO
R/B
tRSU
tST
tSV
1
tWPSU
tWPH
2
FIGURE 6 – WMS7201 TIMING DIAGRAM
Notes: (1) Internal signal only. (2) Only on 10-pin TSSOP package.
- 16 -
WMS7201
TABLE 10 – TIMING PARAMETERS
PARAMETER
SPI Clock Cycle Time
SYMBOL
tCYC
tWH
MIN.
100
50
50
100
100
20
20
5
MAX.
UNIT
ns
SPI Clock HIGH Time
SPI Clock LOW Time
Lead Time
ns
tWL
ns
tLEAD
tLAG
tDSU
tDH
ns
Lag Time
ns
SDI Setup Time
ns
SDI Hold Time
CSto SDO – SPI Line Acquire 1
ns
tLAC
ns
CSto SDO – SPI Line Release 1
tLRL
5
ns
CLK to SDO Propagation Delay 1
tPD
1
ns
Store to NVMEM Save Time
tSV
tCS
2
ms
ns
600
0.1
10
CSDeselect Time
Startup Time
WP Setup Time 1
WP Hold Time 1
tST
tWPSU
ms
ns
tWPH
10
ns
Note: The interface timing characteristics apply to all parts but are guaranteed by design and not
subject to production test.
Note 1: 10-pin package only.
Publication Release Date: January 2003
- 17 -
Revision 1.1
WMS7201
9. ABSOLUTE MAXIMUM RATINGS
TABLE 11 – ABSOLUTE MAXIMUM RATINGS
Condition
Value
Junction temperature
Storage temperature
Voltage applied to any pad
VDD – VSS
150ºC
-65º to +150ºC
(Vss – 0.3V) to (VDD + 0.3V)
-0.3 to 7.0V
Note: Exposure to conditions beyond those listed under: Absolute Maximum Ratings, may adversely
affect the life and reliability of the device.
- 18 -
WMS7201
10. ELECTRICAL CHARACTERISTICS
TABLE 12 – ELECTRICAL CHARACTERISTICS
All Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: –40°C~85°C)
Typical values: VDD=5V and T=25°C
PARAMETER
SYMBOL
MIN.
TYP MAX.
UNITS CONDITIONS
Rheostat Mode
Nominal Resistance
Different Non Linearity
Integral Non Linearity
Rheostat Tempco1
R
DNL
INL
-20
-1
-1
+20
+1
+1
%
LSB
LSB
T=25ºC, VW open
0.3
0.5
500
∆RAB/∆T
ppm/°
C
Wiper Resistance2
RW
VDD=5V,
50
80
100
120
Ω
I=VDD/RTotal
VDD=2.7V,
I=VDD/RTotal
Ω
Potentiometer Mode
Resolution1
N
8
-1
-1
Bits
LSB
LSB
ppm/°
C
LSB
LSB
Different Non Linearity2
Integral Non Linearity2
Potentiometer Tempco1
DNL
INL
+1
+1
+20
Code = 80h
∆Vw/∆T
Full Scale Error
VFSE
VZSE
-1
0
0
1
Code = Full Scale
Code = Zero Scale
Zero Scale Error
Resistor Terminal
Voltage Range1
VA,VB,VW
CA, CB
VSS
VDD
V
pF
pF
Terminal Capacitance1
Wiper Capacitance1
Dynamic Characteristics1
30
30
BW10K
1.5
MHz
VDD=5V, VB=VSS
Code = Full Scale
Bandwidth –3dB
BW50K
BW100K
TS
300
200
80
KHz
KHz
uS
Code = 80h
CL=30pf
Settling Time to 1 LSB
100
VDD=5.5V=VA,
VB=VSS
Analog Output (Buffer enabled)
Amp Output Current2
IOUT
Rout
THD
3
mA
Ω
VO=1/2 scale
Amp Output Resistance2
1
10
VA=2.5V, VDD=5V,
f=1kHz, VIN=1VRMS
Total Harmonic Distortion1
0.08
%
Digital Inputs/Outputs
Input High Voltage
VIH
VIL
VOL
ILI
0.7VDD
-1
V
V
Input Low Voltage
0.3VDD
0.4
+1
Output Low Voltage
Input Leakage Current
V
IOL=2mA
CS=VDD,Vin=Vss
uA
Publication Release Date: January 2003
Revision 1.1
- 19 -
WMS7201
~ VDD
Output Leakage Current
ILo
-1
+1
uA
CS=VDD,Vin=VSS
~ VDD
VDD=5V, fc = 1Mhz
Code = 80h
Input Capacitance1
Output Capacitance1
CIN
25
25
pF
pF
VDD=5V, fc = 1Mhz
Code = 80h
COUT
Power Requirements
Operating Voltage1
VDD
IDDR
2.7
0.5
5.5
1.8
V
All ops except
NVMEM program
During Non-
volatile memory
program
Operating Current
1
1
mA
Operating Current
IDDW
ISA
2
1
1
1
mA
mA
Buffer is active, ,
no load
Standby Current
Buffer is inactive,
Power Down, No
load
2
ISB
0.1
uA
VDD=5V±10%,
Code=80h
Power Supply Rejection Ratio PSRR
LSB/V
Note: 1. Not subject to production test; 2. Only on Final Test; 3. VDD = +2.7V to 5.5V, VSS = 0V, T = 25ºC, unless otherwise
noted.
- 20 -
WMS7201
10.1 TEST CIRCUITS
±
V+ = V 10%
DD
∆
VMS
PSRR(dB) = 20LOG(
)
VA
V+ = VDD
∆
VDD
VA
VB
∆
VMS
1LSB= V+/255
PSS(%/%) =
VW
∆
VDD
VW
V+
V+
VB
VMS
*
VMS
*
WMS7201
WMS7201
*Assume infinite input impedance
*Assume infinite input impedance
Potentiometer divider nonlinearity error
Power supply sensitivity test circuit (PSS, PSRR)
WMS7201
No Connection
WMS7201
VA
VB
+5V
VW
IW
VA
W
VW
VOUT
VB
VMS*
~
VIN
2.5V DC
Offset
*Assume infinite input impedance
Resistor position nonlinearity error test
Capacitance test circuit
circuit (Rheostat Operation: R-INL, R-DNL)
V
*
WMS7201
VA
VW
+5V
I= V /RTotal
DD
VA
VB
IW
~
VIN
VOUT
VW
VB
OFFSET
GND
RW = V /IW
MS
WMS7201
2.5V DC
*Assume infinite input impedance
Gain vs. frequency test circuit
Wiper resistance test circuit
FIGURE 7 – TEST CIRCUITS
Publication Release Date: January 2003
Revision 1.1
- 21 -
WMS7201
11. TYPICAL APPLICATION CIRCUIT
RA
RB
Vin
WMS7201
_
+
VOUT
OP
AMP
R
B
A
VOUT = - VIN
R
RAB(256 −D)
RABD
256
RA =
,
RB =
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS7201
FIGURE 8 – PROGRAMMABLE INVERTING GAIN AMPLIFIER USING THE WMS7201
VIN
+
VOUT
OP
AMP
RA
RB
WMS7201
R
B
A
VOUT = VIN (1+
)
R
RAB(256 −D)
RABD
256
RA =
, RB =
256
RAB = Total resistance of potentiometer
D = Wiper setting for WMS7201
FIGURE 9 – PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING THE WMS7201
- 22 -
WMS7201
V+
I = 32mA
VREFH
VREF = 5.0v
WMS7201
GND
FIGURE 10 – WMS7201 TRIMMING VOLTAGE REFERENCE
VDD
L1
CHOKE
C1
0.1uF
1
2
3
4
8
CS\
SDI
CS
VDD
VA1
VW1
VB1
RF OUT
7
6
5
CLK
CLK
SDI
VSS
Q1
FILTER
RF POWER AMP
WMS7201 WINPOT
C2
RF Input
FIGURE 11 – WMS7201 RF AMP CONTROL
Publication Release Date: January 2003
Revision 1.1
- 23 -
WMS7201
11.1. LAYOUT CONSIDERATIONS
A 0.1µF bypass capacitor as close as possible to the VDD pin is recommended for best performance.
Often this can be done by placing the surface mount capacitor on the bottom side of the PC board,
directly between the VDD and VSS pins. Care should be taken to separate the analog and digital traces.
Sensitive traces should not run under the device or close to the bypass capacitors.
A dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals.
FIGURE 12 – WMS7201 LAYOUT
- 24 -
WMS7201
12. PACKAGE DRAWINGS AND DEMINSIONS
8
5
E
1
4
Control demensions are in milmeters .
E
θ
FIGURE 13 – 8L SOIC – 150MIL
Publication Release Date: January 2003
Revision 1.1
- 25 -
WMS7201
D
8
5
1
E
4
1
B
B
1
E
S
c
2
Base Plane
1
A
A
A
Seating Plane
L
e 1
eA
α
Dimension in inch
Dimension in mm
Symbol
Min
Nom
Max
0.175
Min
Nom
Max
4.45
A
A
A
0.010
0.25
3.18
0.41
1.47
0.20
1
2
0.130
0.018
0.060
0.010
0.360
0.135
0.022
0.064
0.014
0.380
0.125
0.016
0.058
0.008
3.30
0.46
1.52
0.25
9.14
7.62
6.35
2.54
3.30
3.43
0.56
1.63
0.36
9.65
7.87
6.48
2.79
B
B
c
1
D
0.310
0.255
0.110
0.290
0.245
0.090
0.300
0.250
0.100
7.37
6.22
2.29
E
E
e
1
1
0.140
15
3.05
0
0.120
0
0.130
3.56
15
L
α
A
e
S
9.53
1.14
0.335
0.355
0.375
0.045
8.51
9.02
FIGURE 14 – 8L PDIP
- 26 -
WMS7201
FIGURE 15 – 8L MSOP
Publication Release Date: January 2003
Revision 1.1
- 27 -
WMS7201
13. ORDERING INFORMATION
Winbond’s WinPot Part Number Description:
WMS72 XX XXX X
Winbond WinPot Products
Features:
•
•
•
01: Single channel with SPI Interface
02: Dual channels with SPI Interface
04: Quad channels with SPI Interface
End-to-end Resistance:
•
•
•
010: 10KΩ
050: 50KΩ
100: 100KΩ
Package Index:
•
•
•
•
T: TSSOP
S: SOIC
P: PDIP
M: MSOP (Available only for single channel
devices)
For the latest product information, access Winbond’s worldwide website at
http://www.winbond-usa.com
- 28 -
WMS7201
14. VERSION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
1.0
Jan. 2003
All
Initial issue
The contents of this document are provided only as a guide for the applications of Winbond
products. Winbond
completeness of the contents of this publication and reserves the right to discontinue or make
express or implied, to any intellectual property or other right of Winbond or others is granted by this
publication. Except as set forth in Winbond's Standard Terms and Conditions of Sale, Winbond
assumes no liability whatsoever and disclaims any express or implied warranty of merchantability,
fitness for a particular purpose or infringement of any Intellectual property.
Winbond products are not designed, intended, authorized or warranted for use as components in
systems or equipments intended for surgical implantation, atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, or for other applications intended to support or sustain life.
Further, Winbond products are not intended for applications wherein failure of Winbond products
could result or lead to a situation wherein personal injury, death or severe property or
environmental injury could occur.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III
Science-Based Industrial Park,
Hsinchu, Taiwan
2727 North First Street, San Jose,
27F, 299 Yan An W. Rd. Shanghai,
CA 95134, U.S.A.
200336 China
TEL: 1-408-9436666
TEL: 86-21-62365999
FAX: 86-21-62356998
TEL: 886-3-5770066
FAX: 1-408-5441797
FAX: 886-3-5665577
http://www.winbond-usa.com/
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No. 480, Pueiguang Rd.
Neihu District
7F Daini-ueno BLDG. 3-7-18
Shinyokohama Kohokuku,
Yokohama, 222-0033
TEL: 81-45-4781881
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
Taipei, 114 Taiwan
TEL: 886-2-81777168
FAX: 886-2-87153579
TEL: 852-27513100
FAX: 81-45-4781800
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
This product incorporates SuperFlash® technology licensed From SST.
Publication Release Date: January 2003
Revision 1.1
- 29 -
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